2 * Copyright © 2010 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
26 * This file drives the GLSL IR -> LIR translation, contains the
27 * optimizations on the LIR, and drives the generation of native code
31 #include "main/macros.h"
35 #include "brw_vec4_gs_visitor.h"
37 #include "brw_dead_control_flow.h"
38 #include "dev/gen_debug.h"
39 #include "compiler/glsl_types.h"
40 #include "compiler/nir/nir_builder.h"
41 #include "program/prog_parameter.h"
42 #include "util/u_math.h"
46 static unsigned get_lowered_simd_width(const struct gen_device_info
*devinfo
,
50 fs_inst::init(enum opcode opcode
, uint8_t exec_size
, const fs_reg
&dst
,
51 const fs_reg
*src
, unsigned sources
)
53 memset((void*)this, 0, sizeof(*this));
55 this->src
= new fs_reg
[MAX2(sources
, 3)];
56 for (unsigned i
= 0; i
< sources
; i
++)
57 this->src
[i
] = src
[i
];
59 this->opcode
= opcode
;
61 this->sources
= sources
;
62 this->exec_size
= exec_size
;
65 assert(dst
.file
!= IMM
&& dst
.file
!= UNIFORM
);
67 assert(this->exec_size
!= 0);
69 this->conditional_mod
= BRW_CONDITIONAL_NONE
;
71 /* This will be the case for almost all instructions. */
78 this->size_written
= dst
.component_size(exec_size
);
81 this->size_written
= 0;
85 unreachable("Invalid destination register file");
88 this->writes_accumulator
= false;
93 init(BRW_OPCODE_NOP
, 8, dst
, NULL
, 0);
96 fs_inst::fs_inst(enum opcode opcode
, uint8_t exec_size
)
98 init(opcode
, exec_size
, reg_undef
, NULL
, 0);
101 fs_inst::fs_inst(enum opcode opcode
, uint8_t exec_size
, const fs_reg
&dst
)
103 init(opcode
, exec_size
, dst
, NULL
, 0);
106 fs_inst::fs_inst(enum opcode opcode
, uint8_t exec_size
, const fs_reg
&dst
,
109 const fs_reg src
[1] = { src0
};
110 init(opcode
, exec_size
, dst
, src
, 1);
113 fs_inst::fs_inst(enum opcode opcode
, uint8_t exec_size
, const fs_reg
&dst
,
114 const fs_reg
&src0
, const fs_reg
&src1
)
116 const fs_reg src
[2] = { src0
, src1
};
117 init(opcode
, exec_size
, dst
, src
, 2);
120 fs_inst::fs_inst(enum opcode opcode
, uint8_t exec_size
, const fs_reg
&dst
,
121 const fs_reg
&src0
, const fs_reg
&src1
, const fs_reg
&src2
)
123 const fs_reg src
[3] = { src0
, src1
, src2
};
124 init(opcode
, exec_size
, dst
, src
, 3);
127 fs_inst::fs_inst(enum opcode opcode
, uint8_t exec_width
, const fs_reg
&dst
,
128 const fs_reg src
[], unsigned sources
)
130 init(opcode
, exec_width
, dst
, src
, sources
);
133 fs_inst::fs_inst(const fs_inst
&that
)
135 memcpy((void*)this, &that
, sizeof(that
));
137 this->src
= new fs_reg
[MAX2(that
.sources
, 3)];
139 for (unsigned i
= 0; i
< that
.sources
; i
++)
140 this->src
[i
] = that
.src
[i
];
149 fs_inst::resize_sources(uint8_t num_sources
)
151 if (this->sources
!= num_sources
) {
152 fs_reg
*src
= new fs_reg
[MAX2(num_sources
, 3)];
154 for (unsigned i
= 0; i
< MIN2(this->sources
, num_sources
); ++i
)
155 src
[i
] = this->src
[i
];
159 this->sources
= num_sources
;
164 fs_visitor::VARYING_PULL_CONSTANT_LOAD(const fs_builder
&bld
,
166 const fs_reg
&surf_index
,
167 const fs_reg
&varying_offset
,
168 uint32_t const_offset
)
170 /* We have our constant surface use a pitch of 4 bytes, so our index can
171 * be any component of a vector, and then we load 4 contiguous
172 * components starting from that.
174 * We break down the const_offset to a portion added to the variable offset
175 * and a portion done using fs_reg::offset, which means that if you have
176 * GLSL using something like "uniform vec4 a[20]; gl_FragColor = a[i]",
177 * we'll temporarily generate 4 vec4 loads from offset i * 4, and CSE can
178 * later notice that those loads are all the same and eliminate the
181 fs_reg vec4_offset
= vgrf(glsl_type::uint_type
);
182 bld
.ADD(vec4_offset
, varying_offset
, brw_imm_ud(const_offset
& ~0xf));
184 /* The pull load message will load a vec4 (16 bytes). If we are loading
185 * a double this means we are only loading 2 elements worth of data.
186 * We also want to use a 32-bit data type for the dst of the load operation
187 * so other parts of the driver don't get confused about the size of the
190 fs_reg vec4_result
= bld
.vgrf(BRW_REGISTER_TYPE_F
, 4);
191 fs_inst
*inst
= bld
.emit(FS_OPCODE_VARYING_PULL_CONSTANT_LOAD_LOGICAL
,
192 vec4_result
, surf_index
, vec4_offset
);
193 inst
->size_written
= 4 * vec4_result
.component_size(inst
->exec_size
);
195 shuffle_from_32bit_read(bld
, dst
, vec4_result
,
196 (const_offset
& 0xf) / type_sz(dst
.type
), 1);
200 * A helper for MOV generation for fixing up broken hardware SEND dependency
204 fs_visitor::DEP_RESOLVE_MOV(const fs_builder
&bld
, int grf
)
206 /* The caller always wants uncompressed to emit the minimal extra
207 * dependencies, and to avoid having to deal with aligning its regs to 2.
209 const fs_builder ubld
= bld
.annotate("send dependency resolve")
212 ubld
.MOV(ubld
.null_reg_f(), fs_reg(VGRF
, grf
, BRW_REGISTER_TYPE_F
));
216 fs_inst::is_send_from_grf() const
219 case SHADER_OPCODE_SEND
:
220 case SHADER_OPCODE_SHADER_TIME_ADD
:
221 case FS_OPCODE_INTERPOLATE_AT_SAMPLE
:
222 case FS_OPCODE_INTERPOLATE_AT_SHARED_OFFSET
:
223 case FS_OPCODE_INTERPOLATE_AT_PER_SLOT_OFFSET
:
224 case SHADER_OPCODE_URB_WRITE_SIMD8
:
225 case SHADER_OPCODE_URB_WRITE_SIMD8_PER_SLOT
:
226 case SHADER_OPCODE_URB_WRITE_SIMD8_MASKED
:
227 case SHADER_OPCODE_URB_WRITE_SIMD8_MASKED_PER_SLOT
:
228 case SHADER_OPCODE_URB_READ_SIMD8
:
229 case SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT
:
230 case SHADER_OPCODE_INTERLOCK
:
231 case SHADER_OPCODE_MEMORY_FENCE
:
232 case SHADER_OPCODE_BARRIER
:
234 case FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD
:
235 return src
[1].file
== VGRF
;
236 case FS_OPCODE_FB_WRITE
:
237 case FS_OPCODE_FB_READ
:
238 return src
[0].file
== VGRF
;
241 return src
[0].file
== VGRF
;
248 fs_inst::is_control_source(unsigned arg
) const
251 case FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD
:
252 case FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD_GEN7
:
253 case FS_OPCODE_VARYING_PULL_CONSTANT_LOAD_GEN4
:
256 case SHADER_OPCODE_BROADCAST
:
257 case SHADER_OPCODE_SHUFFLE
:
258 case SHADER_OPCODE_QUAD_SWIZZLE
:
259 case FS_OPCODE_INTERPOLATE_AT_SAMPLE
:
260 case FS_OPCODE_INTERPOLATE_AT_SHARED_OFFSET
:
261 case FS_OPCODE_INTERPOLATE_AT_PER_SLOT_OFFSET
:
262 case SHADER_OPCODE_GET_BUFFER_SIZE
:
265 case SHADER_OPCODE_MOV_INDIRECT
:
266 case SHADER_OPCODE_CLUSTER_BROADCAST
:
267 case SHADER_OPCODE_TEX
:
269 case SHADER_OPCODE_TXD
:
270 case SHADER_OPCODE_TXF
:
271 case SHADER_OPCODE_TXF_LZ
:
272 case SHADER_OPCODE_TXF_CMS
:
273 case SHADER_OPCODE_TXF_CMS_W
:
274 case SHADER_OPCODE_TXF_UMS
:
275 case SHADER_OPCODE_TXF_MCS
:
276 case SHADER_OPCODE_TXL
:
277 case SHADER_OPCODE_TXL_LZ
:
278 case SHADER_OPCODE_TXS
:
279 case SHADER_OPCODE_LOD
:
280 case SHADER_OPCODE_TG4
:
281 case SHADER_OPCODE_TG4_OFFSET
:
282 case SHADER_OPCODE_SAMPLEINFO
:
283 return arg
== 1 || arg
== 2;
285 case SHADER_OPCODE_SEND
:
286 return arg
== 0 || arg
== 1;
294 fs_inst::is_payload(unsigned arg
) const
297 case FS_OPCODE_FB_WRITE
:
298 case FS_OPCODE_FB_READ
:
299 case SHADER_OPCODE_URB_WRITE_SIMD8
:
300 case SHADER_OPCODE_URB_WRITE_SIMD8_PER_SLOT
:
301 case SHADER_OPCODE_URB_WRITE_SIMD8_MASKED
:
302 case SHADER_OPCODE_URB_WRITE_SIMD8_MASKED_PER_SLOT
:
303 case SHADER_OPCODE_URB_READ_SIMD8
:
304 case SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT
:
305 case VEC4_OPCODE_UNTYPED_ATOMIC
:
306 case VEC4_OPCODE_UNTYPED_SURFACE_READ
:
307 case VEC4_OPCODE_UNTYPED_SURFACE_WRITE
:
308 case FS_OPCODE_INTERPOLATE_AT_PER_SLOT_OFFSET
:
309 case SHADER_OPCODE_SHADER_TIME_ADD
:
310 case FS_OPCODE_INTERPOLATE_AT_SAMPLE
:
311 case FS_OPCODE_INTERPOLATE_AT_SHARED_OFFSET
:
312 case SHADER_OPCODE_INTERLOCK
:
313 case SHADER_OPCODE_MEMORY_FENCE
:
314 case SHADER_OPCODE_BARRIER
:
317 case FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD_GEN7
:
320 case SHADER_OPCODE_SEND
:
321 return arg
== 2 || arg
== 3;
332 * Returns true if this instruction's sources and destinations cannot
333 * safely be the same register.
335 * In most cases, a register can be written over safely by the same
336 * instruction that is its last use. For a single instruction, the
337 * sources are dereferenced before writing of the destination starts
340 * However, there are a few cases where this can be problematic:
342 * - Virtual opcodes that translate to multiple instructions in the
343 * code generator: if src == dst and one instruction writes the
344 * destination before a later instruction reads the source, then
345 * src will have been clobbered.
347 * - SIMD16 compressed instructions with certain regioning (see below).
349 * The register allocator uses this information to set up conflicts between
350 * GRF sources and the destination.
353 fs_inst::has_source_and_destination_hazard() const
356 case FS_OPCODE_PACK_HALF_2x16_SPLIT
:
357 /* Multiple partial writes to the destination */
359 case SHADER_OPCODE_SHUFFLE
:
360 /* This instruction returns an arbitrary channel from the source and
361 * gets split into smaller instructions in the generator. It's possible
362 * that one of the instructions will read from a channel corresponding
363 * to an earlier instruction.
365 case SHADER_OPCODE_SEL_EXEC
:
366 /* This is implemented as
368 * mov(16) g4<1>D 0D { align1 WE_all 1H };
369 * mov(16) g4<1>D g5<8,8,1>D { align1 1H }
371 * Because the source is only read in the second instruction, the first
372 * may stomp all over it.
375 case SHADER_OPCODE_QUAD_SWIZZLE
:
377 case BRW_SWIZZLE_XXXX
:
378 case BRW_SWIZZLE_YYYY
:
379 case BRW_SWIZZLE_ZZZZ
:
380 case BRW_SWIZZLE_WWWW
:
381 case BRW_SWIZZLE_XXZZ
:
382 case BRW_SWIZZLE_YYWW
:
383 case BRW_SWIZZLE_XYXY
:
384 case BRW_SWIZZLE_ZWZW
:
385 /* These can be implemented as a single Align1 region on all
386 * platforms, so there's never a hazard between source and
387 * destination. C.f. fs_generator::generate_quad_swizzle().
391 return !is_uniform(src
[0]);
394 /* The SIMD16 compressed instruction
396 * add(16) g4<1>F g4<8,8,1>F g6<8,8,1>F
398 * is actually decoded in hardware as:
400 * add(8) g4<1>F g4<8,8,1>F g6<8,8,1>F
401 * add(8) g5<1>F g5<8,8,1>F g7<8,8,1>F
403 * Which is safe. However, if we have uniform accesses
404 * happening, we get into trouble:
406 * add(8) g4<1>F g4<0,1,0>F g6<8,8,1>F
407 * add(8) g5<1>F g4<0,1,0>F g7<8,8,1>F
409 * Now our destination for the first instruction overwrote the
410 * second instruction's src0, and we get garbage for those 8
411 * pixels. There's a similar issue for the pre-gen6
412 * pixel_x/pixel_y, which are registers of 16-bit values and thus
413 * would get stomped by the first decode as well.
415 if (exec_size
== 16) {
416 for (int i
= 0; i
< sources
; i
++) {
417 if (src
[i
].file
== VGRF
&& (src
[i
].stride
== 0 ||
418 src
[i
].type
== BRW_REGISTER_TYPE_UW
||
419 src
[i
].type
== BRW_REGISTER_TYPE_W
||
420 src
[i
].type
== BRW_REGISTER_TYPE_UB
||
421 src
[i
].type
== BRW_REGISTER_TYPE_B
)) {
431 fs_inst::is_copy_payload(const brw::simple_allocator
&grf_alloc
) const
433 if (this->opcode
!= SHADER_OPCODE_LOAD_PAYLOAD
)
436 fs_reg reg
= this->src
[0];
437 if (reg
.file
!= VGRF
|| reg
.offset
!= 0 || reg
.stride
!= 1)
440 if (grf_alloc
.sizes
[reg
.nr
] * REG_SIZE
!= this->size_written
)
443 for (int i
= 0; i
< this->sources
; i
++) {
444 reg
.type
= this->src
[i
].type
;
445 if (!this->src
[i
].equals(reg
))
448 if (i
< this->header_size
) {
449 reg
.offset
+= REG_SIZE
;
451 reg
= horiz_offset(reg
, this->exec_size
);
459 fs_inst::can_do_source_mods(const struct gen_device_info
*devinfo
) const
461 if (devinfo
->gen
== 6 && is_math())
464 if (is_send_from_grf())
467 /* From GEN:BUG:1604601757:
469 * "When multiplying a DW and any lower precision integer, source modifier
472 if (devinfo
->gen
>= 12 && (opcode
== BRW_OPCODE_MUL
||
473 opcode
== BRW_OPCODE_MAD
)) {
474 const brw_reg_type exec_type
= get_exec_type(this);
475 const unsigned min_type_sz
= opcode
== BRW_OPCODE_MAD
?
476 MIN2(type_sz(src
[1].type
), type_sz(src
[2].type
)) :
477 MIN2(type_sz(src
[0].type
), type_sz(src
[1].type
));
479 if (brw_reg_type_is_integer(exec_type
) &&
480 type_sz(exec_type
) >= 4 &&
481 type_sz(exec_type
) != min_type_sz
)
485 if (!backend_instruction::can_do_source_mods())
492 fs_inst::can_do_cmod()
494 if (!backend_instruction::can_do_cmod())
497 /* The accumulator result appears to get used for the conditional modifier
498 * generation. When negating a UD value, there is a 33rd bit generated for
499 * the sign in the accumulator value, so now you can't check, for example,
500 * equality with a 32-bit value. See piglit fs-op-neg-uvec4.
502 for (unsigned i
= 0; i
< sources
; i
++) {
503 if (type_is_unsigned_int(src
[i
].type
) && src
[i
].negate
)
511 fs_inst::can_change_types() const
513 return dst
.type
== src
[0].type
&&
514 !src
[0].abs
&& !src
[0].negate
&& !saturate
&&
515 (opcode
== BRW_OPCODE_MOV
||
516 (opcode
== BRW_OPCODE_SEL
&&
517 dst
.type
== src
[1].type
&&
518 predicate
!= BRW_PREDICATE_NONE
&&
519 !src
[1].abs
&& !src
[1].negate
));
525 memset((void*)this, 0, sizeof(*this));
526 type
= BRW_REGISTER_TYPE_UD
;
530 /** Generic unset register constructor. */
534 this->file
= BAD_FILE
;
537 fs_reg::fs_reg(struct ::brw_reg reg
) :
542 if (this->file
== IMM
&&
543 (this->type
!= BRW_REGISTER_TYPE_V
&&
544 this->type
!= BRW_REGISTER_TYPE_UV
&&
545 this->type
!= BRW_REGISTER_TYPE_VF
)) {
551 fs_reg::equals(const fs_reg
&r
) const
553 return (this->backend_reg::equals(r
) &&
558 fs_reg::negative_equals(const fs_reg
&r
) const
560 return (this->backend_reg::negative_equals(r
) &&
565 fs_reg::is_contiguous() const
571 fs_reg::component_size(unsigned width
) const
573 const unsigned stride
= ((file
!= ARF
&& file
!= FIXED_GRF
) ? this->stride
:
576 return MAX2(width
* stride
, 1) * type_sz(type
);
580 type_size_scalar(const struct glsl_type
*type
, bool bindless
)
582 unsigned int size
, i
;
584 switch (type
->base_type
) {
587 case GLSL_TYPE_FLOAT
:
589 return type
->components();
590 case GLSL_TYPE_UINT16
:
591 case GLSL_TYPE_INT16
:
592 case GLSL_TYPE_FLOAT16
:
593 return DIV_ROUND_UP(type
->components(), 2);
594 case GLSL_TYPE_UINT8
:
596 return DIV_ROUND_UP(type
->components(), 4);
597 case GLSL_TYPE_DOUBLE
:
598 case GLSL_TYPE_UINT64
:
599 case GLSL_TYPE_INT64
:
600 return type
->components() * 2;
601 case GLSL_TYPE_ARRAY
:
602 return type_size_scalar(type
->fields
.array
, bindless
) * type
->length
;
603 case GLSL_TYPE_STRUCT
:
604 case GLSL_TYPE_INTERFACE
:
606 for (i
= 0; i
< type
->length
; i
++) {
607 size
+= type_size_scalar(type
->fields
.structure
[i
].type
, bindless
);
610 case GLSL_TYPE_SAMPLER
:
611 case GLSL_TYPE_IMAGE
:
613 return type
->components() * 2;
614 case GLSL_TYPE_ATOMIC_UINT
:
615 /* Samplers, atomics, and images take up no register space, since
616 * they're baked in at link time.
619 case GLSL_TYPE_SUBROUTINE
:
622 case GLSL_TYPE_ERROR
:
623 case GLSL_TYPE_FUNCTION
:
624 unreachable("not reached");
631 * Create a MOV to read the timestamp register.
633 * The caller is responsible for emitting the MOV. The return value is
634 * the destination of the MOV, with extra parameters set.
637 fs_visitor::get_timestamp(const fs_builder
&bld
)
639 assert(devinfo
->gen
>= 7);
641 fs_reg ts
= fs_reg(retype(brw_vec4_reg(BRW_ARCHITECTURE_REGISTER_FILE
,
644 BRW_REGISTER_TYPE_UD
));
646 fs_reg dst
= fs_reg(VGRF
, alloc
.allocate(1), BRW_REGISTER_TYPE_UD
);
648 /* We want to read the 3 fields we care about even if it's not enabled in
651 bld
.group(4, 0).exec_all().MOV(dst
, ts
);
657 fs_visitor::emit_shader_time_begin()
659 /* We want only the low 32 bits of the timestamp. Since it's running
660 * at the GPU clock rate of ~1.2ghz, it will roll over every ~3 seconds,
661 * which is plenty of time for our purposes. It is identical across the
662 * EUs, but since it's tracking GPU core speed it will increment at a
663 * varying rate as render P-states change.
665 shader_start_time
= component(
666 get_timestamp(bld
.annotate("shader time start")), 0);
670 fs_visitor::emit_shader_time_end()
672 /* Insert our code just before the final SEND with EOT. */
673 exec_node
*end
= this->instructions
.get_tail();
674 assert(end
&& ((fs_inst
*) end
)->eot
);
675 const fs_builder ibld
= bld
.annotate("shader time end")
676 .exec_all().at(NULL
, end
);
677 const fs_reg timestamp
= get_timestamp(ibld
);
679 /* We only use the low 32 bits of the timestamp - see
680 * emit_shader_time_begin()).
682 * We could also check if render P-states have changed (or anything
683 * else that might disrupt timing) by setting smear to 2 and checking if
684 * that field is != 0.
686 const fs_reg shader_end_time
= component(timestamp
, 0);
688 /* Check that there weren't any timestamp reset events (assuming these
689 * were the only two timestamp reads that happened).
691 const fs_reg reset
= component(timestamp
, 2);
692 set_condmod(BRW_CONDITIONAL_Z
,
693 ibld
.AND(ibld
.null_reg_ud(), reset
, brw_imm_ud(1u)));
694 ibld
.IF(BRW_PREDICATE_NORMAL
);
696 fs_reg start
= shader_start_time
;
698 const fs_reg diff
= component(fs_reg(VGRF
, alloc
.allocate(1),
699 BRW_REGISTER_TYPE_UD
),
701 const fs_builder cbld
= ibld
.group(1, 0);
702 cbld
.group(1, 0).ADD(diff
, start
, shader_end_time
);
704 /* If there were no instructions between the two timestamp gets, the diff
705 * is 2 cycles. Remove that overhead, so I can forget about that when
706 * trying to determine the time taken for single instructions.
708 cbld
.ADD(diff
, diff
, brw_imm_ud(-2u));
709 SHADER_TIME_ADD(cbld
, 0, diff
);
710 SHADER_TIME_ADD(cbld
, 1, brw_imm_ud(1u));
711 ibld
.emit(BRW_OPCODE_ELSE
);
712 SHADER_TIME_ADD(cbld
, 2, brw_imm_ud(1u));
713 ibld
.emit(BRW_OPCODE_ENDIF
);
717 fs_visitor::SHADER_TIME_ADD(const fs_builder
&bld
,
718 int shader_time_subindex
,
721 int index
= shader_time_index
* 3 + shader_time_subindex
;
722 struct brw_reg offset
= brw_imm_d(index
* BRW_SHADER_TIME_STRIDE
);
725 if (dispatch_width
== 8)
726 payload
= vgrf(glsl_type::uvec2_type
);
728 payload
= vgrf(glsl_type::uint_type
);
730 bld
.emit(SHADER_OPCODE_SHADER_TIME_ADD
, fs_reg(), payload
, offset
, value
);
734 fs_visitor::vfail(const char *format
, va_list va
)
743 msg
= ralloc_vasprintf(mem_ctx
, format
, va
);
744 msg
= ralloc_asprintf(mem_ctx
, "%s compile failed: %s\n", stage_abbrev
, msg
);
746 this->fail_msg
= msg
;
749 fprintf(stderr
, "%s", msg
);
754 fs_visitor::fail(const char *format
, ...)
758 va_start(va
, format
);
764 * Mark this program as impossible to compile with dispatch width greater
767 * During the SIMD8 compile (which happens first), we can detect and flag
768 * things that are unsupported in SIMD16+ mode, so the compiler can skip the
769 * SIMD16+ compile altogether.
771 * During a compile of dispatch width greater than n (if one happens anyway),
772 * this just calls fail().
775 fs_visitor::limit_dispatch_width(unsigned n
, const char *msg
)
777 if (dispatch_width
> n
) {
780 max_dispatch_width
= n
;
781 compiler
->shader_perf_log(log_data
,
782 "Shader dispatch width limited to SIMD%d: %s",
788 * Returns true if the instruction has a flag that means it won't
789 * update an entire destination register.
791 * For example, dead code elimination and live variable analysis want to know
792 * when a write to a variable screens off any preceding values that were in
796 fs_inst::is_partial_write() const
798 return ((this->predicate
&& this->opcode
!= BRW_OPCODE_SEL
) ||
799 (this->exec_size
* type_sz(this->dst
.type
)) < 32 ||
800 !this->dst
.is_contiguous() ||
801 this->dst
.offset
% REG_SIZE
!= 0);
805 fs_inst::components_read(unsigned i
) const
807 /* Return zero if the source is not present. */
808 if (src
[i
].file
== BAD_FILE
)
812 case FS_OPCODE_LINTERP
:
818 case FS_OPCODE_PIXEL_X
:
819 case FS_OPCODE_PIXEL_Y
:
823 case FS_OPCODE_FB_WRITE_LOGICAL
:
824 assert(src
[FB_WRITE_LOGICAL_SRC_COMPONENTS
].file
== IMM
);
825 /* First/second FB write color. */
827 return src
[FB_WRITE_LOGICAL_SRC_COMPONENTS
].ud
;
831 case SHADER_OPCODE_TEX_LOGICAL
:
832 case SHADER_OPCODE_TXD_LOGICAL
:
833 case SHADER_OPCODE_TXF_LOGICAL
:
834 case SHADER_OPCODE_TXL_LOGICAL
:
835 case SHADER_OPCODE_TXS_LOGICAL
:
836 case SHADER_OPCODE_IMAGE_SIZE_LOGICAL
:
837 case FS_OPCODE_TXB_LOGICAL
:
838 case SHADER_OPCODE_TXF_CMS_LOGICAL
:
839 case SHADER_OPCODE_TXF_CMS_W_LOGICAL
:
840 case SHADER_OPCODE_TXF_UMS_LOGICAL
:
841 case SHADER_OPCODE_TXF_MCS_LOGICAL
:
842 case SHADER_OPCODE_LOD_LOGICAL
:
843 case SHADER_OPCODE_TG4_LOGICAL
:
844 case SHADER_OPCODE_TG4_OFFSET_LOGICAL
:
845 case SHADER_OPCODE_SAMPLEINFO_LOGICAL
:
846 assert(src
[TEX_LOGICAL_SRC_COORD_COMPONENTS
].file
== IMM
&&
847 src
[TEX_LOGICAL_SRC_GRAD_COMPONENTS
].file
== IMM
);
848 /* Texture coordinates. */
849 if (i
== TEX_LOGICAL_SRC_COORDINATE
)
850 return src
[TEX_LOGICAL_SRC_COORD_COMPONENTS
].ud
;
851 /* Texture derivatives. */
852 else if ((i
== TEX_LOGICAL_SRC_LOD
|| i
== TEX_LOGICAL_SRC_LOD2
) &&
853 opcode
== SHADER_OPCODE_TXD_LOGICAL
)
854 return src
[TEX_LOGICAL_SRC_GRAD_COMPONENTS
].ud
;
855 /* Texture offset. */
856 else if (i
== TEX_LOGICAL_SRC_TG4_OFFSET
)
859 else if (i
== TEX_LOGICAL_SRC_MCS
&& opcode
== SHADER_OPCODE_TXF_CMS_W_LOGICAL
)
864 case SHADER_OPCODE_UNTYPED_SURFACE_READ_LOGICAL
:
865 case SHADER_OPCODE_TYPED_SURFACE_READ_LOGICAL
:
866 assert(src
[SURFACE_LOGICAL_SRC_IMM_DIMS
].file
== IMM
);
867 /* Surface coordinates. */
868 if (i
== SURFACE_LOGICAL_SRC_ADDRESS
)
869 return src
[SURFACE_LOGICAL_SRC_IMM_DIMS
].ud
;
870 /* Surface operation source (ignored for reads). */
871 else if (i
== SURFACE_LOGICAL_SRC_DATA
)
876 case SHADER_OPCODE_UNTYPED_SURFACE_WRITE_LOGICAL
:
877 case SHADER_OPCODE_TYPED_SURFACE_WRITE_LOGICAL
:
878 assert(src
[SURFACE_LOGICAL_SRC_IMM_DIMS
].file
== IMM
&&
879 src
[SURFACE_LOGICAL_SRC_IMM_ARG
].file
== IMM
);
880 /* Surface coordinates. */
881 if (i
== SURFACE_LOGICAL_SRC_ADDRESS
)
882 return src
[SURFACE_LOGICAL_SRC_IMM_DIMS
].ud
;
883 /* Surface operation source. */
884 else if (i
== SURFACE_LOGICAL_SRC_DATA
)
885 return src
[SURFACE_LOGICAL_SRC_IMM_ARG
].ud
;
889 case SHADER_OPCODE_A64_UNTYPED_READ_LOGICAL
:
890 assert(src
[2].file
== IMM
);
893 case SHADER_OPCODE_A64_UNTYPED_WRITE_LOGICAL
:
894 assert(src
[2].file
== IMM
);
895 return i
== 1 ? src
[2].ud
: 1;
897 case SHADER_OPCODE_A64_UNTYPED_ATOMIC_LOGICAL
:
898 case SHADER_OPCODE_A64_UNTYPED_ATOMIC_INT64_LOGICAL
:
899 assert(src
[2].file
== IMM
);
902 const unsigned op
= src
[2].ud
;
917 case SHADER_OPCODE_A64_UNTYPED_ATOMIC_FLOAT_LOGICAL
:
918 assert(src
[2].file
== IMM
);
921 const unsigned op
= src
[2].ud
;
922 return op
== BRW_AOP_FCMPWR
? 2 : 1;
927 case SHADER_OPCODE_BYTE_SCATTERED_READ_LOGICAL
:
928 case SHADER_OPCODE_DWORD_SCATTERED_READ_LOGICAL
:
929 /* Scattered logical opcodes use the following params:
930 * src[0] Surface coordinates
931 * src[1] Surface operation source (ignored for reads)
933 * src[3] IMM with always 1 dimension.
934 * src[4] IMM with arg bitsize for scattered read/write 8, 16, 32
936 assert(src
[SURFACE_LOGICAL_SRC_IMM_DIMS
].file
== IMM
&&
937 src
[SURFACE_LOGICAL_SRC_IMM_ARG
].file
== IMM
);
938 return i
== SURFACE_LOGICAL_SRC_DATA
? 0 : 1;
940 case SHADER_OPCODE_BYTE_SCATTERED_WRITE_LOGICAL
:
941 case SHADER_OPCODE_DWORD_SCATTERED_WRITE_LOGICAL
:
942 assert(src
[SURFACE_LOGICAL_SRC_IMM_DIMS
].file
== IMM
&&
943 src
[SURFACE_LOGICAL_SRC_IMM_ARG
].file
== IMM
);
946 case SHADER_OPCODE_UNTYPED_ATOMIC_LOGICAL
:
947 case SHADER_OPCODE_TYPED_ATOMIC_LOGICAL
: {
948 assert(src
[SURFACE_LOGICAL_SRC_IMM_DIMS
].file
== IMM
&&
949 src
[SURFACE_LOGICAL_SRC_IMM_ARG
].file
== IMM
);
950 const unsigned op
= src
[SURFACE_LOGICAL_SRC_IMM_ARG
].ud
;
951 /* Surface coordinates. */
952 if (i
== SURFACE_LOGICAL_SRC_ADDRESS
)
953 return src
[SURFACE_LOGICAL_SRC_IMM_DIMS
].ud
;
954 /* Surface operation source. */
955 else if (i
== SURFACE_LOGICAL_SRC_DATA
&& op
== BRW_AOP_CMPWR
)
957 else if (i
== SURFACE_LOGICAL_SRC_DATA
&&
958 (op
== BRW_AOP_INC
|| op
== BRW_AOP_DEC
|| op
== BRW_AOP_PREDEC
))
963 case FS_OPCODE_INTERPOLATE_AT_PER_SLOT_OFFSET
:
964 return (i
== 0 ? 2 : 1);
966 case SHADER_OPCODE_UNTYPED_ATOMIC_FLOAT_LOGICAL
: {
967 assert(src
[SURFACE_LOGICAL_SRC_IMM_DIMS
].file
== IMM
&&
968 src
[SURFACE_LOGICAL_SRC_IMM_ARG
].file
== IMM
);
969 const unsigned op
= src
[SURFACE_LOGICAL_SRC_IMM_ARG
].ud
;
970 /* Surface coordinates. */
971 if (i
== SURFACE_LOGICAL_SRC_ADDRESS
)
972 return src
[SURFACE_LOGICAL_SRC_IMM_DIMS
].ud
;
973 /* Surface operation source. */
974 else if (i
== SURFACE_LOGICAL_SRC_DATA
&& op
== BRW_AOP_FCMPWR
)
986 fs_inst::size_read(int arg
) const
989 case SHADER_OPCODE_SEND
:
991 return mlen
* REG_SIZE
;
992 } else if (arg
== 3) {
993 return ex_mlen
* REG_SIZE
;
997 case FS_OPCODE_FB_WRITE
:
998 case FS_OPCODE_REP_FB_WRITE
:
1001 return src
[0].file
== BAD_FILE
? 0 : 2 * REG_SIZE
;
1003 return mlen
* REG_SIZE
;
1007 case FS_OPCODE_FB_READ
:
1008 case SHADER_OPCODE_URB_WRITE_SIMD8
:
1009 case SHADER_OPCODE_URB_WRITE_SIMD8_PER_SLOT
:
1010 case SHADER_OPCODE_URB_WRITE_SIMD8_MASKED
:
1011 case SHADER_OPCODE_URB_WRITE_SIMD8_MASKED_PER_SLOT
:
1012 case SHADER_OPCODE_URB_READ_SIMD8
:
1013 case SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT
:
1014 case FS_OPCODE_INTERPOLATE_AT_SAMPLE
:
1015 case FS_OPCODE_INTERPOLATE_AT_SHARED_OFFSET
:
1017 return mlen
* REG_SIZE
;
1020 case FS_OPCODE_SET_SAMPLE_ID
:
1025 case FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD_GEN7
:
1026 /* The payload is actually stored in src1 */
1028 return mlen
* REG_SIZE
;
1031 case FS_OPCODE_LINTERP
:
1036 case SHADER_OPCODE_LOAD_PAYLOAD
:
1037 if (arg
< this->header_size
)
1041 case CS_OPCODE_CS_TERMINATE
:
1042 case SHADER_OPCODE_BARRIER
:
1045 case SHADER_OPCODE_MOV_INDIRECT
:
1047 assert(src
[2].file
== IMM
);
1053 if (is_tex() && arg
== 0 && src
[0].file
== VGRF
)
1054 return mlen
* REG_SIZE
;
1058 switch (src
[arg
].file
) {
1061 return components_read(arg
) * type_sz(src
[arg
].type
);
1067 return components_read(arg
) * src
[arg
].component_size(exec_size
);
1069 unreachable("MRF registers are not allowed as sources");
1076 predicate_width(brw_predicate predicate
)
1078 switch (predicate
) {
1079 case BRW_PREDICATE_NONE
: return 1;
1080 case BRW_PREDICATE_NORMAL
: return 1;
1081 case BRW_PREDICATE_ALIGN1_ANY2H
: return 2;
1082 case BRW_PREDICATE_ALIGN1_ALL2H
: return 2;
1083 case BRW_PREDICATE_ALIGN1_ANY4H
: return 4;
1084 case BRW_PREDICATE_ALIGN1_ALL4H
: return 4;
1085 case BRW_PREDICATE_ALIGN1_ANY8H
: return 8;
1086 case BRW_PREDICATE_ALIGN1_ALL8H
: return 8;
1087 case BRW_PREDICATE_ALIGN1_ANY16H
: return 16;
1088 case BRW_PREDICATE_ALIGN1_ALL16H
: return 16;
1089 case BRW_PREDICATE_ALIGN1_ANY32H
: return 32;
1090 case BRW_PREDICATE_ALIGN1_ALL32H
: return 32;
1091 default: unreachable("Unsupported predicate");
1095 /* Return the subset of flag registers that an instruction could
1096 * potentially read or write based on the execution controls and flag
1097 * subregister number of the instruction.
1100 flag_mask(const fs_inst
*inst
, unsigned width
)
1102 assert(util_is_power_of_two_nonzero(width
));
1103 const unsigned start
= (inst
->flag_subreg
* 16 + inst
->group
) &
1105 const unsigned end
= start
+ ALIGN(inst
->exec_size
, width
);
1106 return ((1 << DIV_ROUND_UP(end
, 8)) - 1) & ~((1 << (start
/ 8)) - 1);
1110 bit_mask(unsigned n
)
1112 return (n
>= CHAR_BIT
* sizeof(bit_mask(n
)) ? ~0u : (1u << n
) - 1);
1116 flag_mask(const fs_reg
&r
, unsigned sz
)
1118 if (r
.file
== ARF
) {
1119 const unsigned start
= (r
.nr
- BRW_ARF_FLAG
) * 4 + r
.subnr
;
1120 const unsigned end
= start
+ sz
;
1121 return bit_mask(end
) & ~bit_mask(start
);
1129 fs_inst::flags_read(const gen_device_info
*devinfo
) const
1131 if (predicate
== BRW_PREDICATE_ALIGN1_ANYV
||
1132 predicate
== BRW_PREDICATE_ALIGN1_ALLV
) {
1133 /* The vertical predication modes combine corresponding bits from
1134 * f0.0 and f1.0 on Gen7+, and f0.0 and f0.1 on older hardware.
1136 const unsigned shift
= devinfo
->gen
>= 7 ? 4 : 2;
1137 return flag_mask(this, 1) << shift
| flag_mask(this, 1);
1138 } else if (predicate
) {
1139 return flag_mask(this, predicate_width(predicate
));
1142 for (int i
= 0; i
< sources
; i
++) {
1143 mask
|= flag_mask(src
[i
], size_read(i
));
1150 fs_inst::flags_written() const
1152 if ((conditional_mod
&& (opcode
!= BRW_OPCODE_SEL
&&
1153 opcode
!= BRW_OPCODE_CSEL
&&
1154 opcode
!= BRW_OPCODE_IF
&&
1155 opcode
!= BRW_OPCODE_WHILE
)) ||
1156 opcode
== SHADER_OPCODE_FIND_LIVE_CHANNEL
||
1157 opcode
== FS_OPCODE_FB_WRITE
) {
1158 return flag_mask(this, 1);
1160 return flag_mask(dst
, size_written
);
1165 * Returns how many MRFs an FS opcode will write over.
1167 * Note that this is not the 0 or 1 implied writes in an actual gen
1168 * instruction -- the FS opcodes often generate MOVs in addition.
1171 fs_visitor::implied_mrf_writes(const fs_inst
*inst
) const
1173 if (inst
->mlen
== 0)
1176 if (inst
->base_mrf
== -1)
1179 switch (inst
->opcode
) {
1180 case SHADER_OPCODE_RCP
:
1181 case SHADER_OPCODE_RSQ
:
1182 case SHADER_OPCODE_SQRT
:
1183 case SHADER_OPCODE_EXP2
:
1184 case SHADER_OPCODE_LOG2
:
1185 case SHADER_OPCODE_SIN
:
1186 case SHADER_OPCODE_COS
:
1187 return 1 * dispatch_width
/ 8;
1188 case SHADER_OPCODE_POW
:
1189 case SHADER_OPCODE_INT_QUOTIENT
:
1190 case SHADER_OPCODE_INT_REMAINDER
:
1191 return 2 * dispatch_width
/ 8;
1192 case SHADER_OPCODE_TEX
:
1194 case SHADER_OPCODE_TXD
:
1195 case SHADER_OPCODE_TXF
:
1196 case SHADER_OPCODE_TXF_CMS
:
1197 case SHADER_OPCODE_TXF_MCS
:
1198 case SHADER_OPCODE_TG4
:
1199 case SHADER_OPCODE_TG4_OFFSET
:
1200 case SHADER_OPCODE_TXL
:
1201 case SHADER_OPCODE_TXS
:
1202 case SHADER_OPCODE_LOD
:
1203 case SHADER_OPCODE_SAMPLEINFO
:
1205 case FS_OPCODE_FB_WRITE
:
1206 case FS_OPCODE_REP_FB_WRITE
:
1207 return inst
->src
[0].file
== BAD_FILE
? 0 : 2;
1208 case FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD
:
1209 case SHADER_OPCODE_GEN4_SCRATCH_READ
:
1211 case FS_OPCODE_VARYING_PULL_CONSTANT_LOAD_GEN4
:
1213 case SHADER_OPCODE_GEN4_SCRATCH_WRITE
:
1216 unreachable("not reached");
1221 fs_visitor::vgrf(const glsl_type
*const type
)
1223 int reg_width
= dispatch_width
/ 8;
1225 alloc
.allocate(type_size_scalar(type
, false) * reg_width
),
1226 brw_type_for_base_type(type
));
1229 fs_reg::fs_reg(enum brw_reg_file file
, int nr
)
1234 this->type
= BRW_REGISTER_TYPE_F
;
1235 this->stride
= (file
== UNIFORM
? 0 : 1);
1238 fs_reg::fs_reg(enum brw_reg_file file
, int nr
, enum brw_reg_type type
)
1244 this->stride
= (file
== UNIFORM
? 0 : 1);
1247 /* For SIMD16, we need to follow from the uniform setup of SIMD8 dispatch.
1248 * This brings in those uniform definitions
1251 fs_visitor::import_uniforms(fs_visitor
*v
)
1253 this->push_constant_loc
= v
->push_constant_loc
;
1254 this->pull_constant_loc
= v
->pull_constant_loc
;
1255 this->uniforms
= v
->uniforms
;
1256 this->subgroup_id
= v
->subgroup_id
;
1260 fs_visitor::emit_fragcoord_interpolation(fs_reg wpos
)
1262 assert(stage
== MESA_SHADER_FRAGMENT
);
1264 /* gl_FragCoord.x */
1265 bld
.MOV(wpos
, this->pixel_x
);
1266 wpos
= offset(wpos
, bld
, 1);
1268 /* gl_FragCoord.y */
1269 bld
.MOV(wpos
, this->pixel_y
);
1270 wpos
= offset(wpos
, bld
, 1);
1272 /* gl_FragCoord.z */
1273 if (devinfo
->gen
>= 6) {
1274 bld
.MOV(wpos
, fetch_payload_reg(bld
, payload
.source_depth_reg
));
1276 bld
.emit(FS_OPCODE_LINTERP
, wpos
,
1277 this->delta_xy
[BRW_BARYCENTRIC_PERSPECTIVE_PIXEL
],
1278 component(interp_reg(VARYING_SLOT_POS
, 2), 0));
1280 wpos
= offset(wpos
, bld
, 1);
1282 /* gl_FragCoord.w: Already set up in emit_interpolation */
1283 bld
.MOV(wpos
, this->wpos_w
);
1286 enum brw_barycentric_mode
1287 brw_barycentric_mode(enum glsl_interp_mode mode
, nir_intrinsic_op op
)
1289 /* Barycentric modes don't make sense for flat inputs. */
1290 assert(mode
!= INTERP_MODE_FLAT
);
1294 case nir_intrinsic_load_barycentric_pixel
:
1295 case nir_intrinsic_load_barycentric_at_offset
:
1296 bary
= BRW_BARYCENTRIC_PERSPECTIVE_PIXEL
;
1298 case nir_intrinsic_load_barycentric_centroid
:
1299 bary
= BRW_BARYCENTRIC_PERSPECTIVE_CENTROID
;
1301 case nir_intrinsic_load_barycentric_sample
:
1302 case nir_intrinsic_load_barycentric_at_sample
:
1303 bary
= BRW_BARYCENTRIC_PERSPECTIVE_SAMPLE
;
1306 unreachable("invalid intrinsic");
1309 if (mode
== INTERP_MODE_NOPERSPECTIVE
)
1312 return (enum brw_barycentric_mode
) bary
;
1316 * Turn one of the two CENTROID barycentric modes into PIXEL mode.
1318 static enum brw_barycentric_mode
1319 centroid_to_pixel(enum brw_barycentric_mode bary
)
1321 assert(bary
== BRW_BARYCENTRIC_PERSPECTIVE_CENTROID
||
1322 bary
== BRW_BARYCENTRIC_NONPERSPECTIVE_CENTROID
);
1323 return (enum brw_barycentric_mode
) ((unsigned) bary
- 1);
1327 fs_visitor::emit_frontfacing_interpolation()
1329 fs_reg
*reg
= new(this->mem_ctx
) fs_reg(vgrf(glsl_type::bool_type
));
1331 if (devinfo
->gen
>= 12) {
1332 fs_reg g1
= fs_reg(retype(brw_vec1_grf(1, 1), BRW_REGISTER_TYPE_W
));
1334 fs_reg tmp
= bld
.vgrf(BRW_REGISTER_TYPE_W
);
1335 bld
.ASR(tmp
, g1
, brw_imm_d(15));
1337 } else if (devinfo
->gen
>= 6) {
1338 /* Bit 15 of g0.0 is 0 if the polygon is front facing. We want to create
1339 * a boolean result from this (~0/true or 0/false).
1341 * We can use the fact that bit 15 is the MSB of g0.0:W to accomplish
1342 * this task in only one instruction:
1343 * - a negation source modifier will flip the bit; and
1344 * - a W -> D type conversion will sign extend the bit into the high
1345 * word of the destination.
1347 * An ASR 15 fills the low word of the destination.
1349 fs_reg g0
= fs_reg(retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_W
));
1352 bld
.ASR(*reg
, g0
, brw_imm_d(15));
1354 /* Bit 31 of g1.6 is 0 if the polygon is front facing. We want to create
1355 * a boolean result from this (1/true or 0/false).
1357 * Like in the above case, since the bit is the MSB of g1.6:UD we can use
1358 * the negation source modifier to flip it. Unfortunately the SHR
1359 * instruction only operates on UD (or D with an abs source modifier)
1360 * sources without negation.
1362 * Instead, use ASR (which will give ~0/true or 0/false).
1364 fs_reg g1_6
= fs_reg(retype(brw_vec1_grf(1, 6), BRW_REGISTER_TYPE_D
));
1367 bld
.ASR(*reg
, g1_6
, brw_imm_d(31));
1374 fs_visitor::compute_sample_position(fs_reg dst
, fs_reg int_sample_pos
)
1376 assert(stage
== MESA_SHADER_FRAGMENT
);
1377 struct brw_wm_prog_data
*wm_prog_data
= brw_wm_prog_data(this->prog_data
);
1378 assert(dst
.type
== BRW_REGISTER_TYPE_F
);
1380 if (wm_prog_data
->persample_dispatch
) {
1381 /* Convert int_sample_pos to floating point */
1382 bld
.MOV(dst
, int_sample_pos
);
1383 /* Scale to the range [0, 1] */
1384 bld
.MUL(dst
, dst
, brw_imm_f(1 / 16.0f
));
1387 /* From ARB_sample_shading specification:
1388 * "When rendering to a non-multisample buffer, or if multisample
1389 * rasterization is disabled, gl_SamplePosition will always be
1392 bld
.MOV(dst
, brw_imm_f(0.5f
));
1397 fs_visitor::emit_samplepos_setup()
1399 assert(devinfo
->gen
>= 6);
1401 const fs_builder abld
= bld
.annotate("compute sample position");
1402 fs_reg
*reg
= new(this->mem_ctx
) fs_reg(vgrf(glsl_type::vec2_type
));
1404 fs_reg int_sample_x
= vgrf(glsl_type::int_type
);
1405 fs_reg int_sample_y
= vgrf(glsl_type::int_type
);
1407 /* WM will be run in MSDISPMODE_PERSAMPLE. So, only one of SIMD8 or SIMD16
1408 * mode will be enabled.
1410 * From the Ivy Bridge PRM, volume 2 part 1, page 344:
1411 * R31.1:0 Position Offset X/Y for Slot[3:0]
1412 * R31.3:2 Position Offset X/Y for Slot[7:4]
1415 * The X, Y sample positions come in as bytes in thread payload. So, read
1416 * the positions using vstride=16, width=8, hstride=2.
1418 const fs_reg sample_pos_reg
=
1419 fetch_payload_reg(abld
, payload
.sample_pos_reg
, BRW_REGISTER_TYPE_W
);
1421 /* Compute gl_SamplePosition.x */
1422 abld
.MOV(int_sample_x
, subscript(sample_pos_reg
, BRW_REGISTER_TYPE_B
, 0));
1423 compute_sample_position(offset(pos
, abld
, 0), int_sample_x
);
1425 /* Compute gl_SamplePosition.y */
1426 abld
.MOV(int_sample_y
, subscript(sample_pos_reg
, BRW_REGISTER_TYPE_B
, 1));
1427 compute_sample_position(offset(pos
, abld
, 1), int_sample_y
);
1432 fs_visitor::emit_sampleid_setup()
1434 assert(stage
== MESA_SHADER_FRAGMENT
);
1435 brw_wm_prog_key
*key
= (brw_wm_prog_key
*) this->key
;
1436 assert(devinfo
->gen
>= 6);
1438 const fs_builder abld
= bld
.annotate("compute sample id");
1439 fs_reg
*reg
= new(this->mem_ctx
) fs_reg(vgrf(glsl_type::uint_type
));
1441 if (!key
->multisample_fbo
) {
1442 /* As per GL_ARB_sample_shading specification:
1443 * "When rendering to a non-multisample buffer, or if multisample
1444 * rasterization is disabled, gl_SampleID will always be zero."
1446 abld
.MOV(*reg
, brw_imm_d(0));
1447 } else if (devinfo
->gen
>= 8) {
1448 /* Sample ID comes in as 4-bit numbers in g1.0:
1450 * 15:12 Slot 3 SampleID (only used in SIMD16)
1451 * 11:8 Slot 2 SampleID (only used in SIMD16)
1452 * 7:4 Slot 1 SampleID
1453 * 3:0 Slot 0 SampleID
1455 * Each slot corresponds to four channels, so we want to replicate each
1456 * half-byte value to 4 channels in a row:
1458 * dst+0: .7 .6 .5 .4 .3 .2 .1 .0
1459 * 7:4 7:4 7:4 7:4 3:0 3:0 3:0 3:0
1461 * dst+1: .7 .6 .5 .4 .3 .2 .1 .0 (if SIMD16)
1462 * 15:12 15:12 15:12 15:12 11:8 11:8 11:8 11:8
1464 * First, we read g1.0 with a <1,8,0>UB region, causing the first 8
1465 * channels to read the first byte (7:0), and the second group of 8
1466 * channels to read the second byte (15:8). Then, we shift right by
1467 * a vector immediate of <4, 4, 4, 4, 0, 0, 0, 0>, moving the slot 1 / 3
1468 * values into place. Finally, we AND with 0xf to keep the low nibble.
1470 * shr(16) tmp<1>W g1.0<1,8,0>B 0x44440000:V
1471 * and(16) dst<1>D tmp<8,8,1>W 0xf:W
1473 * TODO: These payload bits exist on Gen7 too, but they appear to always
1474 * be zero, so this code fails to work. We should find out why.
1476 const fs_reg tmp
= abld
.vgrf(BRW_REGISTER_TYPE_UW
);
1478 for (unsigned i
= 0; i
< DIV_ROUND_UP(dispatch_width
, 16); i
++) {
1479 const fs_builder hbld
= abld
.group(MIN2(16, dispatch_width
), i
);
1480 hbld
.SHR(offset(tmp
, hbld
, i
),
1481 stride(retype(brw_vec1_grf(1 + i
, 0), BRW_REGISTER_TYPE_UB
),
1483 brw_imm_v(0x44440000));
1486 abld
.AND(*reg
, tmp
, brw_imm_w(0xf));
1488 const fs_reg t1
= component(abld
.vgrf(BRW_REGISTER_TYPE_UD
), 0);
1489 const fs_reg t2
= abld
.vgrf(BRW_REGISTER_TYPE_UW
);
1491 /* The PS will be run in MSDISPMODE_PERSAMPLE. For example with
1492 * 8x multisampling, subspan 0 will represent sample N (where N
1493 * is 0, 2, 4 or 6), subspan 1 will represent sample 1, 3, 5 or
1494 * 7. We can find the value of N by looking at R0.0 bits 7:6
1495 * ("Starting Sample Pair Index (SSPI)") and multiplying by two
1496 * (since samples are always delivered in pairs). That is, we
1497 * compute 2*((R0.0 & 0xc0) >> 6) == (R0.0 & 0xc0) >> 5. Then
1498 * we need to add N to the sequence (0, 0, 0, 0, 1, 1, 1, 1) in
1499 * case of SIMD8 and sequence (0, 0, 0, 0, 1, 1, 1, 1, 2, 2, 2,
1500 * 2, 3, 3, 3, 3) in case of SIMD16. We compute this sequence by
1501 * populating a temporary variable with the sequence (0, 1, 2, 3),
1502 * and then reading from it using vstride=1, width=4, hstride=0.
1503 * These computations hold good for 4x multisampling as well.
1505 * For 2x MSAA and SIMD16, we want to use the sequence (0, 1, 0, 1):
1506 * the first four slots are sample 0 of subspan 0; the next four
1507 * are sample 1 of subspan 0; the third group is sample 0 of
1508 * subspan 1, and finally sample 1 of subspan 1.
1511 /* SKL+ has an extra bit for the Starting Sample Pair Index to
1512 * accomodate 16x MSAA.
1514 abld
.exec_all().group(1, 0)
1515 .AND(t1
, fs_reg(retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_UD
)),
1517 abld
.exec_all().group(1, 0).SHR(t1
, t1
, brw_imm_d(5));
1519 /* This works for SIMD8-SIMD16. It also works for SIMD32 but only if we
1520 * can assume 4x MSAA. Disallow it on IVB+
1522 * FINISHME: One day, we could come up with a way to do this that
1523 * actually works on gen7.
1525 if (devinfo
->gen
>= 7)
1526 limit_dispatch_width(16, "gl_SampleId is unsupported in SIMD32 on gen7");
1527 abld
.exec_all().group(8, 0).MOV(t2
, brw_imm_v(0x32103210));
1529 /* This special instruction takes care of setting vstride=1,
1530 * width=4, hstride=0 of t2 during an ADD instruction.
1532 abld
.emit(FS_OPCODE_SET_SAMPLE_ID
, *reg
, t1
, t2
);
1539 fs_visitor::emit_samplemaskin_setup()
1541 assert(stage
== MESA_SHADER_FRAGMENT
);
1542 struct brw_wm_prog_data
*wm_prog_data
= brw_wm_prog_data(this->prog_data
);
1543 assert(devinfo
->gen
>= 6);
1545 fs_reg
*reg
= new(this->mem_ctx
) fs_reg(vgrf(glsl_type::int_type
));
1547 fs_reg coverage_mask
=
1548 fetch_payload_reg(bld
, payload
.sample_mask_in_reg
, BRW_REGISTER_TYPE_D
);
1550 if (wm_prog_data
->persample_dispatch
) {
1551 /* gl_SampleMaskIn[] comes from two sources: the input coverage mask,
1552 * and a mask representing which sample is being processed by the
1553 * current shader invocation.
1555 * From the OES_sample_variables specification:
1556 * "When per-sample shading is active due to the use of a fragment input
1557 * qualified by "sample" or due to the use of the gl_SampleID or
1558 * gl_SamplePosition variables, only the bit for the current sample is
1559 * set in gl_SampleMaskIn."
1561 const fs_builder abld
= bld
.annotate("compute gl_SampleMaskIn");
1563 if (nir_system_values
[SYSTEM_VALUE_SAMPLE_ID
].file
== BAD_FILE
)
1564 nir_system_values
[SYSTEM_VALUE_SAMPLE_ID
] = *emit_sampleid_setup();
1566 fs_reg one
= vgrf(glsl_type::int_type
);
1567 fs_reg enabled_mask
= vgrf(glsl_type::int_type
);
1568 abld
.MOV(one
, brw_imm_d(1));
1569 abld
.SHL(enabled_mask
, one
, nir_system_values
[SYSTEM_VALUE_SAMPLE_ID
]);
1570 abld
.AND(*reg
, enabled_mask
, coverage_mask
);
1572 /* In per-pixel mode, the coverage mask is sufficient. */
1573 *reg
= coverage_mask
;
1579 fs_visitor::resolve_source_modifiers(const fs_reg
&src
)
1581 if (!src
.abs
&& !src
.negate
)
1584 fs_reg temp
= bld
.vgrf(src
.type
);
1591 fs_visitor::emit_discard_jump()
1593 assert(brw_wm_prog_data(this->prog_data
)->uses_kill
);
1595 /* For performance, after a discard, jump to the end of the
1596 * shader if all relevant channels have been discarded.
1598 fs_inst
*discard_jump
= bld
.emit(FS_OPCODE_DISCARD_JUMP
);
1599 discard_jump
->flag_subreg
= 1;
1601 discard_jump
->predicate
= BRW_PREDICATE_ALIGN1_ANY4H
;
1602 discard_jump
->predicate_inverse
= true;
1606 fs_visitor::emit_gs_thread_end()
1608 assert(stage
== MESA_SHADER_GEOMETRY
);
1610 struct brw_gs_prog_data
*gs_prog_data
= brw_gs_prog_data(prog_data
);
1612 if (gs_compile
->control_data_header_size_bits
> 0) {
1613 emit_gs_control_data_bits(this->final_gs_vertex_count
);
1616 const fs_builder abld
= bld
.annotate("thread end");
1619 if (gs_prog_data
->static_vertex_count
!= -1) {
1620 foreach_in_list_reverse(fs_inst
, prev
, &this->instructions
) {
1621 if (prev
->opcode
== SHADER_OPCODE_URB_WRITE_SIMD8
||
1622 prev
->opcode
== SHADER_OPCODE_URB_WRITE_SIMD8_MASKED
||
1623 prev
->opcode
== SHADER_OPCODE_URB_WRITE_SIMD8_PER_SLOT
||
1624 prev
->opcode
== SHADER_OPCODE_URB_WRITE_SIMD8_MASKED_PER_SLOT
) {
1627 /* Delete now dead instructions. */
1628 foreach_in_list_reverse_safe(exec_node
, dead
, &this->instructions
) {
1634 } else if (prev
->is_control_flow() || prev
->has_side_effects()) {
1638 fs_reg hdr
= abld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
1639 abld
.MOV(hdr
, fs_reg(retype(brw_vec8_grf(1, 0), BRW_REGISTER_TYPE_UD
)));
1640 inst
= abld
.emit(SHADER_OPCODE_URB_WRITE_SIMD8
, reg_undef
, hdr
);
1643 fs_reg payload
= abld
.vgrf(BRW_REGISTER_TYPE_UD
, 2);
1644 fs_reg
*sources
= ralloc_array(mem_ctx
, fs_reg
, 2);
1645 sources
[0] = fs_reg(retype(brw_vec8_grf(1, 0), BRW_REGISTER_TYPE_UD
));
1646 sources
[1] = this->final_gs_vertex_count
;
1647 abld
.LOAD_PAYLOAD(payload
, sources
, 2, 2);
1648 inst
= abld
.emit(SHADER_OPCODE_URB_WRITE_SIMD8
, reg_undef
, payload
);
1656 fs_visitor::assign_curb_setup()
1658 unsigned uniform_push_length
= DIV_ROUND_UP(stage_prog_data
->nr_params
, 8);
1660 unsigned ubo_push_length
= 0;
1661 unsigned ubo_push_start
[4];
1662 for (int i
= 0; i
< 4; i
++) {
1663 ubo_push_start
[i
] = 8 * (ubo_push_length
+ uniform_push_length
);
1664 ubo_push_length
+= stage_prog_data
->ubo_ranges
[i
].length
;
1667 prog_data
->curb_read_length
= uniform_push_length
+ ubo_push_length
;
1669 /* Map the offsets in the UNIFORM file to fixed HW regs. */
1670 foreach_block_and_inst(block
, fs_inst
, inst
, cfg
) {
1671 for (unsigned int i
= 0; i
< inst
->sources
; i
++) {
1672 if (inst
->src
[i
].file
== UNIFORM
) {
1673 int uniform_nr
= inst
->src
[i
].nr
+ inst
->src
[i
].offset
/ 4;
1675 if (inst
->src
[i
].nr
>= UBO_START
) {
1676 /* constant_nr is in 32-bit units, the rest are in bytes */
1677 constant_nr
= ubo_push_start
[inst
->src
[i
].nr
- UBO_START
] +
1678 inst
->src
[i
].offset
/ 4;
1679 } else if (uniform_nr
>= 0 && uniform_nr
< (int) uniforms
) {
1680 constant_nr
= push_constant_loc
[uniform_nr
];
1682 /* Section 5.11 of the OpenGL 4.1 spec says:
1683 * "Out-of-bounds reads return undefined values, which include
1684 * values from other variables of the active program or zero."
1685 * Just return the first push constant.
1690 struct brw_reg brw_reg
= brw_vec1_grf(payload
.num_regs
+
1693 brw_reg
.abs
= inst
->src
[i
].abs
;
1694 brw_reg
.negate
= inst
->src
[i
].negate
;
1696 assert(inst
->src
[i
].stride
== 0);
1697 inst
->src
[i
] = byte_offset(
1698 retype(brw_reg
, inst
->src
[i
].type
),
1699 inst
->src
[i
].offset
% 4);
1704 /* This may be updated in assign_urb_setup or assign_vs_urb_setup. */
1705 this->first_non_payload_grf
= payload
.num_regs
+ prog_data
->curb_read_length
;
1709 calculate_urb_setup(const struct gen_device_info
*devinfo
,
1710 const struct brw_wm_prog_key
*key
,
1711 struct brw_wm_prog_data
*prog_data
,
1712 const nir_shader
*nir
)
1714 memset(prog_data
->urb_setup
, -1,
1715 sizeof(prog_data
->urb_setup
[0]) * VARYING_SLOT_MAX
);
1718 /* Figure out where each of the incoming setup attributes lands. */
1719 if (devinfo
->gen
>= 6) {
1720 if (util_bitcount64(nir
->info
.inputs_read
&
1721 BRW_FS_VARYING_INPUT_MASK
) <= 16) {
1722 /* The SF/SBE pipeline stage can do arbitrary rearrangement of the
1723 * first 16 varying inputs, so we can put them wherever we want.
1724 * Just put them in order.
1726 * This is useful because it means that (a) inputs not used by the
1727 * fragment shader won't take up valuable register space, and (b) we
1728 * won't have to recompile the fragment shader if it gets paired with
1729 * a different vertex (or geometry) shader.
1731 for (unsigned int i
= 0; i
< VARYING_SLOT_MAX
; i
++) {
1732 if (nir
->info
.inputs_read
& BRW_FS_VARYING_INPUT_MASK
&
1733 BITFIELD64_BIT(i
)) {
1734 prog_data
->urb_setup
[i
] = urb_next
++;
1738 /* We have enough input varyings that the SF/SBE pipeline stage can't
1739 * arbitrarily rearrange them to suit our whim; we have to put them
1740 * in an order that matches the output of the previous pipeline stage
1741 * (geometry or vertex shader).
1743 struct brw_vue_map prev_stage_vue_map
;
1744 brw_compute_vue_map(devinfo
, &prev_stage_vue_map
,
1745 key
->input_slots_valid
,
1746 nir
->info
.separate_shader
);
1749 brw_compute_first_urb_slot_required(nir
->info
.inputs_read
,
1750 &prev_stage_vue_map
);
1752 assert(prev_stage_vue_map
.num_slots
<= first_slot
+ 32);
1753 for (int slot
= first_slot
; slot
< prev_stage_vue_map
.num_slots
;
1755 int varying
= prev_stage_vue_map
.slot_to_varying
[slot
];
1756 if (varying
!= BRW_VARYING_SLOT_PAD
&&
1757 (nir
->info
.inputs_read
& BRW_FS_VARYING_INPUT_MASK
&
1758 BITFIELD64_BIT(varying
))) {
1759 prog_data
->urb_setup
[varying
] = slot
- first_slot
;
1762 urb_next
= prev_stage_vue_map
.num_slots
- first_slot
;
1765 /* FINISHME: The sf doesn't map VS->FS inputs for us very well. */
1766 for (unsigned int i
= 0; i
< VARYING_SLOT_MAX
; i
++) {
1767 /* Point size is packed into the header, not as a general attribute */
1768 if (i
== VARYING_SLOT_PSIZ
)
1771 if (key
->input_slots_valid
& BITFIELD64_BIT(i
)) {
1772 /* The back color slot is skipped when the front color is
1773 * also written to. In addition, some slots can be
1774 * written in the vertex shader and not read in the
1775 * fragment shader. So the register number must always be
1776 * incremented, mapped or not.
1778 if (_mesa_varying_slot_in_fs((gl_varying_slot
) i
))
1779 prog_data
->urb_setup
[i
] = urb_next
;
1785 * It's a FS only attribute, and we did interpolation for this attribute
1786 * in SF thread. So, count it here, too.
1788 * See compile_sf_prog() for more info.
1790 if (nir
->info
.inputs_read
& BITFIELD64_BIT(VARYING_SLOT_PNTC
))
1791 prog_data
->urb_setup
[VARYING_SLOT_PNTC
] = urb_next
++;
1794 prog_data
->num_varying_inputs
= urb_next
;
1798 fs_visitor::assign_urb_setup()
1800 assert(stage
== MESA_SHADER_FRAGMENT
);
1801 struct brw_wm_prog_data
*prog_data
= brw_wm_prog_data(this->prog_data
);
1803 int urb_start
= payload
.num_regs
+ prog_data
->base
.curb_read_length
;
1805 /* Offset all the urb_setup[] index by the actual position of the
1806 * setup regs, now that the location of the constants has been chosen.
1808 foreach_block_and_inst(block
, fs_inst
, inst
, cfg
) {
1809 for (int i
= 0; i
< inst
->sources
; i
++) {
1810 if (inst
->src
[i
].file
== ATTR
) {
1811 /* ATTR regs in the FS are in units of logical scalar inputs each
1812 * of which consumes half of a GRF register.
1814 assert(inst
->src
[i
].offset
< REG_SIZE
/ 2);
1815 const unsigned grf
= urb_start
+ inst
->src
[i
].nr
/ 2;
1816 const unsigned offset
= (inst
->src
[i
].nr
% 2) * (REG_SIZE
/ 2) +
1817 inst
->src
[i
].offset
;
1818 const unsigned width
= inst
->src
[i
].stride
== 0 ?
1819 1 : MIN2(inst
->exec_size
, 8);
1820 struct brw_reg reg
= stride(
1821 byte_offset(retype(brw_vec8_grf(grf
, 0), inst
->src
[i
].type
),
1823 width
* inst
->src
[i
].stride
,
1824 width
, inst
->src
[i
].stride
);
1825 reg
.abs
= inst
->src
[i
].abs
;
1826 reg
.negate
= inst
->src
[i
].negate
;
1832 /* Each attribute is 4 setup channels, each of which is half a reg. */
1833 this->first_non_payload_grf
+= prog_data
->num_varying_inputs
* 2;
1837 fs_visitor::convert_attr_sources_to_hw_regs(fs_inst
*inst
)
1839 for (int i
= 0; i
< inst
->sources
; i
++) {
1840 if (inst
->src
[i
].file
== ATTR
) {
1841 int grf
= payload
.num_regs
+
1842 prog_data
->curb_read_length
+
1844 inst
->src
[i
].offset
/ REG_SIZE
;
1846 /* As explained at brw_reg_from_fs_reg, From the Haswell PRM:
1848 * VertStride must be used to cross GRF register boundaries. This
1849 * rule implies that elements within a 'Width' cannot cross GRF
1852 * So, for registers that are large enough, we have to split the exec
1853 * size in two and trust the compression state to sort it out.
1855 unsigned total_size
= inst
->exec_size
*
1856 inst
->src
[i
].stride
*
1857 type_sz(inst
->src
[i
].type
);
1859 assert(total_size
<= 2 * REG_SIZE
);
1860 const unsigned exec_size
=
1861 (total_size
<= REG_SIZE
) ? inst
->exec_size
: inst
->exec_size
/ 2;
1863 unsigned width
= inst
->src
[i
].stride
== 0 ? 1 : exec_size
;
1864 struct brw_reg reg
=
1865 stride(byte_offset(retype(brw_vec8_grf(grf
, 0), inst
->src
[i
].type
),
1866 inst
->src
[i
].offset
% REG_SIZE
),
1867 exec_size
* inst
->src
[i
].stride
,
1868 width
, inst
->src
[i
].stride
);
1869 reg
.abs
= inst
->src
[i
].abs
;
1870 reg
.negate
= inst
->src
[i
].negate
;
1878 fs_visitor::assign_vs_urb_setup()
1880 struct brw_vs_prog_data
*vs_prog_data
= brw_vs_prog_data(prog_data
);
1882 assert(stage
== MESA_SHADER_VERTEX
);
1884 /* Each attribute is 4 regs. */
1885 this->first_non_payload_grf
+= 4 * vs_prog_data
->nr_attribute_slots
;
1887 assert(vs_prog_data
->base
.urb_read_length
<= 15);
1889 /* Rewrite all ATTR file references to the hw grf that they land in. */
1890 foreach_block_and_inst(block
, fs_inst
, inst
, cfg
) {
1891 convert_attr_sources_to_hw_regs(inst
);
1896 fs_visitor::assign_tcs_urb_setup()
1898 assert(stage
== MESA_SHADER_TESS_CTRL
);
1900 /* Rewrite all ATTR file references to HW_REGs. */
1901 foreach_block_and_inst(block
, fs_inst
, inst
, cfg
) {
1902 convert_attr_sources_to_hw_regs(inst
);
1907 fs_visitor::assign_tes_urb_setup()
1909 assert(stage
== MESA_SHADER_TESS_EVAL
);
1911 struct brw_vue_prog_data
*vue_prog_data
= brw_vue_prog_data(prog_data
);
1913 first_non_payload_grf
+= 8 * vue_prog_data
->urb_read_length
;
1915 /* Rewrite all ATTR file references to HW_REGs. */
1916 foreach_block_and_inst(block
, fs_inst
, inst
, cfg
) {
1917 convert_attr_sources_to_hw_regs(inst
);
1922 fs_visitor::assign_gs_urb_setup()
1924 assert(stage
== MESA_SHADER_GEOMETRY
);
1926 struct brw_vue_prog_data
*vue_prog_data
= brw_vue_prog_data(prog_data
);
1928 first_non_payload_grf
+=
1929 8 * vue_prog_data
->urb_read_length
* nir
->info
.gs
.vertices_in
;
1931 foreach_block_and_inst(block
, fs_inst
, inst
, cfg
) {
1932 /* Rewrite all ATTR file references to GRFs. */
1933 convert_attr_sources_to_hw_regs(inst
);
1939 * Split large virtual GRFs into separate components if we can.
1941 * This is mostly duplicated with what brw_fs_vector_splitting does,
1942 * but that's really conservative because it's afraid of doing
1943 * splitting that doesn't result in real progress after the rest of
1944 * the optimization phases, which would cause infinite looping in
1945 * optimization. We can do it once here, safely. This also has the
1946 * opportunity to split interpolated values, or maybe even uniforms,
1947 * which we don't have at the IR level.
1949 * We want to split, because virtual GRFs are what we register
1950 * allocate and spill (due to contiguousness requirements for some
1951 * instructions), and they're what we naturally generate in the
1952 * codegen process, but most virtual GRFs don't actually need to be
1953 * contiguous sets of GRFs. If we split, we'll end up with reduced
1954 * live intervals and better dead code elimination and coalescing.
1957 fs_visitor::split_virtual_grfs()
1959 /* Compact the register file so we eliminate dead vgrfs. This
1960 * only defines split points for live registers, so if we have
1961 * too large dead registers they will hit assertions later.
1963 compact_virtual_grfs();
1965 int num_vars
= this->alloc
.count
;
1967 /* Count the total number of registers */
1969 int vgrf_to_reg
[num_vars
];
1970 for (int i
= 0; i
< num_vars
; i
++) {
1971 vgrf_to_reg
[i
] = reg_count
;
1972 reg_count
+= alloc
.sizes
[i
];
1975 /* An array of "split points". For each register slot, this indicates
1976 * if this slot can be separated from the previous slot. Every time an
1977 * instruction uses multiple elements of a register (as a source or
1978 * destination), we mark the used slots as inseparable. Then we go
1979 * through and split the registers into the smallest pieces we can.
1981 bool *split_points
= new bool[reg_count
];
1982 memset(split_points
, 0, reg_count
* sizeof(*split_points
));
1984 /* Mark all used registers as fully splittable */
1985 foreach_block_and_inst(block
, fs_inst
, inst
, cfg
) {
1986 if (inst
->dst
.file
== VGRF
) {
1987 int reg
= vgrf_to_reg
[inst
->dst
.nr
];
1988 for (unsigned j
= 1; j
< this->alloc
.sizes
[inst
->dst
.nr
]; j
++)
1989 split_points
[reg
+ j
] = true;
1992 for (int i
= 0; i
< inst
->sources
; i
++) {
1993 if (inst
->src
[i
].file
== VGRF
) {
1994 int reg
= vgrf_to_reg
[inst
->src
[i
].nr
];
1995 for (unsigned j
= 1; j
< this->alloc
.sizes
[inst
->src
[i
].nr
]; j
++)
1996 split_points
[reg
+ j
] = true;
2001 foreach_block_and_inst(block
, fs_inst
, inst
, cfg
) {
2002 /* We fix up undef instructions later */
2003 if (inst
->opcode
== SHADER_OPCODE_UNDEF
) {
2004 /* UNDEF instructions are currently only used to undef entire
2005 * registers. We need this invariant later when we split them.
2007 assert(inst
->dst
.file
== VGRF
);
2008 assert(inst
->dst
.offset
== 0);
2009 assert(inst
->size_written
== alloc
.sizes
[inst
->dst
.nr
] * REG_SIZE
);
2013 if (inst
->dst
.file
== VGRF
) {
2014 int reg
= vgrf_to_reg
[inst
->dst
.nr
] + inst
->dst
.offset
/ REG_SIZE
;
2015 for (unsigned j
= 1; j
< regs_written(inst
); j
++)
2016 split_points
[reg
+ j
] = false;
2018 for (int i
= 0; i
< inst
->sources
; i
++) {
2019 if (inst
->src
[i
].file
== VGRF
) {
2020 int reg
= vgrf_to_reg
[inst
->src
[i
].nr
] + inst
->src
[i
].offset
/ REG_SIZE
;
2021 for (unsigned j
= 1; j
< regs_read(inst
, i
); j
++)
2022 split_points
[reg
+ j
] = false;
2027 int *new_virtual_grf
= new int[reg_count
];
2028 int *new_reg_offset
= new int[reg_count
];
2031 for (int i
= 0; i
< num_vars
; i
++) {
2032 /* The first one should always be 0 as a quick sanity check. */
2033 assert(split_points
[reg
] == false);
2036 new_reg_offset
[reg
] = 0;
2041 for (unsigned j
= 1; j
< alloc
.sizes
[i
]; j
++) {
2042 /* If this is a split point, reset the offset to 0 and allocate a
2043 * new virtual GRF for the previous offset many registers
2045 if (split_points
[reg
]) {
2046 assert(offset
<= MAX_VGRF_SIZE
);
2047 int grf
= alloc
.allocate(offset
);
2048 for (int k
= reg
- offset
; k
< reg
; k
++)
2049 new_virtual_grf
[k
] = grf
;
2052 new_reg_offset
[reg
] = offset
;
2057 /* The last one gets the original register number */
2058 assert(offset
<= MAX_VGRF_SIZE
);
2059 alloc
.sizes
[i
] = offset
;
2060 for (int k
= reg
- offset
; k
< reg
; k
++)
2061 new_virtual_grf
[k
] = i
;
2063 assert(reg
== reg_count
);
2065 foreach_block_and_inst_safe(block
, fs_inst
, inst
, cfg
) {
2066 if (inst
->opcode
== SHADER_OPCODE_UNDEF
) {
2067 const fs_builder
ibld(this, block
, inst
);
2068 assert(inst
->size_written
% REG_SIZE
== 0);
2069 unsigned reg_offset
= 0;
2070 while (reg_offset
< inst
->size_written
/ REG_SIZE
) {
2071 reg
= vgrf_to_reg
[inst
->dst
.nr
] + reg_offset
;
2072 ibld
.UNDEF(fs_reg(VGRF
, new_virtual_grf
[reg
], inst
->dst
.type
));
2073 reg_offset
+= alloc
.sizes
[new_virtual_grf
[reg
]];
2075 inst
->remove(block
);
2079 if (inst
->dst
.file
== VGRF
) {
2080 reg
= vgrf_to_reg
[inst
->dst
.nr
] + inst
->dst
.offset
/ REG_SIZE
;
2081 inst
->dst
.nr
= new_virtual_grf
[reg
];
2082 inst
->dst
.offset
= new_reg_offset
[reg
] * REG_SIZE
+
2083 inst
->dst
.offset
% REG_SIZE
;
2084 assert((unsigned)new_reg_offset
[reg
] < alloc
.sizes
[new_virtual_grf
[reg
]]);
2086 for (int i
= 0; i
< inst
->sources
; i
++) {
2087 if (inst
->src
[i
].file
== VGRF
) {
2088 reg
= vgrf_to_reg
[inst
->src
[i
].nr
] + inst
->src
[i
].offset
/ REG_SIZE
;
2089 inst
->src
[i
].nr
= new_virtual_grf
[reg
];
2090 inst
->src
[i
].offset
= new_reg_offset
[reg
] * REG_SIZE
+
2091 inst
->src
[i
].offset
% REG_SIZE
;
2092 assert((unsigned)new_reg_offset
[reg
] < alloc
.sizes
[new_virtual_grf
[reg
]]);
2096 invalidate_live_intervals();
2098 delete[] split_points
;
2099 delete[] new_virtual_grf
;
2100 delete[] new_reg_offset
;
2104 * Remove unused virtual GRFs and compact the virtual_grf_* arrays.
2106 * During code generation, we create tons of temporary variables, many of
2107 * which get immediately killed and are never used again. Yet, in later
2108 * optimization and analysis passes, such as compute_live_intervals, we need
2109 * to loop over all the virtual GRFs. Compacting them can save a lot of
2113 fs_visitor::compact_virtual_grfs()
2115 bool progress
= false;
2116 int *remap_table
= new int[this->alloc
.count
];
2117 memset(remap_table
, -1, this->alloc
.count
* sizeof(int));
2119 /* Mark which virtual GRFs are used. */
2120 foreach_block_and_inst(block
, const fs_inst
, inst
, cfg
) {
2121 if (inst
->dst
.file
== VGRF
)
2122 remap_table
[inst
->dst
.nr
] = 0;
2124 for (int i
= 0; i
< inst
->sources
; i
++) {
2125 if (inst
->src
[i
].file
== VGRF
)
2126 remap_table
[inst
->src
[i
].nr
] = 0;
2130 /* Compact the GRF arrays. */
2132 for (unsigned i
= 0; i
< this->alloc
.count
; i
++) {
2133 if (remap_table
[i
] == -1) {
2134 /* We just found an unused register. This means that we are
2135 * actually going to compact something.
2139 remap_table
[i
] = new_index
;
2140 alloc
.sizes
[new_index
] = alloc
.sizes
[i
];
2141 invalidate_live_intervals();
2146 this->alloc
.count
= new_index
;
2148 /* Patch all the instructions to use the newly renumbered registers */
2149 foreach_block_and_inst(block
, fs_inst
, inst
, cfg
) {
2150 if (inst
->dst
.file
== VGRF
)
2151 inst
->dst
.nr
= remap_table
[inst
->dst
.nr
];
2153 for (int i
= 0; i
< inst
->sources
; i
++) {
2154 if (inst
->src
[i
].file
== VGRF
)
2155 inst
->src
[i
].nr
= remap_table
[inst
->src
[i
].nr
];
2159 /* Patch all the references to delta_xy, since they're used in register
2160 * allocation. If they're unused, switch them to BAD_FILE so we don't
2161 * think some random VGRF is delta_xy.
2163 for (unsigned i
= 0; i
< ARRAY_SIZE(delta_xy
); i
++) {
2164 if (delta_xy
[i
].file
== VGRF
) {
2165 if (remap_table
[delta_xy
[i
].nr
] != -1) {
2166 delta_xy
[i
].nr
= remap_table
[delta_xy
[i
].nr
];
2168 delta_xy
[i
].file
= BAD_FILE
;
2173 delete[] remap_table
;
2179 get_subgroup_id_param_index(const brw_stage_prog_data
*prog_data
)
2181 if (prog_data
->nr_params
== 0)
2184 /* The local thread id is always the last parameter in the list */
2185 uint32_t last_param
= prog_data
->param
[prog_data
->nr_params
- 1];
2186 if (last_param
== BRW_PARAM_BUILTIN_SUBGROUP_ID
)
2187 return prog_data
->nr_params
- 1;
2193 * Struct for handling complex alignments.
2195 * A complex alignment is stored as multiplier and an offset. A value is
2196 * considered to be aligned if it is {offset} larger than a multiple of {mul}.
2197 * For instance, with an alignment of {8, 2}, cplx_align_apply would do the
2200 * N | cplx_align_apply({8, 2}, N)
2201 * ----+-----------------------------
2215 #define CPLX_ALIGN_MAX_MUL 8
2218 cplx_align_assert_sane(struct cplx_align a
)
2220 assert(a
.mul
> 0 && util_is_power_of_two_nonzero(a
.mul
));
2221 assert(a
.offset
< a
.mul
);
2225 * Combines two alignments to produce a least multiple of sorts.
2227 * The returned alignment is the smallest (in terms of multiplier) such that
2228 * anything aligned to both a and b will be aligned to the new alignment.
2229 * This function will assert-fail if a and b are not compatible, i.e. if the
2230 * offset parameters are such that no common alignment is possible.
2232 static struct cplx_align
2233 cplx_align_combine(struct cplx_align a
, struct cplx_align b
)
2235 cplx_align_assert_sane(a
);
2236 cplx_align_assert_sane(b
);
2238 /* Assert that the alignments agree. */
2239 assert((a
.offset
& (b
.mul
- 1)) == (b
.offset
& (a
.mul
- 1)));
2241 return a
.mul
> b
.mul
? a
: b
;
2245 * Apply a complex alignment
2247 * This function will return the smallest number greater than or equal to
2248 * offset that is aligned to align.
2251 cplx_align_apply(struct cplx_align align
, unsigned offset
)
2253 return ALIGN(offset
- align
.offset
, align
.mul
) + align
.offset
;
2256 #define UNIFORM_SLOT_SIZE 4
2258 struct uniform_slot_info
{
2259 /** True if the given uniform slot is live */
2262 /** True if this slot and the next slot must remain contiguous */
2263 unsigned contiguous
:1;
2265 struct cplx_align align
;
2269 mark_uniform_slots_read(struct uniform_slot_info
*slots
,
2270 unsigned num_slots
, unsigned alignment
)
2272 assert(alignment
> 0 && util_is_power_of_two_nonzero(alignment
));
2273 assert(alignment
<= CPLX_ALIGN_MAX_MUL
);
2275 /* We can't align a slot to anything less than the slot size */
2276 alignment
= MAX2(alignment
, UNIFORM_SLOT_SIZE
);
2278 struct cplx_align align
= {alignment
, 0};
2279 cplx_align_assert_sane(align
);
2281 for (unsigned i
= 0; i
< num_slots
; i
++) {
2282 slots
[i
].is_live
= true;
2283 if (i
< num_slots
- 1)
2284 slots
[i
].contiguous
= true;
2286 align
.offset
= (i
* UNIFORM_SLOT_SIZE
) & (align
.mul
- 1);
2287 if (slots
[i
].align
.mul
== 0) {
2288 slots
[i
].align
= align
;
2290 slots
[i
].align
= cplx_align_combine(slots
[i
].align
, align
);
2296 * Assign UNIFORM file registers to either push constants or pull constants.
2298 * We allow a fragment shader to have more than the specified minimum
2299 * maximum number of fragment shader uniform components (64). If
2300 * there are too many of these, they'd fill up all of register space.
2301 * So, this will push some of them out to the pull constant buffer and
2302 * update the program to load them.
2305 fs_visitor::assign_constant_locations()
2307 /* Only the first compile gets to decide on locations. */
2308 if (push_constant_loc
) {
2309 assert(pull_constant_loc
);
2313 struct uniform_slot_info slots
[uniforms
];
2314 memset(slots
, 0, sizeof(slots
));
2316 foreach_block_and_inst_safe(block
, fs_inst
, inst
, cfg
) {
2317 for (int i
= 0 ; i
< inst
->sources
; i
++) {
2318 if (inst
->src
[i
].file
!= UNIFORM
)
2321 /* NIR tightly packs things so the uniform number might not be
2322 * aligned (if we have a double right after a float, for instance).
2323 * This is fine because the process of re-arranging them will ensure
2324 * that things are properly aligned. The offset into that uniform,
2325 * however, must be aligned.
2327 * In Vulkan, we have explicit offsets but everything is crammed
2328 * into a single "variable" so inst->src[i].nr will always be 0.
2329 * Everything will be properly aligned relative to that one base.
2331 assert(inst
->src
[i
].offset
% type_sz(inst
->src
[i
].type
) == 0);
2333 unsigned u
= inst
->src
[i
].nr
+
2334 inst
->src
[i
].offset
/ UNIFORM_SLOT_SIZE
;
2339 unsigned slots_read
;
2340 if (inst
->opcode
== SHADER_OPCODE_MOV_INDIRECT
&& i
== 0) {
2341 slots_read
= DIV_ROUND_UP(inst
->src
[2].ud
, UNIFORM_SLOT_SIZE
);
2343 unsigned bytes_read
= inst
->components_read(i
) *
2344 type_sz(inst
->src
[i
].type
);
2345 slots_read
= DIV_ROUND_UP(bytes_read
, UNIFORM_SLOT_SIZE
);
2348 assert(u
+ slots_read
<= uniforms
);
2349 mark_uniform_slots_read(&slots
[u
], slots_read
,
2350 type_sz(inst
->src
[i
].type
));
2354 int subgroup_id_index
= get_subgroup_id_param_index(stage_prog_data
);
2356 /* Only allow 16 registers (128 uniform components) as push constants.
2358 * Just demote the end of the list. We could probably do better
2359 * here, demoting things that are rarely used in the program first.
2361 * If changing this value, note the limitation about total_regs in
2364 unsigned int max_push_components
= 16 * 8;
2365 if (subgroup_id_index
>= 0)
2366 max_push_components
--; /* Save a slot for the thread ID */
2368 /* We push small arrays, but no bigger than 16 floats. This is big enough
2369 * for a vec4 but hopefully not large enough to push out other stuff. We
2370 * should probably use a better heuristic at some point.
2372 const unsigned int max_chunk_size
= 16;
2374 unsigned int num_push_constants
= 0;
2375 unsigned int num_pull_constants
= 0;
2377 push_constant_loc
= ralloc_array(mem_ctx
, int, uniforms
);
2378 pull_constant_loc
= ralloc_array(mem_ctx
, int, uniforms
);
2380 /* Default to -1 meaning no location */
2381 memset(push_constant_loc
, -1, uniforms
* sizeof(*push_constant_loc
));
2382 memset(pull_constant_loc
, -1, uniforms
* sizeof(*pull_constant_loc
));
2384 int chunk_start
= -1;
2385 struct cplx_align align
;
2386 for (unsigned u
= 0; u
< uniforms
; u
++) {
2387 if (!slots
[u
].is_live
) {
2388 assert(chunk_start
== -1);
2392 /* Skip subgroup_id_index to put it in the last push register. */
2393 if (subgroup_id_index
== (int)u
)
2396 if (chunk_start
== -1) {
2398 align
= slots
[u
].align
;
2400 /* Offset into the chunk */
2401 unsigned chunk_offset
= (u
- chunk_start
) * UNIFORM_SLOT_SIZE
;
2403 /* Shift the slot alignment down by the chunk offset so it is
2404 * comparable with the base chunk alignment.
2406 struct cplx_align slot_align
= slots
[u
].align
;
2408 (slot_align
.offset
- chunk_offset
) & (align
.mul
- 1);
2410 align
= cplx_align_combine(align
, slot_align
);
2413 /* Sanity check the alignment */
2414 cplx_align_assert_sane(align
);
2416 if (slots
[u
].contiguous
)
2419 /* Adjust the alignment to be in terms of slots, not bytes */
2420 assert((align
.mul
& (UNIFORM_SLOT_SIZE
- 1)) == 0);
2421 assert((align
.offset
& (UNIFORM_SLOT_SIZE
- 1)) == 0);
2422 align
.mul
/= UNIFORM_SLOT_SIZE
;
2423 align
.offset
/= UNIFORM_SLOT_SIZE
;
2425 unsigned push_start_align
= cplx_align_apply(align
, num_push_constants
);
2426 unsigned chunk_size
= u
- chunk_start
+ 1;
2427 if ((!compiler
->supports_pull_constants
&& u
< UBO_START
) ||
2428 (chunk_size
< max_chunk_size
&&
2429 push_start_align
+ chunk_size
<= max_push_components
)) {
2430 /* Align up the number of push constants */
2431 num_push_constants
= push_start_align
;
2432 for (unsigned i
= 0; i
< chunk_size
; i
++)
2433 push_constant_loc
[chunk_start
+ i
] = num_push_constants
++;
2435 /* We need to pull this one */
2436 num_pull_constants
= cplx_align_apply(align
, num_pull_constants
);
2437 for (unsigned i
= 0; i
< chunk_size
; i
++)
2438 pull_constant_loc
[chunk_start
+ i
] = num_pull_constants
++;
2441 /* Reset the chunk and start again */
2445 /* Add the CS local thread ID uniform at the end of the push constants */
2446 if (subgroup_id_index
>= 0)
2447 push_constant_loc
[subgroup_id_index
] = num_push_constants
++;
2449 /* As the uniforms are going to be reordered, stash the old array and
2450 * create two new arrays for push/pull params.
2452 uint32_t *param
= stage_prog_data
->param
;
2453 stage_prog_data
->nr_params
= num_push_constants
;
2454 if (num_push_constants
) {
2455 stage_prog_data
->param
= rzalloc_array(mem_ctx
, uint32_t,
2456 num_push_constants
);
2458 stage_prog_data
->param
= NULL
;
2460 assert(stage_prog_data
->nr_pull_params
== 0);
2461 assert(stage_prog_data
->pull_param
== NULL
);
2462 if (num_pull_constants
> 0) {
2463 stage_prog_data
->nr_pull_params
= num_pull_constants
;
2464 stage_prog_data
->pull_param
= rzalloc_array(mem_ctx
, uint32_t,
2465 num_pull_constants
);
2468 /* Now that we know how many regular uniforms we'll push, reduce the
2469 * UBO push ranges so we don't exceed the 3DSTATE_CONSTANT limits.
2471 unsigned push_length
= DIV_ROUND_UP(stage_prog_data
->nr_params
, 8);
2472 for (int i
= 0; i
< 4; i
++) {
2473 struct brw_ubo_range
*range
= &prog_data
->ubo_ranges
[i
];
2475 if (push_length
+ range
->length
> 64)
2476 range
->length
= 64 - push_length
;
2478 push_length
+= range
->length
;
2480 assert(push_length
<= 64);
2482 /* Up until now, the param[] array has been indexed by reg + offset
2483 * of UNIFORM registers. Move pull constants into pull_param[] and
2484 * condense param[] to only contain the uniforms we chose to push.
2486 * NOTE: Because we are condensing the params[] array, we know that
2487 * push_constant_loc[i] <= i and we can do it in one smooth loop without
2488 * having to make a copy.
2490 for (unsigned int i
= 0; i
< uniforms
; i
++) {
2491 uint32_t value
= param
[i
];
2492 if (pull_constant_loc
[i
] != -1) {
2493 stage_prog_data
->pull_param
[pull_constant_loc
[i
]] = value
;
2494 } else if (push_constant_loc
[i
] != -1) {
2495 stage_prog_data
->param
[push_constant_loc
[i
]] = value
;
2502 fs_visitor::get_pull_locs(const fs_reg
&src
,
2503 unsigned *out_surf_index
,
2504 unsigned *out_pull_index
)
2506 assert(src
.file
== UNIFORM
);
2508 if (src
.nr
>= UBO_START
) {
2509 const struct brw_ubo_range
*range
=
2510 &prog_data
->ubo_ranges
[src
.nr
- UBO_START
];
2512 /* If this access is in our (reduced) range, use the push data. */
2513 if (src
.offset
/ 32 < range
->length
)
2516 *out_surf_index
= prog_data
->binding_table
.ubo_start
+ range
->block
;
2517 *out_pull_index
= (32 * range
->start
+ src
.offset
) / 4;
2519 prog_data
->has_ubo_pull
= true;
2523 const unsigned location
= src
.nr
+ src
.offset
/ 4;
2525 if (location
< uniforms
&& pull_constant_loc
[location
] != -1) {
2526 /* A regular uniform push constant */
2527 *out_surf_index
= stage_prog_data
->binding_table
.pull_constants_start
;
2528 *out_pull_index
= pull_constant_loc
[location
];
2530 prog_data
->has_ubo_pull
= true;
2538 * Replace UNIFORM register file access with either UNIFORM_PULL_CONSTANT_LOAD
2539 * or VARYING_PULL_CONSTANT_LOAD instructions which load values into VGRFs.
2542 fs_visitor::lower_constant_loads()
2544 unsigned index
, pull_index
;
2546 foreach_block_and_inst_safe (block
, fs_inst
, inst
, cfg
) {
2547 /* Set up the annotation tracking for new generated instructions. */
2548 const fs_builder
ibld(this, block
, inst
);
2550 for (int i
= 0; i
< inst
->sources
; i
++) {
2551 if (inst
->src
[i
].file
!= UNIFORM
)
2554 /* We'll handle this case later */
2555 if (inst
->opcode
== SHADER_OPCODE_MOV_INDIRECT
&& i
== 0)
2558 if (!get_pull_locs(inst
->src
[i
], &index
, &pull_index
))
2561 assert(inst
->src
[i
].stride
== 0);
2563 const unsigned block_sz
= 64; /* Fetch one cacheline at a time. */
2564 const fs_builder ubld
= ibld
.exec_all().group(block_sz
/ 4, 0);
2565 const fs_reg dst
= ubld
.vgrf(BRW_REGISTER_TYPE_UD
);
2566 const unsigned base
= pull_index
* 4;
2568 ubld
.emit(FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD
,
2569 dst
, brw_imm_ud(index
), brw_imm_ud(base
& ~(block_sz
- 1)));
2571 /* Rewrite the instruction to use the temporary VGRF. */
2572 inst
->src
[i
].file
= VGRF
;
2573 inst
->src
[i
].nr
= dst
.nr
;
2574 inst
->src
[i
].offset
= (base
& (block_sz
- 1)) +
2575 inst
->src
[i
].offset
% 4;
2578 if (inst
->opcode
== SHADER_OPCODE_MOV_INDIRECT
&&
2579 inst
->src
[0].file
== UNIFORM
) {
2581 if (!get_pull_locs(inst
->src
[0], &index
, &pull_index
))
2584 VARYING_PULL_CONSTANT_LOAD(ibld
, inst
->dst
,
2588 inst
->remove(block
);
2591 invalidate_live_intervals();
2595 fs_visitor::opt_algebraic()
2597 bool progress
= false;
2599 foreach_block_and_inst_safe(block
, fs_inst
, inst
, cfg
) {
2600 switch (inst
->opcode
) {
2601 case BRW_OPCODE_MOV
:
2602 if (!devinfo
->has_64bit_types
&&
2603 (inst
->dst
.type
== BRW_REGISTER_TYPE_DF
||
2604 inst
->dst
.type
== BRW_REGISTER_TYPE_UQ
||
2605 inst
->dst
.type
== BRW_REGISTER_TYPE_Q
)) {
2606 assert(inst
->dst
.type
== inst
->src
[0].type
);
2607 assert(!inst
->saturate
);
2608 assert(!inst
->src
[0].abs
);
2609 assert(!inst
->src
[0].negate
);
2610 const brw::fs_builder
ibld(this, block
, inst
);
2612 if (inst
->src
[0].file
== IMM
) {
2613 ibld
.MOV(subscript(inst
->dst
, BRW_REGISTER_TYPE_UD
, 1),
2614 brw_imm_ud(inst
->src
[0].u64
>> 32));
2615 ibld
.MOV(subscript(inst
->dst
, BRW_REGISTER_TYPE_UD
, 0),
2616 brw_imm_ud(inst
->src
[0].u64
));
2618 ibld
.MOV(subscript(inst
->dst
, BRW_REGISTER_TYPE_UD
, 1),
2619 subscript(inst
->src
[0], BRW_REGISTER_TYPE_UD
, 1));
2620 ibld
.MOV(subscript(inst
->dst
, BRW_REGISTER_TYPE_UD
, 0),
2621 subscript(inst
->src
[0], BRW_REGISTER_TYPE_UD
, 0));
2624 inst
->remove(block
);
2628 if ((inst
->conditional_mod
== BRW_CONDITIONAL_Z
||
2629 inst
->conditional_mod
== BRW_CONDITIONAL_NZ
) &&
2630 inst
->dst
.is_null() &&
2631 (inst
->src
[0].abs
|| inst
->src
[0].negate
)) {
2632 inst
->src
[0].abs
= false;
2633 inst
->src
[0].negate
= false;
2638 if (inst
->src
[0].file
!= IMM
)
2641 if (inst
->saturate
) {
2642 /* Full mixed-type saturates don't happen. However, we can end up
2645 * mov.sat(8) g21<1>DF -1F
2647 * Other mixed-size-but-same-base-type cases may also be possible.
2649 if (inst
->dst
.type
!= inst
->src
[0].type
&&
2650 inst
->dst
.type
!= BRW_REGISTER_TYPE_DF
&&
2651 inst
->src
[0].type
!= BRW_REGISTER_TYPE_F
)
2652 assert(!"unimplemented: saturate mixed types");
2654 if (brw_saturate_immediate(inst
->src
[0].type
,
2655 &inst
->src
[0].as_brw_reg())) {
2656 inst
->saturate
= false;
2662 case BRW_OPCODE_MUL
:
2663 if (inst
->src
[1].file
!= IMM
)
2667 if (inst
->src
[1].is_one()) {
2668 inst
->opcode
= BRW_OPCODE_MOV
;
2669 inst
->src
[1] = reg_undef
;
2675 if (inst
->src
[1].is_negative_one()) {
2676 inst
->opcode
= BRW_OPCODE_MOV
;
2677 inst
->src
[0].negate
= !inst
->src
[0].negate
;
2678 inst
->src
[1] = reg_undef
;
2683 if (inst
->src
[0].file
== IMM
) {
2684 assert(inst
->src
[0].type
== BRW_REGISTER_TYPE_F
);
2685 inst
->opcode
= BRW_OPCODE_MOV
;
2686 inst
->src
[0].f
*= inst
->src
[1].f
;
2687 inst
->src
[1] = reg_undef
;
2692 case BRW_OPCODE_ADD
:
2693 if (inst
->src
[1].file
!= IMM
)
2696 if (inst
->src
[0].file
== IMM
) {
2697 assert(inst
->src
[0].type
== BRW_REGISTER_TYPE_F
);
2698 inst
->opcode
= BRW_OPCODE_MOV
;
2699 inst
->src
[0].f
+= inst
->src
[1].f
;
2700 inst
->src
[1] = reg_undef
;
2706 if (inst
->src
[0].equals(inst
->src
[1]) ||
2707 inst
->src
[1].is_zero()) {
2708 /* On Gen8+, the OR instruction can have a source modifier that
2709 * performs logical not on the operand. Cases of 'OR r0, ~r1, 0'
2710 * or 'OR r0, ~r1, ~r1' should become a NOT instead of a MOV.
2712 if (inst
->src
[0].negate
) {
2713 inst
->opcode
= BRW_OPCODE_NOT
;
2714 inst
->src
[0].negate
= false;
2716 inst
->opcode
= BRW_OPCODE_MOV
;
2718 inst
->src
[1] = reg_undef
;
2723 case BRW_OPCODE_CMP
:
2724 if ((inst
->conditional_mod
== BRW_CONDITIONAL_Z
||
2725 inst
->conditional_mod
== BRW_CONDITIONAL_NZ
) &&
2726 inst
->src
[1].is_zero() &&
2727 (inst
->src
[0].abs
|| inst
->src
[0].negate
)) {
2728 inst
->src
[0].abs
= false;
2729 inst
->src
[0].negate
= false;
2734 case BRW_OPCODE_SEL
:
2735 if (!devinfo
->has_64bit_types
&&
2736 (inst
->dst
.type
== BRW_REGISTER_TYPE_DF
||
2737 inst
->dst
.type
== BRW_REGISTER_TYPE_UQ
||
2738 inst
->dst
.type
== BRW_REGISTER_TYPE_Q
)) {
2739 assert(inst
->dst
.type
== inst
->src
[0].type
);
2740 assert(!inst
->saturate
);
2741 assert(!inst
->src
[0].abs
&& !inst
->src
[0].negate
);
2742 assert(!inst
->src
[1].abs
&& !inst
->src
[1].negate
);
2743 const brw::fs_builder
ibld(this, block
, inst
);
2745 set_predicate(inst
->predicate
,
2746 ibld
.SEL(subscript(inst
->dst
, BRW_REGISTER_TYPE_UD
, 0),
2747 subscript(inst
->src
[0], BRW_REGISTER_TYPE_UD
, 0),
2748 subscript(inst
->src
[1], BRW_REGISTER_TYPE_UD
, 0)));
2749 set_predicate(inst
->predicate
,
2750 ibld
.SEL(subscript(inst
->dst
, BRW_REGISTER_TYPE_UD
, 1),
2751 subscript(inst
->src
[0], BRW_REGISTER_TYPE_UD
, 1),
2752 subscript(inst
->src
[1], BRW_REGISTER_TYPE_UD
, 1)));
2754 inst
->remove(block
);
2757 if (inst
->src
[0].equals(inst
->src
[1])) {
2758 inst
->opcode
= BRW_OPCODE_MOV
;
2759 inst
->src
[1] = reg_undef
;
2760 inst
->predicate
= BRW_PREDICATE_NONE
;
2761 inst
->predicate_inverse
= false;
2763 } else if (inst
->saturate
&& inst
->src
[1].file
== IMM
) {
2764 switch (inst
->conditional_mod
) {
2765 case BRW_CONDITIONAL_LE
:
2766 case BRW_CONDITIONAL_L
:
2767 switch (inst
->src
[1].type
) {
2768 case BRW_REGISTER_TYPE_F
:
2769 if (inst
->src
[1].f
>= 1.0f
) {
2770 inst
->opcode
= BRW_OPCODE_MOV
;
2771 inst
->src
[1] = reg_undef
;
2772 inst
->conditional_mod
= BRW_CONDITIONAL_NONE
;
2780 case BRW_CONDITIONAL_GE
:
2781 case BRW_CONDITIONAL_G
:
2782 switch (inst
->src
[1].type
) {
2783 case BRW_REGISTER_TYPE_F
:
2784 if (inst
->src
[1].f
<= 0.0f
) {
2785 inst
->opcode
= BRW_OPCODE_MOV
;
2786 inst
->src
[1] = reg_undef
;
2787 inst
->conditional_mod
= BRW_CONDITIONAL_NONE
;
2799 case BRW_OPCODE_MAD
:
2800 if (inst
->src
[0].type
!= BRW_REGISTER_TYPE_F
||
2801 inst
->src
[1].type
!= BRW_REGISTER_TYPE_F
||
2802 inst
->src
[2].type
!= BRW_REGISTER_TYPE_F
)
2804 if (inst
->src
[1].is_one()) {
2805 inst
->opcode
= BRW_OPCODE_ADD
;
2806 inst
->src
[1] = inst
->src
[2];
2807 inst
->src
[2] = reg_undef
;
2809 } else if (inst
->src
[2].is_one()) {
2810 inst
->opcode
= BRW_OPCODE_ADD
;
2811 inst
->src
[2] = reg_undef
;
2815 case SHADER_OPCODE_BROADCAST
:
2816 if (is_uniform(inst
->src
[0])) {
2817 inst
->opcode
= BRW_OPCODE_MOV
;
2819 inst
->force_writemask_all
= true;
2821 } else if (inst
->src
[1].file
== IMM
) {
2822 inst
->opcode
= BRW_OPCODE_MOV
;
2823 /* It's possible that the selected component will be too large and
2824 * overflow the register. This can happen if someone does a
2825 * readInvocation() from GLSL or SPIR-V and provides an OOB
2826 * invocationIndex. If this happens and we some how manage
2827 * to constant fold it in and get here, then component() may cause
2828 * us to start reading outside of the VGRF which will lead to an
2829 * assert later. Instead, just let it wrap around if it goes over
2832 const unsigned comp
= inst
->src
[1].ud
& (inst
->exec_size
- 1);
2833 inst
->src
[0] = component(inst
->src
[0], comp
);
2835 inst
->force_writemask_all
= true;
2840 case SHADER_OPCODE_SHUFFLE
:
2841 if (is_uniform(inst
->src
[0])) {
2842 inst
->opcode
= BRW_OPCODE_MOV
;
2845 } else if (inst
->src
[1].file
== IMM
) {
2846 inst
->opcode
= BRW_OPCODE_MOV
;
2847 inst
->src
[0] = component(inst
->src
[0],
2858 /* Swap if src[0] is immediate. */
2859 if (progress
&& inst
->is_commutative()) {
2860 if (inst
->src
[0].file
== IMM
) {
2861 fs_reg tmp
= inst
->src
[1];
2862 inst
->src
[1] = inst
->src
[0];
2871 * Optimize sample messages that have constant zero values for the trailing
2872 * texture coordinates. We can just reduce the message length for these
2873 * instructions instead of reserving a register for it. Trailing parameters
2874 * that aren't sent default to zero anyway. This will cause the dead code
2875 * eliminator to remove the MOV instruction that would otherwise be emitted to
2876 * set up the zero value.
2879 fs_visitor::opt_zero_samples()
2881 /* Gen4 infers the texturing opcode based on the message length so we can't
2884 if (devinfo
->gen
< 5)
2887 bool progress
= false;
2889 foreach_block_and_inst(block
, fs_inst
, inst
, cfg
) {
2890 if (!inst
->is_tex())
2893 fs_inst
*load_payload
= (fs_inst
*) inst
->prev
;
2895 if (load_payload
->is_head_sentinel() ||
2896 load_payload
->opcode
!= SHADER_OPCODE_LOAD_PAYLOAD
)
2899 /* We don't want to remove the message header or the first parameter.
2900 * Removing the first parameter is not allowed, see the Haswell PRM
2901 * volume 7, page 149:
2903 * "Parameter 0 is required except for the sampleinfo message, which
2904 * has no parameter 0"
2906 while (inst
->mlen
> inst
->header_size
+ inst
->exec_size
/ 8 &&
2907 load_payload
->src
[(inst
->mlen
- inst
->header_size
) /
2908 (inst
->exec_size
/ 8) +
2909 inst
->header_size
- 1].is_zero()) {
2910 inst
->mlen
-= inst
->exec_size
/ 8;
2916 invalidate_live_intervals();
2922 * Optimize sample messages which are followed by the final RT write.
2924 * CHV, and GEN9+ can mark a texturing SEND instruction with EOT to have its
2925 * results sent directly to the framebuffer, bypassing the EU. Recognize the
2926 * final texturing results copied to the framebuffer write payload and modify
2927 * them to write to the framebuffer directly.
2930 fs_visitor::opt_sampler_eot()
2932 brw_wm_prog_key
*key
= (brw_wm_prog_key
*) this->key
;
2934 if (stage
!= MESA_SHADER_FRAGMENT
|| dispatch_width
> 16)
2937 if (devinfo
->gen
!= 9 && !devinfo
->is_cherryview
)
2940 /* FINISHME: It should be possible to implement this optimization when there
2941 * are multiple drawbuffers.
2943 if (key
->nr_color_regions
!= 1)
2946 /* Requires emitting a bunch of saturating MOV instructions during logical
2947 * send lowering to clamp the color payload, which the sampler unit isn't
2948 * going to do for us.
2950 if (key
->clamp_fragment_color
)
2953 /* Look for a texturing instruction immediately before the final FB_WRITE. */
2954 bblock_t
*block
= cfg
->blocks
[cfg
->num_blocks
- 1];
2955 fs_inst
*fb_write
= (fs_inst
*)block
->end();
2956 assert(fb_write
->eot
);
2957 assert(fb_write
->opcode
== FS_OPCODE_FB_WRITE_LOGICAL
);
2959 /* There wasn't one; nothing to do. */
2960 if (unlikely(fb_write
->prev
->is_head_sentinel()))
2963 fs_inst
*tex_inst
= (fs_inst
*) fb_write
->prev
;
2965 /* 3D Sampler » Messages » Message Format
2967 * “Response Length of zero is allowed on all SIMD8* and SIMD16* sampler
2968 * messages except sample+killpix, resinfo, sampleinfo, LOD, and gather4*”
2970 if (tex_inst
->opcode
!= SHADER_OPCODE_TEX_LOGICAL
&&
2971 tex_inst
->opcode
!= SHADER_OPCODE_TXD_LOGICAL
&&
2972 tex_inst
->opcode
!= SHADER_OPCODE_TXF_LOGICAL
&&
2973 tex_inst
->opcode
!= SHADER_OPCODE_TXL_LOGICAL
&&
2974 tex_inst
->opcode
!= FS_OPCODE_TXB_LOGICAL
&&
2975 tex_inst
->opcode
!= SHADER_OPCODE_TXF_CMS_LOGICAL
&&
2976 tex_inst
->opcode
!= SHADER_OPCODE_TXF_CMS_W_LOGICAL
&&
2977 tex_inst
->opcode
!= SHADER_OPCODE_TXF_UMS_LOGICAL
)
2980 /* XXX - This shouldn't be necessary. */
2981 if (tex_inst
->prev
->is_head_sentinel())
2984 /* Check that the FB write sources are fully initialized by the single
2985 * texturing instruction.
2987 for (unsigned i
= 0; i
< FB_WRITE_LOGICAL_NUM_SRCS
; i
++) {
2988 if (i
== FB_WRITE_LOGICAL_SRC_COLOR0
) {
2989 if (!fb_write
->src
[i
].equals(tex_inst
->dst
) ||
2990 fb_write
->size_read(i
) != tex_inst
->size_written
)
2992 } else if (i
!= FB_WRITE_LOGICAL_SRC_COMPONENTS
) {
2993 if (fb_write
->src
[i
].file
!= BAD_FILE
)
2998 assert(!tex_inst
->eot
); /* We can't get here twice */
2999 assert((tex_inst
->offset
& (0xff << 24)) == 0);
3001 const fs_builder
ibld(this, block
, tex_inst
);
3003 tex_inst
->offset
|= fb_write
->target
<< 24;
3004 tex_inst
->eot
= true;
3005 tex_inst
->dst
= ibld
.null_reg_ud();
3006 tex_inst
->size_written
= 0;
3007 fb_write
->remove(cfg
->blocks
[cfg
->num_blocks
- 1]);
3009 /* Marking EOT is sufficient, lower_logical_sends() will notice the EOT
3010 * flag and submit a header together with the sampler message as required
3013 invalidate_live_intervals();
3018 fs_visitor::opt_register_renaming()
3020 bool progress
= false;
3023 unsigned remap
[alloc
.count
];
3024 memset(remap
, ~0u, sizeof(unsigned) * alloc
.count
);
3026 foreach_block_and_inst(block
, fs_inst
, inst
, cfg
) {
3027 if (inst
->opcode
== BRW_OPCODE_IF
|| inst
->opcode
== BRW_OPCODE_DO
) {
3029 } else if (inst
->opcode
== BRW_OPCODE_ENDIF
||
3030 inst
->opcode
== BRW_OPCODE_WHILE
) {
3034 /* Rewrite instruction sources. */
3035 for (int i
= 0; i
< inst
->sources
; i
++) {
3036 if (inst
->src
[i
].file
== VGRF
&&
3037 remap
[inst
->src
[i
].nr
] != ~0u &&
3038 remap
[inst
->src
[i
].nr
] != inst
->src
[i
].nr
) {
3039 inst
->src
[i
].nr
= remap
[inst
->src
[i
].nr
];
3044 const unsigned dst
= inst
->dst
.nr
;
3047 inst
->dst
.file
== VGRF
&&
3048 alloc
.sizes
[inst
->dst
.nr
] * REG_SIZE
== inst
->size_written
&&
3049 !inst
->is_partial_write()) {
3050 if (remap
[dst
] == ~0u) {
3053 remap
[dst
] = alloc
.allocate(regs_written(inst
));
3054 inst
->dst
.nr
= remap
[dst
];
3057 } else if (inst
->dst
.file
== VGRF
&&
3058 remap
[dst
] != ~0u &&
3059 remap
[dst
] != dst
) {
3060 inst
->dst
.nr
= remap
[dst
];
3066 invalidate_live_intervals();
3068 for (unsigned i
= 0; i
< ARRAY_SIZE(delta_xy
); i
++) {
3069 if (delta_xy
[i
].file
== VGRF
&& remap
[delta_xy
[i
].nr
] != ~0u) {
3070 delta_xy
[i
].nr
= remap
[delta_xy
[i
].nr
];
3079 * Remove redundant or useless discard jumps.
3081 * For example, we can eliminate jumps in the following sequence:
3083 * discard-jump (redundant with the next jump)
3084 * discard-jump (useless; jumps to the next instruction)
3088 fs_visitor::opt_redundant_discard_jumps()
3090 bool progress
= false;
3092 bblock_t
*last_bblock
= cfg
->blocks
[cfg
->num_blocks
- 1];
3094 fs_inst
*placeholder_halt
= NULL
;
3095 foreach_inst_in_block_reverse(fs_inst
, inst
, last_bblock
) {
3096 if (inst
->opcode
== FS_OPCODE_PLACEHOLDER_HALT
) {
3097 placeholder_halt
= inst
;
3102 if (!placeholder_halt
)
3105 /* Delete any HALTs immediately before the placeholder halt. */
3106 for (fs_inst
*prev
= (fs_inst
*) placeholder_halt
->prev
;
3107 !prev
->is_head_sentinel() && prev
->opcode
== FS_OPCODE_DISCARD_JUMP
;
3108 prev
= (fs_inst
*) placeholder_halt
->prev
) {
3109 prev
->remove(last_bblock
);
3114 invalidate_live_intervals();
3120 * Compute a bitmask with GRF granularity with a bit set for each GRF starting
3121 * from \p r.offset which overlaps the region starting at \p s.offset and
3122 * spanning \p ds bytes.
3124 static inline unsigned
3125 mask_relative_to(const fs_reg
&r
, const fs_reg
&s
, unsigned ds
)
3127 const int rel_offset
= reg_offset(s
) - reg_offset(r
);
3128 const int shift
= rel_offset
/ REG_SIZE
;
3129 const unsigned n
= DIV_ROUND_UP(rel_offset
% REG_SIZE
+ ds
, REG_SIZE
);
3130 assert(reg_space(r
) == reg_space(s
) &&
3131 shift
>= 0 && shift
< int(8 * sizeof(unsigned)));
3132 return ((1 << n
) - 1) << shift
;
3136 fs_visitor::opt_peephole_csel()
3138 if (devinfo
->gen
< 8)
3141 bool progress
= false;
3143 foreach_block_reverse(block
, cfg
) {
3144 int ip
= block
->end_ip
+ 1;
3146 foreach_inst_in_block_reverse_safe(fs_inst
, inst
, block
) {
3149 if (inst
->opcode
!= BRW_OPCODE_SEL
||
3150 inst
->predicate
!= BRW_PREDICATE_NORMAL
||
3151 (inst
->dst
.type
!= BRW_REGISTER_TYPE_F
&&
3152 inst
->dst
.type
!= BRW_REGISTER_TYPE_D
&&
3153 inst
->dst
.type
!= BRW_REGISTER_TYPE_UD
))
3156 /* Because it is a 3-src instruction, CSEL cannot have an immediate
3157 * value as a source, but we can sometimes handle zero.
3159 if ((inst
->src
[0].file
!= VGRF
&& inst
->src
[0].file
!= ATTR
&&
3160 inst
->src
[0].file
!= UNIFORM
) ||
3161 (inst
->src
[1].file
!= VGRF
&& inst
->src
[1].file
!= ATTR
&&
3162 inst
->src
[1].file
!= UNIFORM
&& !inst
->src
[1].is_zero()))
3165 foreach_inst_in_block_reverse_starting_from(fs_inst
, scan_inst
, inst
) {
3166 if (!scan_inst
->flags_written())
3169 if ((scan_inst
->opcode
!= BRW_OPCODE_CMP
&&
3170 scan_inst
->opcode
!= BRW_OPCODE_MOV
) ||
3171 scan_inst
->predicate
!= BRW_PREDICATE_NONE
||
3172 (scan_inst
->src
[0].file
!= VGRF
&&
3173 scan_inst
->src
[0].file
!= ATTR
&&
3174 scan_inst
->src
[0].file
!= UNIFORM
) ||
3175 scan_inst
->src
[0].type
!= BRW_REGISTER_TYPE_F
)
3178 if (scan_inst
->opcode
== BRW_OPCODE_CMP
&& !scan_inst
->src
[1].is_zero())
3181 const brw::fs_builder
ibld(this, block
, inst
);
3183 const enum brw_conditional_mod cond
=
3184 inst
->predicate_inverse
3185 ? brw_negate_cmod(scan_inst
->conditional_mod
)
3186 : scan_inst
->conditional_mod
;
3188 fs_inst
*csel_inst
= NULL
;
3190 if (inst
->src
[1].file
!= IMM
) {
3191 csel_inst
= ibld
.CSEL(inst
->dst
,
3196 } else if (cond
== BRW_CONDITIONAL_NZ
) {
3197 /* Consider the sequence
3199 * cmp.nz.f0 null<1>F g3<8,8,1>F 0F
3200 * (+f0) sel g124<1>UD g2<8,8,1>UD 0x00000000UD
3202 * The sel will pick the immediate value 0 if r0 is ±0.0.
3203 * Therefore, this sequence is equivalent:
3205 * cmp.nz.f0 null<1>F g3<8,8,1>F 0F
3206 * (+f0) sel g124<1>F g2<8,8,1>F (abs)g3<8,8,1>F
3208 * The abs is ensures that the result is 0UD when g3 is -0.0F.
3209 * By normal cmp-sel merging, this is also equivalent:
3211 * csel.nz g124<1>F g2<4,4,1>F (abs)g3<4,4,1>F g3<4,4,1>F
3213 csel_inst
= ibld
.CSEL(inst
->dst
,
3219 csel_inst
->src
[1].abs
= true;
3222 if (csel_inst
!= NULL
) {
3224 csel_inst
->saturate
= inst
->saturate
;
3225 inst
->remove(block
);
3237 fs_visitor::compute_to_mrf()
3239 bool progress
= false;
3242 /* No MRFs on Gen >= 7. */
3243 if (devinfo
->gen
>= 7)
3246 calculate_live_intervals();
3248 foreach_block_and_inst_safe(block
, fs_inst
, inst
, cfg
) {
3252 if (inst
->opcode
!= BRW_OPCODE_MOV
||
3253 inst
->is_partial_write() ||
3254 inst
->dst
.file
!= MRF
|| inst
->src
[0].file
!= VGRF
||
3255 inst
->dst
.type
!= inst
->src
[0].type
||
3256 inst
->src
[0].abs
|| inst
->src
[0].negate
||
3257 !inst
->src
[0].is_contiguous() ||
3258 inst
->src
[0].offset
% REG_SIZE
!= 0)
3261 /* Can't compute-to-MRF this GRF if someone else was going to
3264 if (this->virtual_grf_end
[inst
->src
[0].nr
] > ip
)
3267 /* Found a move of a GRF to a MRF. Let's see if we can go rewrite the
3268 * things that computed the value of all GRFs of the source region. The
3269 * regs_left bitset keeps track of the registers we haven't yet found a
3270 * generating instruction for.
3272 unsigned regs_left
= (1 << regs_read(inst
, 0)) - 1;
3274 foreach_inst_in_block_reverse_starting_from(fs_inst
, scan_inst
, inst
) {
3275 if (regions_overlap(scan_inst
->dst
, scan_inst
->size_written
,
3276 inst
->src
[0], inst
->size_read(0))) {
3277 /* Found the last thing to write our reg we want to turn
3278 * into a compute-to-MRF.
3281 /* If this one instruction didn't populate all the
3282 * channels, bail. We might be able to rewrite everything
3283 * that writes that reg, but it would require smarter
3286 if (scan_inst
->is_partial_write())
3289 /* Handling things not fully contained in the source of the copy
3290 * would need us to understand coalescing out more than one MOV at
3293 if (!region_contained_in(scan_inst
->dst
, scan_inst
->size_written
,
3294 inst
->src
[0], inst
->size_read(0)))
3297 /* SEND instructions can't have MRF as a destination. */
3298 if (scan_inst
->mlen
)
3301 if (devinfo
->gen
== 6) {
3302 /* gen6 math instructions must have the destination be
3303 * GRF, so no compute-to-MRF for them.
3305 if (scan_inst
->is_math()) {
3310 /* Clear the bits for any registers this instruction overwrites. */
3311 regs_left
&= ~mask_relative_to(
3312 inst
->src
[0], scan_inst
->dst
, scan_inst
->size_written
);
3317 /* We don't handle control flow here. Most computation of
3318 * values that end up in MRFs are shortly before the MRF
3321 if (block
->start() == scan_inst
)
3324 /* You can't read from an MRF, so if someone else reads our
3325 * MRF's source GRF that we wanted to rewrite, that stops us.
3327 bool interfered
= false;
3328 for (int i
= 0; i
< scan_inst
->sources
; i
++) {
3329 if (regions_overlap(scan_inst
->src
[i
], scan_inst
->size_read(i
),
3330 inst
->src
[0], inst
->size_read(0))) {
3337 if (regions_overlap(scan_inst
->dst
, scan_inst
->size_written
,
3338 inst
->dst
, inst
->size_written
)) {
3339 /* If somebody else writes our MRF here, we can't
3340 * compute-to-MRF before that.
3345 if (scan_inst
->mlen
> 0 && scan_inst
->base_mrf
!= -1 &&
3346 regions_overlap(fs_reg(MRF
, scan_inst
->base_mrf
), scan_inst
->mlen
* REG_SIZE
,
3347 inst
->dst
, inst
->size_written
)) {
3348 /* Found a SEND instruction, which means that there are
3349 * live values in MRFs from base_mrf to base_mrf +
3350 * scan_inst->mlen - 1. Don't go pushing our MRF write up
3360 /* Found all generating instructions of our MRF's source value, so it
3361 * should be safe to rewrite them to point to the MRF directly.
3363 regs_left
= (1 << regs_read(inst
, 0)) - 1;
3365 foreach_inst_in_block_reverse_starting_from(fs_inst
, scan_inst
, inst
) {
3366 if (regions_overlap(scan_inst
->dst
, scan_inst
->size_written
,
3367 inst
->src
[0], inst
->size_read(0))) {
3368 /* Clear the bits for any registers this instruction overwrites. */
3369 regs_left
&= ~mask_relative_to(
3370 inst
->src
[0], scan_inst
->dst
, scan_inst
->size_written
);
3372 const unsigned rel_offset
= reg_offset(scan_inst
->dst
) -
3373 reg_offset(inst
->src
[0]);
3375 if (inst
->dst
.nr
& BRW_MRF_COMPR4
) {
3376 /* Apply the same address transformation done by the hardware
3377 * for COMPR4 MRF writes.
3379 assert(rel_offset
< 2 * REG_SIZE
);
3380 scan_inst
->dst
.nr
= inst
->dst
.nr
+ rel_offset
/ REG_SIZE
* 4;
3382 /* Clear the COMPR4 bit if the generating instruction is not
3385 if (scan_inst
->size_written
< 2 * REG_SIZE
)
3386 scan_inst
->dst
.nr
&= ~BRW_MRF_COMPR4
;
3389 /* Calculate the MRF number the result of this instruction is
3390 * ultimately written to.
3392 scan_inst
->dst
.nr
= inst
->dst
.nr
+ rel_offset
/ REG_SIZE
;
3395 scan_inst
->dst
.file
= MRF
;
3396 scan_inst
->dst
.offset
= inst
->dst
.offset
+ rel_offset
% REG_SIZE
;
3397 scan_inst
->saturate
|= inst
->saturate
;
3404 inst
->remove(block
);
3409 invalidate_live_intervals();
3415 * Eliminate FIND_LIVE_CHANNEL instructions occurring outside any control
3416 * flow. We could probably do better here with some form of divergence
3420 fs_visitor::eliminate_find_live_channel()
3422 bool progress
= false;
3425 if (!brw_stage_has_packed_dispatch(devinfo
, stage
, stage_prog_data
)) {
3426 /* The optimization below assumes that channel zero is live on thread
3427 * dispatch, which may not be the case if the fixed function dispatches
3433 foreach_block_and_inst_safe(block
, fs_inst
, inst
, cfg
) {
3434 switch (inst
->opcode
) {
3440 case BRW_OPCODE_ENDIF
:
3441 case BRW_OPCODE_WHILE
:
3445 case FS_OPCODE_DISCARD_JUMP
:
3446 /* This can potentially make control flow non-uniform until the end
3451 case SHADER_OPCODE_FIND_LIVE_CHANNEL
:
3453 inst
->opcode
= BRW_OPCODE_MOV
;
3454 inst
->src
[0] = brw_imm_ud(0u);
3456 inst
->force_writemask_all
= true;
3470 * Once we've generated code, try to convert normal FS_OPCODE_FB_WRITE
3471 * instructions to FS_OPCODE_REP_FB_WRITE.
3474 fs_visitor::emit_repclear_shader()
3476 brw_wm_prog_key
*key
= (brw_wm_prog_key
*) this->key
;
3478 int color_mrf
= base_mrf
+ 2;
3482 mov
= bld
.exec_all().group(4, 0)
3483 .MOV(brw_message_reg(color_mrf
),
3484 fs_reg(UNIFORM
, 0, BRW_REGISTER_TYPE_F
));
3486 struct brw_reg reg
=
3487 brw_reg(BRW_GENERAL_REGISTER_FILE
, 2, 3, 0, 0, BRW_REGISTER_TYPE_F
,
3488 BRW_VERTICAL_STRIDE_8
, BRW_WIDTH_2
, BRW_HORIZONTAL_STRIDE_4
,
3489 BRW_SWIZZLE_XYZW
, WRITEMASK_XYZW
);
3491 mov
= bld
.exec_all().group(4, 0)
3492 .MOV(vec4(brw_message_reg(color_mrf
)), fs_reg(reg
));
3495 fs_inst
*write
= NULL
;
3496 if (key
->nr_color_regions
== 1) {
3497 write
= bld
.emit(FS_OPCODE_REP_FB_WRITE
);
3498 write
->saturate
= key
->clamp_fragment_color
;
3499 write
->base_mrf
= color_mrf
;
3501 write
->header_size
= 0;
3504 assume(key
->nr_color_regions
> 0);
3506 struct brw_reg header
=
3507 retype(brw_message_reg(base_mrf
), BRW_REGISTER_TYPE_UD
);
3508 bld
.exec_all().group(16, 0)
3509 .MOV(header
, retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_UD
));
3511 for (int i
= 0; i
< key
->nr_color_regions
; ++i
) {
3513 bld
.exec_all().group(1, 0)
3514 .MOV(component(header
, 2), brw_imm_ud(i
));
3517 write
= bld
.emit(FS_OPCODE_REP_FB_WRITE
);
3518 write
->saturate
= key
->clamp_fragment_color
;
3519 write
->base_mrf
= base_mrf
;
3521 write
->header_size
= 2;
3526 write
->last_rt
= true;
3530 assign_constant_locations();
3531 assign_curb_setup();
3533 /* Now that we have the uniform assigned, go ahead and force it to a vec4. */
3535 assert(mov
->src
[0].file
== FIXED_GRF
);
3536 mov
->src
[0] = brw_vec4_grf(mov
->src
[0].nr
, 0);
3543 * Walks through basic blocks, looking for repeated MRF writes and
3544 * removing the later ones.
3547 fs_visitor::remove_duplicate_mrf_writes()
3549 fs_inst
*last_mrf_move
[BRW_MAX_MRF(devinfo
->gen
)];
3550 bool progress
= false;
3552 /* Need to update the MRF tracking for compressed instructions. */
3553 if (dispatch_width
>= 16)
3556 memset(last_mrf_move
, 0, sizeof(last_mrf_move
));
3558 foreach_block_and_inst_safe (block
, fs_inst
, inst
, cfg
) {
3559 if (inst
->is_control_flow()) {
3560 memset(last_mrf_move
, 0, sizeof(last_mrf_move
));
3563 if (inst
->opcode
== BRW_OPCODE_MOV
&&
3564 inst
->dst
.file
== MRF
) {
3565 fs_inst
*prev_inst
= last_mrf_move
[inst
->dst
.nr
];
3566 if (prev_inst
&& prev_inst
->opcode
== BRW_OPCODE_MOV
&&
3567 inst
->dst
.equals(prev_inst
->dst
) &&
3568 inst
->src
[0].equals(prev_inst
->src
[0]) &&
3569 inst
->saturate
== prev_inst
->saturate
&&
3570 inst
->predicate
== prev_inst
->predicate
&&
3571 inst
->conditional_mod
== prev_inst
->conditional_mod
&&
3572 inst
->exec_size
== prev_inst
->exec_size
) {
3573 inst
->remove(block
);
3579 /* Clear out the last-write records for MRFs that were overwritten. */
3580 if (inst
->dst
.file
== MRF
) {
3581 last_mrf_move
[inst
->dst
.nr
] = NULL
;
3584 if (inst
->mlen
> 0 && inst
->base_mrf
!= -1) {
3585 /* Found a SEND instruction, which will include two or fewer
3586 * implied MRF writes. We could do better here.
3588 for (int i
= 0; i
< implied_mrf_writes(inst
); i
++) {
3589 last_mrf_move
[inst
->base_mrf
+ i
] = NULL
;
3593 /* Clear out any MRF move records whose sources got overwritten. */
3594 for (unsigned i
= 0; i
< ARRAY_SIZE(last_mrf_move
); i
++) {
3595 if (last_mrf_move
[i
] &&
3596 regions_overlap(inst
->dst
, inst
->size_written
,
3597 last_mrf_move
[i
]->src
[0],
3598 last_mrf_move
[i
]->size_read(0))) {
3599 last_mrf_move
[i
] = NULL
;
3603 if (inst
->opcode
== BRW_OPCODE_MOV
&&
3604 inst
->dst
.file
== MRF
&&
3605 inst
->src
[0].file
!= ARF
&&
3606 !inst
->is_partial_write()) {
3607 last_mrf_move
[inst
->dst
.nr
] = inst
;
3612 invalidate_live_intervals();
3618 * Rounding modes for conversion instructions are included for each
3619 * conversion, but right now it is a state. So once it is set,
3620 * we don't need to call it again for subsequent calls.
3622 * This is useful for vector/matrices conversions, as setting the
3623 * mode once is enough for the full vector/matrix
3626 fs_visitor::remove_extra_rounding_modes()
3628 bool progress
= false;
3629 unsigned execution_mode
= this->nir
->info
.float_controls_execution_mode
;
3631 brw_rnd_mode base_mode
= BRW_RND_MODE_UNSPECIFIED
;
3632 if ((FLOAT_CONTROLS_ROUNDING_MODE_RTE_FP16
|
3633 FLOAT_CONTROLS_ROUNDING_MODE_RTE_FP32
|
3634 FLOAT_CONTROLS_ROUNDING_MODE_RTE_FP64
) &
3636 base_mode
= BRW_RND_MODE_RTNE
;
3637 if ((FLOAT_CONTROLS_ROUNDING_MODE_RTZ_FP16
|
3638 FLOAT_CONTROLS_ROUNDING_MODE_RTZ_FP32
|
3639 FLOAT_CONTROLS_ROUNDING_MODE_RTZ_FP64
) &
3641 base_mode
= BRW_RND_MODE_RTZ
;
3643 foreach_block (block
, cfg
) {
3644 brw_rnd_mode prev_mode
= base_mode
;
3646 foreach_inst_in_block_safe (fs_inst
, inst
, block
) {
3647 if (inst
->opcode
== SHADER_OPCODE_RND_MODE
) {
3648 assert(inst
->src
[0].file
== BRW_IMMEDIATE_VALUE
);
3649 const brw_rnd_mode mode
= (brw_rnd_mode
) inst
->src
[0].d
;
3650 if (mode
== prev_mode
) {
3651 inst
->remove(block
);
3661 invalidate_live_intervals();
3667 clear_deps_for_inst_src(fs_inst
*inst
, bool *deps
, int first_grf
, int grf_len
)
3669 /* Clear the flag for registers that actually got read (as expected). */
3670 for (int i
= 0; i
< inst
->sources
; i
++) {
3672 if (inst
->src
[i
].file
== VGRF
|| inst
->src
[i
].file
== FIXED_GRF
) {
3673 grf
= inst
->src
[i
].nr
;
3678 if (grf
>= first_grf
&&
3679 grf
< first_grf
+ grf_len
) {
3680 deps
[grf
- first_grf
] = false;
3681 if (inst
->exec_size
== 16)
3682 deps
[grf
- first_grf
+ 1] = false;
3688 * Implements this workaround for the original 965:
3690 * "[DevBW, DevCL] Implementation Restrictions: As the hardware does not
3691 * check for post destination dependencies on this instruction, software
3692 * must ensure that there is no destination hazard for the case of ‘write
3693 * followed by a posted write’ shown in the following example.
3696 * 2. send r3.xy <rest of send instruction>
3699 * Due to no post-destination dependency check on the ‘send’, the above
3700 * code sequence could have two instructions (1 and 2) in flight at the
3701 * same time that both consider ‘r3’ as the target of their final writes.
3704 fs_visitor::insert_gen4_pre_send_dependency_workarounds(bblock_t
*block
,
3707 int write_len
= regs_written(inst
);
3708 int first_write_grf
= inst
->dst
.nr
;
3709 bool needs_dep
[BRW_MAX_MRF(devinfo
->gen
)];
3710 assert(write_len
< (int)sizeof(needs_dep
) - 1);
3712 memset(needs_dep
, false, sizeof(needs_dep
));
3713 memset(needs_dep
, true, write_len
);
3715 clear_deps_for_inst_src(inst
, needs_dep
, first_write_grf
, write_len
);
3717 /* Walk backwards looking for writes to registers we're writing which
3718 * aren't read since being written. If we hit the start of the program,
3719 * we assume that there are no outstanding dependencies on entry to the
3722 foreach_inst_in_block_reverse_starting_from(fs_inst
, scan_inst
, inst
) {
3723 /* If we hit control flow, assume that there *are* outstanding
3724 * dependencies, and force their cleanup before our instruction.
3726 if (block
->start() == scan_inst
&& block
->num
!= 0) {
3727 for (int i
= 0; i
< write_len
; i
++) {
3729 DEP_RESOLVE_MOV(fs_builder(this, block
, inst
),
3730 first_write_grf
+ i
);
3735 /* We insert our reads as late as possible on the assumption that any
3736 * instruction but a MOV that might have left us an outstanding
3737 * dependency has more latency than a MOV.
3739 if (scan_inst
->dst
.file
== VGRF
) {
3740 for (unsigned i
= 0; i
< regs_written(scan_inst
); i
++) {
3741 int reg
= scan_inst
->dst
.nr
+ i
;
3743 if (reg
>= first_write_grf
&&
3744 reg
< first_write_grf
+ write_len
&&
3745 needs_dep
[reg
- first_write_grf
]) {
3746 DEP_RESOLVE_MOV(fs_builder(this, block
, inst
), reg
);
3747 needs_dep
[reg
- first_write_grf
] = false;
3748 if (scan_inst
->exec_size
== 16)
3749 needs_dep
[reg
- first_write_grf
+ 1] = false;
3754 /* Clear the flag for registers that actually got read (as expected). */
3755 clear_deps_for_inst_src(scan_inst
, needs_dep
, first_write_grf
, write_len
);
3757 /* Continue the loop only if we haven't resolved all the dependencies */
3759 for (i
= 0; i
< write_len
; i
++) {
3769 * Implements this workaround for the original 965:
3771 * "[DevBW, DevCL] Errata: A destination register from a send can not be
3772 * used as a destination register until after it has been sourced by an
3773 * instruction with a different destination register.
3776 fs_visitor::insert_gen4_post_send_dependency_workarounds(bblock_t
*block
, fs_inst
*inst
)
3778 int write_len
= regs_written(inst
);
3779 unsigned first_write_grf
= inst
->dst
.nr
;
3780 bool needs_dep
[BRW_MAX_MRF(devinfo
->gen
)];
3781 assert(write_len
< (int)sizeof(needs_dep
) - 1);
3783 memset(needs_dep
, false, sizeof(needs_dep
));
3784 memset(needs_dep
, true, write_len
);
3785 /* Walk forwards looking for writes to registers we're writing which aren't
3786 * read before being written.
3788 foreach_inst_in_block_starting_from(fs_inst
, scan_inst
, inst
) {
3789 /* If we hit control flow, force resolve all remaining dependencies. */
3790 if (block
->end() == scan_inst
&& block
->num
!= cfg
->num_blocks
- 1) {
3791 for (int i
= 0; i
< write_len
; i
++) {
3793 DEP_RESOLVE_MOV(fs_builder(this, block
, scan_inst
),
3794 first_write_grf
+ i
);
3799 /* Clear the flag for registers that actually got read (as expected). */
3800 clear_deps_for_inst_src(scan_inst
, needs_dep
, first_write_grf
, write_len
);
3802 /* We insert our reads as late as possible since they're reading the
3803 * result of a SEND, which has massive latency.
3805 if (scan_inst
->dst
.file
== VGRF
&&
3806 scan_inst
->dst
.nr
>= first_write_grf
&&
3807 scan_inst
->dst
.nr
< first_write_grf
+ write_len
&&
3808 needs_dep
[scan_inst
->dst
.nr
- first_write_grf
]) {
3809 DEP_RESOLVE_MOV(fs_builder(this, block
, scan_inst
),
3811 needs_dep
[scan_inst
->dst
.nr
- first_write_grf
] = false;
3814 /* Continue the loop only if we haven't resolved all the dependencies */
3816 for (i
= 0; i
< write_len
; i
++) {
3826 fs_visitor::insert_gen4_send_dependency_workarounds()
3828 if (devinfo
->gen
!= 4 || devinfo
->is_g4x
)
3831 bool progress
= false;
3833 foreach_block_and_inst(block
, fs_inst
, inst
, cfg
) {
3834 if (inst
->mlen
!= 0 && inst
->dst
.file
== VGRF
) {
3835 insert_gen4_pre_send_dependency_workarounds(block
, inst
);
3836 insert_gen4_post_send_dependency_workarounds(block
, inst
);
3842 invalidate_live_intervals();
3846 * Turns the generic expression-style uniform pull constant load instruction
3847 * into a hardware-specific series of instructions for loading a pull
3850 * The expression style allows the CSE pass before this to optimize out
3851 * repeated loads from the same offset, and gives the pre-register-allocation
3852 * scheduling full flexibility, while the conversion to native instructions
3853 * allows the post-register-allocation scheduler the best information
3856 * Note that execution masking for setting up pull constant loads is special:
3857 * the channels that need to be written are unrelated to the current execution
3858 * mask, since a later instruction will use one of the result channels as a
3859 * source operand for all 8 or 16 of its channels.
3862 fs_visitor::lower_uniform_pull_constant_loads()
3864 foreach_block_and_inst (block
, fs_inst
, inst
, cfg
) {
3865 if (inst
->opcode
!= FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD
)
3868 if (devinfo
->gen
>= 7) {
3869 const fs_builder ubld
= fs_builder(this, block
, inst
).exec_all();
3870 const fs_reg payload
= ubld
.group(8, 0).vgrf(BRW_REGISTER_TYPE_UD
);
3872 ubld
.group(8, 0).MOV(payload
,
3873 retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_UD
));
3874 ubld
.group(1, 0).MOV(component(payload
, 2),
3875 brw_imm_ud(inst
->src
[1].ud
/ 16));
3877 inst
->opcode
= FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD_GEN7
;
3878 inst
->src
[1] = payload
;
3879 inst
->header_size
= 1;
3882 invalidate_live_intervals();
3884 /* Before register allocation, we didn't tell the scheduler about the
3885 * MRF we use. We know it's safe to use this MRF because nothing
3886 * else does except for register spill/unspill, which generates and
3887 * uses its MRF within a single IR instruction.
3889 inst
->base_mrf
= FIRST_PULL_LOAD_MRF(devinfo
->gen
) + 1;
3896 fs_visitor::lower_load_payload()
3898 bool progress
= false;
3900 foreach_block_and_inst_safe (block
, fs_inst
, inst
, cfg
) {
3901 if (inst
->opcode
!= SHADER_OPCODE_LOAD_PAYLOAD
)
3904 assert(inst
->dst
.file
== MRF
|| inst
->dst
.file
== VGRF
);
3905 assert(inst
->saturate
== false);
3906 fs_reg dst
= inst
->dst
;
3908 /* Get rid of COMPR4. We'll add it back in if we need it */
3909 if (dst
.file
== MRF
)
3910 dst
.nr
= dst
.nr
& ~BRW_MRF_COMPR4
;
3912 const fs_builder
ibld(this, block
, inst
);
3913 const fs_builder hbld
= ibld
.exec_all().group(8, 0);
3915 for (uint8_t i
= 0; i
< inst
->header_size
; i
++) {
3916 if (inst
->src
[i
].file
!= BAD_FILE
) {
3917 fs_reg mov_dst
= retype(dst
, BRW_REGISTER_TYPE_UD
);
3918 fs_reg mov_src
= retype(inst
->src
[i
], BRW_REGISTER_TYPE_UD
);
3919 hbld
.MOV(mov_dst
, mov_src
);
3921 dst
= offset(dst
, hbld
, 1);
3924 if (inst
->dst
.file
== MRF
&& (inst
->dst
.nr
& BRW_MRF_COMPR4
) &&
3925 inst
->exec_size
> 8) {
3926 /* In this case, the payload portion of the LOAD_PAYLOAD isn't
3927 * a straightforward copy. Instead, the result of the
3928 * LOAD_PAYLOAD is treated as interleaved and the first four
3929 * non-header sources are unpacked as:
3940 * This is used for gen <= 5 fb writes.
3942 assert(inst
->exec_size
== 16);
3943 assert(inst
->header_size
+ 4 <= inst
->sources
);
3944 for (uint8_t i
= inst
->header_size
; i
< inst
->header_size
+ 4; i
++) {
3945 if (inst
->src
[i
].file
!= BAD_FILE
) {
3946 if (devinfo
->has_compr4
) {
3947 fs_reg compr4_dst
= retype(dst
, inst
->src
[i
].type
);
3948 compr4_dst
.nr
|= BRW_MRF_COMPR4
;
3949 ibld
.MOV(compr4_dst
, inst
->src
[i
]);
3951 /* Platform doesn't have COMPR4. We have to fake it */
3952 fs_reg mov_dst
= retype(dst
, inst
->src
[i
].type
);
3953 ibld
.half(0).MOV(mov_dst
, half(inst
->src
[i
], 0));
3955 ibld
.half(1).MOV(mov_dst
, half(inst
->src
[i
], 1));
3962 /* The loop above only ever incremented us through the first set
3963 * of 4 registers. However, thanks to the magic of COMPR4, we
3964 * actually wrote to the first 8 registers, so we need to take
3965 * that into account now.
3969 /* The COMPR4 code took care of the first 4 sources. We'll let
3970 * the regular path handle any remaining sources. Yes, we are
3971 * modifying the instruction but we're about to delete it so
3972 * this really doesn't hurt anything.
3974 inst
->header_size
+= 4;
3977 for (uint8_t i
= inst
->header_size
; i
< inst
->sources
; i
++) {
3978 if (inst
->src
[i
].file
!= BAD_FILE
) {
3979 dst
.type
= inst
->src
[i
].type
;
3980 ibld
.MOV(dst
, inst
->src
[i
]);
3982 dst
.type
= BRW_REGISTER_TYPE_UD
;
3984 dst
= offset(dst
, ibld
, 1);
3987 inst
->remove(block
);
3992 invalidate_live_intervals();
3998 fs_visitor::lower_mul_dword_inst(fs_inst
*inst
, bblock_t
*block
)
4000 const fs_builder
ibld(this, block
, inst
);
4002 if (inst
->src
[1].file
== IMM
&& inst
->src
[1].ud
< (1 << 16)) {
4003 /* The MUL instruction isn't commutative. On Gen <= 6, only the low
4004 * 16-bits of src0 are read, and on Gen >= 7 only the low 16-bits of
4007 * If multiplying by an immediate value that fits in 16-bits, do a
4008 * single MUL instruction with that value in the proper location.
4010 if (devinfo
->gen
< 7) {
4011 fs_reg
imm(VGRF
, alloc
.allocate(dispatch_width
/ 8), inst
->dst
.type
);
4012 ibld
.MOV(imm
, inst
->src
[1]);
4013 ibld
.MUL(inst
->dst
, imm
, inst
->src
[0]);
4015 const bool ud
= (inst
->src
[1].type
== BRW_REGISTER_TYPE_UD
);
4016 ibld
.MUL(inst
->dst
, inst
->src
[0],
4017 ud
? brw_imm_uw(inst
->src
[1].ud
)
4018 : brw_imm_w(inst
->src
[1].d
));
4021 /* Gen < 8 (and some Gen8+ low-power parts like Cherryview) cannot
4022 * do 32-bit integer multiplication in one instruction, but instead
4023 * must do a sequence (which actually calculates a 64-bit result):
4025 * mul(8) acc0<1>D g3<8,8,1>D g4<8,8,1>D
4026 * mach(8) null g3<8,8,1>D g4<8,8,1>D
4027 * mov(8) g2<1>D acc0<8,8,1>D
4029 * But on Gen > 6, the ability to use second accumulator register
4030 * (acc1) for non-float data types was removed, preventing a simple
4031 * implementation in SIMD16. A 16-channel result can be calculated by
4032 * executing the three instructions twice in SIMD8, once with quarter
4033 * control of 1Q for the first eight channels and again with 2Q for
4034 * the second eight channels.
4036 * Which accumulator register is implicitly accessed (by AccWrEnable
4037 * for instance) is determined by the quarter control. Unfortunately
4038 * Ivybridge (and presumably Baytrail) has a hardware bug in which an
4039 * implicit accumulator access by an instruction with 2Q will access
4040 * acc1 regardless of whether the data type is usable in acc1.
4042 * Specifically, the 2Q mach(8) writes acc1 which does not exist for
4043 * integer data types.
4045 * Since we only want the low 32-bits of the result, we can do two
4046 * 32-bit x 16-bit multiplies (like the mul and mach are doing), and
4047 * adjust the high result and add them (like the mach is doing):
4049 * mul(8) g7<1>D g3<8,8,1>D g4.0<8,8,1>UW
4050 * mul(8) g8<1>D g3<8,8,1>D g4.1<8,8,1>UW
4051 * shl(8) g9<1>D g8<8,8,1>D 16D
4052 * add(8) g2<1>D g7<8,8,1>D g8<8,8,1>D
4054 * We avoid the shl instruction by realizing that we only want to add
4055 * the low 16-bits of the "high" result to the high 16-bits of the
4056 * "low" result and using proper regioning on the add:
4058 * mul(8) g7<1>D g3<8,8,1>D g4.0<16,8,2>UW
4059 * mul(8) g8<1>D g3<8,8,1>D g4.1<16,8,2>UW
4060 * add(8) g7.1<2>UW g7.1<16,8,2>UW g8<16,8,2>UW
4062 * Since it does not use the (single) accumulator register, we can
4063 * schedule multi-component multiplications much better.
4066 bool needs_mov
= false;
4067 fs_reg orig_dst
= inst
->dst
;
4069 /* Get a new VGRF for the "low" 32x16-bit multiplication result if
4070 * reusing the original destination is impossible due to hardware
4071 * restrictions, source/destination overlap, or it being the null
4074 fs_reg low
= inst
->dst
;
4075 if (orig_dst
.is_null() || orig_dst
.file
== MRF
||
4076 regions_overlap(inst
->dst
, inst
->size_written
,
4077 inst
->src
[0], inst
->size_read(0)) ||
4078 regions_overlap(inst
->dst
, inst
->size_written
,
4079 inst
->src
[1], inst
->size_read(1)) ||
4080 inst
->dst
.stride
>= 4) {
4082 low
= fs_reg(VGRF
, alloc
.allocate(regs_written(inst
)),
4086 /* Get a new VGRF but keep the same stride as inst->dst */
4087 fs_reg
high(VGRF
, alloc
.allocate(regs_written(inst
)), inst
->dst
.type
);
4088 high
.stride
= inst
->dst
.stride
;
4089 high
.offset
= inst
->dst
.offset
% REG_SIZE
;
4091 if (devinfo
->gen
>= 7) {
4092 if (inst
->src
[1].abs
)
4093 lower_src_modifiers(this, block
, inst
, 1);
4095 if (inst
->src
[1].file
== IMM
) {
4096 ibld
.MUL(low
, inst
->src
[0],
4097 brw_imm_uw(inst
->src
[1].ud
& 0xffff));
4098 ibld
.MUL(high
, inst
->src
[0],
4099 brw_imm_uw(inst
->src
[1].ud
>> 16));
4101 ibld
.MUL(low
, inst
->src
[0],
4102 subscript(inst
->src
[1], BRW_REGISTER_TYPE_UW
, 0));
4103 ibld
.MUL(high
, inst
->src
[0],
4104 subscript(inst
->src
[1], BRW_REGISTER_TYPE_UW
, 1));
4107 if (inst
->src
[0].abs
)
4108 lower_src_modifiers(this, block
, inst
, 0);
4110 ibld
.MUL(low
, subscript(inst
->src
[0], BRW_REGISTER_TYPE_UW
, 0),
4112 ibld
.MUL(high
, subscript(inst
->src
[0], BRW_REGISTER_TYPE_UW
, 1),
4116 ibld
.ADD(subscript(low
, BRW_REGISTER_TYPE_UW
, 1),
4117 subscript(low
, BRW_REGISTER_TYPE_UW
, 1),
4118 subscript(high
, BRW_REGISTER_TYPE_UW
, 0));
4120 if (needs_mov
|| inst
->conditional_mod
)
4121 set_condmod(inst
->conditional_mod
, ibld
.MOV(orig_dst
, low
));
4126 fs_visitor::lower_mul_qword_inst(fs_inst
*inst
, bblock_t
*block
)
4128 const fs_builder
ibld(this, block
, inst
);
4130 /* Considering two 64-bit integers ab and cd where each letter ab
4131 * corresponds to 32 bits, we get a 128-bit result WXYZ. We * cd
4132 * only need to provide the YZ part of the result. -------
4134 * Only BD needs to be 64 bits. For AD and BC we only care + AD
4135 * about the lower 32 bits (since they are part of the upper + BC
4136 * 32 bits of our result). AC is not needed since it starts + AC
4137 * on the 65th bit of the result. -------
4140 unsigned int q_regs
= regs_written(inst
);
4141 unsigned int d_regs
= (q_regs
+ 1) / 2;
4143 fs_reg
bd(VGRF
, alloc
.allocate(q_regs
), BRW_REGISTER_TYPE_UQ
);
4144 fs_reg
ad(VGRF
, alloc
.allocate(d_regs
), BRW_REGISTER_TYPE_UD
);
4145 fs_reg
bc(VGRF
, alloc
.allocate(d_regs
), BRW_REGISTER_TYPE_UD
);
4147 /* Here we need the full 64 bit result for 32b * 32b. */
4148 if (devinfo
->has_integer_dword_mul
) {
4149 ibld
.MUL(bd
, subscript(inst
->src
[0], BRW_REGISTER_TYPE_UD
, 0),
4150 subscript(inst
->src
[1], BRW_REGISTER_TYPE_UD
, 0));
4152 fs_reg
bd_high(VGRF
, alloc
.allocate(d_regs
), BRW_REGISTER_TYPE_UD
);
4153 fs_reg
bd_low(VGRF
, alloc
.allocate(d_regs
), BRW_REGISTER_TYPE_UD
);
4154 fs_reg acc
= retype(brw_acc_reg(inst
->exec_size
), BRW_REGISTER_TYPE_UD
);
4156 fs_inst
*mul
= ibld
.MUL(acc
,
4157 subscript(inst
->src
[0], BRW_REGISTER_TYPE_UD
, 0),
4158 subscript(inst
->src
[1], BRW_REGISTER_TYPE_UW
, 0));
4159 mul
->writes_accumulator
= true;
4161 ibld
.MACH(bd_high
, subscript(inst
->src
[0], BRW_REGISTER_TYPE_UD
, 0),
4162 subscript(inst
->src
[1], BRW_REGISTER_TYPE_UD
, 0));
4163 ibld
.MOV(bd_low
, acc
);
4165 ibld
.MOV(subscript(bd
, BRW_REGISTER_TYPE_UD
, 0), bd_low
);
4166 ibld
.MOV(subscript(bd
, BRW_REGISTER_TYPE_UD
, 1), bd_high
);
4169 ibld
.MUL(ad
, subscript(inst
->src
[0], BRW_REGISTER_TYPE_UD
, 1),
4170 subscript(inst
->src
[1], BRW_REGISTER_TYPE_UD
, 0));
4171 ibld
.MUL(bc
, subscript(inst
->src
[0], BRW_REGISTER_TYPE_UD
, 0),
4172 subscript(inst
->src
[1], BRW_REGISTER_TYPE_UD
, 1));
4174 ibld
.ADD(ad
, ad
, bc
);
4175 ibld
.ADD(subscript(bd
, BRW_REGISTER_TYPE_UD
, 1),
4176 subscript(bd
, BRW_REGISTER_TYPE_UD
, 1), ad
);
4178 ibld
.MOV(inst
->dst
, bd
);
4182 fs_visitor::lower_mulh_inst(fs_inst
*inst
, bblock_t
*block
)
4184 const fs_builder
ibld(this, block
, inst
);
4186 /* According to the BDW+ BSpec page for the "Multiply Accumulate
4187 * High" instruction:
4189 * "An added preliminary mov is required for source modification on
4191 * mov (8) r3.0<1>:d -r3<8;8,1>:d
4192 * mul (8) acc0:d r2.0<8;8,1>:d r3.0<16;8,2>:uw
4193 * mach (8) r5.0<1>:d r2.0<8;8,1>:d r3.0<8;8,1>:d"
4195 if (devinfo
->gen
>= 8 && (inst
->src
[1].negate
|| inst
->src
[1].abs
))
4196 lower_src_modifiers(this, block
, inst
, 1);
4198 /* Should have been lowered to 8-wide. */
4199 assert(inst
->exec_size
<= get_lowered_simd_width(devinfo
, inst
));
4200 const fs_reg acc
= retype(brw_acc_reg(inst
->exec_size
), inst
->dst
.type
);
4201 fs_inst
*mul
= ibld
.MUL(acc
, inst
->src
[0], inst
->src
[1]);
4202 fs_inst
*mach
= ibld
.MACH(inst
->dst
, inst
->src
[0], inst
->src
[1]);
4204 if (devinfo
->gen
>= 8) {
4205 /* Until Gen8, integer multiplies read 32-bits from one source,
4206 * and 16-bits from the other, and relying on the MACH instruction
4207 * to generate the high bits of the result.
4209 * On Gen8, the multiply instruction does a full 32x32-bit
4210 * multiply, but in order to do a 64-bit multiply we can simulate
4211 * the previous behavior and then use a MACH instruction.
4213 assert(mul
->src
[1].type
== BRW_REGISTER_TYPE_D
||
4214 mul
->src
[1].type
== BRW_REGISTER_TYPE_UD
);
4215 mul
->src
[1].type
= BRW_REGISTER_TYPE_UW
;
4216 mul
->src
[1].stride
*= 2;
4218 if (mul
->src
[1].file
== IMM
) {
4219 mul
->src
[1] = brw_imm_uw(mul
->src
[1].ud
);
4221 } else if (devinfo
->gen
== 7 && !devinfo
->is_haswell
&&
4223 /* Among other things the quarter control bits influence which
4224 * accumulator register is used by the hardware for instructions
4225 * that access the accumulator implicitly (e.g. MACH). A
4226 * second-half instruction would normally map to acc1, which
4227 * doesn't exist on Gen7 and up (the hardware does emulate it for
4228 * floating-point instructions *only* by taking advantage of the
4229 * extra precision of acc0 not normally used for floating point
4232 * HSW and up are careful enough not to try to access an
4233 * accumulator register that doesn't exist, but on earlier Gen7
4234 * hardware we need to make sure that the quarter control bits are
4235 * zero to avoid non-deterministic behaviour and emit an extra MOV
4236 * to get the result masked correctly according to the current
4240 mach
->force_writemask_all
= true;
4241 mach
->dst
= ibld
.vgrf(inst
->dst
.type
);
4242 ibld
.MOV(inst
->dst
, mach
->dst
);
4247 fs_visitor::lower_integer_multiplication()
4249 bool progress
= false;
4251 foreach_block_and_inst_safe(block
, fs_inst
, inst
, cfg
) {
4252 if (inst
->opcode
== BRW_OPCODE_MUL
) {
4253 if ((inst
->dst
.type
== BRW_REGISTER_TYPE_Q
||
4254 inst
->dst
.type
== BRW_REGISTER_TYPE_UQ
) &&
4255 (inst
->src
[0].type
== BRW_REGISTER_TYPE_Q
||
4256 inst
->src
[0].type
== BRW_REGISTER_TYPE_UQ
) &&
4257 (inst
->src
[1].type
== BRW_REGISTER_TYPE_Q
||
4258 inst
->src
[1].type
== BRW_REGISTER_TYPE_UQ
)) {
4259 lower_mul_qword_inst(inst
, block
);
4260 inst
->remove(block
);
4262 } else if (!inst
->dst
.is_accumulator() &&
4263 (inst
->dst
.type
== BRW_REGISTER_TYPE_D
||
4264 inst
->dst
.type
== BRW_REGISTER_TYPE_UD
) &&
4265 !devinfo
->has_integer_dword_mul
) {
4266 lower_mul_dword_inst(inst
, block
);
4267 inst
->remove(block
);
4270 } else if (inst
->opcode
== SHADER_OPCODE_MULH
) {
4271 lower_mulh_inst(inst
, block
);
4272 inst
->remove(block
);
4279 invalidate_live_intervals();
4285 fs_visitor::lower_minmax()
4287 assert(devinfo
->gen
< 6);
4289 bool progress
= false;
4291 foreach_block_and_inst_safe(block
, fs_inst
, inst
, cfg
) {
4292 const fs_builder
ibld(this, block
, inst
);
4294 if (inst
->opcode
== BRW_OPCODE_SEL
&&
4295 inst
->predicate
== BRW_PREDICATE_NONE
) {
4296 /* FIXME: Using CMP doesn't preserve the NaN propagation semantics of
4297 * the original SEL.L/GE instruction
4299 ibld
.CMP(ibld
.null_reg_d(), inst
->src
[0], inst
->src
[1],
4300 inst
->conditional_mod
);
4301 inst
->predicate
= BRW_PREDICATE_NORMAL
;
4302 inst
->conditional_mod
= BRW_CONDITIONAL_NONE
;
4309 invalidate_live_intervals();
4315 setup_color_payload(const fs_builder
&bld
, const brw_wm_prog_key
*key
,
4316 fs_reg
*dst
, fs_reg color
, unsigned components
)
4318 if (key
->clamp_fragment_color
) {
4319 fs_reg tmp
= bld
.vgrf(BRW_REGISTER_TYPE_F
, 4);
4320 assert(color
.type
== BRW_REGISTER_TYPE_F
);
4322 for (unsigned i
= 0; i
< components
; i
++)
4324 bld
.MOV(offset(tmp
, bld
, i
), offset(color
, bld
, i
)));
4329 for (unsigned i
= 0; i
< components
; i
++)
4330 dst
[i
] = offset(color
, bld
, i
);
4334 brw_fb_write_msg_control(const fs_inst
*inst
,
4335 const struct brw_wm_prog_data
*prog_data
)
4339 if (inst
->opcode
== FS_OPCODE_REP_FB_WRITE
) {
4340 assert(inst
->group
== 0 && inst
->exec_size
== 16);
4341 mctl
= BRW_DATAPORT_RENDER_TARGET_WRITE_SIMD16_SINGLE_SOURCE_REPLICATED
;
4342 } else if (prog_data
->dual_src_blend
) {
4343 assert(inst
->exec_size
== 8);
4345 if (inst
->group
% 16 == 0)
4346 mctl
= BRW_DATAPORT_RENDER_TARGET_WRITE_SIMD8_DUAL_SOURCE_SUBSPAN01
;
4347 else if (inst
->group
% 16 == 8)
4348 mctl
= BRW_DATAPORT_RENDER_TARGET_WRITE_SIMD8_DUAL_SOURCE_SUBSPAN23
;
4350 unreachable("Invalid dual-source FB write instruction group");
4352 assert(inst
->group
== 0 || (inst
->group
== 16 && inst
->exec_size
== 16));
4354 if (inst
->exec_size
== 16)
4355 mctl
= BRW_DATAPORT_RENDER_TARGET_WRITE_SIMD16_SINGLE_SOURCE
;
4356 else if (inst
->exec_size
== 8)
4357 mctl
= BRW_DATAPORT_RENDER_TARGET_WRITE_SIMD8_SINGLE_SOURCE_SUBSPAN01
;
4359 unreachable("Invalid FB write execution size");
4366 lower_fb_write_logical_send(const fs_builder
&bld
, fs_inst
*inst
,
4367 const struct brw_wm_prog_data
*prog_data
,
4368 const brw_wm_prog_key
*key
,
4369 const fs_visitor::thread_payload
&payload
)
4371 assert(inst
->src
[FB_WRITE_LOGICAL_SRC_COMPONENTS
].file
== IMM
);
4372 const gen_device_info
*devinfo
= bld
.shader
->devinfo
;
4373 const fs_reg
&color0
= inst
->src
[FB_WRITE_LOGICAL_SRC_COLOR0
];
4374 const fs_reg
&color1
= inst
->src
[FB_WRITE_LOGICAL_SRC_COLOR1
];
4375 const fs_reg
&src0_alpha
= inst
->src
[FB_WRITE_LOGICAL_SRC_SRC0_ALPHA
];
4376 const fs_reg
&src_depth
= inst
->src
[FB_WRITE_LOGICAL_SRC_SRC_DEPTH
];
4377 const fs_reg
&dst_depth
= inst
->src
[FB_WRITE_LOGICAL_SRC_DST_DEPTH
];
4378 const fs_reg
&src_stencil
= inst
->src
[FB_WRITE_LOGICAL_SRC_SRC_STENCIL
];
4379 fs_reg sample_mask
= inst
->src
[FB_WRITE_LOGICAL_SRC_OMASK
];
4380 const unsigned components
=
4381 inst
->src
[FB_WRITE_LOGICAL_SRC_COMPONENTS
].ud
;
4383 /* We can potentially have a message length of up to 15, so we have to set
4384 * base_mrf to either 0 or 1 in order to fit in m0..m15.
4387 int header_size
= 2, payload_header_size
;
4388 unsigned length
= 0;
4390 if (devinfo
->gen
< 6) {
4391 /* TODO: Support SIMD32 on gen4-5 */
4392 assert(bld
.group() < 16);
4394 /* For gen4-5, we always have a header consisting of g0 and g1. We have
4395 * an implied MOV from g0,g1 to the start of the message. The MOV from
4396 * g0 is handled by the hardware and the MOV from g1 is provided by the
4397 * generator. This is required because, on gen4-5, the generator may
4398 * generate two write messages with different message lengths in order
4399 * to handle AA data properly.
4401 * Also, since the pixel mask goes in the g0 portion of the message and
4402 * since render target writes are the last thing in the shader, we write
4403 * the pixel mask directly into g0 and it will get copied as part of the
4406 if (prog_data
->uses_kill
) {
4407 bld
.exec_all().group(1, 0)
4408 .MOV(retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_UW
),
4409 brw_flag_reg(0, 1));
4412 assert(length
== 0);
4414 } else if ((devinfo
->gen
<= 7 && !devinfo
->is_haswell
&&
4415 prog_data
->uses_kill
) ||
4416 (devinfo
->gen
< 11 &&
4417 (color1
.file
!= BAD_FILE
|| key
->nr_color_regions
> 1))) {
4418 /* From the Sandy Bridge PRM, volume 4, page 198:
4420 * "Dispatched Pixel Enables. One bit per pixel indicating
4421 * which pixels were originally enabled when the thread was
4422 * dispatched. This field is only required for the end-of-
4423 * thread message and on all dual-source messages."
4425 const fs_builder ubld
= bld
.exec_all().group(8, 0);
4427 fs_reg header
= ubld
.vgrf(BRW_REGISTER_TYPE_UD
, 2);
4428 if (bld
.group() < 16) {
4429 /* The header starts off as g0 and g1 for the first half */
4430 ubld
.group(16, 0).MOV(header
, retype(brw_vec8_grf(0, 0),
4431 BRW_REGISTER_TYPE_UD
));
4433 /* The header starts off as g0 and g2 for the second half */
4434 assert(bld
.group() < 32);
4435 const fs_reg header_sources
[2] = {
4436 retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_UD
),
4437 retype(brw_vec8_grf(2, 0), BRW_REGISTER_TYPE_UD
),
4439 ubld
.LOAD_PAYLOAD(header
, header_sources
, 2, 0);
4442 uint32_t g00_bits
= 0;
4444 /* Set "Source0 Alpha Present to RenderTarget" bit in message
4447 if (inst
->target
> 0 && prog_data
->replicate_alpha
)
4448 g00_bits
|= 1 << 11;
4450 /* Set computes stencil to render target */
4451 if (prog_data
->computed_stencil
)
4452 g00_bits
|= 1 << 14;
4455 /* OR extra bits into g0.0 */
4456 ubld
.group(1, 0).OR(component(header
, 0),
4457 retype(brw_vec1_grf(0, 0),
4458 BRW_REGISTER_TYPE_UD
),
4459 brw_imm_ud(g00_bits
));
4462 /* Set the render target index for choosing BLEND_STATE. */
4463 if (inst
->target
> 0) {
4464 ubld
.group(1, 0).MOV(component(header
, 2), brw_imm_ud(inst
->target
));
4467 if (prog_data
->uses_kill
) {
4468 assert(bld
.group() < 16);
4469 ubld
.group(1, 0).MOV(retype(component(header
, 15),
4470 BRW_REGISTER_TYPE_UW
),
4471 brw_flag_reg(0, 1));
4474 assert(length
== 0);
4475 sources
[0] = header
;
4476 sources
[1] = horiz_offset(header
, 8);
4479 assert(length
== 0 || length
== 2);
4480 header_size
= length
;
4482 if (payload
.aa_dest_stencil_reg
[0]) {
4483 assert(inst
->group
< 16);
4484 sources
[length
] = fs_reg(VGRF
, bld
.shader
->alloc
.allocate(1));
4485 bld
.group(8, 0).exec_all().annotate("FB write stencil/AA alpha")
4486 .MOV(sources
[length
],
4487 fs_reg(brw_vec8_grf(payload
.aa_dest_stencil_reg
[0], 0)));
4491 bool src0_alpha_present
= false;
4493 if (src0_alpha
.file
!= BAD_FILE
) {
4494 for (unsigned i
= 0; i
< bld
.dispatch_width() / 8; i
++) {
4495 const fs_builder
&ubld
= bld
.exec_all().group(8, i
)
4496 .annotate("FB write src0 alpha");
4497 const fs_reg tmp
= ubld
.vgrf(BRW_REGISTER_TYPE_F
);
4498 ubld
.MOV(tmp
, horiz_offset(src0_alpha
, i
* 8));
4499 setup_color_payload(ubld
, key
, &sources
[length
], tmp
, 1);
4502 src0_alpha_present
= true;
4503 } else if (prog_data
->replicate_alpha
&& inst
->target
!= 0) {
4504 /* Handle the case when fragment shader doesn't write to draw buffer
4505 * zero. No need to call setup_color_payload() for src0_alpha because
4506 * alpha value will be undefined.
4508 length
+= bld
.dispatch_width() / 8;
4509 src0_alpha_present
= true;
4512 if (sample_mask
.file
!= BAD_FILE
) {
4513 sources
[length
] = fs_reg(VGRF
, bld
.shader
->alloc
.allocate(1),
4514 BRW_REGISTER_TYPE_UD
);
4516 /* Hand over gl_SampleMask. Only the lower 16 bits of each channel are
4517 * relevant. Since it's unsigned single words one vgrf is always
4518 * 16-wide, but only the lower or higher 8 channels will be used by the
4519 * hardware when doing a SIMD8 write depending on whether we have
4520 * selected the subspans for the first or second half respectively.
4522 assert(sample_mask
.file
!= BAD_FILE
&& type_sz(sample_mask
.type
) == 4);
4523 sample_mask
.type
= BRW_REGISTER_TYPE_UW
;
4524 sample_mask
.stride
*= 2;
4526 bld
.exec_all().annotate("FB write oMask")
4527 .MOV(horiz_offset(retype(sources
[length
], BRW_REGISTER_TYPE_UW
),
4533 payload_header_size
= length
;
4535 setup_color_payload(bld
, key
, &sources
[length
], color0
, components
);
4538 if (color1
.file
!= BAD_FILE
) {
4539 setup_color_payload(bld
, key
, &sources
[length
], color1
, components
);
4543 if (src_depth
.file
!= BAD_FILE
) {
4544 sources
[length
] = src_depth
;
4548 if (dst_depth
.file
!= BAD_FILE
) {
4549 sources
[length
] = dst_depth
;
4553 if (src_stencil
.file
!= BAD_FILE
) {
4554 assert(devinfo
->gen
>= 9);
4555 assert(bld
.dispatch_width() == 8);
4557 /* XXX: src_stencil is only available on gen9+. dst_depth is never
4558 * available on gen9+. As such it's impossible to have both enabled at the
4559 * same time and therefore length cannot overrun the array.
4561 assert(length
< 15);
4563 sources
[length
] = bld
.vgrf(BRW_REGISTER_TYPE_UD
);
4564 bld
.exec_all().annotate("FB write OS")
4565 .MOV(retype(sources
[length
], BRW_REGISTER_TYPE_UB
),
4566 subscript(src_stencil
, BRW_REGISTER_TYPE_UB
, 0));
4571 if (devinfo
->gen
>= 7) {
4572 /* Send from the GRF */
4573 fs_reg payload
= fs_reg(VGRF
, -1, BRW_REGISTER_TYPE_F
);
4574 load
= bld
.LOAD_PAYLOAD(payload
, sources
, length
, payload_header_size
);
4575 payload
.nr
= bld
.shader
->alloc
.allocate(regs_written(load
));
4576 load
->dst
= payload
;
4578 uint32_t msg_ctl
= brw_fb_write_msg_control(inst
, prog_data
);
4579 uint32_t ex_desc
= 0;
4582 (inst
->group
/ 16) << 11 | /* rt slot group */
4583 brw_dp_write_desc(devinfo
, inst
->target
, msg_ctl
,
4584 GEN6_DATAPORT_WRITE_MESSAGE_RENDER_TARGET_WRITE
,
4585 inst
->last_rt
, false);
4587 if (devinfo
->gen
>= 11) {
4588 /* Set the "Render Target Index" and "Src0 Alpha Present" fields
4589 * in the extended message descriptor, in lieu of using a header.
4591 ex_desc
= inst
->target
<< 12 | src0_alpha_present
<< 15;
4593 if (key
->nr_color_regions
== 0)
4594 ex_desc
|= 1 << 20; /* Null Render Target */
4597 inst
->opcode
= SHADER_OPCODE_SEND
;
4598 inst
->resize_sources(3);
4599 inst
->sfid
= GEN6_SFID_DATAPORT_RENDER_CACHE
;
4600 inst
->src
[0] = brw_imm_ud(inst
->desc
);
4601 inst
->src
[1] = brw_imm_ud(ex_desc
);
4602 inst
->src
[2] = payload
;
4603 inst
->mlen
= regs_written(load
);
4605 inst
->header_size
= header_size
;
4606 inst
->check_tdr
= true;
4607 inst
->send_has_side_effects
= true;
4609 /* Send from the MRF */
4610 load
= bld
.LOAD_PAYLOAD(fs_reg(MRF
, 1, BRW_REGISTER_TYPE_F
),
4611 sources
, length
, payload_header_size
);
4613 /* On pre-SNB, we have to interlace the color values. LOAD_PAYLOAD
4614 * will do this for us if we just give it a COMPR4 destination.
4616 if (devinfo
->gen
< 6 && bld
.dispatch_width() == 16)
4617 load
->dst
.nr
|= BRW_MRF_COMPR4
;
4619 if (devinfo
->gen
< 6) {
4620 /* Set up src[0] for the implied MOV from grf0-1 */
4621 inst
->resize_sources(1);
4622 inst
->src
[0] = brw_vec8_grf(0, 0);
4624 inst
->resize_sources(0);
4627 inst
->opcode
= FS_OPCODE_FB_WRITE
;
4628 inst
->mlen
= regs_written(load
);
4629 inst
->header_size
= header_size
;
4634 lower_fb_read_logical_send(const fs_builder
&bld
, fs_inst
*inst
)
4636 const fs_builder
&ubld
= bld
.exec_all().group(8, 0);
4637 const unsigned length
= 2;
4638 const fs_reg header
= ubld
.vgrf(BRW_REGISTER_TYPE_UD
, length
);
4640 if (bld
.group() < 16) {
4641 ubld
.group(16, 0).MOV(header
, retype(brw_vec8_grf(0, 0),
4642 BRW_REGISTER_TYPE_UD
));
4644 assert(bld
.group() < 32);
4645 const fs_reg header_sources
[] = {
4646 retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_UD
),
4647 retype(brw_vec8_grf(2, 0), BRW_REGISTER_TYPE_UD
)
4649 ubld
.LOAD_PAYLOAD(header
, header_sources
, ARRAY_SIZE(header_sources
), 0);
4652 inst
->resize_sources(1);
4653 inst
->src
[0] = header
;
4654 inst
->opcode
= FS_OPCODE_FB_READ
;
4655 inst
->mlen
= length
;
4656 inst
->header_size
= length
;
4660 lower_sampler_logical_send_gen4(const fs_builder
&bld
, fs_inst
*inst
, opcode op
,
4661 const fs_reg
&coordinate
,
4662 const fs_reg
&shadow_c
,
4663 const fs_reg
&lod
, const fs_reg
&lod2
,
4664 const fs_reg
&surface
,
4665 const fs_reg
&sampler
,
4666 unsigned coord_components
,
4667 unsigned grad_components
)
4669 const bool has_lod
= (op
== SHADER_OPCODE_TXL
|| op
== FS_OPCODE_TXB
||
4670 op
== SHADER_OPCODE_TXF
|| op
== SHADER_OPCODE_TXS
);
4671 fs_reg
msg_begin(MRF
, 1, BRW_REGISTER_TYPE_F
);
4672 fs_reg msg_end
= msg_begin
;
4675 msg_end
= offset(msg_end
, bld
.group(8, 0), 1);
4677 for (unsigned i
= 0; i
< coord_components
; i
++)
4678 bld
.MOV(retype(offset(msg_end
, bld
, i
), coordinate
.type
),
4679 offset(coordinate
, bld
, i
));
4681 msg_end
= offset(msg_end
, bld
, coord_components
);
4683 /* Messages other than SAMPLE and RESINFO in SIMD16 and TXD in SIMD8
4684 * require all three components to be present and zero if they are unused.
4686 if (coord_components
> 0 &&
4687 (has_lod
|| shadow_c
.file
!= BAD_FILE
||
4688 (op
== SHADER_OPCODE_TEX
&& bld
.dispatch_width() == 8))) {
4689 for (unsigned i
= coord_components
; i
< 3; i
++)
4690 bld
.MOV(offset(msg_end
, bld
, i
), brw_imm_f(0.0f
));
4692 msg_end
= offset(msg_end
, bld
, 3 - coord_components
);
4695 if (op
== SHADER_OPCODE_TXD
) {
4696 /* TXD unsupported in SIMD16 mode. */
4697 assert(bld
.dispatch_width() == 8);
4699 /* the slots for u and v are always present, but r is optional */
4700 if (coord_components
< 2)
4701 msg_end
= offset(msg_end
, bld
, 2 - coord_components
);
4704 * dPdx = dudx, dvdx, drdx
4705 * dPdy = dudy, dvdy, drdy
4707 * 1-arg: Does not exist.
4709 * 2-arg: dudx dvdx dudy dvdy
4710 * dPdx.x dPdx.y dPdy.x dPdy.y
4713 * 3-arg: dudx dvdx drdx dudy dvdy drdy
4714 * dPdx.x dPdx.y dPdx.z dPdy.x dPdy.y dPdy.z
4715 * m5 m6 m7 m8 m9 m10
4717 for (unsigned i
= 0; i
< grad_components
; i
++)
4718 bld
.MOV(offset(msg_end
, bld
, i
), offset(lod
, bld
, i
));
4720 msg_end
= offset(msg_end
, bld
, MAX2(grad_components
, 2));
4722 for (unsigned i
= 0; i
< grad_components
; i
++)
4723 bld
.MOV(offset(msg_end
, bld
, i
), offset(lod2
, bld
, i
));
4725 msg_end
= offset(msg_end
, bld
, MAX2(grad_components
, 2));
4729 /* Bias/LOD with shadow comparator is unsupported in SIMD16 -- *Without*
4730 * shadow comparator (including RESINFO) it's unsupported in SIMD8 mode.
4732 assert(shadow_c
.file
!= BAD_FILE
? bld
.dispatch_width() == 8 :
4733 bld
.dispatch_width() == 16);
4735 const brw_reg_type type
=
4736 (op
== SHADER_OPCODE_TXF
|| op
== SHADER_OPCODE_TXS
?
4737 BRW_REGISTER_TYPE_UD
: BRW_REGISTER_TYPE_F
);
4738 bld
.MOV(retype(msg_end
, type
), lod
);
4739 msg_end
= offset(msg_end
, bld
, 1);
4742 if (shadow_c
.file
!= BAD_FILE
) {
4743 if (op
== SHADER_OPCODE_TEX
&& bld
.dispatch_width() == 8) {
4744 /* There's no plain shadow compare message, so we use shadow
4745 * compare with a bias of 0.0.
4747 bld
.MOV(msg_end
, brw_imm_f(0.0f
));
4748 msg_end
= offset(msg_end
, bld
, 1);
4751 bld
.MOV(msg_end
, shadow_c
);
4752 msg_end
= offset(msg_end
, bld
, 1);
4756 inst
->src
[0] = reg_undef
;
4757 inst
->src
[1] = surface
;
4758 inst
->src
[2] = sampler
;
4759 inst
->resize_sources(3);
4760 inst
->base_mrf
= msg_begin
.nr
;
4761 inst
->mlen
= msg_end
.nr
- msg_begin
.nr
;
4762 inst
->header_size
= 1;
4766 lower_sampler_logical_send_gen5(const fs_builder
&bld
, fs_inst
*inst
, opcode op
,
4767 const fs_reg
&coordinate
,
4768 const fs_reg
&shadow_c
,
4769 const fs_reg
&lod
, const fs_reg
&lod2
,
4770 const fs_reg
&sample_index
,
4771 const fs_reg
&surface
,
4772 const fs_reg
&sampler
,
4773 unsigned coord_components
,
4774 unsigned grad_components
)
4776 fs_reg
message(MRF
, 2, BRW_REGISTER_TYPE_F
);
4777 fs_reg msg_coords
= message
;
4778 unsigned header_size
= 0;
4780 if (inst
->offset
!= 0) {
4781 /* The offsets set up by the visitor are in the m1 header, so we can't
4788 for (unsigned i
= 0; i
< coord_components
; i
++)
4789 bld
.MOV(retype(offset(msg_coords
, bld
, i
), coordinate
.type
),
4790 offset(coordinate
, bld
, i
));
4792 fs_reg msg_end
= offset(msg_coords
, bld
, coord_components
);
4793 fs_reg msg_lod
= offset(msg_coords
, bld
, 4);
4795 if (shadow_c
.file
!= BAD_FILE
) {
4796 fs_reg msg_shadow
= msg_lod
;
4797 bld
.MOV(msg_shadow
, shadow_c
);
4798 msg_lod
= offset(msg_shadow
, bld
, 1);
4803 case SHADER_OPCODE_TXL
:
4805 bld
.MOV(msg_lod
, lod
);
4806 msg_end
= offset(msg_lod
, bld
, 1);
4808 case SHADER_OPCODE_TXD
:
4811 * dPdx = dudx, dvdx, drdx
4812 * dPdy = dudy, dvdy, drdy
4814 * Load up these values:
4815 * - dudx dudy dvdx dvdy drdx drdy
4816 * - dPdx.x dPdy.x dPdx.y dPdy.y dPdx.z dPdy.z
4819 for (unsigned i
= 0; i
< grad_components
; i
++) {
4820 bld
.MOV(msg_end
, offset(lod
, bld
, i
));
4821 msg_end
= offset(msg_end
, bld
, 1);
4823 bld
.MOV(msg_end
, offset(lod2
, bld
, i
));
4824 msg_end
= offset(msg_end
, bld
, 1);
4827 case SHADER_OPCODE_TXS
:
4828 msg_lod
= retype(msg_end
, BRW_REGISTER_TYPE_UD
);
4829 bld
.MOV(msg_lod
, lod
);
4830 msg_end
= offset(msg_lod
, bld
, 1);
4832 case SHADER_OPCODE_TXF
:
4833 msg_lod
= offset(msg_coords
, bld
, 3);
4834 bld
.MOV(retype(msg_lod
, BRW_REGISTER_TYPE_UD
), lod
);
4835 msg_end
= offset(msg_lod
, bld
, 1);
4837 case SHADER_OPCODE_TXF_CMS
:
4838 msg_lod
= offset(msg_coords
, bld
, 3);
4840 bld
.MOV(retype(msg_lod
, BRW_REGISTER_TYPE_UD
), brw_imm_ud(0u));
4842 bld
.MOV(retype(offset(msg_lod
, bld
, 1), BRW_REGISTER_TYPE_UD
), sample_index
);
4843 msg_end
= offset(msg_lod
, bld
, 2);
4850 inst
->src
[0] = reg_undef
;
4851 inst
->src
[1] = surface
;
4852 inst
->src
[2] = sampler
;
4853 inst
->resize_sources(3);
4854 inst
->base_mrf
= message
.nr
;
4855 inst
->mlen
= msg_end
.nr
- message
.nr
;
4856 inst
->header_size
= header_size
;
4858 /* Message length > MAX_SAMPLER_MESSAGE_SIZE disallowed by hardware. */
4859 assert(inst
->mlen
<= MAX_SAMPLER_MESSAGE_SIZE
);
4863 is_high_sampler(const struct gen_device_info
*devinfo
, const fs_reg
&sampler
)
4865 if (devinfo
->gen
< 8 && !devinfo
->is_haswell
)
4868 return sampler
.file
!= IMM
|| sampler
.ud
>= 16;
4872 sampler_msg_type(const gen_device_info
*devinfo
,
4873 opcode opcode
, bool shadow_compare
)
4875 assert(devinfo
->gen
>= 5);
4877 case SHADER_OPCODE_TEX
:
4878 return shadow_compare
? GEN5_SAMPLER_MESSAGE_SAMPLE_COMPARE
:
4879 GEN5_SAMPLER_MESSAGE_SAMPLE
;
4881 return shadow_compare
? GEN5_SAMPLER_MESSAGE_SAMPLE_BIAS_COMPARE
:
4882 GEN5_SAMPLER_MESSAGE_SAMPLE_BIAS
;
4883 case SHADER_OPCODE_TXL
:
4884 return shadow_compare
? GEN5_SAMPLER_MESSAGE_SAMPLE_LOD_COMPARE
:
4885 GEN5_SAMPLER_MESSAGE_SAMPLE_LOD
;
4886 case SHADER_OPCODE_TXL_LZ
:
4887 return shadow_compare
? GEN9_SAMPLER_MESSAGE_SAMPLE_C_LZ
:
4888 GEN9_SAMPLER_MESSAGE_SAMPLE_LZ
;
4889 case SHADER_OPCODE_TXS
:
4890 case SHADER_OPCODE_IMAGE_SIZE_LOGICAL
:
4891 return GEN5_SAMPLER_MESSAGE_SAMPLE_RESINFO
;
4892 case SHADER_OPCODE_TXD
:
4893 assert(!shadow_compare
|| devinfo
->gen
>= 8 || devinfo
->is_haswell
);
4894 return shadow_compare
? HSW_SAMPLER_MESSAGE_SAMPLE_DERIV_COMPARE
:
4895 GEN5_SAMPLER_MESSAGE_SAMPLE_DERIVS
;
4896 case SHADER_OPCODE_TXF
:
4897 return GEN5_SAMPLER_MESSAGE_SAMPLE_LD
;
4898 case SHADER_OPCODE_TXF_LZ
:
4899 assert(devinfo
->gen
>= 9);
4900 return GEN9_SAMPLER_MESSAGE_SAMPLE_LD_LZ
;
4901 case SHADER_OPCODE_TXF_CMS_W
:
4902 assert(devinfo
->gen
>= 9);
4903 return GEN9_SAMPLER_MESSAGE_SAMPLE_LD2DMS_W
;
4904 case SHADER_OPCODE_TXF_CMS
:
4905 return devinfo
->gen
>= 7 ? GEN7_SAMPLER_MESSAGE_SAMPLE_LD2DMS
:
4906 GEN5_SAMPLER_MESSAGE_SAMPLE_LD
;
4907 case SHADER_OPCODE_TXF_UMS
:
4908 assert(devinfo
->gen
>= 7);
4909 return GEN7_SAMPLER_MESSAGE_SAMPLE_LD2DSS
;
4910 case SHADER_OPCODE_TXF_MCS
:
4911 assert(devinfo
->gen
>= 7);
4912 return GEN7_SAMPLER_MESSAGE_SAMPLE_LD_MCS
;
4913 case SHADER_OPCODE_LOD
:
4914 return GEN5_SAMPLER_MESSAGE_LOD
;
4915 case SHADER_OPCODE_TG4
:
4916 assert(devinfo
->gen
>= 7);
4917 return shadow_compare
? GEN7_SAMPLER_MESSAGE_SAMPLE_GATHER4_C
:
4918 GEN7_SAMPLER_MESSAGE_SAMPLE_GATHER4
;
4920 case SHADER_OPCODE_TG4_OFFSET
:
4921 assert(devinfo
->gen
>= 7);
4922 return shadow_compare
? GEN7_SAMPLER_MESSAGE_SAMPLE_GATHER4_PO_C
:
4923 GEN7_SAMPLER_MESSAGE_SAMPLE_GATHER4_PO
;
4924 case SHADER_OPCODE_SAMPLEINFO
:
4925 return GEN6_SAMPLER_MESSAGE_SAMPLE_SAMPLEINFO
;
4927 unreachable("not reached");
4932 lower_sampler_logical_send_gen7(const fs_builder
&bld
, fs_inst
*inst
, opcode op
,
4933 const fs_reg
&coordinate
,
4934 const fs_reg
&shadow_c
,
4935 fs_reg lod
, const fs_reg
&lod2
,
4936 const fs_reg
&min_lod
,
4937 const fs_reg
&sample_index
,
4939 const fs_reg
&surface
,
4940 const fs_reg
&sampler
,
4941 const fs_reg
&surface_handle
,
4942 const fs_reg
&sampler_handle
,
4943 const fs_reg
&tg4_offset
,
4944 unsigned coord_components
,
4945 unsigned grad_components
)
4947 const gen_device_info
*devinfo
= bld
.shader
->devinfo
;
4948 const brw_stage_prog_data
*prog_data
= bld
.shader
->stage_prog_data
;
4949 unsigned reg_width
= bld
.dispatch_width() / 8;
4950 unsigned header_size
= 0, length
= 0;
4951 fs_reg sources
[MAX_SAMPLER_MESSAGE_SIZE
];
4952 for (unsigned i
= 0; i
< ARRAY_SIZE(sources
); i
++)
4953 sources
[i
] = bld
.vgrf(BRW_REGISTER_TYPE_F
);
4955 /* We must have exactly one of surface/sampler and surface/sampler_handle */
4956 assert((surface
.file
== BAD_FILE
) != (surface_handle
.file
== BAD_FILE
));
4957 assert((sampler
.file
== BAD_FILE
) != (sampler_handle
.file
== BAD_FILE
));
4959 if (op
== SHADER_OPCODE_TG4
|| op
== SHADER_OPCODE_TG4_OFFSET
||
4960 inst
->offset
!= 0 || inst
->eot
||
4961 op
== SHADER_OPCODE_SAMPLEINFO
||
4962 sampler_handle
.file
!= BAD_FILE
||
4963 is_high_sampler(devinfo
, sampler
)) {
4964 /* For general texture offsets (no txf workaround), we need a header to
4967 * TG4 needs to place its channel select in the header, for interaction
4968 * with ARB_texture_swizzle. The sampler index is only 4-bits, so for
4969 * larger sampler numbers we need to offset the Sampler State Pointer in
4972 fs_reg header
= retype(sources
[0], BRW_REGISTER_TYPE_UD
);
4976 /* If we're requesting fewer than four channels worth of response,
4977 * and we have an explicit header, we need to set up the sampler
4978 * writemask. It's reversed from normal: 1 means "don't write".
4980 if (!inst
->eot
&& regs_written(inst
) != 4 * reg_width
) {
4981 assert(regs_written(inst
) % reg_width
== 0);
4982 unsigned mask
= ~((1 << (regs_written(inst
) / reg_width
)) - 1) & 0xf;
4983 inst
->offset
|= mask
<< 12;
4986 /* Build the actual header */
4987 const fs_builder ubld
= bld
.exec_all().group(8, 0);
4988 const fs_builder ubld1
= ubld
.group(1, 0);
4989 ubld
.MOV(header
, retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_UD
));
4991 ubld1
.MOV(component(header
, 2), brw_imm_ud(inst
->offset
));
4992 } else if (bld
.shader
->stage
!= MESA_SHADER_VERTEX
&&
4993 bld
.shader
->stage
!= MESA_SHADER_FRAGMENT
) {
4994 /* The vertex and fragment stages have g0.2 set to 0, so
4995 * header0.2 is 0 when g0 is copied. Other stages may not, so we
4996 * must set it to 0 to avoid setting undesirable bits in the
4999 ubld1
.MOV(component(header
, 2), brw_imm_ud(0));
5002 if (sampler_handle
.file
!= BAD_FILE
) {
5003 /* Bindless sampler handles aren't relative to the sampler state
5004 * pointer passed into the shader through SAMPLER_STATE_POINTERS_*.
5005 * Instead, it's an absolute pointer relative to dynamic state base
5008 * Sampler states are 16 bytes each and the pointer we give here has
5009 * to be 32-byte aligned. In order to avoid more indirect messages
5010 * than required, we assume that all bindless sampler states are
5011 * 32-byte aligned. This sacrifices a bit of general state base
5012 * address space but means we can do something more efficient in the
5015 ubld1
.MOV(component(header
, 3), sampler_handle
);
5016 } else if (is_high_sampler(devinfo
, sampler
)) {
5017 if (sampler
.file
== BRW_IMMEDIATE_VALUE
) {
5018 assert(sampler
.ud
>= 16);
5019 const int sampler_state_size
= 16; /* 16 bytes */
5021 ubld1
.ADD(component(header
, 3),
5022 retype(brw_vec1_grf(0, 3), BRW_REGISTER_TYPE_UD
),
5023 brw_imm_ud(16 * (sampler
.ud
/ 16) * sampler_state_size
));
5025 fs_reg tmp
= ubld1
.vgrf(BRW_REGISTER_TYPE_UD
);
5026 ubld1
.AND(tmp
, sampler
, brw_imm_ud(0x0f0));
5027 ubld1
.SHL(tmp
, tmp
, brw_imm_ud(4));
5028 ubld1
.ADD(component(header
, 3),
5029 retype(brw_vec1_grf(0, 3), BRW_REGISTER_TYPE_UD
),
5035 if (shadow_c
.file
!= BAD_FILE
) {
5036 bld
.MOV(sources
[length
], shadow_c
);
5040 bool coordinate_done
= false;
5042 /* Set up the LOD info */
5045 case SHADER_OPCODE_TXL
:
5046 if (devinfo
->gen
>= 9 && op
== SHADER_OPCODE_TXL
&& lod
.is_zero()) {
5047 op
= SHADER_OPCODE_TXL_LZ
;
5050 bld
.MOV(sources
[length
], lod
);
5053 case SHADER_OPCODE_TXD
:
5054 /* TXD should have been lowered in SIMD16 mode. */
5055 assert(bld
.dispatch_width() == 8);
5057 /* Load dPdx and the coordinate together:
5058 * [hdr], [ref], x, dPdx.x, dPdy.x, y, dPdx.y, dPdy.y, z, dPdx.z, dPdy.z
5060 for (unsigned i
= 0; i
< coord_components
; i
++) {
5061 bld
.MOV(sources
[length
++], offset(coordinate
, bld
, i
));
5063 /* For cube map array, the coordinate is (u,v,r,ai) but there are
5064 * only derivatives for (u, v, r).
5066 if (i
< grad_components
) {
5067 bld
.MOV(sources
[length
++], offset(lod
, bld
, i
));
5068 bld
.MOV(sources
[length
++], offset(lod2
, bld
, i
));
5072 coordinate_done
= true;
5074 case SHADER_OPCODE_TXS
:
5075 bld
.MOV(retype(sources
[length
], BRW_REGISTER_TYPE_UD
), lod
);
5078 case SHADER_OPCODE_IMAGE_SIZE_LOGICAL
:
5079 /* We need an LOD; just use 0 */
5080 bld
.MOV(retype(sources
[length
], BRW_REGISTER_TYPE_UD
), brw_imm_ud(0));
5083 case SHADER_OPCODE_TXF
:
5084 /* Unfortunately, the parameters for LD are intermixed: u, lod, v, r.
5085 * On Gen9 they are u, v, lod, r
5087 bld
.MOV(retype(sources
[length
++], BRW_REGISTER_TYPE_D
), coordinate
);
5089 if (devinfo
->gen
>= 9) {
5090 if (coord_components
>= 2) {
5091 bld
.MOV(retype(sources
[length
], BRW_REGISTER_TYPE_D
),
5092 offset(coordinate
, bld
, 1));
5094 sources
[length
] = brw_imm_d(0);
5099 if (devinfo
->gen
>= 9 && lod
.is_zero()) {
5100 op
= SHADER_OPCODE_TXF_LZ
;
5102 bld
.MOV(retype(sources
[length
], BRW_REGISTER_TYPE_D
), lod
);
5106 for (unsigned i
= devinfo
->gen
>= 9 ? 2 : 1; i
< coord_components
; i
++)
5107 bld
.MOV(retype(sources
[length
++], BRW_REGISTER_TYPE_D
),
5108 offset(coordinate
, bld
, i
));
5110 coordinate_done
= true;
5113 case SHADER_OPCODE_TXF_CMS
:
5114 case SHADER_OPCODE_TXF_CMS_W
:
5115 case SHADER_OPCODE_TXF_UMS
:
5116 case SHADER_OPCODE_TXF_MCS
:
5117 if (op
== SHADER_OPCODE_TXF_UMS
||
5118 op
== SHADER_OPCODE_TXF_CMS
||
5119 op
== SHADER_OPCODE_TXF_CMS_W
) {
5120 bld
.MOV(retype(sources
[length
], BRW_REGISTER_TYPE_UD
), sample_index
);
5124 if (op
== SHADER_OPCODE_TXF_CMS
|| op
== SHADER_OPCODE_TXF_CMS_W
) {
5125 /* Data from the multisample control surface. */
5126 bld
.MOV(retype(sources
[length
], BRW_REGISTER_TYPE_UD
), mcs
);
5129 /* On Gen9+ we'll use ld2dms_w instead which has two registers for
5132 if (op
== SHADER_OPCODE_TXF_CMS_W
) {
5133 bld
.MOV(retype(sources
[length
], BRW_REGISTER_TYPE_UD
),
5136 offset(mcs
, bld
, 1));
5141 /* There is no offsetting for this message; just copy in the integer
5142 * texture coordinates.
5144 for (unsigned i
= 0; i
< coord_components
; i
++)
5145 bld
.MOV(retype(sources
[length
++], BRW_REGISTER_TYPE_D
),
5146 offset(coordinate
, bld
, i
));
5148 coordinate_done
= true;
5150 case SHADER_OPCODE_TG4_OFFSET
:
5151 /* More crazy intermixing */
5152 for (unsigned i
= 0; i
< 2; i
++) /* u, v */
5153 bld
.MOV(sources
[length
++], offset(coordinate
, bld
, i
));
5155 for (unsigned i
= 0; i
< 2; i
++) /* offu, offv */
5156 bld
.MOV(retype(sources
[length
++], BRW_REGISTER_TYPE_D
),
5157 offset(tg4_offset
, bld
, i
));
5159 if (coord_components
== 3) /* r if present */
5160 bld
.MOV(sources
[length
++], offset(coordinate
, bld
, 2));
5162 coordinate_done
= true;
5168 /* Set up the coordinate (except for cases where it was done above) */
5169 if (!coordinate_done
) {
5170 for (unsigned i
= 0; i
< coord_components
; i
++)
5171 bld
.MOV(sources
[length
++], offset(coordinate
, bld
, i
));
5174 if (min_lod
.file
!= BAD_FILE
) {
5175 /* Account for all of the missing coordinate sources */
5176 length
+= 4 - coord_components
;
5177 if (op
== SHADER_OPCODE_TXD
)
5178 length
+= (3 - grad_components
) * 2;
5180 bld
.MOV(sources
[length
++], min_lod
);
5185 mlen
= length
* reg_width
- header_size
;
5187 mlen
= length
* reg_width
;
5189 const fs_reg src_payload
= fs_reg(VGRF
, bld
.shader
->alloc
.allocate(mlen
),
5190 BRW_REGISTER_TYPE_F
);
5191 bld
.LOAD_PAYLOAD(src_payload
, sources
, length
, header_size
);
5193 /* Generate the SEND. */
5194 inst
->opcode
= SHADER_OPCODE_SEND
;
5196 inst
->header_size
= header_size
;
5198 const unsigned msg_type
=
5199 sampler_msg_type(devinfo
, op
, inst
->shadow_compare
);
5200 const unsigned simd_mode
=
5201 inst
->exec_size
<= 8 ? BRW_SAMPLER_SIMD_MODE_SIMD8
:
5202 BRW_SAMPLER_SIMD_MODE_SIMD16
;
5204 uint32_t base_binding_table_index
;
5206 case SHADER_OPCODE_TG4
:
5207 case SHADER_OPCODE_TG4_OFFSET
:
5208 base_binding_table_index
= prog_data
->binding_table
.gather_texture_start
;
5210 case SHADER_OPCODE_IMAGE_SIZE_LOGICAL
:
5211 base_binding_table_index
= prog_data
->binding_table
.image_start
;
5214 base_binding_table_index
= prog_data
->binding_table
.texture_start
;
5218 inst
->sfid
= BRW_SFID_SAMPLER
;
5219 if (surface
.file
== IMM
&&
5220 (sampler
.file
== IMM
|| sampler_handle
.file
!= BAD_FILE
)) {
5221 inst
->desc
= brw_sampler_desc(devinfo
,
5222 surface
.ud
+ base_binding_table_index
,
5223 sampler
.file
== IMM
? sampler
.ud
% 16 : 0,
5226 0 /* return_format unused on gen7+ */);
5227 inst
->src
[0] = brw_imm_ud(0);
5228 inst
->src
[1] = brw_imm_ud(0); /* ex_desc */
5229 } else if (surface_handle
.file
!= BAD_FILE
) {
5230 /* Bindless surface */
5231 assert(devinfo
->gen
>= 9);
5232 inst
->desc
= brw_sampler_desc(devinfo
,
5234 sampler
.file
== IMM
? sampler
.ud
% 16 : 0,
5237 0 /* return_format unused on gen7+ */);
5239 /* For bindless samplers, the entire address is included in the message
5240 * header so we can leave the portion in the message descriptor 0.
5242 if (sampler_handle
.file
!= BAD_FILE
|| sampler
.file
== IMM
) {
5243 inst
->src
[0] = brw_imm_ud(0);
5245 const fs_builder ubld
= bld
.group(1, 0).exec_all();
5246 fs_reg desc
= ubld
.vgrf(BRW_REGISTER_TYPE_UD
);
5247 ubld
.SHL(desc
, sampler
, brw_imm_ud(8));
5248 inst
->src
[0] = desc
;
5251 /* We assume that the driver provided the handle in the top 20 bits so
5252 * we can use the surface handle directly as the extended descriptor.
5254 inst
->src
[1] = retype(surface_handle
, BRW_REGISTER_TYPE_UD
);
5256 /* Immediate portion of the descriptor */
5257 inst
->desc
= brw_sampler_desc(devinfo
,
5262 0 /* return_format unused on gen7+ */);
5263 const fs_builder ubld
= bld
.group(1, 0).exec_all();
5264 fs_reg desc
= ubld
.vgrf(BRW_REGISTER_TYPE_UD
);
5265 if (surface
.equals(sampler
)) {
5266 /* This case is common in GL */
5267 ubld
.MUL(desc
, surface
, brw_imm_ud(0x101));
5269 if (sampler_handle
.file
!= BAD_FILE
) {
5270 ubld
.MOV(desc
, surface
);
5271 } else if (sampler
.file
== IMM
) {
5272 ubld
.OR(desc
, surface
, brw_imm_ud(sampler
.ud
<< 8));
5274 ubld
.SHL(desc
, sampler
, brw_imm_ud(8));
5275 ubld
.OR(desc
, desc
, surface
);
5278 if (base_binding_table_index
)
5279 ubld
.ADD(desc
, desc
, brw_imm_ud(base_binding_table_index
));
5280 ubld
.AND(desc
, desc
, brw_imm_ud(0xfff));
5282 inst
->src
[0] = component(desc
, 0);
5283 inst
->src
[1] = brw_imm_ud(0); /* ex_desc */
5286 inst
->src
[2] = src_payload
;
5287 inst
->resize_sources(3);
5290 /* EOT sampler messages don't make sense to split because it would
5291 * involve ending half of the thread early.
5293 assert(inst
->group
== 0);
5294 /* We need to use SENDC for EOT sampler messages */
5295 inst
->check_tdr
= true;
5296 inst
->send_has_side_effects
= true;
5299 /* Message length > MAX_SAMPLER_MESSAGE_SIZE disallowed by hardware. */
5300 assert(inst
->mlen
<= MAX_SAMPLER_MESSAGE_SIZE
);
5304 lower_sampler_logical_send(const fs_builder
&bld
, fs_inst
*inst
, opcode op
)
5306 const gen_device_info
*devinfo
= bld
.shader
->devinfo
;
5307 const fs_reg
&coordinate
= inst
->src
[TEX_LOGICAL_SRC_COORDINATE
];
5308 const fs_reg
&shadow_c
= inst
->src
[TEX_LOGICAL_SRC_SHADOW_C
];
5309 const fs_reg
&lod
= inst
->src
[TEX_LOGICAL_SRC_LOD
];
5310 const fs_reg
&lod2
= inst
->src
[TEX_LOGICAL_SRC_LOD2
];
5311 const fs_reg
&min_lod
= inst
->src
[TEX_LOGICAL_SRC_MIN_LOD
];
5312 const fs_reg
&sample_index
= inst
->src
[TEX_LOGICAL_SRC_SAMPLE_INDEX
];
5313 const fs_reg
&mcs
= inst
->src
[TEX_LOGICAL_SRC_MCS
];
5314 const fs_reg
&surface
= inst
->src
[TEX_LOGICAL_SRC_SURFACE
];
5315 const fs_reg
&sampler
= inst
->src
[TEX_LOGICAL_SRC_SAMPLER
];
5316 const fs_reg
&surface_handle
= inst
->src
[TEX_LOGICAL_SRC_SURFACE_HANDLE
];
5317 const fs_reg
&sampler_handle
= inst
->src
[TEX_LOGICAL_SRC_SAMPLER_HANDLE
];
5318 const fs_reg
&tg4_offset
= inst
->src
[TEX_LOGICAL_SRC_TG4_OFFSET
];
5319 assert(inst
->src
[TEX_LOGICAL_SRC_COORD_COMPONENTS
].file
== IMM
);
5320 const unsigned coord_components
= inst
->src
[TEX_LOGICAL_SRC_COORD_COMPONENTS
].ud
;
5321 assert(inst
->src
[TEX_LOGICAL_SRC_GRAD_COMPONENTS
].file
== IMM
);
5322 const unsigned grad_components
= inst
->src
[TEX_LOGICAL_SRC_GRAD_COMPONENTS
].ud
;
5324 if (devinfo
->gen
>= 7) {
5325 lower_sampler_logical_send_gen7(bld
, inst
, op
, coordinate
,
5326 shadow_c
, lod
, lod2
, min_lod
,
5328 mcs
, surface
, sampler
,
5329 surface_handle
, sampler_handle
,
5331 coord_components
, grad_components
);
5332 } else if (devinfo
->gen
>= 5) {
5333 lower_sampler_logical_send_gen5(bld
, inst
, op
, coordinate
,
5334 shadow_c
, lod
, lod2
, sample_index
,
5336 coord_components
, grad_components
);
5338 lower_sampler_logical_send_gen4(bld
, inst
, op
, coordinate
,
5339 shadow_c
, lod
, lod2
,
5341 coord_components
, grad_components
);
5346 lower_surface_logical_send(const fs_builder
&bld
, fs_inst
*inst
)
5348 const gen_device_info
*devinfo
= bld
.shader
->devinfo
;
5350 /* Get the logical send arguments. */
5351 const fs_reg
&addr
= inst
->src
[SURFACE_LOGICAL_SRC_ADDRESS
];
5352 const fs_reg
&src
= inst
->src
[SURFACE_LOGICAL_SRC_DATA
];
5353 const fs_reg
&surface
= inst
->src
[SURFACE_LOGICAL_SRC_SURFACE
];
5354 const fs_reg
&surface_handle
= inst
->src
[SURFACE_LOGICAL_SRC_SURFACE_HANDLE
];
5355 const UNUSED fs_reg
&dims
= inst
->src
[SURFACE_LOGICAL_SRC_IMM_DIMS
];
5356 const fs_reg
&arg
= inst
->src
[SURFACE_LOGICAL_SRC_IMM_ARG
];
5357 assert(arg
.file
== IMM
);
5359 /* We must have exactly one of surface and surface_handle */
5360 assert((surface
.file
== BAD_FILE
) != (surface_handle
.file
== BAD_FILE
));
5362 /* Calculate the total number of components of the payload. */
5363 const unsigned addr_sz
= inst
->components_read(SURFACE_LOGICAL_SRC_ADDRESS
);
5364 const unsigned src_sz
= inst
->components_read(SURFACE_LOGICAL_SRC_DATA
);
5366 const bool is_typed_access
=
5367 inst
->opcode
== SHADER_OPCODE_TYPED_SURFACE_READ_LOGICAL
||
5368 inst
->opcode
== SHADER_OPCODE_TYPED_SURFACE_WRITE_LOGICAL
||
5369 inst
->opcode
== SHADER_OPCODE_TYPED_ATOMIC_LOGICAL
;
5371 const bool is_surface_access
= is_typed_access
||
5372 inst
->opcode
== SHADER_OPCODE_UNTYPED_SURFACE_READ_LOGICAL
||
5373 inst
->opcode
== SHADER_OPCODE_UNTYPED_SURFACE_WRITE_LOGICAL
||
5374 inst
->opcode
== SHADER_OPCODE_UNTYPED_ATOMIC_LOGICAL
;
5376 const bool is_stateless
=
5377 surface
.file
== IMM
&& (surface
.ud
== BRW_BTI_STATELESS
||
5378 surface
.ud
== GEN8_BTI_STATELESS_NON_COHERENT
);
5380 const bool has_side_effects
= inst
->has_side_effects();
5381 fs_reg sample_mask
= has_side_effects
? bld
.sample_mask_reg() :
5382 fs_reg(brw_imm_d(0xffff));
5384 /* From the BDW PRM Volume 7, page 147:
5386 * "For the Data Cache Data Port*, the header must be present for the
5387 * following message types: [...] Typed read/write/atomics"
5389 * Earlier generations have a similar wording. Because of this restriction
5390 * we don't attempt to implement sample masks via predication for such
5391 * messages prior to Gen9, since we have to provide a header anyway. On
5392 * Gen11+ the header has been removed so we can only use predication.
5394 * For all stateless A32 messages, we also need a header
5397 if ((devinfo
->gen
< 9 && is_typed_access
) || is_stateless
) {
5398 fs_builder ubld
= bld
.exec_all().group(8, 0);
5399 header
= ubld
.vgrf(BRW_REGISTER_TYPE_UD
);
5400 ubld
.MOV(header
, brw_imm_d(0));
5402 /* Both the typed and scattered byte/dword A32 messages take a buffer
5403 * base address in R0.5:[31:0] (See MH1_A32_PSM for typed messages or
5404 * MH_A32_GO for byte/dword scattered messages in the SKL PRM Vol. 2d
5405 * for more details.) This is conveniently where the HW places the
5406 * scratch surface base address.
5408 * From the SKL PRM Vol. 7 "Per-Thread Scratch Space":
5410 * "When a thread becomes 'active' it is allocated a portion of
5411 * scratch space, sized according to PerThreadScratchSpace. The
5412 * starting location of each thread’s scratch space allocation,
5413 * ScratchSpaceOffset, is passed in the thread payload in
5414 * R0.5[31:10] and is specified as a 1KB-granular offset from the
5415 * GeneralStateBaseAddress. The computation of ScratchSpaceOffset
5416 * includes the starting address of the stage’s scratch space
5417 * allocation, as programmed by ScratchSpaceBasePointer."
5419 * The base address is passed in bits R0.5[31:10] and the bottom 10
5420 * bits of R0.5 are used for other things. Therefore, we have to
5421 * mask off the bottom 10 bits so that we don't get a garbage base
5424 ubld
.group(1, 0).AND(component(header
, 5),
5425 retype(brw_vec1_grf(0, 5), BRW_REGISTER_TYPE_UD
),
5426 brw_imm_ud(0xfffffc00));
5428 if (is_surface_access
)
5429 ubld
.group(1, 0).MOV(component(header
, 7), sample_mask
);
5431 const unsigned header_sz
= header
.file
!= BAD_FILE
? 1 : 0;
5433 fs_reg payload
, payload2
;
5434 unsigned mlen
, ex_mlen
= 0;
5435 if (devinfo
->gen
>= 9 &&
5436 (src
.file
== BAD_FILE
|| header
.file
== BAD_FILE
)) {
5437 /* We have split sends on gen9 and above */
5438 if (header
.file
== BAD_FILE
) {
5439 payload
= bld
.move_to_vgrf(addr
, addr_sz
);
5440 payload2
= bld
.move_to_vgrf(src
, src_sz
);
5441 mlen
= addr_sz
* (inst
->exec_size
/ 8);
5442 ex_mlen
= src_sz
* (inst
->exec_size
/ 8);
5444 assert(src
.file
== BAD_FILE
);
5446 payload2
= bld
.move_to_vgrf(addr
, addr_sz
);
5448 ex_mlen
= addr_sz
* (inst
->exec_size
/ 8);
5451 /* Allocate space for the payload. */
5452 const unsigned sz
= header_sz
+ addr_sz
+ src_sz
;
5453 payload
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, sz
);
5454 fs_reg
*const components
= new fs_reg
[sz
];
5457 /* Construct the payload. */
5458 if (header
.file
!= BAD_FILE
)
5459 components
[n
++] = header
;
5461 for (unsigned i
= 0; i
< addr_sz
; i
++)
5462 components
[n
++] = offset(addr
, bld
, i
);
5464 for (unsigned i
= 0; i
< src_sz
; i
++)
5465 components
[n
++] = offset(src
, bld
, i
);
5467 bld
.LOAD_PAYLOAD(payload
, components
, sz
, header_sz
);
5468 mlen
= header_sz
+ (addr_sz
+ src_sz
) * inst
->exec_size
/ 8;
5470 delete[] components
;
5473 /* Predicate the instruction on the sample mask if no header is
5476 if ((header
.file
== BAD_FILE
|| !is_surface_access
) &&
5477 sample_mask
.file
!= BAD_FILE
&& sample_mask
.file
!= IMM
) {
5478 const fs_builder ubld
= bld
.group(1, 0).exec_all();
5479 if (inst
->predicate
) {
5480 assert(inst
->predicate
== BRW_PREDICATE_NORMAL
);
5481 assert(!inst
->predicate_inverse
);
5482 assert(inst
->flag_subreg
< 2);
5483 /* Combine the sample mask with the existing predicate by using a
5484 * vertical predication mode.
5486 inst
->predicate
= BRW_PREDICATE_ALIGN1_ALLV
;
5487 ubld
.MOV(retype(brw_flag_subreg(inst
->flag_subreg
+ 2),
5491 inst
->flag_subreg
= 2;
5492 inst
->predicate
= BRW_PREDICATE_NORMAL
;
5493 inst
->predicate_inverse
= false;
5494 ubld
.MOV(retype(brw_flag_subreg(inst
->flag_subreg
), sample_mask
.type
),
5500 switch (inst
->opcode
) {
5501 case SHADER_OPCODE_BYTE_SCATTERED_WRITE_LOGICAL
:
5502 case SHADER_OPCODE_BYTE_SCATTERED_READ_LOGICAL
:
5503 /* Byte scattered opcodes go through the normal data cache */
5504 sfid
= GEN7_SFID_DATAPORT_DATA_CACHE
;
5507 case SHADER_OPCODE_DWORD_SCATTERED_READ_LOGICAL
:
5508 case SHADER_OPCODE_DWORD_SCATTERED_WRITE_LOGICAL
:
5509 sfid
= devinfo
->gen
>= 7 ? GEN7_SFID_DATAPORT_DATA_CACHE
:
5510 devinfo
->gen
>= 6 ? GEN6_SFID_DATAPORT_RENDER_CACHE
:
5511 BRW_DATAPORT_READ_TARGET_RENDER_CACHE
;
5514 case SHADER_OPCODE_UNTYPED_SURFACE_READ_LOGICAL
:
5515 case SHADER_OPCODE_UNTYPED_SURFACE_WRITE_LOGICAL
:
5516 case SHADER_OPCODE_UNTYPED_ATOMIC_LOGICAL
:
5517 case SHADER_OPCODE_UNTYPED_ATOMIC_FLOAT_LOGICAL
:
5518 /* Untyped Surface messages go through the data cache but the SFID value
5519 * changed on Haswell.
5521 sfid
= (devinfo
->gen
>= 8 || devinfo
->is_haswell
?
5522 HSW_SFID_DATAPORT_DATA_CACHE_1
:
5523 GEN7_SFID_DATAPORT_DATA_CACHE
);
5526 case SHADER_OPCODE_TYPED_SURFACE_READ_LOGICAL
:
5527 case SHADER_OPCODE_TYPED_SURFACE_WRITE_LOGICAL
:
5528 case SHADER_OPCODE_TYPED_ATOMIC_LOGICAL
:
5529 /* Typed surface messages go through the render cache on IVB and the
5530 * data cache on HSW+.
5532 sfid
= (devinfo
->gen
>= 8 || devinfo
->is_haswell
?
5533 HSW_SFID_DATAPORT_DATA_CACHE_1
:
5534 GEN6_SFID_DATAPORT_RENDER_CACHE
);
5538 unreachable("Unsupported surface opcode");
5542 switch (inst
->opcode
) {
5543 case SHADER_OPCODE_UNTYPED_SURFACE_READ_LOGICAL
:
5544 desc
= brw_dp_untyped_surface_rw_desc(devinfo
, inst
->exec_size
,
5545 arg
.ud
, /* num_channels */
5549 case SHADER_OPCODE_UNTYPED_SURFACE_WRITE_LOGICAL
:
5550 desc
= brw_dp_untyped_surface_rw_desc(devinfo
, inst
->exec_size
,
5551 arg
.ud
, /* num_channels */
5555 case SHADER_OPCODE_BYTE_SCATTERED_READ_LOGICAL
:
5556 desc
= brw_dp_byte_scattered_rw_desc(devinfo
, inst
->exec_size
,
5557 arg
.ud
, /* bit_size */
5561 case SHADER_OPCODE_BYTE_SCATTERED_WRITE_LOGICAL
:
5562 desc
= brw_dp_byte_scattered_rw_desc(devinfo
, inst
->exec_size
,
5563 arg
.ud
, /* bit_size */
5567 case SHADER_OPCODE_DWORD_SCATTERED_READ_LOGICAL
:
5568 assert(arg
.ud
== 32); /* bit_size */
5569 desc
= brw_dp_dword_scattered_rw_desc(devinfo
, inst
->exec_size
,
5573 case SHADER_OPCODE_DWORD_SCATTERED_WRITE_LOGICAL
:
5574 assert(arg
.ud
== 32); /* bit_size */
5575 desc
= brw_dp_dword_scattered_rw_desc(devinfo
, inst
->exec_size
,
5579 case SHADER_OPCODE_UNTYPED_ATOMIC_LOGICAL
:
5580 desc
= brw_dp_untyped_atomic_desc(devinfo
, inst
->exec_size
,
5581 arg
.ud
, /* atomic_op */
5582 !inst
->dst
.is_null());
5585 case SHADER_OPCODE_UNTYPED_ATOMIC_FLOAT_LOGICAL
:
5586 desc
= brw_dp_untyped_atomic_float_desc(devinfo
, inst
->exec_size
,
5587 arg
.ud
, /* atomic_op */
5588 !inst
->dst
.is_null());
5591 case SHADER_OPCODE_TYPED_SURFACE_READ_LOGICAL
:
5592 desc
= brw_dp_typed_surface_rw_desc(devinfo
, inst
->exec_size
, inst
->group
,
5593 arg
.ud
, /* num_channels */
5597 case SHADER_OPCODE_TYPED_SURFACE_WRITE_LOGICAL
:
5598 desc
= brw_dp_typed_surface_rw_desc(devinfo
, inst
->exec_size
, inst
->group
,
5599 arg
.ud
, /* num_channels */
5603 case SHADER_OPCODE_TYPED_ATOMIC_LOGICAL
:
5604 desc
= brw_dp_typed_atomic_desc(devinfo
, inst
->exec_size
, inst
->group
,
5605 arg
.ud
, /* atomic_op */
5606 !inst
->dst
.is_null());
5610 unreachable("Unknown surface logical instruction");
5613 /* Update the original instruction. */
5614 inst
->opcode
= SHADER_OPCODE_SEND
;
5616 inst
->ex_mlen
= ex_mlen
;
5617 inst
->header_size
= header_sz
;
5618 inst
->send_has_side_effects
= has_side_effects
;
5619 inst
->send_is_volatile
= !has_side_effects
;
5621 /* Set up SFID and descriptors */
5624 if (surface
.file
== IMM
) {
5625 inst
->desc
|= surface
.ud
& 0xff;
5626 inst
->src
[0] = brw_imm_ud(0);
5627 inst
->src
[1] = brw_imm_ud(0); /* ex_desc */
5628 } else if (surface_handle
.file
!= BAD_FILE
) {
5629 /* Bindless surface */
5630 assert(devinfo
->gen
>= 9);
5631 inst
->desc
|= GEN9_BTI_BINDLESS
;
5632 inst
->src
[0] = brw_imm_ud(0);
5634 /* We assume that the driver provided the handle in the top 20 bits so
5635 * we can use the surface handle directly as the extended descriptor.
5637 inst
->src
[1] = retype(surface_handle
, BRW_REGISTER_TYPE_UD
);
5639 const fs_builder ubld
= bld
.exec_all().group(1, 0);
5640 fs_reg tmp
= ubld
.vgrf(BRW_REGISTER_TYPE_UD
);
5641 ubld
.AND(tmp
, surface
, brw_imm_ud(0xff));
5642 inst
->src
[0] = component(tmp
, 0);
5643 inst
->src
[1] = brw_imm_ud(0); /* ex_desc */
5646 /* Finally, the payload */
5647 inst
->src
[2] = payload
;
5648 inst
->src
[3] = payload2
;
5650 inst
->resize_sources(4);
5654 lower_a64_logical_send(const fs_builder
&bld
, fs_inst
*inst
)
5656 const gen_device_info
*devinfo
= bld
.shader
->devinfo
;
5658 const fs_reg
&addr
= inst
->src
[0];
5659 const fs_reg
&src
= inst
->src
[1];
5660 const unsigned src_comps
= inst
->components_read(1);
5661 assert(inst
->src
[2].file
== IMM
);
5662 const unsigned arg
= inst
->src
[2].ud
;
5663 const bool has_side_effects
= inst
->has_side_effects();
5665 /* If the surface message has side effects and we're a fragment shader, we
5666 * have to predicate with the sample mask to avoid helper invocations.
5668 if (has_side_effects
&& bld
.shader
->stage
== MESA_SHADER_FRAGMENT
) {
5669 inst
->flag_subreg
= 2;
5670 inst
->predicate
= BRW_PREDICATE_NORMAL
;
5671 inst
->predicate_inverse
= false;
5673 fs_reg sample_mask
= bld
.sample_mask_reg();
5674 const fs_builder ubld
= bld
.group(1, 0).exec_all();
5675 ubld
.MOV(retype(brw_flag_subreg(inst
->flag_subreg
), sample_mask
.type
),
5679 fs_reg payload
, payload2
;
5680 unsigned mlen
, ex_mlen
= 0;
5681 if (devinfo
->gen
>= 9) {
5682 /* On Skylake and above, we have SENDS */
5683 mlen
= 2 * (inst
->exec_size
/ 8);
5684 ex_mlen
= src_comps
* type_sz(src
.type
) * inst
->exec_size
/ REG_SIZE
;
5685 payload
= retype(bld
.move_to_vgrf(addr
, 1), BRW_REGISTER_TYPE_UD
);
5686 payload2
= retype(bld
.move_to_vgrf(src
, src_comps
),
5687 BRW_REGISTER_TYPE_UD
);
5689 /* Add two because the address is 64-bit */
5690 const unsigned dwords
= 2 + src_comps
;
5691 mlen
= dwords
* (inst
->exec_size
/ 8);
5697 for (unsigned i
= 0; i
< src_comps
; i
++)
5698 sources
[1 + i
] = offset(src
, bld
, i
);
5700 payload
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, dwords
);
5701 bld
.LOAD_PAYLOAD(payload
, sources
, 1 + src_comps
, 0);
5705 switch (inst
->opcode
) {
5706 case SHADER_OPCODE_A64_UNTYPED_READ_LOGICAL
:
5707 desc
= brw_dp_a64_untyped_surface_rw_desc(devinfo
, inst
->exec_size
,
5708 arg
, /* num_channels */
5712 case SHADER_OPCODE_A64_UNTYPED_WRITE_LOGICAL
:
5713 desc
= brw_dp_a64_untyped_surface_rw_desc(devinfo
, inst
->exec_size
,
5714 arg
, /* num_channels */
5718 case SHADER_OPCODE_A64_BYTE_SCATTERED_READ_LOGICAL
:
5719 desc
= brw_dp_a64_byte_scattered_rw_desc(devinfo
, inst
->exec_size
,
5724 case SHADER_OPCODE_A64_BYTE_SCATTERED_WRITE_LOGICAL
:
5725 desc
= brw_dp_a64_byte_scattered_rw_desc(devinfo
, inst
->exec_size
,
5730 case SHADER_OPCODE_A64_UNTYPED_ATOMIC_LOGICAL
:
5731 desc
= brw_dp_a64_untyped_atomic_desc(devinfo
, inst
->exec_size
, 32,
5732 arg
, /* atomic_op */
5733 !inst
->dst
.is_null());
5736 case SHADER_OPCODE_A64_UNTYPED_ATOMIC_INT64_LOGICAL
:
5737 desc
= brw_dp_a64_untyped_atomic_desc(devinfo
, inst
->exec_size
, 64,
5738 arg
, /* atomic_op */
5739 !inst
->dst
.is_null());
5743 case SHADER_OPCODE_A64_UNTYPED_ATOMIC_FLOAT_LOGICAL
:
5744 desc
= brw_dp_a64_untyped_atomic_float_desc(devinfo
, inst
->exec_size
,
5745 arg
, /* atomic_op */
5746 !inst
->dst
.is_null());
5750 unreachable("Unknown A64 logical instruction");
5753 /* Update the original instruction. */
5754 inst
->opcode
= SHADER_OPCODE_SEND
;
5756 inst
->ex_mlen
= ex_mlen
;
5757 inst
->header_size
= 0;
5758 inst
->send_has_side_effects
= has_side_effects
;
5759 inst
->send_is_volatile
= !has_side_effects
;
5761 /* Set up SFID and descriptors */
5762 inst
->sfid
= HSW_SFID_DATAPORT_DATA_CACHE_1
;
5764 inst
->resize_sources(4);
5765 inst
->src
[0] = brw_imm_ud(0); /* desc */
5766 inst
->src
[1] = brw_imm_ud(0); /* ex_desc */
5767 inst
->src
[2] = payload
;
5768 inst
->src
[3] = payload2
;
5772 lower_varying_pull_constant_logical_send(const fs_builder
&bld
, fs_inst
*inst
)
5774 const gen_device_info
*devinfo
= bld
.shader
->devinfo
;
5776 if (devinfo
->gen
>= 7) {
5777 fs_reg index
= inst
->src
[0];
5778 /* We are switching the instruction from an ALU-like instruction to a
5779 * send-from-grf instruction. Since sends can't handle strides or
5780 * source modifiers, we have to make a copy of the offset source.
5782 fs_reg offset
= bld
.vgrf(BRW_REGISTER_TYPE_UD
);
5783 bld
.MOV(offset
, inst
->src
[1]);
5785 const unsigned simd_mode
=
5786 inst
->exec_size
<= 8 ? BRW_SAMPLER_SIMD_MODE_SIMD8
:
5787 BRW_SAMPLER_SIMD_MODE_SIMD16
;
5789 inst
->opcode
= SHADER_OPCODE_SEND
;
5790 inst
->mlen
= inst
->exec_size
/ 8;
5791 inst
->resize_sources(3);
5793 inst
->sfid
= BRW_SFID_SAMPLER
;
5794 inst
->desc
= brw_sampler_desc(devinfo
, 0, 0,
5795 GEN5_SAMPLER_MESSAGE_SAMPLE_LD
,
5797 if (index
.file
== IMM
) {
5798 inst
->desc
|= index
.ud
& 0xff;
5799 inst
->src
[0] = brw_imm_ud(0);
5801 const fs_builder ubld
= bld
.exec_all().group(1, 0);
5802 fs_reg tmp
= ubld
.vgrf(BRW_REGISTER_TYPE_UD
);
5803 ubld
.AND(tmp
, index
, brw_imm_ud(0xff));
5804 inst
->src
[0] = component(tmp
, 0);
5806 inst
->src
[1] = brw_imm_ud(0); /* ex_desc */
5807 inst
->src
[2] = offset
; /* payload */
5809 const fs_reg
payload(MRF
, FIRST_PULL_LOAD_MRF(devinfo
->gen
),
5810 BRW_REGISTER_TYPE_UD
);
5812 bld
.MOV(byte_offset(payload
, REG_SIZE
), inst
->src
[1]);
5814 inst
->opcode
= FS_OPCODE_VARYING_PULL_CONSTANT_LOAD_GEN4
;
5815 inst
->resize_sources(1);
5816 inst
->base_mrf
= payload
.nr
;
5817 inst
->header_size
= 1;
5818 inst
->mlen
= 1 + inst
->exec_size
/ 8;
5823 lower_math_logical_send(const fs_builder
&bld
, fs_inst
*inst
)
5825 assert(bld
.shader
->devinfo
->gen
< 6);
5828 inst
->mlen
= inst
->sources
* inst
->exec_size
/ 8;
5830 if (inst
->sources
> 1) {
5831 /* From the Ironlake PRM, Volume 4, Part 1, Section 6.1.13
5832 * "Message Payload":
5834 * "Operand0[7]. For the INT DIV functions, this operand is the
5837 * "Operand1[7]. For the INT DIV functions, this operand is the
5840 const bool is_int_div
= inst
->opcode
!= SHADER_OPCODE_POW
;
5841 const fs_reg src0
= is_int_div
? inst
->src
[1] : inst
->src
[0];
5842 const fs_reg src1
= is_int_div
? inst
->src
[0] : inst
->src
[1];
5844 inst
->resize_sources(1);
5845 inst
->src
[0] = src0
;
5847 assert(inst
->exec_size
== 8);
5848 bld
.MOV(fs_reg(MRF
, inst
->base_mrf
+ 1, src1
.type
), src1
);
5853 fs_visitor::lower_logical_sends()
5855 bool progress
= false;
5857 foreach_block_and_inst_safe(block
, fs_inst
, inst
, cfg
) {
5858 const fs_builder
ibld(this, block
, inst
);
5860 switch (inst
->opcode
) {
5861 case FS_OPCODE_FB_WRITE_LOGICAL
:
5862 assert(stage
== MESA_SHADER_FRAGMENT
);
5863 lower_fb_write_logical_send(ibld
, inst
,
5864 brw_wm_prog_data(prog_data
),
5865 (const brw_wm_prog_key
*)key
,
5869 case FS_OPCODE_FB_READ_LOGICAL
:
5870 lower_fb_read_logical_send(ibld
, inst
);
5873 case SHADER_OPCODE_TEX_LOGICAL
:
5874 lower_sampler_logical_send(ibld
, inst
, SHADER_OPCODE_TEX
);
5877 case SHADER_OPCODE_TXD_LOGICAL
:
5878 lower_sampler_logical_send(ibld
, inst
, SHADER_OPCODE_TXD
);
5881 case SHADER_OPCODE_TXF_LOGICAL
:
5882 lower_sampler_logical_send(ibld
, inst
, SHADER_OPCODE_TXF
);
5885 case SHADER_OPCODE_TXL_LOGICAL
:
5886 lower_sampler_logical_send(ibld
, inst
, SHADER_OPCODE_TXL
);
5889 case SHADER_OPCODE_TXS_LOGICAL
:
5890 lower_sampler_logical_send(ibld
, inst
, SHADER_OPCODE_TXS
);
5893 case SHADER_OPCODE_IMAGE_SIZE_LOGICAL
:
5894 lower_sampler_logical_send(ibld
, inst
,
5895 SHADER_OPCODE_IMAGE_SIZE_LOGICAL
);
5898 case FS_OPCODE_TXB_LOGICAL
:
5899 lower_sampler_logical_send(ibld
, inst
, FS_OPCODE_TXB
);
5902 case SHADER_OPCODE_TXF_CMS_LOGICAL
:
5903 lower_sampler_logical_send(ibld
, inst
, SHADER_OPCODE_TXF_CMS
);
5906 case SHADER_OPCODE_TXF_CMS_W_LOGICAL
:
5907 lower_sampler_logical_send(ibld
, inst
, SHADER_OPCODE_TXF_CMS_W
);
5910 case SHADER_OPCODE_TXF_UMS_LOGICAL
:
5911 lower_sampler_logical_send(ibld
, inst
, SHADER_OPCODE_TXF_UMS
);
5914 case SHADER_OPCODE_TXF_MCS_LOGICAL
:
5915 lower_sampler_logical_send(ibld
, inst
, SHADER_OPCODE_TXF_MCS
);
5918 case SHADER_OPCODE_LOD_LOGICAL
:
5919 lower_sampler_logical_send(ibld
, inst
, SHADER_OPCODE_LOD
);
5922 case SHADER_OPCODE_TG4_LOGICAL
:
5923 lower_sampler_logical_send(ibld
, inst
, SHADER_OPCODE_TG4
);
5926 case SHADER_OPCODE_TG4_OFFSET_LOGICAL
:
5927 lower_sampler_logical_send(ibld
, inst
, SHADER_OPCODE_TG4_OFFSET
);
5930 case SHADER_OPCODE_SAMPLEINFO_LOGICAL
:
5931 lower_sampler_logical_send(ibld
, inst
, SHADER_OPCODE_SAMPLEINFO
);
5934 case SHADER_OPCODE_UNTYPED_SURFACE_READ_LOGICAL
:
5935 case SHADER_OPCODE_UNTYPED_SURFACE_WRITE_LOGICAL
:
5936 case SHADER_OPCODE_BYTE_SCATTERED_READ_LOGICAL
:
5937 case SHADER_OPCODE_BYTE_SCATTERED_WRITE_LOGICAL
:
5938 case SHADER_OPCODE_DWORD_SCATTERED_READ_LOGICAL
:
5939 case SHADER_OPCODE_DWORD_SCATTERED_WRITE_LOGICAL
:
5940 case SHADER_OPCODE_UNTYPED_ATOMIC_LOGICAL
:
5941 case SHADER_OPCODE_UNTYPED_ATOMIC_FLOAT_LOGICAL
:
5942 case SHADER_OPCODE_TYPED_SURFACE_READ_LOGICAL
:
5943 case SHADER_OPCODE_TYPED_SURFACE_WRITE_LOGICAL
:
5944 case SHADER_OPCODE_TYPED_ATOMIC_LOGICAL
:
5945 lower_surface_logical_send(ibld
, inst
);
5948 case SHADER_OPCODE_A64_UNTYPED_WRITE_LOGICAL
:
5949 case SHADER_OPCODE_A64_UNTYPED_READ_LOGICAL
:
5950 case SHADER_OPCODE_A64_BYTE_SCATTERED_WRITE_LOGICAL
:
5951 case SHADER_OPCODE_A64_BYTE_SCATTERED_READ_LOGICAL
:
5952 case SHADER_OPCODE_A64_UNTYPED_ATOMIC_LOGICAL
:
5953 case SHADER_OPCODE_A64_UNTYPED_ATOMIC_INT64_LOGICAL
:
5954 case SHADER_OPCODE_A64_UNTYPED_ATOMIC_FLOAT_LOGICAL
:
5955 lower_a64_logical_send(ibld
, inst
);
5958 case FS_OPCODE_VARYING_PULL_CONSTANT_LOAD_LOGICAL
:
5959 lower_varying_pull_constant_logical_send(ibld
, inst
);
5962 case SHADER_OPCODE_RCP
:
5963 case SHADER_OPCODE_RSQ
:
5964 case SHADER_OPCODE_SQRT
:
5965 case SHADER_OPCODE_EXP2
:
5966 case SHADER_OPCODE_LOG2
:
5967 case SHADER_OPCODE_SIN
:
5968 case SHADER_OPCODE_COS
:
5969 case SHADER_OPCODE_POW
:
5970 case SHADER_OPCODE_INT_QUOTIENT
:
5971 case SHADER_OPCODE_INT_REMAINDER
:
5972 /* The math opcodes are overloaded for the send-like and
5973 * expression-like instructions which seems kind of icky. Gen6+ has
5974 * a native (but rather quirky) MATH instruction so we don't need to
5975 * do anything here. On Gen4-5 we'll have to lower the Gen6-like
5976 * logical instructions (which we can easily recognize because they
5977 * have mlen = 0) into send-like virtual instructions.
5979 if (devinfo
->gen
< 6 && inst
->mlen
== 0) {
5980 lower_math_logical_send(ibld
, inst
);
5995 invalidate_live_intervals();
6001 is_mixed_float_with_fp32_dst(const fs_inst
*inst
)
6003 /* This opcode sometimes uses :W type on the source even if the operand is
6004 * a :HF, because in gen7 there is no support for :HF, and thus it uses :W.
6006 if (inst
->opcode
== BRW_OPCODE_F16TO32
)
6009 if (inst
->dst
.type
!= BRW_REGISTER_TYPE_F
)
6012 for (int i
= 0; i
< inst
->sources
; i
++) {
6013 if (inst
->src
[i
].type
== BRW_REGISTER_TYPE_HF
)
6021 is_mixed_float_with_packed_fp16_dst(const fs_inst
*inst
)
6023 /* This opcode sometimes uses :W type on the destination even if the
6024 * destination is a :HF, because in gen7 there is no support for :HF, and
6027 if (inst
->opcode
== BRW_OPCODE_F32TO16
&&
6028 inst
->dst
.stride
== 1)
6031 if (inst
->dst
.type
!= BRW_REGISTER_TYPE_HF
||
6032 inst
->dst
.stride
!= 1)
6035 for (int i
= 0; i
< inst
->sources
; i
++) {
6036 if (inst
->src
[i
].type
== BRW_REGISTER_TYPE_F
)
6044 * Get the closest allowed SIMD width for instruction \p inst accounting for
6045 * some common regioning and execution control restrictions that apply to FPU
6046 * instructions. These restrictions don't necessarily have any relevance to
6047 * instructions not executed by the FPU pipeline like extended math, control
6048 * flow or send message instructions.
6050 * For virtual opcodes it's really up to the instruction -- In some cases
6051 * (e.g. where a virtual instruction unrolls into a simple sequence of FPU
6052 * instructions) it may simplify virtual instruction lowering if we can
6053 * enforce FPU-like regioning restrictions already on the virtual instruction,
6054 * in other cases (e.g. virtual send-like instructions) this may be
6055 * excessively restrictive.
6058 get_fpu_lowered_simd_width(const struct gen_device_info
*devinfo
,
6059 const fs_inst
*inst
)
6061 /* Maximum execution size representable in the instruction controls. */
6062 unsigned max_width
= MIN2(32, inst
->exec_size
);
6064 /* According to the PRMs:
6065 * "A. In Direct Addressing mode, a source cannot span more than 2
6066 * adjacent GRF registers.
6067 * B. A destination cannot span more than 2 adjacent GRF registers."
6069 * Look for the source or destination with the largest register region
6070 * which is the one that is going to limit the overall execution size of
6071 * the instruction due to this rule.
6073 unsigned reg_count
= DIV_ROUND_UP(inst
->size_written
, REG_SIZE
);
6075 for (unsigned i
= 0; i
< inst
->sources
; i
++)
6076 reg_count
= MAX2(reg_count
, DIV_ROUND_UP(inst
->size_read(i
), REG_SIZE
));
6078 /* Calculate the maximum execution size of the instruction based on the
6079 * factor by which it goes over the hardware limit of 2 GRFs.
6082 max_width
= MIN2(max_width
, inst
->exec_size
/ DIV_ROUND_UP(reg_count
, 2));
6084 /* According to the IVB PRMs:
6085 * "When destination spans two registers, the source MUST span two
6086 * registers. The exception to the above rule:
6088 * - When source is scalar, the source registers are not incremented.
6089 * - When source is packed integer Word and destination is packed
6090 * integer DWord, the source register is not incremented but the
6091 * source sub register is incremented."
6093 * The hardware specs from Gen4 to Gen7.5 mention similar regioning
6094 * restrictions. The code below intentionally doesn't check whether the
6095 * destination type is integer because empirically the hardware doesn't
6096 * seem to care what the actual type is as long as it's dword-aligned.
6098 if (devinfo
->gen
< 8) {
6099 for (unsigned i
= 0; i
< inst
->sources
; i
++) {
6100 /* IVB implements DF scalars as <0;2,1> regions. */
6101 const bool is_scalar_exception
= is_uniform(inst
->src
[i
]) &&
6102 (devinfo
->is_haswell
|| type_sz(inst
->src
[i
].type
) != 8);
6103 const bool is_packed_word_exception
=
6104 type_sz(inst
->dst
.type
) == 4 && inst
->dst
.stride
== 1 &&
6105 type_sz(inst
->src
[i
].type
) == 2 && inst
->src
[i
].stride
== 1;
6107 /* We check size_read(i) against size_written instead of REG_SIZE
6108 * because we want to properly handle SIMD32. In SIMD32, you can end
6109 * up with writes to 4 registers and a source that reads 2 registers
6110 * and we may still need to lower all the way to SIMD8 in that case.
6112 if (inst
->size_written
> REG_SIZE
&&
6113 inst
->size_read(i
) != 0 &&
6114 inst
->size_read(i
) < inst
->size_written
&&
6115 !is_scalar_exception
&& !is_packed_word_exception
) {
6116 const unsigned reg_count
= DIV_ROUND_UP(inst
->size_written
, REG_SIZE
);
6117 max_width
= MIN2(max_width
, inst
->exec_size
/ reg_count
);
6122 if (devinfo
->gen
< 6) {
6123 /* From the G45 PRM, Volume 4 Page 361:
6125 * "Operand Alignment Rule: With the exceptions listed below, a
6126 * source/destination operand in general should be aligned to even
6127 * 256-bit physical register with a region size equal to two 256-bit
6128 * physical registers."
6130 * Normally we enforce this by allocating virtual registers to the
6131 * even-aligned class. But we need to handle payload registers.
6133 for (unsigned i
= 0; i
< inst
->sources
; i
++) {
6134 if (inst
->src
[i
].file
== FIXED_GRF
&& (inst
->src
[i
].nr
& 1) &&
6135 inst
->size_read(i
) > REG_SIZE
) {
6136 max_width
= MIN2(max_width
, 8);
6141 /* From the IVB PRMs:
6142 * "When an instruction is SIMD32, the low 16 bits of the execution mask
6143 * are applied for both halves of the SIMD32 instruction. If different
6144 * execution mask channels are required, split the instruction into two
6145 * SIMD16 instructions."
6147 * There is similar text in the HSW PRMs. Gen4-6 don't even implement
6148 * 32-wide control flow support in hardware and will behave similarly.
6150 if (devinfo
->gen
< 8 && !inst
->force_writemask_all
)
6151 max_width
= MIN2(max_width
, 16);
6153 /* From the IVB PRMs (applies to HSW too):
6154 * "Instructions with condition modifiers must not use SIMD32."
6156 * From the BDW PRMs (applies to later hardware too):
6157 * "Ternary instruction with condition modifiers must not use SIMD32."
6159 if (inst
->conditional_mod
&& (devinfo
->gen
< 8 || inst
->is_3src(devinfo
)))
6160 max_width
= MIN2(max_width
, 16);
6162 /* From the IVB PRMs (applies to other devices that don't have the
6163 * gen_device_info::supports_simd16_3src flag set):
6164 * "In Align16 access mode, SIMD16 is not allowed for DW operations and
6165 * SIMD8 is not allowed for DF operations."
6167 if (inst
->is_3src(devinfo
) && !devinfo
->supports_simd16_3src
)
6168 max_width
= MIN2(max_width
, inst
->exec_size
/ reg_count
);
6170 /* Pre-Gen8 EUs are hardwired to use the QtrCtrl+1 (where QtrCtrl is
6171 * the 8-bit quarter of the execution mask signals specified in the
6172 * instruction control fields) for the second compressed half of any
6173 * single-precision instruction (for double-precision instructions
6174 * it's hardwired to use NibCtrl+1, at least on HSW), which means that
6175 * the EU will apply the wrong execution controls for the second
6176 * sequential GRF write if the number of channels per GRF is not exactly
6177 * eight in single-precision mode (or four in double-float mode).
6179 * In this situation we calculate the maximum size of the split
6180 * instructions so they only ever write to a single register.
6182 if (devinfo
->gen
< 8 && inst
->size_written
> REG_SIZE
&&
6183 !inst
->force_writemask_all
) {
6184 const unsigned channels_per_grf
= inst
->exec_size
/
6185 DIV_ROUND_UP(inst
->size_written
, REG_SIZE
);
6186 const unsigned exec_type_size
= get_exec_type_size(inst
);
6187 assert(exec_type_size
);
6189 /* The hardware shifts exactly 8 channels per compressed half of the
6190 * instruction in single-precision mode and exactly 4 in double-precision.
6192 if (channels_per_grf
!= (exec_type_size
== 8 ? 4 : 8))
6193 max_width
= MIN2(max_width
, channels_per_grf
);
6195 /* Lower all non-force_writemask_all DF instructions to SIMD4 on IVB/BYT
6196 * because HW applies the same channel enable signals to both halves of
6197 * the compressed instruction which will be just wrong under
6198 * non-uniform control flow.
6200 if (devinfo
->gen
== 7 && !devinfo
->is_haswell
&&
6201 (exec_type_size
== 8 || type_sz(inst
->dst
.type
) == 8))
6202 max_width
= MIN2(max_width
, 4);
6205 /* From the SKL PRM, Special Restrictions for Handling Mixed Mode
6208 * "No SIMD16 in mixed mode when destination is f32. Instruction
6209 * execution size must be no more than 8."
6211 * FIXME: the simulator doesn't seem to complain if we don't do this and
6212 * empirical testing with existing CTS tests show that they pass just fine
6213 * without implementing this, however, since our interpretation of the PRM
6214 * is that conversion MOVs between HF and F are still mixed-float
6215 * instructions (and therefore subject to this restriction) we decided to
6216 * split them to be safe. Might be useful to do additional investigation to
6217 * lift the restriction if we can ensure that it is safe though, since these
6218 * conversions are common when half-float types are involved since many
6219 * instructions do not support HF types and conversions from/to F are
6222 if (is_mixed_float_with_fp32_dst(inst
))
6223 max_width
= MIN2(max_width
, 8);
6225 /* From the SKL PRM, Special Restrictions for Handling Mixed Mode
6228 * "No SIMD16 in mixed mode when destination is packed f16 for both
6229 * Align1 and Align16."
6231 if (is_mixed_float_with_packed_fp16_dst(inst
))
6232 max_width
= MIN2(max_width
, 8);
6234 /* Only power-of-two execution sizes are representable in the instruction
6237 return 1 << _mesa_logbase2(max_width
);
6241 * Get the maximum allowed SIMD width for instruction \p inst accounting for
6242 * various payload size restrictions that apply to sampler message
6245 * This is only intended to provide a maximum theoretical bound for the
6246 * execution size of the message based on the number of argument components
6247 * alone, which in most cases will determine whether the SIMD8 or SIMD16
6248 * variant of the message can be used, though some messages may have
6249 * additional restrictions not accounted for here (e.g. pre-ILK hardware uses
6250 * the message length to determine the exact SIMD width and argument count,
6251 * which makes a number of sampler message combinations impossible to
6255 get_sampler_lowered_simd_width(const struct gen_device_info
*devinfo
,
6256 const fs_inst
*inst
)
6258 /* If we have a min_lod parameter on anything other than a simple sample
6259 * message, it will push it over 5 arguments and we have to fall back to
6262 if (inst
->opcode
!= SHADER_OPCODE_TEX
&&
6263 inst
->components_read(TEX_LOGICAL_SRC_MIN_LOD
))
6266 /* Calculate the number of coordinate components that have to be present
6267 * assuming that additional arguments follow the texel coordinates in the
6268 * message payload. On IVB+ there is no need for padding, on ILK-SNB we
6269 * need to pad to four or three components depending on the message,
6270 * pre-ILK we need to pad to at most three components.
6272 const unsigned req_coord_components
=
6273 (devinfo
->gen
>= 7 ||
6274 !inst
->components_read(TEX_LOGICAL_SRC_COORDINATE
)) ? 0 :
6275 (devinfo
->gen
>= 5 && inst
->opcode
!= SHADER_OPCODE_TXF_LOGICAL
&&
6276 inst
->opcode
!= SHADER_OPCODE_TXF_CMS_LOGICAL
) ? 4 :
6279 /* On Gen9+ the LOD argument is for free if we're able to use the LZ
6280 * variant of the TXL or TXF message.
6282 const bool implicit_lod
= devinfo
->gen
>= 9 &&
6283 (inst
->opcode
== SHADER_OPCODE_TXL
||
6284 inst
->opcode
== SHADER_OPCODE_TXF
) &&
6285 inst
->src
[TEX_LOGICAL_SRC_LOD
].is_zero();
6287 /* Calculate the total number of argument components that need to be passed
6288 * to the sampler unit.
6290 const unsigned num_payload_components
=
6291 MAX2(inst
->components_read(TEX_LOGICAL_SRC_COORDINATE
),
6292 req_coord_components
) +
6293 inst
->components_read(TEX_LOGICAL_SRC_SHADOW_C
) +
6294 (implicit_lod
? 0 : inst
->components_read(TEX_LOGICAL_SRC_LOD
)) +
6295 inst
->components_read(TEX_LOGICAL_SRC_LOD2
) +
6296 inst
->components_read(TEX_LOGICAL_SRC_SAMPLE_INDEX
) +
6297 (inst
->opcode
== SHADER_OPCODE_TG4_OFFSET_LOGICAL
?
6298 inst
->components_read(TEX_LOGICAL_SRC_TG4_OFFSET
) : 0) +
6299 inst
->components_read(TEX_LOGICAL_SRC_MCS
);
6301 /* SIMD16 messages with more than five arguments exceed the maximum message
6302 * size supported by the sampler, regardless of whether a header is
6305 return MIN2(inst
->exec_size
,
6306 num_payload_components
> MAX_SAMPLER_MESSAGE_SIZE
/ 2 ? 8 : 16);
6310 * Get the closest native SIMD width supported by the hardware for instruction
6311 * \p inst. The instruction will be left untouched by
6312 * fs_visitor::lower_simd_width() if the returned value is equal to the
6313 * original execution size.
6316 get_lowered_simd_width(const struct gen_device_info
*devinfo
,
6317 const fs_inst
*inst
)
6319 switch (inst
->opcode
) {
6320 case BRW_OPCODE_MOV
:
6321 case BRW_OPCODE_SEL
:
6322 case BRW_OPCODE_NOT
:
6323 case BRW_OPCODE_AND
:
6325 case BRW_OPCODE_XOR
:
6326 case BRW_OPCODE_SHR
:
6327 case BRW_OPCODE_SHL
:
6328 case BRW_OPCODE_ASR
:
6329 case BRW_OPCODE_CMPN
:
6330 case BRW_OPCODE_CSEL
:
6331 case BRW_OPCODE_F32TO16
:
6332 case BRW_OPCODE_F16TO32
:
6333 case BRW_OPCODE_BFREV
:
6334 case BRW_OPCODE_BFE
:
6335 case BRW_OPCODE_ADD
:
6336 case BRW_OPCODE_MUL
:
6337 case BRW_OPCODE_AVG
:
6338 case BRW_OPCODE_FRC
:
6339 case BRW_OPCODE_RNDU
:
6340 case BRW_OPCODE_RNDD
:
6341 case BRW_OPCODE_RNDE
:
6342 case BRW_OPCODE_RNDZ
:
6343 case BRW_OPCODE_LZD
:
6344 case BRW_OPCODE_FBH
:
6345 case BRW_OPCODE_FBL
:
6346 case BRW_OPCODE_CBIT
:
6347 case BRW_OPCODE_SAD2
:
6348 case BRW_OPCODE_MAD
:
6349 case BRW_OPCODE_LRP
:
6350 case FS_OPCODE_PACK
:
6351 case SHADER_OPCODE_SEL_EXEC
:
6352 case SHADER_OPCODE_CLUSTER_BROADCAST
:
6353 return get_fpu_lowered_simd_width(devinfo
, inst
);
6355 case BRW_OPCODE_CMP
: {
6356 /* The Ivybridge/BayTrail WaCMPInstFlagDepClearedEarly workaround says that
6357 * when the destination is a GRF the dependency-clear bit on the flag
6358 * register is cleared early.
6360 * Suggested workarounds are to disable coissuing CMP instructions
6361 * or to split CMP(16) instructions into two CMP(8) instructions.
6363 * We choose to split into CMP(8) instructions since disabling
6364 * coissuing would affect CMP instructions not otherwise affected by
6367 const unsigned max_width
= (devinfo
->gen
== 7 && !devinfo
->is_haswell
&&
6368 !inst
->dst
.is_null() ? 8 : ~0);
6369 return MIN2(max_width
, get_fpu_lowered_simd_width(devinfo
, inst
));
6371 case BRW_OPCODE_BFI1
:
6372 case BRW_OPCODE_BFI2
:
6373 /* The Haswell WaForceSIMD8ForBFIInstruction workaround says that we
6375 * "Force BFI instructions to be executed always in SIMD8."
6377 return MIN2(devinfo
->is_haswell
? 8 : ~0u,
6378 get_fpu_lowered_simd_width(devinfo
, inst
));
6381 assert(inst
->src
[0].file
== BAD_FILE
|| inst
->exec_size
<= 16);
6382 return inst
->exec_size
;
6384 case SHADER_OPCODE_RCP
:
6385 case SHADER_OPCODE_RSQ
:
6386 case SHADER_OPCODE_SQRT
:
6387 case SHADER_OPCODE_EXP2
:
6388 case SHADER_OPCODE_LOG2
:
6389 case SHADER_OPCODE_SIN
:
6390 case SHADER_OPCODE_COS
: {
6391 /* Unary extended math instructions are limited to SIMD8 on Gen4 and
6392 * Gen6. Extended Math Function is limited to SIMD8 with half-float.
6394 if (devinfo
->gen
== 6 || (devinfo
->gen
== 4 && !devinfo
->is_g4x
))
6395 return MIN2(8, inst
->exec_size
);
6396 if (inst
->dst
.type
== BRW_REGISTER_TYPE_HF
)
6397 return MIN2(8, inst
->exec_size
);
6398 return MIN2(16, inst
->exec_size
);
6401 case SHADER_OPCODE_POW
: {
6402 /* SIMD16 is only allowed on Gen7+. Extended Math Function is limited
6403 * to SIMD8 with half-float
6405 if (devinfo
->gen
< 7)
6406 return MIN2(8, inst
->exec_size
);
6407 if (inst
->dst
.type
== BRW_REGISTER_TYPE_HF
)
6408 return MIN2(8, inst
->exec_size
);
6409 return MIN2(16, inst
->exec_size
);
6412 case SHADER_OPCODE_INT_QUOTIENT
:
6413 case SHADER_OPCODE_INT_REMAINDER
:
6414 /* Integer division is limited to SIMD8 on all generations. */
6415 return MIN2(8, inst
->exec_size
);
6417 case FS_OPCODE_LINTERP
:
6418 case SHADER_OPCODE_GET_BUFFER_SIZE
:
6419 case FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD
:
6420 case FS_OPCODE_PACK_HALF_2x16_SPLIT
:
6421 case FS_OPCODE_INTERPOLATE_AT_SAMPLE
:
6422 case FS_OPCODE_INTERPOLATE_AT_SHARED_OFFSET
:
6423 case FS_OPCODE_INTERPOLATE_AT_PER_SLOT_OFFSET
:
6424 return MIN2(16, inst
->exec_size
);
6426 case FS_OPCODE_VARYING_PULL_CONSTANT_LOAD_LOGICAL
:
6427 /* Pre-ILK hardware doesn't have a SIMD8 variant of the texel fetch
6428 * message used to implement varying pull constant loads, so expand it
6429 * to SIMD16. An alternative with longer message payload length but
6430 * shorter return payload would be to use the SIMD8 sampler message that
6431 * takes (header, u, v, r) as parameters instead of (header, u).
6433 return (devinfo
->gen
== 4 ? 16 : MIN2(16, inst
->exec_size
));
6435 case FS_OPCODE_DDX_COARSE
:
6436 case FS_OPCODE_DDX_FINE
:
6437 case FS_OPCODE_DDY_COARSE
:
6438 case FS_OPCODE_DDY_FINE
:
6439 /* The implementation of this virtual opcode may require emitting
6440 * compressed Align16 instructions, which are severely limited on some
6443 * From the Ivy Bridge PRM, volume 4 part 3, section 3.3.9 (Register
6444 * Region Restrictions):
6446 * "In Align16 access mode, SIMD16 is not allowed for DW operations
6447 * and SIMD8 is not allowed for DF operations."
6449 * In this context, "DW operations" means "operations acting on 32-bit
6450 * values", so it includes operations on floats.
6452 * Gen4 has a similar restriction. From the i965 PRM, section 11.5.3
6453 * (Instruction Compression -> Rules and Restrictions):
6455 * "A compressed instruction must be in Align1 access mode. Align16
6456 * mode instructions cannot be compressed."
6458 * Similar text exists in the g45 PRM.
6460 * Empirically, compressed align16 instructions using odd register
6461 * numbers don't appear to work on Sandybridge either.
6463 return (devinfo
->gen
== 4 || devinfo
->gen
== 6 ||
6464 (devinfo
->gen
== 7 && !devinfo
->is_haswell
) ?
6465 MIN2(8, inst
->exec_size
) : MIN2(16, inst
->exec_size
));
6467 case SHADER_OPCODE_MULH
:
6468 /* MULH is lowered to the MUL/MACH sequence using the accumulator, which
6469 * is 8-wide on Gen7+.
6471 return (devinfo
->gen
>= 7 ? 8 :
6472 get_fpu_lowered_simd_width(devinfo
, inst
));
6474 case FS_OPCODE_FB_WRITE_LOGICAL
:
6475 /* Gen6 doesn't support SIMD16 depth writes but we cannot handle them
6478 assert(devinfo
->gen
!= 6 ||
6479 inst
->src
[FB_WRITE_LOGICAL_SRC_SRC_DEPTH
].file
== BAD_FILE
||
6480 inst
->exec_size
== 8);
6481 /* Dual-source FB writes are unsupported in SIMD16 mode. */
6482 return (inst
->src
[FB_WRITE_LOGICAL_SRC_COLOR1
].file
!= BAD_FILE
?
6483 8 : MIN2(16, inst
->exec_size
));
6485 case FS_OPCODE_FB_READ_LOGICAL
:
6486 return MIN2(16, inst
->exec_size
);
6488 case SHADER_OPCODE_TEX_LOGICAL
:
6489 case SHADER_OPCODE_TXF_CMS_LOGICAL
:
6490 case SHADER_OPCODE_TXF_UMS_LOGICAL
:
6491 case SHADER_OPCODE_TXF_MCS_LOGICAL
:
6492 case SHADER_OPCODE_LOD_LOGICAL
:
6493 case SHADER_OPCODE_TG4_LOGICAL
:
6494 case SHADER_OPCODE_SAMPLEINFO_LOGICAL
:
6495 case SHADER_OPCODE_TXF_CMS_W_LOGICAL
:
6496 case SHADER_OPCODE_TG4_OFFSET_LOGICAL
:
6497 return get_sampler_lowered_simd_width(devinfo
, inst
);
6499 case SHADER_OPCODE_TXD_LOGICAL
:
6500 /* TXD is unsupported in SIMD16 mode. */
6503 case SHADER_OPCODE_TXL_LOGICAL
:
6504 case FS_OPCODE_TXB_LOGICAL
:
6505 /* Only one execution size is representable pre-ILK depending on whether
6506 * the shadow reference argument is present.
6508 if (devinfo
->gen
== 4)
6509 return inst
->src
[TEX_LOGICAL_SRC_SHADOW_C
].file
== BAD_FILE
? 16 : 8;
6511 return get_sampler_lowered_simd_width(devinfo
, inst
);
6513 case SHADER_OPCODE_TXF_LOGICAL
:
6514 case SHADER_OPCODE_TXS_LOGICAL
:
6515 /* Gen4 doesn't have SIMD8 variants for the RESINFO and LD-with-LOD
6516 * messages. Use SIMD16 instead.
6518 if (devinfo
->gen
== 4)
6521 return get_sampler_lowered_simd_width(devinfo
, inst
);
6523 case SHADER_OPCODE_TYPED_ATOMIC_LOGICAL
:
6524 case SHADER_OPCODE_TYPED_SURFACE_READ_LOGICAL
:
6525 case SHADER_OPCODE_TYPED_SURFACE_WRITE_LOGICAL
:
6528 case SHADER_OPCODE_UNTYPED_ATOMIC_LOGICAL
:
6529 case SHADER_OPCODE_UNTYPED_ATOMIC_FLOAT_LOGICAL
:
6530 case SHADER_OPCODE_UNTYPED_SURFACE_READ_LOGICAL
:
6531 case SHADER_OPCODE_UNTYPED_SURFACE_WRITE_LOGICAL
:
6532 case SHADER_OPCODE_BYTE_SCATTERED_WRITE_LOGICAL
:
6533 case SHADER_OPCODE_BYTE_SCATTERED_READ_LOGICAL
:
6534 case SHADER_OPCODE_DWORD_SCATTERED_WRITE_LOGICAL
:
6535 case SHADER_OPCODE_DWORD_SCATTERED_READ_LOGICAL
:
6536 return MIN2(16, inst
->exec_size
);
6538 case SHADER_OPCODE_A64_UNTYPED_WRITE_LOGICAL
:
6539 case SHADER_OPCODE_A64_UNTYPED_READ_LOGICAL
:
6540 case SHADER_OPCODE_A64_BYTE_SCATTERED_WRITE_LOGICAL
:
6541 case SHADER_OPCODE_A64_BYTE_SCATTERED_READ_LOGICAL
:
6542 return devinfo
->gen
<= 8 ? 8 : MIN2(16, inst
->exec_size
);
6544 case SHADER_OPCODE_A64_UNTYPED_ATOMIC_LOGICAL
:
6545 case SHADER_OPCODE_A64_UNTYPED_ATOMIC_INT64_LOGICAL
:
6546 case SHADER_OPCODE_A64_UNTYPED_ATOMIC_FLOAT_LOGICAL
:
6549 case SHADER_OPCODE_URB_READ_SIMD8
:
6550 case SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT
:
6551 case SHADER_OPCODE_URB_WRITE_SIMD8
:
6552 case SHADER_OPCODE_URB_WRITE_SIMD8_PER_SLOT
:
6553 case SHADER_OPCODE_URB_WRITE_SIMD8_MASKED
:
6554 case SHADER_OPCODE_URB_WRITE_SIMD8_MASKED_PER_SLOT
:
6555 return MIN2(8, inst
->exec_size
);
6557 case SHADER_OPCODE_QUAD_SWIZZLE
: {
6558 const unsigned swiz
= inst
->src
[1].ud
;
6559 return (is_uniform(inst
->src
[0]) ?
6560 get_fpu_lowered_simd_width(devinfo
, inst
) :
6561 devinfo
->gen
< 11 && type_sz(inst
->src
[0].type
) == 4 ? 8 :
6562 swiz
== BRW_SWIZZLE_XYXY
|| swiz
== BRW_SWIZZLE_ZWZW
? 4 :
6563 get_fpu_lowered_simd_width(devinfo
, inst
));
6565 case SHADER_OPCODE_MOV_INDIRECT
: {
6566 /* From IVB and HSW PRMs:
6568 * "2.When the destination requires two registers and the sources are
6569 * indirect, the sources must use 1x1 regioning mode.
6571 * In case of DF instructions in HSW/IVB, the exec_size is limited by
6572 * the EU decompression logic not handling VxH indirect addressing
6575 const unsigned max_size
= (devinfo
->gen
>= 8 ? 2 : 1) * REG_SIZE
;
6576 /* Prior to Broadwell, we only have 8 address subregisters. */
6577 return MIN3(devinfo
->gen
>= 8 ? 16 : 8,
6578 max_size
/ (inst
->dst
.stride
* type_sz(inst
->dst
.type
)),
6582 case SHADER_OPCODE_LOAD_PAYLOAD
: {
6583 const unsigned reg_count
=
6584 DIV_ROUND_UP(inst
->dst
.component_size(inst
->exec_size
), REG_SIZE
);
6586 if (reg_count
> 2) {
6587 /* Only LOAD_PAYLOAD instructions with per-channel destination region
6588 * can be easily lowered (which excludes headers and heterogeneous
6591 assert(!inst
->header_size
);
6592 for (unsigned i
= 0; i
< inst
->sources
; i
++)
6593 assert(type_sz(inst
->dst
.type
) == type_sz(inst
->src
[i
].type
) ||
6594 inst
->src
[i
].file
== BAD_FILE
);
6596 return inst
->exec_size
/ DIV_ROUND_UP(reg_count
, 2);
6598 return inst
->exec_size
;
6602 return inst
->exec_size
;
6607 * Return true if splitting out the group of channels of instruction \p inst
6608 * given by lbld.group() requires allocating a temporary for the i-th source
6609 * of the lowered instruction.
6612 needs_src_copy(const fs_builder
&lbld
, const fs_inst
*inst
, unsigned i
)
6614 return !(is_periodic(inst
->src
[i
], lbld
.dispatch_width()) ||
6615 (inst
->components_read(i
) == 1 &&
6616 lbld
.dispatch_width() <= inst
->exec_size
)) ||
6617 (inst
->flags_written() &
6618 flag_mask(inst
->src
[i
], type_sz(inst
->src
[i
].type
)));
6622 * Extract the data that would be consumed by the channel group given by
6623 * lbld.group() from the i-th source region of instruction \p inst and return
6624 * it as result in packed form.
6627 emit_unzip(const fs_builder
&lbld
, fs_inst
*inst
, unsigned i
)
6629 assert(lbld
.group() >= inst
->group
);
6631 /* Specified channel group from the source region. */
6632 const fs_reg src
= horiz_offset(inst
->src
[i
], lbld
.group() - inst
->group
);
6634 if (needs_src_copy(lbld
, inst
, i
)) {
6635 /* Builder of the right width to perform the copy avoiding uninitialized
6636 * data if the lowered execution size is greater than the original
6637 * execution size of the instruction.
6639 const fs_builder cbld
= lbld
.group(MIN2(lbld
.dispatch_width(),
6640 inst
->exec_size
), 0);
6641 const fs_reg tmp
= lbld
.vgrf(inst
->src
[i
].type
, inst
->components_read(i
));
6643 for (unsigned k
= 0; k
< inst
->components_read(i
); ++k
)
6644 cbld
.MOV(offset(tmp
, lbld
, k
), offset(src
, inst
->exec_size
, k
));
6648 } else if (is_periodic(inst
->src
[i
], lbld
.dispatch_width())) {
6649 /* The source is invariant for all dispatch_width-wide groups of the
6652 return inst
->src
[i
];
6655 /* We can just point the lowered instruction at the right channel group
6656 * from the original region.
6663 * Return true if splitting out the group of channels of instruction \p inst
6664 * given by lbld.group() requires allocating a temporary for the destination
6665 * of the lowered instruction and copying the data back to the original
6666 * destination region.
6669 needs_dst_copy(const fs_builder
&lbld
, const fs_inst
*inst
)
6671 /* If the instruction writes more than one component we'll have to shuffle
6672 * the results of multiple lowered instructions in order to make sure that
6673 * they end up arranged correctly in the original destination region.
6675 if (inst
->size_written
> inst
->dst
.component_size(inst
->exec_size
))
6678 /* If the lowered execution size is larger than the original the result of
6679 * the instruction won't fit in the original destination, so we'll have to
6680 * allocate a temporary in any case.
6682 if (lbld
.dispatch_width() > inst
->exec_size
)
6685 for (unsigned i
= 0; i
< inst
->sources
; i
++) {
6686 /* If we already made a copy of the source for other reasons there won't
6687 * be any overlap with the destination.
6689 if (needs_src_copy(lbld
, inst
, i
))
6692 /* In order to keep the logic simple we emit a copy whenever the
6693 * destination region doesn't exactly match an overlapping source, which
6694 * may point at the source and destination not being aligned group by
6695 * group which could cause one of the lowered instructions to overwrite
6696 * the data read from the same source by other lowered instructions.
6698 if (regions_overlap(inst
->dst
, inst
->size_written
,
6699 inst
->src
[i
], inst
->size_read(i
)) &&
6700 !inst
->dst
.equals(inst
->src
[i
]))
6708 * Insert data from a packed temporary into the channel group given by
6709 * lbld.group() of the destination region of instruction \p inst and return
6710 * the temporary as result. Any copy instructions that are required for
6711 * unzipping the previous value (in the case of partial writes) will be
6712 * inserted using \p lbld_before and any copy instructions required for
6713 * zipping up the destination of \p inst will be inserted using \p lbld_after.
6716 emit_zip(const fs_builder
&lbld_before
, const fs_builder
&lbld_after
,
6719 assert(lbld_before
.dispatch_width() == lbld_after
.dispatch_width());
6720 assert(lbld_before
.group() == lbld_after
.group());
6721 assert(lbld_after
.group() >= inst
->group
);
6723 /* Specified channel group from the destination region. */
6724 const fs_reg dst
= horiz_offset(inst
->dst
, lbld_after
.group() - inst
->group
);
6725 const unsigned dst_size
= inst
->size_written
/
6726 inst
->dst
.component_size(inst
->exec_size
);
6728 if (needs_dst_copy(lbld_after
, inst
)) {
6729 const fs_reg tmp
= lbld_after
.vgrf(inst
->dst
.type
, dst_size
);
6731 if (inst
->predicate
) {
6732 /* Handle predication by copying the original contents of
6733 * the destination into the temporary before emitting the
6734 * lowered instruction.
6736 const fs_builder gbld_before
=
6737 lbld_before
.group(MIN2(lbld_before
.dispatch_width(),
6738 inst
->exec_size
), 0);
6739 for (unsigned k
= 0; k
< dst_size
; ++k
) {
6740 gbld_before
.MOV(offset(tmp
, lbld_before
, k
),
6741 offset(dst
, inst
->exec_size
, k
));
6745 const fs_builder gbld_after
=
6746 lbld_after
.group(MIN2(lbld_after
.dispatch_width(),
6747 inst
->exec_size
), 0);
6748 for (unsigned k
= 0; k
< dst_size
; ++k
) {
6749 /* Use a builder of the right width to perform the copy avoiding
6750 * uninitialized data if the lowered execution size is greater than
6751 * the original execution size of the instruction.
6753 gbld_after
.MOV(offset(dst
, inst
->exec_size
, k
),
6754 offset(tmp
, lbld_after
, k
));
6760 /* No need to allocate a temporary for the lowered instruction, just
6761 * take the right group of channels from the original region.
6768 fs_visitor::lower_simd_width()
6770 bool progress
= false;
6772 foreach_block_and_inst_safe(block
, fs_inst
, inst
, cfg
) {
6773 const unsigned lower_width
= get_lowered_simd_width(devinfo
, inst
);
6775 if (lower_width
!= inst
->exec_size
) {
6776 /* Builder matching the original instruction. We may also need to
6777 * emit an instruction of width larger than the original, set the
6778 * execution size of the builder to the highest of both for now so
6779 * we're sure that both cases can be handled.
6781 const unsigned max_width
= MAX2(inst
->exec_size
, lower_width
);
6782 const fs_builder ibld
= bld
.at(block
, inst
)
6783 .exec_all(inst
->force_writemask_all
)
6784 .group(max_width
, inst
->group
/ max_width
);
6786 /* Split the copies in chunks of the execution width of either the
6787 * original or the lowered instruction, whichever is lower.
6789 const unsigned n
= DIV_ROUND_UP(inst
->exec_size
, lower_width
);
6790 const unsigned dst_size
= inst
->size_written
/
6791 inst
->dst
.component_size(inst
->exec_size
);
6793 assert(!inst
->writes_accumulator
&& !inst
->mlen
);
6795 /* Inserting the zip, unzip, and duplicated instructions in all of
6796 * the right spots is somewhat tricky. All of the unzip and any
6797 * instructions from the zip which unzip the destination prior to
6798 * writing need to happen before all of the per-group instructions
6799 * and the zip instructions need to happen after. In order to sort
6800 * this all out, we insert the unzip instructions before \p inst,
6801 * insert the per-group instructions after \p inst (i.e. before
6802 * inst->next), and insert the zip instructions before the
6803 * instruction after \p inst. Since we are inserting instructions
6804 * after \p inst, inst->next is a moving target and we need to save
6805 * it off here so that we insert the zip instructions in the right
6808 * Since we're inserting split instructions after after_inst, the
6809 * instructions will end up in the reverse order that we insert them.
6810 * However, certain render target writes require that the low group
6811 * instructions come before the high group. From the Ivy Bridge PRM
6812 * Vol. 4, Pt. 1, Section 3.9.11:
6814 * "If multiple SIMD8 Dual Source messages are delivered by the
6815 * pixel shader thread, each SIMD8_DUALSRC_LO message must be
6816 * issued before the SIMD8_DUALSRC_HI message with the same Slot
6817 * Group Select setting."
6819 * And, from Section 3.9.11.1 of the same PRM:
6821 * "When SIMD32 or SIMD16 PS threads send render target writes
6822 * with multiple SIMD8 and SIMD16 messages, the following must
6825 * All the slots (as described above) must have a corresponding
6826 * render target write irrespective of the slot's validity. A slot
6827 * is considered valid when at least one sample is enabled. For
6828 * example, a SIMD16 PS thread must send two SIMD8 render target
6829 * writes to cover all the slots.
6831 * PS thread must send SIMD render target write messages with
6832 * increasing slot numbers. For example, SIMD16 thread has
6833 * Slot[15:0] and if two SIMD8 render target writes are used, the
6834 * first SIMD8 render target write must send Slot[7:0] and the
6835 * next one must send Slot[15:8]."
6837 * In order to make low group instructions come before high group
6838 * instructions (this is required for some render target writes), we
6839 * split from the highest group to lowest.
6841 exec_node
*const after_inst
= inst
->next
;
6842 for (int i
= n
- 1; i
>= 0; i
--) {
6843 /* Emit a copy of the original instruction with the lowered width.
6844 * If the EOT flag was set throw it away except for the last
6845 * instruction to avoid killing the thread prematurely.
6847 fs_inst split_inst
= *inst
;
6848 split_inst
.exec_size
= lower_width
;
6849 split_inst
.eot
= inst
->eot
&& i
== int(n
- 1);
6851 /* Select the correct channel enables for the i-th group, then
6852 * transform the sources and destination and emit the lowered
6855 const fs_builder lbld
= ibld
.group(lower_width
, i
);
6857 for (unsigned j
= 0; j
< inst
->sources
; j
++)
6858 split_inst
.src
[j
] = emit_unzip(lbld
.at(block
, inst
), inst
, j
);
6860 split_inst
.dst
= emit_zip(lbld
.at(block
, inst
),
6861 lbld
.at(block
, after_inst
), inst
);
6862 split_inst
.size_written
=
6863 split_inst
.dst
.component_size(lower_width
) * dst_size
;
6865 lbld
.at(block
, inst
->next
).emit(split_inst
);
6868 inst
->remove(block
);
6874 invalidate_live_intervals();
6880 fs_visitor::dump_instructions()
6882 dump_instructions(NULL
);
6886 fs_visitor::dump_instructions(const char *name
)
6888 FILE *file
= stderr
;
6889 if (name
&& geteuid() != 0) {
6890 file
= fopen(name
, "w");
6896 calculate_register_pressure();
6897 int ip
= 0, max_pressure
= 0;
6898 foreach_block_and_inst(block
, backend_instruction
, inst
, cfg
) {
6899 max_pressure
= MAX2(max_pressure
, regs_live_at_ip
[ip
]);
6900 fprintf(file
, "{%3d} %4d: ", regs_live_at_ip
[ip
], ip
);
6901 dump_instruction(inst
, file
);
6904 fprintf(file
, "Maximum %3d registers live at once.\n", max_pressure
);
6907 foreach_in_list(backend_instruction
, inst
, &instructions
) {
6908 fprintf(file
, "%4d: ", ip
++);
6909 dump_instruction(inst
, file
);
6913 if (file
!= stderr
) {
6919 fs_visitor::dump_instruction(backend_instruction
*be_inst
)
6921 dump_instruction(be_inst
, stderr
);
6925 fs_visitor::dump_instruction(backend_instruction
*be_inst
, FILE *file
)
6927 fs_inst
*inst
= (fs_inst
*)be_inst
;
6929 if (inst
->predicate
) {
6930 fprintf(file
, "(%cf%d.%d) ",
6931 inst
->predicate_inverse
? '-' : '+',
6932 inst
->flag_subreg
/ 2,
6933 inst
->flag_subreg
% 2);
6936 fprintf(file
, "%s", brw_instruction_name(devinfo
, inst
->opcode
));
6938 fprintf(file
, ".sat");
6939 if (inst
->conditional_mod
) {
6940 fprintf(file
, "%s", conditional_modifier
[inst
->conditional_mod
]);
6941 if (!inst
->predicate
&&
6942 (devinfo
->gen
< 5 || (inst
->opcode
!= BRW_OPCODE_SEL
&&
6943 inst
->opcode
!= BRW_OPCODE_CSEL
&&
6944 inst
->opcode
!= BRW_OPCODE_IF
&&
6945 inst
->opcode
!= BRW_OPCODE_WHILE
))) {
6946 fprintf(file
, ".f%d.%d", inst
->flag_subreg
/ 2,
6947 inst
->flag_subreg
% 2);
6950 fprintf(file
, "(%d) ", inst
->exec_size
);
6953 fprintf(file
, "(mlen: %d) ", inst
->mlen
);
6956 if (inst
->ex_mlen
) {
6957 fprintf(file
, "(ex_mlen: %d) ", inst
->ex_mlen
);
6961 fprintf(file
, "(EOT) ");
6964 switch (inst
->dst
.file
) {
6966 fprintf(file
, "vgrf%d", inst
->dst
.nr
);
6969 fprintf(file
, "g%d", inst
->dst
.nr
);
6972 fprintf(file
, "m%d", inst
->dst
.nr
);
6975 fprintf(file
, "(null)");
6978 fprintf(file
, "***u%d***", inst
->dst
.nr
);
6981 fprintf(file
, "***attr%d***", inst
->dst
.nr
);
6984 switch (inst
->dst
.nr
) {
6986 fprintf(file
, "null");
6988 case BRW_ARF_ADDRESS
:
6989 fprintf(file
, "a0.%d", inst
->dst
.subnr
);
6991 case BRW_ARF_ACCUMULATOR
:
6992 fprintf(file
, "acc%d", inst
->dst
.subnr
);
6995 fprintf(file
, "f%d.%d", inst
->dst
.nr
& 0xf, inst
->dst
.subnr
);
6998 fprintf(file
, "arf%d.%d", inst
->dst
.nr
& 0xf, inst
->dst
.subnr
);
7003 unreachable("not reached");
7006 if (inst
->dst
.offset
||
7007 (inst
->dst
.file
== VGRF
&&
7008 alloc
.sizes
[inst
->dst
.nr
] * REG_SIZE
!= inst
->size_written
)) {
7009 const unsigned reg_size
= (inst
->dst
.file
== UNIFORM
? 4 : REG_SIZE
);
7010 fprintf(file
, "+%d.%d", inst
->dst
.offset
/ reg_size
,
7011 inst
->dst
.offset
% reg_size
);
7014 if (inst
->dst
.stride
!= 1)
7015 fprintf(file
, "<%u>", inst
->dst
.stride
);
7016 fprintf(file
, ":%s, ", brw_reg_type_to_letters(inst
->dst
.type
));
7018 for (int i
= 0; i
< inst
->sources
; i
++) {
7019 if (inst
->src
[i
].negate
)
7021 if (inst
->src
[i
].abs
)
7023 switch (inst
->src
[i
].file
) {
7025 fprintf(file
, "vgrf%d", inst
->src
[i
].nr
);
7028 fprintf(file
, "g%d", inst
->src
[i
].nr
);
7031 fprintf(file
, "***m%d***", inst
->src
[i
].nr
);
7034 fprintf(file
, "attr%d", inst
->src
[i
].nr
);
7037 fprintf(file
, "u%d", inst
->src
[i
].nr
);
7040 fprintf(file
, "(null)");
7043 switch (inst
->src
[i
].type
) {
7044 case BRW_REGISTER_TYPE_F
:
7045 fprintf(file
, "%-gf", inst
->src
[i
].f
);
7047 case BRW_REGISTER_TYPE_DF
:
7048 fprintf(file
, "%fdf", inst
->src
[i
].df
);
7050 case BRW_REGISTER_TYPE_W
:
7051 case BRW_REGISTER_TYPE_D
:
7052 fprintf(file
, "%dd", inst
->src
[i
].d
);
7054 case BRW_REGISTER_TYPE_UW
:
7055 case BRW_REGISTER_TYPE_UD
:
7056 fprintf(file
, "%uu", inst
->src
[i
].ud
);
7058 case BRW_REGISTER_TYPE_Q
:
7059 fprintf(file
, "%" PRId64
"q", inst
->src
[i
].d64
);
7061 case BRW_REGISTER_TYPE_UQ
:
7062 fprintf(file
, "%" PRIu64
"uq", inst
->src
[i
].u64
);
7064 case BRW_REGISTER_TYPE_VF
:
7065 fprintf(file
, "[%-gF, %-gF, %-gF, %-gF]",
7066 brw_vf_to_float((inst
->src
[i
].ud
>> 0) & 0xff),
7067 brw_vf_to_float((inst
->src
[i
].ud
>> 8) & 0xff),
7068 brw_vf_to_float((inst
->src
[i
].ud
>> 16) & 0xff),
7069 brw_vf_to_float((inst
->src
[i
].ud
>> 24) & 0xff));
7071 case BRW_REGISTER_TYPE_V
:
7072 case BRW_REGISTER_TYPE_UV
:
7073 fprintf(file
, "%08x%s", inst
->src
[i
].ud
,
7074 inst
->src
[i
].type
== BRW_REGISTER_TYPE_V
? "V" : "UV");
7077 fprintf(file
, "???");
7082 switch (inst
->src
[i
].nr
) {
7084 fprintf(file
, "null");
7086 case BRW_ARF_ADDRESS
:
7087 fprintf(file
, "a0.%d", inst
->src
[i
].subnr
);
7089 case BRW_ARF_ACCUMULATOR
:
7090 fprintf(file
, "acc%d", inst
->src
[i
].subnr
);
7093 fprintf(file
, "f%d.%d", inst
->src
[i
].nr
& 0xf, inst
->src
[i
].subnr
);
7096 fprintf(file
, "arf%d.%d", inst
->src
[i
].nr
& 0xf, inst
->src
[i
].subnr
);
7102 if (inst
->src
[i
].offset
||
7103 (inst
->src
[i
].file
== VGRF
&&
7104 alloc
.sizes
[inst
->src
[i
].nr
] * REG_SIZE
!= inst
->size_read(i
))) {
7105 const unsigned reg_size
= (inst
->src
[i
].file
== UNIFORM
? 4 : REG_SIZE
);
7106 fprintf(file
, "+%d.%d", inst
->src
[i
].offset
/ reg_size
,
7107 inst
->src
[i
].offset
% reg_size
);
7110 if (inst
->src
[i
].abs
)
7113 if (inst
->src
[i
].file
!= IMM
) {
7115 if (inst
->src
[i
].file
== ARF
|| inst
->src
[i
].file
== FIXED_GRF
) {
7116 unsigned hstride
= inst
->src
[i
].hstride
;
7117 stride
= (hstride
== 0 ? 0 : (1 << (hstride
- 1)));
7119 stride
= inst
->src
[i
].stride
;
7122 fprintf(file
, "<%u>", stride
);
7124 fprintf(file
, ":%s", brw_reg_type_to_letters(inst
->src
[i
].type
));
7127 if (i
< inst
->sources
- 1 && inst
->src
[i
+ 1].file
!= BAD_FILE
)
7128 fprintf(file
, ", ");
7133 if (inst
->force_writemask_all
)
7134 fprintf(file
, "NoMask ");
7136 if (inst
->exec_size
!= dispatch_width
)
7137 fprintf(file
, "group%d ", inst
->group
);
7139 fprintf(file
, "\n");
7143 fs_visitor::setup_fs_payload_gen6()
7145 assert(stage
== MESA_SHADER_FRAGMENT
);
7146 struct brw_wm_prog_data
*prog_data
= brw_wm_prog_data(this->prog_data
);
7147 const unsigned payload_width
= MIN2(16, dispatch_width
);
7148 assert(dispatch_width
% payload_width
== 0);
7149 assert(devinfo
->gen
>= 6);
7151 prog_data
->uses_src_depth
= prog_data
->uses_src_w
=
7152 (nir
->info
.system_values_read
& (1ull << SYSTEM_VALUE_FRAG_COORD
)) != 0;
7154 prog_data
->uses_sample_mask
=
7155 (nir
->info
.system_values_read
& SYSTEM_BIT_SAMPLE_MASK_IN
) != 0;
7157 /* From the Ivy Bridge PRM documentation for 3DSTATE_PS:
7159 * "MSDISPMODE_PERSAMPLE is required in order to select
7162 * So we can only really get sample positions if we are doing real
7163 * per-sample dispatch. If we need gl_SamplePosition and we don't have
7164 * persample dispatch, we hard-code it to 0.5.
7166 prog_data
->uses_pos_offset
= prog_data
->persample_dispatch
&&
7167 (nir
->info
.system_values_read
& SYSTEM_BIT_SAMPLE_POS
);
7169 /* R0: PS thread payload header. */
7172 for (unsigned j
= 0; j
< dispatch_width
/ payload_width
; j
++) {
7173 /* R1: masks, pixel X/Y coordinates. */
7174 payload
.subspan_coord_reg
[j
] = payload
.num_regs
++;
7177 for (unsigned j
= 0; j
< dispatch_width
/ payload_width
; j
++) {
7178 /* R3-26: barycentric interpolation coordinates. These appear in the
7179 * same order that they appear in the brw_barycentric_mode enum. Each
7180 * set of coordinates occupies 2 registers if dispatch width == 8 and 4
7181 * registers if dispatch width == 16. Coordinates only appear if they
7182 * were enabled using the "Barycentric Interpolation Mode" bits in
7185 for (int i
= 0; i
< BRW_BARYCENTRIC_MODE_COUNT
; ++i
) {
7186 if (prog_data
->barycentric_interp_modes
& (1 << i
)) {
7187 payload
.barycentric_coord_reg
[i
][j
] = payload
.num_regs
;
7188 payload
.num_regs
+= payload_width
/ 4;
7192 /* R27-28: interpolated depth if uses source depth */
7193 if (prog_data
->uses_src_depth
) {
7194 payload
.source_depth_reg
[j
] = payload
.num_regs
;
7195 payload
.num_regs
+= payload_width
/ 8;
7198 /* R29-30: interpolated W set if GEN6_WM_USES_SOURCE_W. */
7199 if (prog_data
->uses_src_w
) {
7200 payload
.source_w_reg
[j
] = payload
.num_regs
;
7201 payload
.num_regs
+= payload_width
/ 8;
7204 /* R31: MSAA position offsets. */
7205 if (prog_data
->uses_pos_offset
) {
7206 payload
.sample_pos_reg
[j
] = payload
.num_regs
;
7210 /* R32-33: MSAA input coverage mask */
7211 if (prog_data
->uses_sample_mask
) {
7212 assert(devinfo
->gen
>= 7);
7213 payload
.sample_mask_in_reg
[j
] = payload
.num_regs
;
7214 payload
.num_regs
+= payload_width
/ 8;
7218 if (nir
->info
.outputs_written
& BITFIELD64_BIT(FRAG_RESULT_DEPTH
)) {
7219 source_depth_to_render_target
= true;
7224 fs_visitor::setup_vs_payload()
7226 /* R0: thread header, R1: urb handles */
7227 payload
.num_regs
= 2;
7231 fs_visitor::setup_gs_payload()
7233 assert(stage
== MESA_SHADER_GEOMETRY
);
7235 struct brw_gs_prog_data
*gs_prog_data
= brw_gs_prog_data(prog_data
);
7236 struct brw_vue_prog_data
*vue_prog_data
= brw_vue_prog_data(prog_data
);
7238 /* R0: thread header, R1: output URB handles */
7239 payload
.num_regs
= 2;
7241 if (gs_prog_data
->include_primitive_id
) {
7242 /* R2: Primitive ID 0..7 */
7246 /* Always enable VUE handles so we can safely use pull model if needed.
7248 * The push model for a GS uses a ton of register space even for trivial
7249 * scenarios with just a few inputs, so just make things easier and a bit
7250 * safer by always having pull model available.
7252 gs_prog_data
->base
.include_vue_handles
= true;
7254 /* R3..RN: ICP Handles for each incoming vertex (when using pull model) */
7255 payload
.num_regs
+= nir
->info
.gs
.vertices_in
;
7257 /* Use a maximum of 24 registers for push-model inputs. */
7258 const unsigned max_push_components
= 24;
7260 /* If pushing our inputs would take too many registers, reduce the URB read
7261 * length (which is in HWords, or 8 registers), and resort to pulling.
7263 * Note that the GS reads <URB Read Length> HWords for every vertex - so we
7264 * have to multiply by VerticesIn to obtain the total storage requirement.
7266 if (8 * vue_prog_data
->urb_read_length
* nir
->info
.gs
.vertices_in
>
7267 max_push_components
) {
7268 vue_prog_data
->urb_read_length
=
7269 ROUND_DOWN_TO(max_push_components
/ nir
->info
.gs
.vertices_in
, 8) / 8;
7274 fs_visitor::setup_cs_payload()
7276 assert(devinfo
->gen
>= 7);
7277 payload
.num_regs
= 1;
7281 fs_visitor::calculate_register_pressure()
7283 invalidate_live_intervals();
7284 calculate_live_intervals();
7286 unsigned num_instructions
= 0;
7287 foreach_block(block
, cfg
)
7288 num_instructions
+= block
->instructions
.length();
7290 regs_live_at_ip
= rzalloc_array(mem_ctx
, int, num_instructions
);
7292 for (unsigned reg
= 0; reg
< alloc
.count
; reg
++) {
7293 for (int ip
= virtual_grf_start
[reg
]; ip
<= virtual_grf_end
[reg
]; ip
++)
7294 regs_live_at_ip
[ip
] += alloc
.sizes
[reg
];
7299 fs_visitor::optimize()
7301 /* Start by validating the shader we currently have. */
7304 /* bld is the common builder object pointing at the end of the program we
7305 * used to translate it into i965 IR. For the optimization and lowering
7306 * passes coming next, any code added after the end of the program without
7307 * having explicitly called fs_builder::at() clearly points at a mistake.
7308 * Ideally optimization passes wouldn't be part of the visitor so they
7309 * wouldn't have access to bld at all, but they do, so just in case some
7310 * pass forgets to ask for a location explicitly set it to NULL here to
7311 * make it trip. The dispatch width is initialized to a bogus value to
7312 * make sure that optimizations set the execution controls explicitly to
7313 * match the code they are manipulating instead of relying on the defaults.
7315 bld
= fs_builder(this, 64);
7317 assign_constant_locations();
7318 lower_constant_loads();
7322 split_virtual_grfs();
7325 #define OPT(pass, args...) ({ \
7327 bool this_progress = pass(args); \
7329 if (unlikely(INTEL_DEBUG & DEBUG_OPTIMIZER) && this_progress) { \
7330 char filename[64]; \
7331 snprintf(filename, 64, "%s%d-%s-%02d-%02d-" #pass, \
7332 stage_abbrev, dispatch_width, nir->info.name, iteration, pass_num); \
7334 backend_shader::dump_instructions(filename); \
7339 progress = progress || this_progress; \
7343 if (unlikely(INTEL_DEBUG
& DEBUG_OPTIMIZER
)) {
7345 snprintf(filename
, 64, "%s%d-%s-00-00-start",
7346 stage_abbrev
, dispatch_width
, nir
->info
.name
);
7348 backend_shader::dump_instructions(filename
);
7351 bool progress
= false;
7355 /* Before anything else, eliminate dead code. The results of some NIR
7356 * instructions may effectively be calculated twice. Once when the
7357 * instruction is encountered, and again when the user of that result is
7358 * encountered. Wipe those away before algebraic optimizations and
7359 * especially copy propagation can mix things up.
7361 OPT(dead_code_eliminate
);
7363 OPT(remove_extra_rounding_modes
);
7370 OPT(remove_duplicate_mrf_writes
);
7374 OPT(opt_copy_propagation
);
7375 OPT(opt_predicated_break
, this);
7376 OPT(opt_cmod_propagation
);
7377 OPT(dead_code_eliminate
);
7378 OPT(opt_peephole_sel
);
7379 OPT(dead_control_flow_eliminate
, this);
7380 OPT(opt_register_renaming
);
7381 OPT(opt_saturate_propagation
);
7382 OPT(register_coalesce
);
7383 OPT(compute_to_mrf
);
7384 OPT(eliminate_find_live_channel
);
7386 OPT(compact_virtual_grfs
);
7389 /* Do this after cmod propagation has had every possible opportunity to
7390 * propagate results into SEL instructions.
7392 if (OPT(opt_peephole_csel
))
7393 OPT(dead_code_eliminate
);
7398 if (OPT(lower_pack
)) {
7399 OPT(register_coalesce
);
7400 OPT(dead_code_eliminate
);
7403 OPT(lower_simd_width
);
7405 /* After SIMD lowering just in case we had to unroll the EOT send. */
7406 OPT(opt_sampler_eot
);
7408 OPT(lower_logical_sends
);
7411 OPT(opt_copy_propagation
);
7412 /* Only run after logical send lowering because it's easier to implement
7413 * in terms of physical sends.
7415 if (OPT(opt_zero_samples
))
7416 OPT(opt_copy_propagation
);
7417 /* Run after logical send lowering to give it a chance to CSE the
7418 * LOAD_PAYLOAD instructions created to construct the payloads of
7419 * e.g. texturing messages in cases where it wasn't possible to CSE the
7420 * whole logical instruction.
7423 OPT(register_coalesce
);
7424 OPT(compute_to_mrf
);
7425 OPT(dead_code_eliminate
);
7426 OPT(remove_duplicate_mrf_writes
);
7427 OPT(opt_peephole_sel
);
7430 OPT(opt_redundant_discard_jumps
);
7432 if (OPT(lower_load_payload
)) {
7433 split_virtual_grfs();
7434 OPT(register_coalesce
);
7435 OPT(lower_simd_width
);
7436 OPT(compute_to_mrf
);
7437 OPT(dead_code_eliminate
);
7440 OPT(opt_combine_constants
);
7441 OPT(lower_integer_multiplication
);
7443 if (devinfo
->gen
<= 5 && OPT(lower_minmax
)) {
7444 OPT(opt_cmod_propagation
);
7446 OPT(opt_copy_propagation
);
7447 OPT(dead_code_eliminate
);
7450 if (OPT(lower_regioning
)) {
7451 OPT(opt_copy_propagation
);
7452 OPT(dead_code_eliminate
);
7453 OPT(lower_simd_width
);
7456 OPT(fixup_sends_duplicate_payload
);
7458 lower_uniform_pull_constant_loads();
7464 * From the Skylake PRM Vol. 2a docs for sends:
7466 * "It is required that the second block of GRFs does not overlap with the
7469 * There are plenty of cases where we may accidentally violate this due to
7470 * having, for instance, both sources be the constant 0. This little pass
7471 * just adds a new vgrf for the second payload and copies it over.
7474 fs_visitor::fixup_sends_duplicate_payload()
7476 bool progress
= false;
7478 foreach_block_and_inst_safe (block
, fs_inst
, inst
, cfg
) {
7479 if (inst
->opcode
== SHADER_OPCODE_SEND
&& inst
->ex_mlen
> 0 &&
7480 regions_overlap(inst
->src
[2], inst
->mlen
* REG_SIZE
,
7481 inst
->src
[3], inst
->ex_mlen
* REG_SIZE
)) {
7482 fs_reg tmp
= fs_reg(VGRF
, alloc
.allocate(inst
->ex_mlen
),
7483 BRW_REGISTER_TYPE_UD
);
7484 /* Sadly, we've lost all notion of channels and bit sizes at this
7485 * point. Just WE_all it.
7487 const fs_builder ibld
= bld
.at(block
, inst
).exec_all().group(16, 0);
7488 fs_reg copy_src
= retype(inst
->src
[3], BRW_REGISTER_TYPE_UD
);
7489 fs_reg copy_dst
= tmp
;
7490 for (unsigned i
= 0; i
< inst
->ex_mlen
; i
+= 2) {
7491 if (inst
->ex_mlen
== i
+ 1) {
7492 /* Only one register left; do SIMD8 */
7493 ibld
.group(8, 0).MOV(copy_dst
, copy_src
);
7495 ibld
.MOV(copy_dst
, copy_src
);
7497 copy_src
= offset(copy_src
, ibld
, 1);
7498 copy_dst
= offset(copy_dst
, ibld
, 1);
7506 invalidate_live_intervals();
7512 * Three source instruction must have a GRF/MRF destination register.
7513 * ARF NULL is not allowed. Fix that up by allocating a temporary GRF.
7516 fs_visitor::fixup_3src_null_dest()
7518 bool progress
= false;
7520 foreach_block_and_inst_safe (block
, fs_inst
, inst
, cfg
) {
7521 if (inst
->is_3src(devinfo
) && inst
->dst
.is_null()) {
7522 inst
->dst
= fs_reg(VGRF
, alloc
.allocate(dispatch_width
/ 8),
7529 invalidate_live_intervals();
7533 fs_visitor::allocate_registers(unsigned min_dispatch_width
, bool allow_spilling
)
7537 static const enum instruction_scheduler_mode pre_modes
[] = {
7539 SCHEDULE_PRE_NON_LIFO
,
7543 static const char *scheduler_mode_name
[] = {
7549 bool spill_all
= allow_spilling
&& (INTEL_DEBUG
& DEBUG_SPILL_FS
);
7551 /* Try each scheduling heuristic to see if it can successfully register
7552 * allocate without spilling. They should be ordered by decreasing
7553 * performance but increasing likelihood of allocating.
7555 for (unsigned i
= 0; i
< ARRAY_SIZE(pre_modes
); i
++) {
7556 schedule_instructions(pre_modes
[i
]);
7557 this->shader_stats
.scheduler_mode
= scheduler_mode_name
[i
];
7560 assign_regs_trivial();
7565 /* We only allow spilling for the last schedule mode and only if the
7566 * allow_spilling parameter and dispatch width work out ok.
7568 bool can_spill
= allow_spilling
&&
7569 (i
== ARRAY_SIZE(pre_modes
) - 1) &&
7570 dispatch_width
== min_dispatch_width
;
7572 /* We should only spill registers on the last scheduling. */
7573 assert(!spilled_any_registers
);
7575 allocated
= assign_regs(can_spill
, spill_all
);
7581 if (!allow_spilling
)
7582 fail("Failure to register allocate and spilling is not allowed.");
7584 /* We assume that any spilling is worse than just dropping back to
7585 * SIMD8. There's probably actually some intermediate point where
7586 * SIMD16 with a couple of spills is still better.
7588 if (dispatch_width
> min_dispatch_width
) {
7589 fail("Failure to register allocate. Reduce number of "
7590 "live scalar values to avoid this.");
7593 /* If we failed to allocate, we must have a reason */
7595 } else if (spilled_any_registers
) {
7596 compiler
->shader_perf_log(log_data
,
7597 "%s shader triggered register spilling. "
7598 "Try reducing the number of live scalar "
7599 "values to improve performance.\n",
7603 /* This must come after all optimization and register allocation, since
7604 * it inserts dead code that happens to have side effects, and it does
7605 * so based on the actual physical registers in use.
7607 insert_gen4_send_dependency_workarounds();
7612 opt_bank_conflicts();
7614 schedule_instructions(SCHEDULE_POST
);
7616 if (last_scratch
> 0) {
7617 ASSERTED
unsigned max_scratch_size
= 2 * 1024 * 1024;
7619 prog_data
->total_scratch
= brw_get_scratch_size(last_scratch
);
7621 if (stage
== MESA_SHADER_COMPUTE
) {
7622 if (devinfo
->is_haswell
) {
7623 /* According to the MEDIA_VFE_STATE's "Per Thread Scratch Space"
7624 * field documentation, Haswell supports a minimum of 2kB of
7625 * scratch space for compute shaders, unlike every other stage
7628 prog_data
->total_scratch
= MAX2(prog_data
->total_scratch
, 2048);
7629 } else if (devinfo
->gen
<= 7) {
7630 /* According to the MEDIA_VFE_STATE's "Per Thread Scratch Space"
7631 * field documentation, platforms prior to Haswell measure scratch
7632 * size linearly with a range of [1kB, 12kB] and 1kB granularity.
7634 prog_data
->total_scratch
= ALIGN(last_scratch
, 1024);
7635 max_scratch_size
= 12 * 1024;
7639 /* We currently only support up to 2MB of scratch space. If we
7640 * need to support more eventually, the documentation suggests
7641 * that we could allocate a larger buffer, and partition it out
7642 * ourselves. We'd just have to undo the hardware's address
7643 * calculation by subtracting (FFTID * Per Thread Scratch Space)
7644 * and then add FFTID * (Larger Per Thread Scratch Space).
7646 * See 3D-Media-GPGPU Engine > Media GPGPU Pipeline >
7647 * Thread Group Tracking > Local Memory/Scratch Space.
7649 assert(prog_data
->total_scratch
< max_scratch_size
);
7656 fs_visitor::run_vs()
7658 assert(stage
== MESA_SHADER_VERTEX
);
7662 if (shader_time_index
>= 0)
7663 emit_shader_time_begin();
7672 if (shader_time_index
>= 0)
7673 emit_shader_time_end();
7679 assign_curb_setup();
7680 assign_vs_urb_setup();
7682 fixup_3src_null_dest();
7683 allocate_registers(8, true);
7689 fs_visitor::set_tcs_invocation_id()
7691 struct brw_tcs_prog_data
*tcs_prog_data
= brw_tcs_prog_data(prog_data
);
7692 struct brw_vue_prog_data
*vue_prog_data
= &tcs_prog_data
->base
;
7694 const unsigned instance_id_mask
=
7695 devinfo
->gen
>= 11 ? INTEL_MASK(22, 16) : INTEL_MASK(23, 17);
7696 const unsigned instance_id_shift
=
7697 devinfo
->gen
>= 11 ? 16 : 17;
7699 /* Get instance number from g0.2 bits 22:16 or 23:17 */
7700 fs_reg t
= bld
.vgrf(BRW_REGISTER_TYPE_UD
);
7701 bld
.AND(t
, fs_reg(retype(brw_vec1_grf(0, 2), BRW_REGISTER_TYPE_UD
)),
7702 brw_imm_ud(instance_id_mask
));
7704 invocation_id
= bld
.vgrf(BRW_REGISTER_TYPE_UD
);
7706 if (vue_prog_data
->dispatch_mode
== DISPATCH_MODE_TCS_8_PATCH
) {
7707 /* gl_InvocationID is just the thread number */
7708 bld
.SHR(invocation_id
, t
, brw_imm_ud(instance_id_shift
));
7712 assert(vue_prog_data
->dispatch_mode
== DISPATCH_MODE_TCS_SINGLE_PATCH
);
7714 fs_reg channels_uw
= bld
.vgrf(BRW_REGISTER_TYPE_UW
);
7715 fs_reg channels_ud
= bld
.vgrf(BRW_REGISTER_TYPE_UD
);
7716 bld
.MOV(channels_uw
, fs_reg(brw_imm_uv(0x76543210)));
7717 bld
.MOV(channels_ud
, channels_uw
);
7719 if (tcs_prog_data
->instances
== 1) {
7720 invocation_id
= channels_ud
;
7722 fs_reg instance_times_8
= bld
.vgrf(BRW_REGISTER_TYPE_UD
);
7723 bld
.SHR(instance_times_8
, t
, brw_imm_ud(instance_id_shift
- 3));
7724 bld
.ADD(invocation_id
, instance_times_8
, channels_ud
);
7729 fs_visitor::run_tcs()
7731 assert(stage
== MESA_SHADER_TESS_CTRL
);
7733 struct brw_vue_prog_data
*vue_prog_data
= brw_vue_prog_data(prog_data
);
7734 struct brw_tcs_prog_data
*tcs_prog_data
= brw_tcs_prog_data(prog_data
);
7735 struct brw_tcs_prog_key
*tcs_key
= (struct brw_tcs_prog_key
*) key
;
7737 assert(vue_prog_data
->dispatch_mode
== DISPATCH_MODE_TCS_SINGLE_PATCH
||
7738 vue_prog_data
->dispatch_mode
== DISPATCH_MODE_TCS_8_PATCH
);
7740 if (vue_prog_data
->dispatch_mode
== DISPATCH_MODE_TCS_SINGLE_PATCH
) {
7741 /* r1-r4 contain the ICP handles. */
7742 payload
.num_regs
= 5;
7744 assert(vue_prog_data
->dispatch_mode
== DISPATCH_MODE_TCS_8_PATCH
);
7745 assert(tcs_key
->input_vertices
> 0);
7746 /* r1 contains output handles, r2 may contain primitive ID, then the
7747 * ICP handles occupy the next 1-32 registers.
7749 payload
.num_regs
= 2 + tcs_prog_data
->include_primitive_id
+
7750 tcs_key
->input_vertices
;
7753 if (shader_time_index
>= 0)
7754 emit_shader_time_begin();
7756 /* Initialize gl_InvocationID */
7757 set_tcs_invocation_id();
7759 const bool fix_dispatch_mask
=
7760 vue_prog_data
->dispatch_mode
== DISPATCH_MODE_TCS_SINGLE_PATCH
&&
7761 (nir
->info
.tess
.tcs_vertices_out
% 8) != 0;
7763 /* Fix the disptach mask */
7764 if (fix_dispatch_mask
) {
7765 bld
.CMP(bld
.null_reg_ud(), invocation_id
,
7766 brw_imm_ud(nir
->info
.tess
.tcs_vertices_out
), BRW_CONDITIONAL_L
);
7767 bld
.IF(BRW_PREDICATE_NORMAL
);
7772 if (fix_dispatch_mask
) {
7773 bld
.emit(BRW_OPCODE_ENDIF
);
7776 /* Emit EOT write; set TR DS Cache bit */
7778 fs_reg(get_tcs_output_urb_handle()),
7779 fs_reg(brw_imm_ud(WRITEMASK_X
<< 16)),
7780 fs_reg(brw_imm_ud(0)),
7782 fs_reg payload
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 3);
7783 bld
.LOAD_PAYLOAD(payload
, srcs
, 3, 2);
7785 fs_inst
*inst
= bld
.emit(SHADER_OPCODE_URB_WRITE_SIMD8_MASKED
,
7786 bld
.null_reg_ud(), payload
);
7790 if (shader_time_index
>= 0)
7791 emit_shader_time_end();
7800 assign_curb_setup();
7801 assign_tcs_urb_setup();
7803 fixup_3src_null_dest();
7804 allocate_registers(8, true);
7810 fs_visitor::run_tes()
7812 assert(stage
== MESA_SHADER_TESS_EVAL
);
7814 /* R0: thread header, R1-3: gl_TessCoord.xyz, R4: URB handles */
7815 payload
.num_regs
= 5;
7817 if (shader_time_index
>= 0)
7818 emit_shader_time_begin();
7827 if (shader_time_index
>= 0)
7828 emit_shader_time_end();
7834 assign_curb_setup();
7835 assign_tes_urb_setup();
7837 fixup_3src_null_dest();
7838 allocate_registers(8, true);
7844 fs_visitor::run_gs()
7846 assert(stage
== MESA_SHADER_GEOMETRY
);
7850 this->final_gs_vertex_count
= vgrf(glsl_type::uint_type
);
7852 if (gs_compile
->control_data_header_size_bits
> 0) {
7853 /* Create a VGRF to store accumulated control data bits. */
7854 this->control_data_bits
= vgrf(glsl_type::uint_type
);
7856 /* If we're outputting more than 32 control data bits, then EmitVertex()
7857 * will set control_data_bits to 0 after emitting the first vertex.
7858 * Otherwise, we need to initialize it to 0 here.
7860 if (gs_compile
->control_data_header_size_bits
<= 32) {
7861 const fs_builder abld
= bld
.annotate("initialize control data bits");
7862 abld
.MOV(this->control_data_bits
, brw_imm_ud(0u));
7866 if (shader_time_index
>= 0)
7867 emit_shader_time_begin();
7871 emit_gs_thread_end();
7873 if (shader_time_index
>= 0)
7874 emit_shader_time_end();
7883 assign_curb_setup();
7884 assign_gs_urb_setup();
7886 fixup_3src_null_dest();
7887 allocate_registers(8, true);
7892 /* From the SKL PRM, Volume 16, Workarounds:
7894 * 0877 3D Pixel Shader Hang possible when pixel shader dispatched with
7895 * only header phases (R0-R2)
7897 * WA: Enable a non-header phase (e.g. push constant) when dispatch would
7898 * have been header only.
7900 * Instead of enabling push constants one can alternatively enable one of the
7901 * inputs. Here one simply chooses "layer" which shouldn't impose much
7905 gen9_ps_header_only_workaround(struct brw_wm_prog_data
*wm_prog_data
)
7907 if (wm_prog_data
->num_varying_inputs
)
7910 if (wm_prog_data
->base
.curb_read_length
)
7913 wm_prog_data
->urb_setup
[VARYING_SLOT_LAYER
] = 0;
7914 wm_prog_data
->num_varying_inputs
= 1;
7918 fs_visitor::run_fs(bool allow_spilling
, bool do_rep_send
)
7920 struct brw_wm_prog_data
*wm_prog_data
= brw_wm_prog_data(this->prog_data
);
7921 brw_wm_prog_key
*wm_key
= (brw_wm_prog_key
*) this->key
;
7923 assert(stage
== MESA_SHADER_FRAGMENT
);
7925 if (devinfo
->gen
>= 6)
7926 setup_fs_payload_gen6();
7928 setup_fs_payload_gen4();
7932 } else if (do_rep_send
) {
7933 assert(dispatch_width
== 16);
7934 emit_repclear_shader();
7936 if (shader_time_index
>= 0)
7937 emit_shader_time_begin();
7939 if (nir
->info
.inputs_read
> 0 ||
7940 (nir
->info
.system_values_read
& (1ull << SYSTEM_VALUE_FRAG_COORD
)) ||
7941 (nir
->info
.outputs_read
> 0 && !wm_key
->coherent_fb_fetch
)) {
7942 if (devinfo
->gen
< 6)
7943 emit_interpolation_setup_gen4();
7945 emit_interpolation_setup_gen6();
7948 /* We handle discards by keeping track of the still-live pixels in f0.1.
7949 * Initialize it with the dispatched pixels.
7951 if (wm_prog_data
->uses_kill
) {
7952 const fs_reg dispatch_mask
=
7953 devinfo
->gen
>= 6 ? brw_vec1_grf(1, 7) : brw_vec1_grf(0, 0);
7954 bld
.exec_all().group(1, 0)
7955 .MOV(retype(brw_flag_reg(0, 1), BRW_REGISTER_TYPE_UW
),
7956 retype(dispatch_mask
, BRW_REGISTER_TYPE_UW
));
7964 if (wm_prog_data
->uses_kill
)
7965 bld
.emit(FS_OPCODE_PLACEHOLDER_HALT
);
7967 if (wm_key
->alpha_test_func
)
7972 if (shader_time_index
>= 0)
7973 emit_shader_time_end();
7979 assign_curb_setup();
7981 if (devinfo
->gen
>= 9)
7982 gen9_ps_header_only_workaround(wm_prog_data
);
7986 fixup_3src_null_dest();
7987 allocate_registers(8, allow_spilling
);
7997 fs_visitor::run_cs(unsigned min_dispatch_width
)
7999 assert(stage
== MESA_SHADER_COMPUTE
);
8000 assert(dispatch_width
>= min_dispatch_width
);
8004 if (shader_time_index
>= 0)
8005 emit_shader_time_begin();
8007 if (devinfo
->is_haswell
&& prog_data
->total_shared
> 0) {
8008 /* Move SLM index from g0.0[27:24] to sr0.1[11:8] */
8009 const fs_builder abld
= bld
.exec_all().group(1, 0);
8010 abld
.MOV(retype(brw_sr0_reg(1), BRW_REGISTER_TYPE_UW
),
8011 suboffset(retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_UW
), 1));
8019 emit_cs_terminate();
8021 if (shader_time_index
>= 0)
8022 emit_shader_time_end();
8028 assign_curb_setup();
8030 fixup_3src_null_dest();
8031 allocate_registers(min_dispatch_width
, true);
8040 is_used_in_not_interp_frag_coord(nir_ssa_def
*def
)
8042 nir_foreach_use(src
, def
) {
8043 if (src
->parent_instr
->type
!= nir_instr_type_intrinsic
)
8046 nir_intrinsic_instr
*intrin
= nir_instr_as_intrinsic(src
->parent_instr
);
8047 if (intrin
->intrinsic
!= nir_intrinsic_load_frag_coord
)
8051 nir_foreach_if_use(src
, def
)
8058 * Return a bitfield where bit n is set if barycentric interpolation mode n
8059 * (see enum brw_barycentric_mode) is needed by the fragment shader.
8061 * We examine the load_barycentric intrinsics rather than looking at input
8062 * variables so that we catch interpolateAtCentroid() messages too, which
8063 * also need the BRW_BARYCENTRIC_[NON]PERSPECTIVE_CENTROID mode set up.
8066 brw_compute_barycentric_interp_modes(const struct gen_device_info
*devinfo
,
8067 const nir_shader
*shader
)
8069 unsigned barycentric_interp_modes
= 0;
8071 nir_foreach_function(f
, shader
) {
8075 nir_foreach_block(block
, f
->impl
) {
8076 nir_foreach_instr(instr
, block
) {
8077 if (instr
->type
!= nir_instr_type_intrinsic
)
8080 nir_intrinsic_instr
*intrin
= nir_instr_as_intrinsic(instr
);
8081 switch (intrin
->intrinsic
) {
8082 case nir_intrinsic_load_barycentric_pixel
:
8083 case nir_intrinsic_load_barycentric_centroid
:
8084 case nir_intrinsic_load_barycentric_sample
:
8090 /* Ignore WPOS; it doesn't require interpolation. */
8091 assert(intrin
->dest
.is_ssa
);
8092 if (!is_used_in_not_interp_frag_coord(&intrin
->dest
.ssa
))
8095 enum glsl_interp_mode interp
= (enum glsl_interp_mode
)
8096 nir_intrinsic_interp_mode(intrin
);
8097 nir_intrinsic_op bary_op
= intrin
->intrinsic
;
8098 enum brw_barycentric_mode bary
=
8099 brw_barycentric_mode(interp
, bary_op
);
8101 barycentric_interp_modes
|= 1 << bary
;
8103 if (devinfo
->needs_unlit_centroid_workaround
&&
8104 bary_op
== nir_intrinsic_load_barycentric_centroid
)
8105 barycentric_interp_modes
|= 1 << centroid_to_pixel(bary
);
8110 return barycentric_interp_modes
;
8114 brw_compute_flat_inputs(struct brw_wm_prog_data
*prog_data
,
8115 const nir_shader
*shader
)
8117 prog_data
->flat_inputs
= 0;
8119 nir_foreach_variable(var
, &shader
->inputs
) {
8120 unsigned slots
= glsl_count_attribute_slots(var
->type
, false);
8121 for (unsigned s
= 0; s
< slots
; s
++) {
8122 int input_index
= prog_data
->urb_setup
[var
->data
.location
+ s
];
8124 if (input_index
< 0)
8128 if (var
->data
.interpolation
== INTERP_MODE_FLAT
)
8129 prog_data
->flat_inputs
|= 1 << input_index
;
8135 computed_depth_mode(const nir_shader
*shader
)
8137 if (shader
->info
.outputs_written
& BITFIELD64_BIT(FRAG_RESULT_DEPTH
)) {
8138 switch (shader
->info
.fs
.depth_layout
) {
8139 case FRAG_DEPTH_LAYOUT_NONE
:
8140 case FRAG_DEPTH_LAYOUT_ANY
:
8141 return BRW_PSCDEPTH_ON
;
8142 case FRAG_DEPTH_LAYOUT_GREATER
:
8143 return BRW_PSCDEPTH_ON_GE
;
8144 case FRAG_DEPTH_LAYOUT_LESS
:
8145 return BRW_PSCDEPTH_ON_LE
;
8146 case FRAG_DEPTH_LAYOUT_UNCHANGED
:
8147 return BRW_PSCDEPTH_OFF
;
8150 return BRW_PSCDEPTH_OFF
;
8154 * Move load_interpolated_input with simple (payload-based) barycentric modes
8155 * to the top of the program so we don't emit multiple PLNs for the same input.
8157 * This works around CSE not being able to handle non-dominating cases
8163 * interpolate the same exact input
8166 * This should be replaced by global value numbering someday.
8169 move_interpolation_to_top(nir_shader
*nir
)
8171 bool progress
= false;
8173 nir_foreach_function(f
, nir
) {
8177 nir_block
*top
= nir_start_block(f
->impl
);
8178 exec_node
*cursor_node
= NULL
;
8180 nir_foreach_block(block
, f
->impl
) {
8184 nir_foreach_instr_safe(instr
, block
) {
8185 if (instr
->type
!= nir_instr_type_intrinsic
)
8188 nir_intrinsic_instr
*intrin
= nir_instr_as_intrinsic(instr
);
8189 if (intrin
->intrinsic
!= nir_intrinsic_load_interpolated_input
)
8191 nir_intrinsic_instr
*bary_intrinsic
=
8192 nir_instr_as_intrinsic(intrin
->src
[0].ssa
->parent_instr
);
8193 nir_intrinsic_op op
= bary_intrinsic
->intrinsic
;
8195 /* Leave interpolateAtSample/Offset() where they are. */
8196 if (op
== nir_intrinsic_load_barycentric_at_sample
||
8197 op
== nir_intrinsic_load_barycentric_at_offset
)
8200 nir_instr
*move
[3] = {
8201 &bary_intrinsic
->instr
,
8202 intrin
->src
[1].ssa
->parent_instr
,
8206 for (unsigned i
= 0; i
< ARRAY_SIZE(move
); i
++) {
8207 if (move
[i
]->block
!= top
) {
8208 move
[i
]->block
= top
;
8209 exec_node_remove(&move
[i
]->node
);
8211 exec_node_insert_after(cursor_node
, &move
[i
]->node
);
8213 exec_list_push_head(&top
->instr_list
, &move
[i
]->node
);
8215 cursor_node
= &move
[i
]->node
;
8221 nir_metadata_preserve(f
->impl
, (nir_metadata
)
8222 ((unsigned) nir_metadata_block_index
|
8223 (unsigned) nir_metadata_dominance
));
8230 * Demote per-sample barycentric intrinsics to centroid.
8232 * Useful when rendering to a non-multisampled buffer.
8235 demote_sample_qualifiers(nir_shader
*nir
)
8237 bool progress
= true;
8239 nir_foreach_function(f
, nir
) {
8244 nir_builder_init(&b
, f
->impl
);
8246 nir_foreach_block(block
, f
->impl
) {
8247 nir_foreach_instr_safe(instr
, block
) {
8248 if (instr
->type
!= nir_instr_type_intrinsic
)
8251 nir_intrinsic_instr
*intrin
= nir_instr_as_intrinsic(instr
);
8252 if (intrin
->intrinsic
!= nir_intrinsic_load_barycentric_sample
&&
8253 intrin
->intrinsic
!= nir_intrinsic_load_barycentric_at_sample
)
8256 b
.cursor
= nir_before_instr(instr
);
8257 nir_ssa_def
*centroid
=
8258 nir_load_barycentric(&b
, nir_intrinsic_load_barycentric_centroid
,
8259 nir_intrinsic_interp_mode(intrin
));
8260 nir_ssa_def_rewrite_uses(&intrin
->dest
.ssa
,
8261 nir_src_for_ssa(centroid
));
8262 nir_instr_remove(instr
);
8267 nir_metadata_preserve(f
->impl
, (nir_metadata
)
8268 ((unsigned) nir_metadata_block_index
|
8269 (unsigned) nir_metadata_dominance
));
8276 * Pre-gen6, the register file of the EUs was shared between threads,
8277 * and each thread used some subset allocated on a 16-register block
8278 * granularity. The unit states wanted these block counts.
8281 brw_register_blocks(int reg_count
)
8283 return ALIGN(reg_count
, 16) / 16 - 1;
8287 brw_compile_fs(const struct brw_compiler
*compiler
, void *log_data
,
8289 const struct brw_wm_prog_key
*key
,
8290 struct brw_wm_prog_data
*prog_data
,
8292 int shader_time_index8
, int shader_time_index16
,
8293 int shader_time_index32
, bool allow_spilling
,
8294 bool use_rep_send
, struct brw_vue_map
*vue_map
,
8295 struct brw_compile_stats
*stats
,
8298 const struct gen_device_info
*devinfo
= compiler
->devinfo
;
8300 unsigned max_subgroup_size
= unlikely(INTEL_DEBUG
& DEBUG_DO32
) ? 32 : 16;
8302 brw_nir_apply_key(shader
, compiler
, &key
->base
, max_subgroup_size
, true);
8303 brw_nir_lower_fs_inputs(shader
, devinfo
, key
);
8304 brw_nir_lower_fs_outputs(shader
);
8306 if (devinfo
->gen
< 6)
8307 brw_setup_vue_interpolation(vue_map
, shader
, prog_data
);
8309 /* From the SKL PRM, Volume 7, "Alpha Coverage":
8310 * "If Pixel Shader outputs oMask, AlphaToCoverage is disabled in
8311 * hardware, regardless of the state setting for this feature."
8313 if (devinfo
->gen
> 6 && key
->alpha_to_coverage
) {
8314 /* Run constant fold optimization in order to get the correct source
8315 * offset to determine render target 0 store instruction in
8316 * emit_alpha_to_coverage pass.
8318 NIR_PASS_V(shader
, nir_opt_constant_folding
);
8319 NIR_PASS_V(shader
, brw_nir_lower_alpha_to_coverage
);
8322 if (!key
->multisample_fbo
)
8323 NIR_PASS_V(shader
, demote_sample_qualifiers
);
8324 NIR_PASS_V(shader
, move_interpolation_to_top
);
8325 brw_postprocess_nir(shader
, compiler
, true);
8327 /* key->alpha_test_func means simulating alpha testing via discards,
8328 * so the shader definitely kills pixels.
8330 prog_data
->uses_kill
= shader
->info
.fs
.uses_discard
||
8331 key
->alpha_test_func
;
8332 prog_data
->uses_omask
= key
->multisample_fbo
&&
8333 shader
->info
.outputs_written
& BITFIELD64_BIT(FRAG_RESULT_SAMPLE_MASK
);
8334 prog_data
->computed_depth_mode
= computed_depth_mode(shader
);
8335 prog_data
->computed_stencil
=
8336 shader
->info
.outputs_written
& BITFIELD64_BIT(FRAG_RESULT_STENCIL
);
8338 prog_data
->persample_dispatch
=
8339 key
->multisample_fbo
&&
8340 (key
->persample_interp
||
8341 (shader
->info
.system_values_read
& (SYSTEM_BIT_SAMPLE_ID
|
8342 SYSTEM_BIT_SAMPLE_POS
)) ||
8343 shader
->info
.fs
.uses_sample_qualifier
||
8344 shader
->info
.outputs_read
);
8346 prog_data
->has_render_target_reads
= shader
->info
.outputs_read
!= 0ull;
8348 prog_data
->early_fragment_tests
= shader
->info
.fs
.early_fragment_tests
;
8349 prog_data
->post_depth_coverage
= shader
->info
.fs
.post_depth_coverage
;
8350 prog_data
->inner_coverage
= shader
->info
.fs
.inner_coverage
;
8352 prog_data
->barycentric_interp_modes
=
8353 brw_compute_barycentric_interp_modes(compiler
->devinfo
, shader
);
8355 calculate_urb_setup(devinfo
, key
, prog_data
, shader
);
8356 brw_compute_flat_inputs(prog_data
, shader
);
8358 cfg_t
*simd8_cfg
= NULL
, *simd16_cfg
= NULL
, *simd32_cfg
= NULL
;
8360 fs_visitor
v8(compiler
, log_data
, mem_ctx
, &key
->base
,
8361 &prog_data
->base
, shader
, 8,
8362 shader_time_index8
);
8363 if (!v8
.run_fs(allow_spilling
, false /* do_rep_send */)) {
8365 *error_str
= ralloc_strdup(mem_ctx
, v8
.fail_msg
);
8368 } else if (likely(!(INTEL_DEBUG
& DEBUG_NO8
))) {
8370 prog_data
->base
.dispatch_grf_start_reg
= v8
.payload
.num_regs
;
8371 prog_data
->reg_blocks_8
= brw_register_blocks(v8
.grf_used
);
8374 if (v8
.max_dispatch_width
>= 16 &&
8375 likely(!(INTEL_DEBUG
& DEBUG_NO16
) || use_rep_send
)) {
8376 /* Try a SIMD16 compile */
8377 fs_visitor
v16(compiler
, log_data
, mem_ctx
, &key
->base
,
8378 &prog_data
->base
, shader
, 16,
8379 shader_time_index16
);
8380 v16
.import_uniforms(&v8
);
8381 if (!v16
.run_fs(allow_spilling
, use_rep_send
)) {
8382 compiler
->shader_perf_log(log_data
,
8383 "SIMD16 shader failed to compile: %s",
8386 simd16_cfg
= v16
.cfg
;
8387 prog_data
->dispatch_grf_start_reg_16
= v16
.payload
.num_regs
;
8388 prog_data
->reg_blocks_16
= brw_register_blocks(v16
.grf_used
);
8392 /* Currently, the compiler only supports SIMD32 on SNB+ */
8393 if (v8
.max_dispatch_width
>= 32 && !use_rep_send
&&
8394 compiler
->devinfo
->gen
>= 6 &&
8395 unlikely(INTEL_DEBUG
& DEBUG_DO32
)) {
8396 /* Try a SIMD32 compile */
8397 fs_visitor
v32(compiler
, log_data
, mem_ctx
, &key
->base
,
8398 &prog_data
->base
, shader
, 32,
8399 shader_time_index32
);
8400 v32
.import_uniforms(&v8
);
8401 if (!v32
.run_fs(allow_spilling
, false)) {
8402 compiler
->shader_perf_log(log_data
,
8403 "SIMD32 shader failed to compile: %s",
8406 simd32_cfg
= v32
.cfg
;
8407 prog_data
->dispatch_grf_start_reg_32
= v32
.payload
.num_regs
;
8408 prog_data
->reg_blocks_32
= brw_register_blocks(v32
.grf_used
);
8412 /* When the caller requests a repclear shader, they want SIMD16-only */
8416 /* Prior to Iron Lake, the PS had a single shader offset with a jump table
8417 * at the top to select the shader. We've never implemented that.
8418 * Instead, we just give them exactly one shader and we pick the widest one
8421 if (compiler
->devinfo
->gen
< 5) {
8422 if (simd32_cfg
|| simd16_cfg
)
8428 /* If computed depth is enabled SNB only allows SIMD8. */
8429 if (compiler
->devinfo
->gen
== 6 &&
8430 prog_data
->computed_depth_mode
!= BRW_PSCDEPTH_OFF
)
8431 assert(simd16_cfg
== NULL
&& simd32_cfg
== NULL
);
8433 if (compiler
->devinfo
->gen
<= 5 && !simd8_cfg
) {
8434 /* Iron lake and earlier only have one Dispatch GRF start field. Make
8435 * the data available in the base prog data struct for convenience.
8438 prog_data
->base
.dispatch_grf_start_reg
=
8439 prog_data
->dispatch_grf_start_reg_16
;
8440 } else if (simd32_cfg
) {
8441 prog_data
->base
.dispatch_grf_start_reg
=
8442 prog_data
->dispatch_grf_start_reg_32
;
8446 if (prog_data
->persample_dispatch
) {
8447 /* Starting with SandyBridge (where we first get MSAA), the different
8448 * pixel dispatch combinations are grouped into classifications A
8449 * through F (SNB PRM Vol. 2 Part 1 Section 7.7.1). On all hardware
8450 * generations, the only configurations supporting persample dispatch
8451 * are are this in which only one dispatch width is enabled.
8453 if (simd32_cfg
|| simd16_cfg
)
8459 fs_generator
g(compiler
, log_data
, mem_ctx
, &prog_data
->base
,
8460 v8
.shader_stats
, v8
.runtime_check_aads_emit
,
8461 MESA_SHADER_FRAGMENT
);
8463 if (unlikely(INTEL_DEBUG
& DEBUG_WM
)) {
8464 g
.enable_debug(ralloc_asprintf(mem_ctx
, "%s fragment shader %s",
8465 shader
->info
.label
?
8466 shader
->info
.label
: "unnamed",
8467 shader
->info
.name
));
8471 prog_data
->dispatch_8
= true;
8472 g
.generate_code(simd8_cfg
, 8, stats
);
8473 stats
= stats
? stats
+ 1 : NULL
;
8477 prog_data
->dispatch_16
= true;
8478 prog_data
->prog_offset_16
= g
.generate_code(simd16_cfg
, 16, stats
);
8479 stats
= stats
? stats
+ 1 : NULL
;
8483 prog_data
->dispatch_32
= true;
8484 prog_data
->prog_offset_32
= g
.generate_code(simd32_cfg
, 32, stats
);
8485 stats
= stats
? stats
+ 1 : NULL
;
8488 return g
.get_assembly();
8492 fs_visitor::emit_cs_work_group_id_setup()
8494 assert(stage
== MESA_SHADER_COMPUTE
);
8496 fs_reg
*reg
= new(this->mem_ctx
) fs_reg(vgrf(glsl_type::uvec3_type
));
8498 struct brw_reg
r0_1(retype(brw_vec1_grf(0, 1), BRW_REGISTER_TYPE_UD
));
8499 struct brw_reg
r0_6(retype(brw_vec1_grf(0, 6), BRW_REGISTER_TYPE_UD
));
8500 struct brw_reg
r0_7(retype(brw_vec1_grf(0, 7), BRW_REGISTER_TYPE_UD
));
8502 bld
.MOV(*reg
, r0_1
);
8503 bld
.MOV(offset(*reg
, bld
, 1), r0_6
);
8504 bld
.MOV(offset(*reg
, bld
, 2), r0_7
);
8510 fill_push_const_block_info(struct brw_push_const_block
*block
, unsigned dwords
)
8512 block
->dwords
= dwords
;
8513 block
->regs
= DIV_ROUND_UP(dwords
, 8);
8514 block
->size
= block
->regs
* 32;
8518 cs_fill_push_const_info(const struct gen_device_info
*devinfo
,
8519 struct brw_cs_prog_data
*cs_prog_data
)
8521 const struct brw_stage_prog_data
*prog_data
= &cs_prog_data
->base
;
8522 int subgroup_id_index
= get_subgroup_id_param_index(prog_data
);
8523 bool cross_thread_supported
= devinfo
->gen
> 7 || devinfo
->is_haswell
;
8525 /* The thread ID should be stored in the last param dword */
8526 assert(subgroup_id_index
== -1 ||
8527 subgroup_id_index
== (int)prog_data
->nr_params
- 1);
8529 unsigned cross_thread_dwords
, per_thread_dwords
;
8530 if (!cross_thread_supported
) {
8531 cross_thread_dwords
= 0u;
8532 per_thread_dwords
= prog_data
->nr_params
;
8533 } else if (subgroup_id_index
>= 0) {
8534 /* Fill all but the last register with cross-thread payload */
8535 cross_thread_dwords
= 8 * (subgroup_id_index
/ 8);
8536 per_thread_dwords
= prog_data
->nr_params
- cross_thread_dwords
;
8537 assert(per_thread_dwords
> 0 && per_thread_dwords
<= 8);
8539 /* Fill all data using cross-thread payload */
8540 cross_thread_dwords
= prog_data
->nr_params
;
8541 per_thread_dwords
= 0u;
8544 fill_push_const_block_info(&cs_prog_data
->push
.cross_thread
, cross_thread_dwords
);
8545 fill_push_const_block_info(&cs_prog_data
->push
.per_thread
, per_thread_dwords
);
8547 unsigned total_dwords
=
8548 (cs_prog_data
->push
.per_thread
.size
* cs_prog_data
->threads
+
8549 cs_prog_data
->push
.cross_thread
.size
) / 4;
8550 fill_push_const_block_info(&cs_prog_data
->push
.total
, total_dwords
);
8552 assert(cs_prog_data
->push
.cross_thread
.dwords
% 8 == 0 ||
8553 cs_prog_data
->push
.per_thread
.size
== 0);
8554 assert(cs_prog_data
->push
.cross_thread
.dwords
+
8555 cs_prog_data
->push
.per_thread
.dwords
==
8556 prog_data
->nr_params
);
8560 cs_set_simd_size(struct brw_cs_prog_data
*cs_prog_data
, unsigned size
)
8562 cs_prog_data
->simd_size
= size
;
8563 unsigned group_size
= cs_prog_data
->local_size
[0] *
8564 cs_prog_data
->local_size
[1] * cs_prog_data
->local_size
[2];
8565 cs_prog_data
->threads
= (group_size
+ size
- 1) / size
;
8569 compile_cs_to_nir(const struct brw_compiler
*compiler
,
8571 const struct brw_cs_prog_key
*key
,
8572 const nir_shader
*src_shader
,
8573 unsigned dispatch_width
)
8575 nir_shader
*shader
= nir_shader_clone(mem_ctx
, src_shader
);
8576 brw_nir_apply_key(shader
, compiler
, &key
->base
, dispatch_width
, true);
8578 NIR_PASS_V(shader
, brw_nir_lower_cs_intrinsics
, dispatch_width
);
8580 /* Clean up after the local index and ID calculations. */
8581 NIR_PASS_V(shader
, nir_opt_constant_folding
);
8582 NIR_PASS_V(shader
, nir_opt_dce
);
8584 brw_postprocess_nir(shader
, compiler
, true);
8590 brw_compile_cs(const struct brw_compiler
*compiler
, void *log_data
,
8592 const struct brw_cs_prog_key
*key
,
8593 struct brw_cs_prog_data
*prog_data
,
8594 const nir_shader
*src_shader
,
8595 int shader_time_index
,
8596 struct brw_compile_stats
*stats
,
8599 prog_data
->base
.total_shared
= src_shader
->info
.cs
.shared_size
;
8600 prog_data
->local_size
[0] = src_shader
->info
.cs
.local_size
[0];
8601 prog_data
->local_size
[1] = src_shader
->info
.cs
.local_size
[1];
8602 prog_data
->local_size
[2] = src_shader
->info
.cs
.local_size
[2];
8603 prog_data
->slm_size
= src_shader
->num_shared
;
8604 unsigned local_workgroup_size
=
8605 src_shader
->info
.cs
.local_size
[0] * src_shader
->info
.cs
.local_size
[1] *
8606 src_shader
->info
.cs
.local_size
[2];
8608 unsigned min_dispatch_width
=
8609 DIV_ROUND_UP(local_workgroup_size
, compiler
->devinfo
->max_cs_threads
);
8610 min_dispatch_width
= MAX2(8, min_dispatch_width
);
8611 min_dispatch_width
= util_next_power_of_two(min_dispatch_width
);
8612 assert(min_dispatch_width
<= 32);
8613 unsigned max_dispatch_width
= 32;
8615 fs_visitor
*v8
= NULL
, *v16
= NULL
, *v32
= NULL
;
8616 fs_visitor
*v
= NULL
;
8617 const char *fail_msg
= NULL
;
8619 if ((int)key
->base
.subgroup_size_type
>= (int)BRW_SUBGROUP_SIZE_REQUIRE_8
) {
8620 /* These enum values are expressly chosen to be equal to the subgroup
8621 * size that they require.
8623 const unsigned required_dispatch_width
=
8624 (unsigned)key
->base
.subgroup_size_type
;
8625 assert(required_dispatch_width
== 8 ||
8626 required_dispatch_width
== 16 ||
8627 required_dispatch_width
== 32);
8628 if (required_dispatch_width
< min_dispatch_width
||
8629 required_dispatch_width
> max_dispatch_width
) {
8630 fail_msg
= "Cannot satisfy explicit subgroup size";
8632 min_dispatch_width
= max_dispatch_width
= required_dispatch_width
;
8636 /* Now the main event: Visit the shader IR and generate our CS IR for it.
8638 if (!fail_msg
&& min_dispatch_width
<= 8 && max_dispatch_width
>= 8) {
8639 nir_shader
*nir8
= compile_cs_to_nir(compiler
, mem_ctx
, key
,
8641 v8
= new fs_visitor(compiler
, log_data
, mem_ctx
, &key
->base
,
8643 nir8
, 8, shader_time_index
);
8644 if (!v8
->run_cs(min_dispatch_width
)) {
8645 fail_msg
= v8
->fail_msg
;
8647 /* We should always be able to do SIMD32 for compute shaders */
8648 assert(v8
->max_dispatch_width
>= 32);
8651 cs_set_simd_size(prog_data
, 8);
8652 cs_fill_push_const_info(compiler
->devinfo
, prog_data
);
8656 if (likely(!(INTEL_DEBUG
& DEBUG_NO16
)) &&
8657 !fail_msg
&& min_dispatch_width
<= 16 && max_dispatch_width
>= 16) {
8658 /* Try a SIMD16 compile */
8659 nir_shader
*nir16
= compile_cs_to_nir(compiler
, mem_ctx
, key
,
8661 v16
= new fs_visitor(compiler
, log_data
, mem_ctx
, &key
->base
,
8663 nir16
, 16, shader_time_index
);
8665 v16
->import_uniforms(v8
);
8667 if (!v16
->run_cs(min_dispatch_width
)) {
8668 compiler
->shader_perf_log(log_data
,
8669 "SIMD16 shader failed to compile: %s",
8673 "Couldn't generate SIMD16 program and not "
8674 "enough threads for SIMD8";
8677 /* We should always be able to do SIMD32 for compute shaders */
8678 assert(v16
->max_dispatch_width
>= 32);
8681 cs_set_simd_size(prog_data
, 16);
8682 cs_fill_push_const_info(compiler
->devinfo
, prog_data
);
8686 /* We should always be able to do SIMD32 for compute shaders */
8687 assert(!v16
|| v16
->max_dispatch_width
>= 32);
8689 if (!fail_msg
&& (min_dispatch_width
> 16 || (INTEL_DEBUG
& DEBUG_DO32
)) &&
8690 max_dispatch_width
>= 32) {
8691 /* Try a SIMD32 compile */
8692 nir_shader
*nir32
= compile_cs_to_nir(compiler
, mem_ctx
, key
,
8694 v32
= new fs_visitor(compiler
, log_data
, mem_ctx
, &key
->base
,
8696 nir32
, 32, shader_time_index
);
8698 v32
->import_uniforms(v8
);
8700 v32
->import_uniforms(v16
);
8702 if (!v32
->run_cs(min_dispatch_width
)) {
8703 compiler
->shader_perf_log(log_data
,
8704 "SIMD32 shader failed to compile: %s",
8708 "Couldn't generate SIMD32 program and not "
8709 "enough threads for SIMD16";
8713 cs_set_simd_size(prog_data
, 32);
8714 cs_fill_push_const_info(compiler
->devinfo
, prog_data
);
8718 const unsigned *ret
= NULL
;
8719 if (unlikely(v
== NULL
)) {
8722 *error_str
= ralloc_strdup(mem_ctx
, fail_msg
);
8724 fs_generator
g(compiler
, log_data
, mem_ctx
, &prog_data
->base
,
8725 v
->shader_stats
, v
->runtime_check_aads_emit
,
8726 MESA_SHADER_COMPUTE
);
8727 if (INTEL_DEBUG
& DEBUG_CS
) {
8728 char *name
= ralloc_asprintf(mem_ctx
, "%s compute shader %s",
8729 src_shader
->info
.label
?
8730 src_shader
->info
.label
: "unnamed",
8731 src_shader
->info
.name
);
8732 g
.enable_debug(name
);
8735 g
.generate_code(v
->cfg
, prog_data
->simd_size
, stats
);
8737 ret
= g
.get_assembly();
8748 * Test the dispatch mask packing assumptions of
8749 * brw_stage_has_packed_dispatch(). Call this from e.g. the top of
8750 * fs_visitor::emit_nir_code() to cause a GPU hang if any shader invocation is
8751 * executed with an unexpected dispatch mask.
8754 brw_fs_test_dispatch_packing(const fs_builder
&bld
)
8756 const gl_shader_stage stage
= bld
.shader
->stage
;
8758 if (brw_stage_has_packed_dispatch(bld
.shader
->devinfo
, stage
,
8759 bld
.shader
->stage_prog_data
)) {
8760 const fs_builder ubld
= bld
.exec_all().group(1, 0);
8761 const fs_reg tmp
= component(bld
.vgrf(BRW_REGISTER_TYPE_UD
), 0);
8762 const fs_reg mask
= (stage
== MESA_SHADER_FRAGMENT
? brw_vmask_reg() :
8765 ubld
.ADD(tmp
, mask
, brw_imm_ud(1));
8766 ubld
.AND(tmp
, mask
, tmp
);
8768 /* This will loop forever if the dispatch mask doesn't have the expected
8769 * form '2^n-1', in which case tmp will be non-zero.
8771 bld
.emit(BRW_OPCODE_DO
);
8772 bld
.CMP(bld
.null_reg_ud(), tmp
, brw_imm_ud(0), BRW_CONDITIONAL_NZ
);
8773 set_predicate(BRW_PREDICATE_NORMAL
, bld
.emit(BRW_OPCODE_WHILE
));