2 * Copyright © 2010 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 /** @file brw_fs_generator.cpp
26 * This file supports generating code from the FS LIR to the actual
27 * native instructions.
33 #include "util/mesa-sha1.h"
35 static enum brw_reg_file
36 brw_file_from_reg(fs_reg
*reg
)
40 return BRW_ARCHITECTURE_REGISTER_FILE
;
43 return BRW_GENERAL_REGISTER_FILE
;
45 return BRW_MESSAGE_REGISTER_FILE
;
47 return BRW_IMMEDIATE_VALUE
;
51 unreachable("not reached");
53 return BRW_ARCHITECTURE_REGISTER_FILE
;
57 brw_reg_from_fs_reg(const struct gen_device_info
*devinfo
, fs_inst
*inst
,
58 fs_reg
*reg
, bool compressed
)
60 struct brw_reg brw_reg
;
64 assert((reg
->nr
& ~BRW_MRF_COMPR4
) < BRW_MAX_MRF(devinfo
->gen
));
67 if (reg
->stride
== 0) {
68 brw_reg
= brw_vec1_reg(brw_file_from_reg(reg
), reg
->nr
, 0);
70 /* From the Haswell PRM:
72 * "VertStride must be used to cross GRF register boundaries. This
73 * rule implies that elements within a 'Width' cannot cross GRF
76 * The maximum width value that could satisfy this restriction is:
78 const unsigned reg_width
= REG_SIZE
/ (reg
->stride
* type_sz(reg
->type
));
80 /* Because the hardware can only split source regions at a whole
81 * multiple of width during decompression (i.e. vertically), clamp
82 * the value obtained above to the physical execution size of a
83 * single decompressed chunk of the instruction:
85 const unsigned phys_width
= compressed
? inst
->exec_size
/ 2 :
88 /* XXX - The equation above is strictly speaking not correct on
89 * hardware that supports unbalanced GRF writes -- On Gen9+
90 * each decompressed chunk of the instruction may have a
91 * different execution size when the number of components
92 * written to each destination GRF is not the same.
94 if (reg
->stride
> 4) {
95 assert(reg
!= &inst
->dst
);
96 assert(reg
->stride
* type_sz(reg
->type
) <= REG_SIZE
);
97 brw_reg
= brw_vecn_reg(1, brw_file_from_reg(reg
), reg
->nr
, 0);
98 brw_reg
= stride(brw_reg
, reg
->stride
, 1, 0);
100 const unsigned width
= MIN2(reg_width
, phys_width
);
101 brw_reg
= brw_vecn_reg(width
, brw_file_from_reg(reg
), reg
->nr
, 0);
102 brw_reg
= stride(brw_reg
, width
* reg
->stride
, width
, reg
->stride
);
105 if (devinfo
->gen
== 7 && !devinfo
->is_haswell
) {
106 /* From the IvyBridge PRM (EU Changes by Processor Generation, page 13):
107 * "Each DF (Double Float) operand uses an element size of 4 rather
108 * than 8 and all regioning parameters are twice what the values
109 * would be based on the true element size: ExecSize, Width,
110 * HorzStride, and VertStride. Each DF operand uses a pair of
111 * channels and all masking and swizzing should be adjusted
114 * From the IvyBridge PRM (Special Requirements for Handling Double
115 * Precision Data Types, page 71):
116 * "In Align1 mode, all regioning parameters like stride, execution
117 * size, and width must use the syntax of a pair of packed
118 * floats. The offsets for these data types must be 64-bit
119 * aligned. The execution size and regioning parameters are in terms
122 * Summarized: when handling DF-typed arguments, ExecSize,
123 * VertStride, and Width must be doubled.
125 * It applies to BayTrail too.
127 if (type_sz(reg
->type
) == 8) {
129 if (brw_reg
.vstride
> 0)
131 assert(brw_reg
.hstride
== BRW_HORIZONTAL_STRIDE_1
);
134 /* When converting from DF->F, we set the destination stride to 2
135 * because each d2f conversion implicitly writes 2 floats, being
136 * the first one the converted value. IVB/BYT actually writes two
137 * F components per SIMD channel, and every other component is
138 * filled with garbage.
140 if (reg
== &inst
->dst
&& get_exec_type_size(inst
) == 8 &&
141 type_sz(inst
->dst
.type
) < 8) {
142 assert(brw_reg
.hstride
> BRW_HORIZONTAL_STRIDE_1
);
148 brw_reg
= retype(brw_reg
, reg
->type
);
149 brw_reg
= byte_offset(brw_reg
, reg
->offset
);
150 brw_reg
.abs
= reg
->abs
;
151 brw_reg
.negate
= reg
->negate
;
156 assert(reg
->offset
== 0);
157 brw_reg
= reg
->as_brw_reg();
160 /* Probably unused. */
161 brw_reg
= brw_null_reg();
165 unreachable("not reached");
168 /* On HSW+, scalar DF sources can be accessed using the normal <0,1,0>
169 * region, but on IVB and BYT DF regions must be programmed in terms of
170 * floats. A <0,2,1> region accomplishes this.
172 if (devinfo
->gen
== 7 && !devinfo
->is_haswell
&&
173 type_sz(reg
->type
) == 8 &&
174 brw_reg
.vstride
== BRW_VERTICAL_STRIDE_0
&&
175 brw_reg
.width
== BRW_WIDTH_1
&&
176 brw_reg
.hstride
== BRW_HORIZONTAL_STRIDE_0
) {
177 brw_reg
.width
= BRW_WIDTH_2
;
178 brw_reg
.hstride
= BRW_HORIZONTAL_STRIDE_1
;
184 fs_generator::fs_generator(const struct brw_compiler
*compiler
, void *log_data
,
186 struct brw_stage_prog_data
*prog_data
,
187 struct shader_stats shader_stats
,
188 bool runtime_check_aads_emit
,
189 gl_shader_stage stage
)
191 : compiler(compiler
), log_data(log_data
),
192 devinfo(compiler
->devinfo
),
193 prog_data(prog_data
),
194 shader_stats(shader_stats
),
195 runtime_check_aads_emit(runtime_check_aads_emit
), debug_flag(false),
196 stage(stage
), mem_ctx(mem_ctx
)
198 p
= rzalloc(mem_ctx
, struct brw_codegen
);
199 brw_init_codegen(devinfo
, p
, mem_ctx
);
201 /* In the FS code generator, we are very careful to ensure that we always
202 * set the right execution size so we don't need the EU code to "help" us
203 * by trying to infer it. Sometimes, it infers the wrong thing.
205 p
->automatic_exec_sizes
= false;
208 fs_generator::~fs_generator()
212 class ip_record
: public exec_node
{
214 DECLARE_RALLOC_CXX_OPERATORS(ip_record
)
225 fs_generator::patch_discard_jumps_to_fb_writes()
227 if (devinfo
->gen
< 6 || this->discard_halt_patches
.is_empty())
230 int scale
= brw_jump_scale(p
->devinfo
);
232 /* There is a somewhat strange undocumented requirement of using
233 * HALT, according to the simulator. If some channel has HALTed to
234 * a particular UIP, then by the end of the program, every channel
235 * must have HALTed to that UIP. Furthermore, the tracking is a
236 * stack, so you can't do the final halt of a UIP after starting
237 * halting to a new UIP.
239 * Symptoms of not emitting this instruction on actual hardware
240 * included GPU hangs and sparkly rendering on the piglit discard
243 brw_inst
*last_halt
= gen6_HALT(p
);
244 brw_inst_set_uip(p
->devinfo
, last_halt
, 1 * scale
);
245 brw_inst_set_jip(p
->devinfo
, last_halt
, 1 * scale
);
249 foreach_in_list(ip_record
, patch_ip
, &discard_halt_patches
) {
250 brw_inst
*patch
= &p
->store
[patch_ip
->ip
];
252 assert(brw_inst_opcode(p
->devinfo
, patch
) == BRW_OPCODE_HALT
);
253 /* HALT takes a half-instruction distance from the pre-incremented IP. */
254 brw_inst_set_uip(p
->devinfo
, patch
, (ip
- patch_ip
->ip
) * scale
);
257 this->discard_halt_patches
.make_empty();
262 fs_generator::generate_send(fs_inst
*inst
,
265 struct brw_reg ex_desc
,
266 struct brw_reg payload
,
267 struct brw_reg payload2
)
269 const bool dst_is_null
= dst
.file
== BRW_ARCHITECTURE_REGISTER_FILE
&&
270 dst
.nr
== BRW_ARF_NULL
;
271 const unsigned rlen
= dst_is_null
? 0 : inst
->size_written
/ REG_SIZE
;
273 uint32_t desc_imm
= inst
->desc
|
274 brw_message_desc(devinfo
, inst
->mlen
, rlen
, inst
->header_size
);
276 uint32_t ex_desc_imm
= brw_message_ex_desc(devinfo
, inst
->ex_mlen
);
278 if (ex_desc
.file
!= BRW_IMMEDIATE_VALUE
|| ex_desc
.ud
|| ex_desc_imm
) {
279 /* If we have any sort of extended descriptor, then we need SENDS. This
280 * also covers the dual-payload case because ex_mlen goes in ex_desc.
282 brw_send_indirect_split_message(p
, inst
->sfid
, dst
, payload
, payload2
,
283 desc
, desc_imm
, ex_desc
, ex_desc_imm
,
286 brw_inst_set_opcode(p
->devinfo
, brw_last_inst
, BRW_OPCODE_SENDSC
);
288 brw_send_indirect_message(p
, inst
->sfid
, dst
, payload
, desc
, desc_imm
,
291 brw_inst_set_opcode(p
->devinfo
, brw_last_inst
, BRW_OPCODE_SENDC
);
296 fs_generator::fire_fb_write(fs_inst
*inst
,
297 struct brw_reg payload
,
298 struct brw_reg implied_header
,
301 struct brw_wm_prog_data
*prog_data
= brw_wm_prog_data(this->prog_data
);
303 if (devinfo
->gen
< 6) {
304 brw_push_insn_state(p
);
305 brw_set_default_exec_size(p
, BRW_EXECUTE_8
);
306 brw_set_default_mask_control(p
, BRW_MASK_DISABLE
);
307 brw_set_default_predicate_control(p
, BRW_PREDICATE_NONE
);
308 brw_set_default_compression_control(p
, BRW_COMPRESSION_NONE
);
309 brw_MOV(p
, offset(retype(payload
, BRW_REGISTER_TYPE_UD
), 1),
310 offset(retype(implied_header
, BRW_REGISTER_TYPE_UD
), 1));
311 brw_pop_insn_state(p
);
314 uint32_t msg_control
= brw_fb_write_msg_control(inst
, prog_data
);
316 /* We assume render targets start at 0, because headerless FB write
317 * messages set "Render Target Index" to 0. Using a different binding
318 * table index would make it impossible to use headerless messages.
320 const uint32_t surf_index
= inst
->target
;
322 brw_inst
*insn
= brw_fb_WRITE(p
,
324 retype(implied_header
, BRW_REGISTER_TYPE_UW
),
331 inst
->header_size
!= 0);
333 if (devinfo
->gen
>= 6)
334 brw_inst_set_rt_slot_group(devinfo
, insn
, inst
->group
/ 16);
338 fs_generator::generate_fb_write(fs_inst
*inst
, struct brw_reg payload
)
340 if (devinfo
->gen
< 8 && !devinfo
->is_haswell
) {
341 brw_set_default_predicate_control(p
, BRW_PREDICATE_NONE
);
342 brw_set_default_flag_reg(p
, 0, 0);
345 const struct brw_reg implied_header
=
346 devinfo
->gen
< 6 ? payload
: brw_null_reg();
348 if (inst
->base_mrf
>= 0)
349 payload
= brw_message_reg(inst
->base_mrf
);
351 if (!runtime_check_aads_emit
) {
352 fire_fb_write(inst
, payload
, implied_header
, inst
->mlen
);
354 /* This can only happen in gen < 6 */
355 assert(devinfo
->gen
< 6);
357 struct brw_reg v1_null_ud
= vec1(retype(brw_null_reg(), BRW_REGISTER_TYPE_UD
));
359 /* Check runtime bit to detect if we have to send AA data or not */
360 brw_push_insn_state(p
);
361 brw_set_default_compression_control(p
, BRW_COMPRESSION_NONE
);
362 brw_set_default_exec_size(p
, BRW_EXECUTE_1
);
365 retype(brw_vec1_grf(1, 6), BRW_REGISTER_TYPE_UD
),
367 brw_inst_set_cond_modifier(p
->devinfo
, brw_last_inst
, BRW_CONDITIONAL_NZ
);
369 int jmp
= brw_JMPI(p
, brw_imm_ud(0), BRW_PREDICATE_NORMAL
) - p
->store
;
370 brw_pop_insn_state(p
);
372 /* Don't send AA data */
373 fire_fb_write(inst
, offset(payload
, 1), implied_header
, inst
->mlen
-1);
375 brw_land_fwd_jump(p
, jmp
);
376 fire_fb_write(inst
, payload
, implied_header
, inst
->mlen
);
381 fs_generator::generate_fb_read(fs_inst
*inst
, struct brw_reg dst
,
382 struct brw_reg payload
)
384 assert(inst
->size_written
% REG_SIZE
== 0);
385 struct brw_wm_prog_data
*prog_data
= brw_wm_prog_data(this->prog_data
);
386 /* We assume that render targets start at binding table index 0. */
387 const unsigned surf_index
= inst
->target
;
389 gen9_fb_READ(p
, dst
, payload
, surf_index
,
390 inst
->header_size
, inst
->size_written
/ REG_SIZE
,
391 prog_data
->persample_dispatch
);
395 fs_generator::generate_mov_indirect(fs_inst
*inst
,
398 struct brw_reg indirect_byte_offset
)
400 assert(indirect_byte_offset
.type
== BRW_REGISTER_TYPE_UD
);
401 assert(indirect_byte_offset
.file
== BRW_GENERAL_REGISTER_FILE
);
402 assert(!reg
.abs
&& !reg
.negate
);
403 assert(reg
.type
== dst
.type
);
405 unsigned imm_byte_offset
= reg
.nr
* REG_SIZE
+ reg
.subnr
;
407 if (indirect_byte_offset
.file
== BRW_IMMEDIATE_VALUE
) {
408 imm_byte_offset
+= indirect_byte_offset
.ud
;
410 reg
.nr
= imm_byte_offset
/ REG_SIZE
;
411 reg
.subnr
= imm_byte_offset
% REG_SIZE
;
412 brw_MOV(p
, dst
, reg
);
414 /* Prior to Broadwell, there are only 8 address registers. */
415 assert(inst
->exec_size
<= 8 || devinfo
->gen
>= 8);
417 /* We use VxH indirect addressing, clobbering a0.0 through a0.7. */
418 struct brw_reg addr
= vec8(brw_address_reg(0));
420 /* The destination stride of an instruction (in bytes) must be greater
421 * than or equal to the size of the rest of the instruction. Since the
422 * address register is of type UW, we can't use a D-type instruction.
423 * In order to get around this, re retype to UW and use a stride.
425 indirect_byte_offset
=
426 retype(spread(indirect_byte_offset
, 2), BRW_REGISTER_TYPE_UW
);
428 /* There are a number of reasons why we don't use the base offset here.
429 * One reason is that the field is only 9 bits which means we can only
430 * use it to access the first 16 GRFs. Also, from the Haswell PRM
431 * section "Register Region Restrictions":
433 * "The lower bits of the AddressImmediate must not overflow to
434 * change the register address. The lower 5 bits of Address
435 * Immediate when added to lower 5 bits of address register gives
436 * the sub-register offset. The upper bits of Address Immediate
437 * when added to upper bits of address register gives the register
438 * address. Any overflow from sub-register offset is dropped."
440 * Since the indirect may cause us to cross a register boundary, this
441 * makes the base offset almost useless. We could try and do something
442 * clever where we use a actual base offset if base_offset % 32 == 0 but
443 * that would mean we were generating different code depending on the
444 * base offset. Instead, for the sake of consistency, we'll just do the
445 * add ourselves. This restriction is only listed in the Haswell PRM
446 * but empirical testing indicates that it applies on all older
447 * generations and is lifted on Broadwell.
449 * In the end, while base_offset is nice to look at in the generated
450 * code, using it saves us 0 instructions and would require quite a bit
451 * of case-by-case work. It's just not worth it.
453 brw_ADD(p
, addr
, indirect_byte_offset
, brw_imm_uw(imm_byte_offset
));
455 if (type_sz(reg
.type
) > 4 &&
456 ((devinfo
->gen
== 7 && !devinfo
->is_haswell
) ||
457 devinfo
->is_cherryview
|| gen_device_info_is_9lp(devinfo
) ||
458 !devinfo
->has_64bit_types
)) {
459 /* IVB has an issue (which we found empirically) where it reads two
460 * address register components per channel for indirectly addressed
463 * From the Cherryview PRM Vol 7. "Register Region Restrictions":
465 * "When source or destination datatype is 64b or operation is
466 * integer DWord multiply, indirect addressing must not be used."
468 * To work around both of these, we do two integer MOVs insead of one
469 * 64-bit MOV. Because no double value should ever cross a register
470 * boundary, it's safe to use the immediate offset in the indirect
471 * here to handle adding 4 bytes to the offset and avoid the extra
472 * ADD to the register file.
474 brw_MOV(p
, subscript(dst
, BRW_REGISTER_TYPE_D
, 0),
475 retype(brw_VxH_indirect(0, 0), BRW_REGISTER_TYPE_D
));
476 brw_MOV(p
, subscript(dst
, BRW_REGISTER_TYPE_D
, 1),
477 retype(brw_VxH_indirect(0, 4), BRW_REGISTER_TYPE_D
));
479 struct brw_reg ind_src
= brw_VxH_indirect(0, 0);
481 brw_inst
*mov
= brw_MOV(p
, dst
, retype(ind_src
, reg
.type
));
483 if (devinfo
->gen
== 6 && dst
.file
== BRW_MESSAGE_REGISTER_FILE
&&
484 !inst
->get_next()->is_tail_sentinel() &&
485 ((fs_inst
*)inst
->get_next())->mlen
> 0) {
486 /* From the Sandybridge PRM:
488 * "[Errata: DevSNB(SNB)] If MRF register is updated by any
489 * instruction that “indexed/indirect” source AND is followed
490 * by a send, the instruction requires a “Switch”. This is to
491 * avoid race condition where send may dispatch before MRF is
494 brw_inst_set_thread_control(devinfo
, mov
, BRW_THREAD_SWITCH
);
501 fs_generator::generate_shuffle(fs_inst
*inst
,
506 /* Ivy bridge has some strange behavior that makes this a real pain to
507 * implement for 64-bit values so we just don't bother.
509 assert(devinfo
->gen
>= 8 || devinfo
->is_haswell
|| type_sz(src
.type
) <= 4);
511 /* Because we're using the address register, we're limited to 8-wide
512 * execution on gen7. On gen8, we're limited to 16-wide by the address
513 * register file and 8-wide for 64-bit types. We could try and make this
514 * instruction splittable higher up in the compiler but that gets weird
515 * because it reads all of the channels regardless of execution size. It's
516 * easier just to split it here.
518 const unsigned lower_width
=
519 (devinfo
->gen
<= 7 || type_sz(src
.type
) > 4) ?
520 8 : MIN2(16, inst
->exec_size
);
522 brw_set_default_exec_size(p
, cvt(lower_width
) - 1);
523 for (unsigned group
= 0; group
< inst
->exec_size
; group
+= lower_width
) {
524 brw_set_default_group(p
, group
);
526 if ((src
.vstride
== 0 && src
.hstride
== 0) ||
527 idx
.file
== BRW_IMMEDIATE_VALUE
) {
528 /* Trivial, the source is already uniform or the index is a constant.
529 * We will typically not get here if the optimizer is doing its job,
530 * but asserting would be mean.
532 const unsigned i
= idx
.file
== BRW_IMMEDIATE_VALUE
? idx
.ud
: 0;
533 brw_MOV(p
, suboffset(dst
, group
), stride(suboffset(src
, i
), 0, 1, 0));
535 /* We use VxH indirect addressing, clobbering a0.0 through a0.7. */
536 struct brw_reg addr
= vec8(brw_address_reg(0));
538 struct brw_reg group_idx
= suboffset(idx
, group
);
540 if (lower_width
== 8 && group_idx
.width
== BRW_WIDTH_16
) {
541 /* Things get grumpy if the register is too wide. */
546 assert(type_sz(group_idx
.type
) <= 4);
547 if (type_sz(group_idx
.type
) == 4) {
548 /* The destination stride of an instruction (in bytes) must be
549 * greater than or equal to the size of the rest of the
550 * instruction. Since the address register is of type UW, we
551 * can't use a D-type instruction. In order to get around this,
552 * re retype to UW and use a stride.
554 group_idx
= retype(spread(group_idx
, 2), BRW_REGISTER_TYPE_W
);
557 /* Take into account the component size and horizontal stride. */
558 assert(src
.vstride
== src
.hstride
+ src
.width
);
559 brw_SHL(p
, addr
, group_idx
,
560 brw_imm_uw(_mesa_logbase2(type_sz(src
.type
)) +
563 /* Add on the register start offset */
564 brw_ADD(p
, addr
, addr
, brw_imm_uw(src
.nr
* REG_SIZE
+ src
.subnr
));
566 if (type_sz(src
.type
) > 4 &&
567 ((devinfo
->gen
== 7 && !devinfo
->is_haswell
) ||
568 devinfo
->is_cherryview
|| gen_device_info_is_9lp(devinfo
))) {
569 /* IVB has an issue (which we found empirically) where it reads
570 * two address register components per channel for indirectly
571 * addressed 64-bit sources.
573 * From the Cherryview PRM Vol 7. "Register Region Restrictions":
575 * "When source or destination datatype is 64b or operation is
576 * integer DWord multiply, indirect addressing must not be
579 * To work around both of these, we do two integer MOVs insead of
580 * one 64-bit MOV. Because no double value should ever cross a
581 * register boundary, it's safe to use the immediate offset in the
582 * indirect here to handle adding 4 bytes to the offset and avoid
583 * the extra ADD to the register file.
585 struct brw_reg gdst
= suboffset(dst
, group
);
586 struct brw_reg dst_d
= retype(spread(gdst
, 2),
587 BRW_REGISTER_TYPE_D
);
589 retype(brw_VxH_indirect(0, 0), BRW_REGISTER_TYPE_D
));
590 brw_MOV(p
, byte_offset(dst_d
, 4),
591 retype(brw_VxH_indirect(0, 4), BRW_REGISTER_TYPE_D
));
593 brw_MOV(p
, suboffset(dst
, group
),
594 retype(brw_VxH_indirect(0, 0), src
.type
));
601 fs_generator::generate_quad_swizzle(const fs_inst
*inst
,
602 struct brw_reg dst
, struct brw_reg src
,
605 /* Requires a quad. */
606 assert(inst
->exec_size
>= 4);
608 if (src
.file
== BRW_IMMEDIATE_VALUE
||
609 has_scalar_region(src
)) {
610 /* The value is uniform across all channels */
611 brw_MOV(p
, dst
, src
);
613 } else if (devinfo
->gen
< 11 && type_sz(src
.type
) == 4) {
614 /* This only works on 8-wide 32-bit values */
615 assert(inst
->exec_size
== 8);
616 assert(src
.hstride
== BRW_HORIZONTAL_STRIDE_1
);
617 assert(src
.vstride
== src
.width
+ 1);
618 brw_set_default_access_mode(p
, BRW_ALIGN_16
);
619 struct brw_reg swiz_src
= stride(src
, 4, 4, 1);
620 swiz_src
.swizzle
= swiz
;
621 brw_MOV(p
, dst
, swiz_src
);
624 assert(src
.hstride
== BRW_HORIZONTAL_STRIDE_1
);
625 assert(src
.vstride
== src
.width
+ 1);
626 const struct brw_reg src_0
= suboffset(src
, BRW_GET_SWZ(swiz
, 0));
629 case BRW_SWIZZLE_XXXX
:
630 case BRW_SWIZZLE_YYYY
:
631 case BRW_SWIZZLE_ZZZZ
:
632 case BRW_SWIZZLE_WWWW
:
633 brw_MOV(p
, dst
, stride(src_0
, 4, 4, 0));
636 case BRW_SWIZZLE_XXZZ
:
637 case BRW_SWIZZLE_YYWW
:
638 brw_MOV(p
, dst
, stride(src_0
, 2, 2, 0));
641 case BRW_SWIZZLE_XYXY
:
642 case BRW_SWIZZLE_ZWZW
:
643 assert(inst
->exec_size
== 4);
644 brw_MOV(p
, dst
, stride(src_0
, 0, 2, 1));
648 assert(inst
->force_writemask_all
);
649 brw_set_default_exec_size(p
, cvt(inst
->exec_size
/ 4) - 1);
651 for (unsigned c
= 0; c
< 4; c
++) {
652 brw_inst
*insn
= brw_MOV(
653 p
, stride(suboffset(dst
, c
),
654 4 * inst
->dst
.stride
, 1, 4 * inst
->dst
.stride
),
655 stride(suboffset(src
, BRW_GET_SWZ(swiz
, c
)), 4, 1, 0));
657 brw_inst_set_no_dd_clear(devinfo
, insn
, c
< 3);
658 brw_inst_set_no_dd_check(devinfo
, insn
, c
> 0);
667 fs_generator::generate_urb_read(fs_inst
*inst
,
669 struct brw_reg header
)
671 assert(inst
->size_written
% REG_SIZE
== 0);
672 assert(header
.file
== BRW_GENERAL_REGISTER_FILE
);
673 assert(header
.type
== BRW_REGISTER_TYPE_UD
);
675 brw_inst
*send
= brw_next_insn(p
, BRW_OPCODE_SEND
);
676 brw_set_dest(p
, send
, retype(dst
, BRW_REGISTER_TYPE_UD
));
677 brw_set_src0(p
, send
, header
);
678 brw_set_src1(p
, send
, brw_imm_ud(0u));
680 brw_inst_set_sfid(p
->devinfo
, send
, BRW_SFID_URB
);
681 brw_inst_set_urb_opcode(p
->devinfo
, send
, GEN8_URB_OPCODE_SIMD8_READ
);
683 if (inst
->opcode
== SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT
)
684 brw_inst_set_urb_per_slot_offset(p
->devinfo
, send
, true);
686 brw_inst_set_mlen(p
->devinfo
, send
, inst
->mlen
);
687 brw_inst_set_rlen(p
->devinfo
, send
, inst
->size_written
/ REG_SIZE
);
688 brw_inst_set_header_present(p
->devinfo
, send
, true);
689 brw_inst_set_urb_global_offset(p
->devinfo
, send
, inst
->offset
);
693 fs_generator::generate_urb_write(fs_inst
*inst
, struct brw_reg payload
)
697 /* WaClearTDRRegBeforeEOTForNonPS.
699 * WA: Clear tdr register before send EOT in all non-PS shader kernels
701 * mov(8) tdr0:ud 0x0:ud {NoMask}"
703 if (inst
->eot
&& p
->devinfo
->gen
== 10) {
704 brw_push_insn_state(p
);
705 brw_set_default_mask_control(p
, BRW_MASK_DISABLE
);
706 brw_MOV(p
, brw_tdr_reg(), brw_imm_uw(0));
707 brw_pop_insn_state(p
);
710 insn
= brw_next_insn(p
, BRW_OPCODE_SEND
);
712 brw_set_dest(p
, insn
, brw_null_reg());
713 brw_set_src0(p
, insn
, payload
);
714 brw_set_src1(p
, insn
, brw_imm_ud(0u));
716 brw_inst_set_sfid(p
->devinfo
, insn
, BRW_SFID_URB
);
717 brw_inst_set_urb_opcode(p
->devinfo
, insn
, GEN8_URB_OPCODE_SIMD8_WRITE
);
719 if (inst
->opcode
== SHADER_OPCODE_URB_WRITE_SIMD8_PER_SLOT
||
720 inst
->opcode
== SHADER_OPCODE_URB_WRITE_SIMD8_MASKED_PER_SLOT
)
721 brw_inst_set_urb_per_slot_offset(p
->devinfo
, insn
, true);
723 if (inst
->opcode
== SHADER_OPCODE_URB_WRITE_SIMD8_MASKED
||
724 inst
->opcode
== SHADER_OPCODE_URB_WRITE_SIMD8_MASKED_PER_SLOT
)
725 brw_inst_set_urb_channel_mask_present(p
->devinfo
, insn
, true);
727 brw_inst_set_mlen(p
->devinfo
, insn
, inst
->mlen
);
728 brw_inst_set_rlen(p
->devinfo
, insn
, 0);
729 brw_inst_set_eot(p
->devinfo
, insn
, inst
->eot
);
730 brw_inst_set_header_present(p
->devinfo
, insn
, true);
731 brw_inst_set_urb_global_offset(p
->devinfo
, insn
, inst
->offset
);
735 fs_generator::generate_cs_terminate(fs_inst
*inst
, struct brw_reg payload
)
737 struct brw_inst
*insn
;
739 insn
= brw_next_insn(p
, BRW_OPCODE_SEND
);
741 brw_set_dest(p
, insn
, retype(brw_null_reg(), BRW_REGISTER_TYPE_UW
));
742 brw_set_src0(p
, insn
, retype(payload
, BRW_REGISTER_TYPE_UW
));
743 brw_set_src1(p
, insn
, brw_imm_ud(0u));
745 /* Terminate a compute shader by sending a message to the thread spawner.
747 brw_inst_set_sfid(devinfo
, insn
, BRW_SFID_THREAD_SPAWNER
);
748 brw_inst_set_mlen(devinfo
, insn
, 1);
749 brw_inst_set_rlen(devinfo
, insn
, 0);
750 brw_inst_set_eot(devinfo
, insn
, inst
->eot
);
751 brw_inst_set_header_present(devinfo
, insn
, false);
753 brw_inst_set_ts_opcode(devinfo
, insn
, 0); /* Dereference resource */
754 brw_inst_set_ts_request_type(devinfo
, insn
, 0); /* Root thread */
756 /* Note that even though the thread has a URB resource associated with it,
757 * we set the "do not dereference URB" bit, because the URB resource is
758 * managed by the fixed-function unit, so it will free it automatically.
760 brw_inst_set_ts_resource_select(devinfo
, insn
, 1); /* Do not dereference URB */
762 brw_inst_set_mask_control(devinfo
, insn
, BRW_MASK_DISABLE
);
766 fs_generator::generate_barrier(fs_inst
*, struct brw_reg src
)
773 fs_generator::generate_linterp(fs_inst
*inst
,
774 struct brw_reg dst
, struct brw_reg
*src
)
778 * -----------------------------------
779 * | src1+0 | src1+1 | src1+2 | src1+3 |
780 * |-----------------------------------|
781 * |(x0, x1)|(y0, y1)|(x2, x3)|(y2, y3)|
782 * -----------------------------------
784 * but for the LINE/MAC pair, the LINE reads Xs and the MAC reads Ys:
786 * -----------------------------------
787 * | src1+0 | src1+1 | src1+2 | src1+3 |
788 * |-----------------------------------|
789 * |(x0, x1)|(y0, y1)| | | in SIMD8
790 * |-----------------------------------|
791 * |(x0, x1)|(x2, x3)|(y0, y1)|(y2, y3)| in SIMD16
792 * -----------------------------------
794 * See also: emit_interpolation_setup_gen4().
796 struct brw_reg delta_x
= src
[0];
797 struct brw_reg delta_y
= offset(src
[0], inst
->exec_size
/ 8);
798 struct brw_reg interp
= src
[1];
801 /* nir_lower_interpolation() will do the lowering to MAD instructions for
804 assert(devinfo
->gen
< 11);
806 if (devinfo
->has_pln
) {
807 if (devinfo
->gen
<= 6 && (delta_x
.nr
& 1) != 0) {
808 /* From the Sandy Bridge PRM Vol. 4, Pt. 2, Section 8.3.53, "Plane":
810 * "[DevSNB]:<src1> must be even register aligned.
812 * This restriction is lifted on Ivy Bridge.
814 * This means that we need to split PLN into LINE+MAC on-the-fly.
815 * Unfortunately, the inputs are laid out for PLN and not LINE+MAC so
816 * we have to split into SIMD8 pieces. For gen4 (!has_pln), the
817 * coordinate registers are laid out differently so we leave it as a
818 * SIMD16 instruction.
820 assert(inst
->exec_size
== 8 || inst
->exec_size
== 16);
821 assert(inst
->group
% 16 == 0);
823 brw_push_insn_state(p
);
824 brw_set_default_exec_size(p
, BRW_EXECUTE_8
);
826 /* Thanks to two accumulators, we can emit all the LINEs and then all
827 * the MACs. This improves parallelism a bit.
829 for (unsigned g
= 0; g
< inst
->exec_size
/ 8; g
++) {
830 brw_inst
*line
= brw_LINE(p
, brw_null_reg(), interp
,
831 offset(delta_x
, g
* 2));
832 brw_inst_set_group(devinfo
, line
, inst
->group
+ g
* 8);
834 /* LINE writes the accumulator automatically on gen4-5. On Sandy
835 * Bridge and later, we have to explicitly enable it.
837 if (devinfo
->gen
>= 6)
838 brw_inst_set_acc_wr_control(p
->devinfo
, line
, true);
840 /* brw_set_default_saturate() is called before emitting
841 * instructions, so the saturate bit is set in each instruction,
842 * so we need to unset it on the LINE instructions.
844 brw_inst_set_saturate(p
->devinfo
, line
, false);
847 for (unsigned g
= 0; g
< inst
->exec_size
/ 8; g
++) {
848 brw_inst
*mac
= brw_MAC(p
, offset(dst
, g
), suboffset(interp
, 1),
849 offset(delta_x
, g
* 2 + 1));
850 brw_inst_set_group(devinfo
, mac
, inst
->group
+ g
* 8);
851 brw_inst_set_cond_modifier(p
->devinfo
, mac
, inst
->conditional_mod
);
854 brw_pop_insn_state(p
);
858 brw_PLN(p
, dst
, interp
, delta_x
);
863 i
[0] = brw_LINE(p
, brw_null_reg(), interp
, delta_x
);
864 i
[1] = brw_MAC(p
, dst
, suboffset(interp
, 1), delta_y
);
866 brw_inst_set_cond_modifier(p
->devinfo
, i
[1], inst
->conditional_mod
);
868 /* brw_set_default_saturate() is called before emitting instructions, so
869 * the saturate bit is set in each instruction, so we need to unset it on
870 * the first instruction.
872 brw_inst_set_saturate(p
->devinfo
, i
[0], false);
879 fs_generator::generate_get_buffer_size(fs_inst
*inst
,
882 struct brw_reg surf_index
)
884 assert(devinfo
->gen
>= 7);
885 assert(surf_index
.file
== BRW_IMMEDIATE_VALUE
);
890 switch (inst
->exec_size
) {
892 simd_mode
= BRW_SAMPLER_SIMD_MODE_SIMD8
;
895 simd_mode
= BRW_SAMPLER_SIMD_MODE_SIMD16
;
898 unreachable("Invalid width for texture instruction");
901 if (simd_mode
== BRW_SAMPLER_SIMD_MODE_SIMD16
) {
907 retype(dst
, BRW_REGISTER_TYPE_UW
),
912 GEN5_SAMPLER_MESSAGE_SAMPLE_RESINFO
,
913 rlen
, /* response length */
915 inst
->header_size
> 0,
917 BRW_SAMPLER_RETURN_FORMAT_SINT32
);
921 fs_generator::generate_tex(fs_inst
*inst
, struct brw_reg dst
,
922 struct brw_reg surface_index
,
923 struct brw_reg sampler_index
)
925 assert(devinfo
->gen
< 7);
926 assert(inst
->size_written
% REG_SIZE
== 0);
929 uint32_t return_format
;
931 /* Sampler EOT message of less than the dispatch width would kill the
932 * thread prematurely.
934 assert(!inst
->eot
|| inst
->exec_size
== dispatch_width
);
937 case BRW_REGISTER_TYPE_D
:
938 return_format
= BRW_SAMPLER_RETURN_FORMAT_SINT32
;
940 case BRW_REGISTER_TYPE_UD
:
941 return_format
= BRW_SAMPLER_RETURN_FORMAT_UINT32
;
944 return_format
= BRW_SAMPLER_RETURN_FORMAT_FLOAT32
;
948 /* Stomp the resinfo output type to UINT32. On gens 4-5, the output type
949 * is set as part of the message descriptor. On gen4, the PRM seems to
950 * allow UINT32 and FLOAT32 (i965 PRM, Vol. 4 Section 4.8.1.1), but on
951 * later gens UINT32 is required. Once you hit Sandy Bridge, the bit is
952 * gone from the message descriptor entirely and you just get UINT32 all
953 * the time regasrdless. Since we can really only do non-UINT32 on gen4,
954 * just stomp it to UINT32 all the time.
956 if (inst
->opcode
== SHADER_OPCODE_TXS
)
957 return_format
= BRW_SAMPLER_RETURN_FORMAT_UINT32
;
959 switch (inst
->exec_size
) {
961 simd_mode
= BRW_SAMPLER_SIMD_MODE_SIMD8
;
964 simd_mode
= BRW_SAMPLER_SIMD_MODE_SIMD16
;
967 unreachable("Invalid width for texture instruction");
970 if (devinfo
->gen
>= 5) {
971 switch (inst
->opcode
) {
972 case SHADER_OPCODE_TEX
:
973 if (inst
->shadow_compare
) {
974 msg_type
= GEN5_SAMPLER_MESSAGE_SAMPLE_COMPARE
;
976 msg_type
= GEN5_SAMPLER_MESSAGE_SAMPLE
;
980 if (inst
->shadow_compare
) {
981 msg_type
= GEN5_SAMPLER_MESSAGE_SAMPLE_BIAS_COMPARE
;
983 msg_type
= GEN5_SAMPLER_MESSAGE_SAMPLE_BIAS
;
986 case SHADER_OPCODE_TXL
:
987 if (inst
->shadow_compare
) {
988 msg_type
= GEN5_SAMPLER_MESSAGE_SAMPLE_LOD_COMPARE
;
990 msg_type
= GEN5_SAMPLER_MESSAGE_SAMPLE_LOD
;
993 case SHADER_OPCODE_TXS
:
994 msg_type
= GEN5_SAMPLER_MESSAGE_SAMPLE_RESINFO
;
996 case SHADER_OPCODE_TXD
:
997 assert(!inst
->shadow_compare
);
998 msg_type
= GEN5_SAMPLER_MESSAGE_SAMPLE_DERIVS
;
1000 case SHADER_OPCODE_TXF
:
1001 msg_type
= GEN5_SAMPLER_MESSAGE_SAMPLE_LD
;
1003 case SHADER_OPCODE_TXF_CMS
:
1004 msg_type
= GEN5_SAMPLER_MESSAGE_SAMPLE_LD
;
1006 case SHADER_OPCODE_LOD
:
1007 msg_type
= GEN5_SAMPLER_MESSAGE_LOD
;
1009 case SHADER_OPCODE_TG4
:
1010 assert(devinfo
->gen
== 6);
1011 assert(!inst
->shadow_compare
);
1012 msg_type
= GEN7_SAMPLER_MESSAGE_SAMPLE_GATHER4
;
1014 case SHADER_OPCODE_SAMPLEINFO
:
1015 msg_type
= GEN6_SAMPLER_MESSAGE_SAMPLE_SAMPLEINFO
;
1018 unreachable("not reached");
1021 switch (inst
->opcode
) {
1022 case SHADER_OPCODE_TEX
:
1023 /* Note that G45 and older determines shadow compare and dispatch width
1024 * from message length for most messages.
1026 if (inst
->exec_size
== 8) {
1027 msg_type
= BRW_SAMPLER_MESSAGE_SIMD8_SAMPLE
;
1028 if (inst
->shadow_compare
) {
1029 assert(inst
->mlen
== 6);
1031 assert(inst
->mlen
<= 4);
1034 if (inst
->shadow_compare
) {
1035 msg_type
= BRW_SAMPLER_MESSAGE_SIMD16_SAMPLE_COMPARE
;
1036 assert(inst
->mlen
== 9);
1038 msg_type
= BRW_SAMPLER_MESSAGE_SIMD16_SAMPLE
;
1039 assert(inst
->mlen
<= 7 && inst
->mlen
% 2 == 1);
1044 if (inst
->shadow_compare
) {
1045 assert(inst
->exec_size
== 8);
1046 assert(inst
->mlen
== 6);
1047 msg_type
= BRW_SAMPLER_MESSAGE_SIMD8_SAMPLE_BIAS_COMPARE
;
1049 assert(inst
->mlen
== 9);
1050 msg_type
= BRW_SAMPLER_MESSAGE_SIMD16_SAMPLE_BIAS
;
1051 simd_mode
= BRW_SAMPLER_SIMD_MODE_SIMD16
;
1054 case SHADER_OPCODE_TXL
:
1055 if (inst
->shadow_compare
) {
1056 assert(inst
->exec_size
== 8);
1057 assert(inst
->mlen
== 6);
1058 msg_type
= BRW_SAMPLER_MESSAGE_SIMD8_SAMPLE_LOD_COMPARE
;
1060 assert(inst
->mlen
== 9);
1061 msg_type
= BRW_SAMPLER_MESSAGE_SIMD16_SAMPLE_LOD
;
1062 simd_mode
= BRW_SAMPLER_SIMD_MODE_SIMD16
;
1065 case SHADER_OPCODE_TXD
:
1066 /* There is no sample_d_c message; comparisons are done manually */
1067 assert(inst
->exec_size
== 8);
1068 assert(inst
->mlen
== 7 || inst
->mlen
== 10);
1069 msg_type
= BRW_SAMPLER_MESSAGE_SIMD8_SAMPLE_GRADIENTS
;
1071 case SHADER_OPCODE_TXF
:
1072 assert(inst
->mlen
<= 9 && inst
->mlen
% 2 == 1);
1073 msg_type
= BRW_SAMPLER_MESSAGE_SIMD16_LD
;
1074 simd_mode
= BRW_SAMPLER_SIMD_MODE_SIMD16
;
1076 case SHADER_OPCODE_TXS
:
1077 assert(inst
->mlen
== 3);
1078 msg_type
= BRW_SAMPLER_MESSAGE_SIMD16_RESINFO
;
1079 simd_mode
= BRW_SAMPLER_SIMD_MODE_SIMD16
;
1082 unreachable("not reached");
1085 assert(msg_type
!= -1);
1087 if (simd_mode
== BRW_SAMPLER_SIMD_MODE_SIMD16
) {
1091 assert(sampler_index
.type
== BRW_REGISTER_TYPE_UD
);
1093 /* Load the message header if present. If there's a texture offset,
1094 * we need to set it up explicitly and load the offset bitfield.
1095 * Otherwise, we can use an implied move from g0 to the first message reg.
1097 struct brw_reg src
= brw_null_reg();
1098 if (inst
->header_size
!= 0) {
1099 if (devinfo
->gen
< 6 && !inst
->offset
) {
1100 /* Set up an implied move from g0 to the MRF. */
1101 src
= retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_UW
);
1103 assert(inst
->base_mrf
!= -1);
1104 struct brw_reg header_reg
= brw_message_reg(inst
->base_mrf
);
1106 brw_push_insn_state(p
);
1107 brw_set_default_exec_size(p
, BRW_EXECUTE_8
);
1108 brw_set_default_mask_control(p
, BRW_MASK_DISABLE
);
1109 brw_set_default_compression_control(p
, BRW_COMPRESSION_NONE
);
1110 /* Explicitly set up the message header by copying g0 to the MRF. */
1111 brw_MOV(p
, header_reg
, brw_vec8_grf(0, 0));
1113 brw_set_default_exec_size(p
, BRW_EXECUTE_1
);
1115 /* Set the offset bits in DWord 2. */
1116 brw_MOV(p
, get_element_ud(header_reg
, 2),
1117 brw_imm_ud(inst
->offset
));
1120 brw_pop_insn_state(p
);
1124 uint32_t base_binding_table_index
;
1125 switch (inst
->opcode
) {
1126 case SHADER_OPCODE_TG4
:
1127 base_binding_table_index
= prog_data
->binding_table
.gather_texture_start
;
1130 base_binding_table_index
= prog_data
->binding_table
.texture_start
;
1134 assert(surface_index
.file
== BRW_IMMEDIATE_VALUE
);
1135 assert(sampler_index
.file
== BRW_IMMEDIATE_VALUE
);
1138 retype(dst
, BRW_REGISTER_TYPE_UW
),
1141 surface_index
.ud
+ base_binding_table_index
,
1142 sampler_index
.ud
% 16,
1144 inst
->size_written
/ REG_SIZE
,
1146 inst
->header_size
!= 0,
1152 /* For OPCODE_DDX and OPCODE_DDY, per channel of output we've got input
1155 * arg0: ss0.tl ss0.tr ss0.bl ss0.br ss1.tl ss1.tr ss1.bl ss1.br
1157 * Ideally, we want to produce:
1160 * dst: (ss0.tr - ss0.tl) (ss0.tl - ss0.bl)
1161 * (ss0.tr - ss0.tl) (ss0.tr - ss0.br)
1162 * (ss0.br - ss0.bl) (ss0.tl - ss0.bl)
1163 * (ss0.br - ss0.bl) (ss0.tr - ss0.br)
1164 * (ss1.tr - ss1.tl) (ss1.tl - ss1.bl)
1165 * (ss1.tr - ss1.tl) (ss1.tr - ss1.br)
1166 * (ss1.br - ss1.bl) (ss1.tl - ss1.bl)
1167 * (ss1.br - ss1.bl) (ss1.tr - ss1.br)
1169 * and add another set of two more subspans if in 16-pixel dispatch mode.
1171 * For DDX, it ends up being easy: width = 2, horiz=0 gets us the same result
1172 * for each pair, and vertstride = 2 jumps us 2 elements after processing a
1173 * pair. But the ideal approximation may impose a huge performance cost on
1174 * sample_d. On at least Haswell, sample_d instruction does some
1175 * optimizations if the same LOD is used for all pixels in the subspan.
1177 * For DDY, we need to use ALIGN16 mode since it's capable of doing the
1178 * appropriate swizzling.
1181 fs_generator::generate_ddx(const fs_inst
*inst
,
1182 struct brw_reg dst
, struct brw_reg src
)
1184 unsigned vstride
, width
;
1186 if (devinfo
->gen
>= 8) {
1187 if (inst
->opcode
== FS_OPCODE_DDX_FINE
) {
1188 /* produce accurate derivatives */
1189 vstride
= BRW_VERTICAL_STRIDE_2
;
1190 width
= BRW_WIDTH_2
;
1192 /* replicate the derivative at the top-left pixel to other pixels */
1193 vstride
= BRW_VERTICAL_STRIDE_4
;
1194 width
= BRW_WIDTH_4
;
1197 struct brw_reg src0
= byte_offset(src
, type_sz(src
.type
));;
1198 struct brw_reg src1
= src
;
1200 src0
.vstride
= vstride
;
1202 src0
.hstride
= BRW_HORIZONTAL_STRIDE_0
;
1203 src1
.vstride
= vstride
;
1205 src1
.hstride
= BRW_HORIZONTAL_STRIDE_0
;
1207 brw_ADD(p
, dst
, src0
, negate(src1
));
1209 /* On Haswell and earlier, the region used above appears to not work
1210 * correctly for compressed instructions. At least on Haswell and
1211 * Iron Lake, compressed ALIGN16 instructions do work. Since we
1212 * would have to split to SIMD8 no matter which method we choose, we
1213 * may as well use ALIGN16 on all platforms gen7 and earlier.
1215 struct brw_reg src0
= stride(src
, 4, 4, 1);
1216 struct brw_reg src1
= stride(src
, 4, 4, 1);
1217 if (inst
->opcode
== FS_OPCODE_DDX_FINE
) {
1218 src0
.swizzle
= BRW_SWIZZLE_XXZZ
;
1219 src1
.swizzle
= BRW_SWIZZLE_YYWW
;
1221 src0
.swizzle
= BRW_SWIZZLE_XXXX
;
1222 src1
.swizzle
= BRW_SWIZZLE_YYYY
;
1225 brw_push_insn_state(p
);
1226 brw_set_default_access_mode(p
, BRW_ALIGN_16
);
1227 brw_ADD(p
, dst
, negate(src0
), src1
);
1228 brw_pop_insn_state(p
);
1232 /* The negate_value boolean is used to negate the derivative computation for
1233 * FBOs, since they place the origin at the upper left instead of the lower
1237 fs_generator::generate_ddy(const fs_inst
*inst
,
1238 struct brw_reg dst
, struct brw_reg src
)
1240 const uint32_t type_size
= type_sz(src
.type
);
1242 if (inst
->opcode
== FS_OPCODE_DDY_FINE
) {
1243 /* produce accurate derivatives.
1245 * From the Broadwell PRM, Volume 7 (3D-Media-GPGPU)
1246 * "Register Region Restrictions", Section "1. Special Restrictions":
1248 * "In Align16 mode, the channel selects and channel enables apply to
1249 * a pair of half-floats, because these parameters are defined for
1250 * DWord elements ONLY. This is applicable when both source and
1251 * destination are half-floats."
1253 * So for half-float operations we use the Gen11+ Align1 path. CHV
1254 * inherits its FP16 hardware from SKL, so it is not affected.
1256 if (devinfo
->gen
>= 11 ||
1257 (devinfo
->is_broadwell
&& src
.type
== BRW_REGISTER_TYPE_HF
)) {
1258 src
= stride(src
, 0, 2, 1);
1260 brw_push_insn_state(p
);
1261 brw_set_default_exec_size(p
, BRW_EXECUTE_4
);
1262 for (uint32_t g
= 0; g
< inst
->exec_size
; g
+= 4) {
1263 brw_set_default_group(p
, inst
->group
+ g
);
1264 brw_ADD(p
, byte_offset(dst
, g
* type_size
),
1265 negate(byte_offset(src
, g
* type_size
)),
1266 byte_offset(src
, (g
+ 2) * type_size
));
1268 brw_pop_insn_state(p
);
1270 struct brw_reg src0
= stride(src
, 4, 4, 1);
1271 struct brw_reg src1
= stride(src
, 4, 4, 1);
1272 src0
.swizzle
= BRW_SWIZZLE_XYXY
;
1273 src1
.swizzle
= BRW_SWIZZLE_ZWZW
;
1275 brw_push_insn_state(p
);
1276 brw_set_default_access_mode(p
, BRW_ALIGN_16
);
1277 brw_ADD(p
, dst
, negate(src0
), src1
);
1278 brw_pop_insn_state(p
);
1281 /* replicate the derivative at the top-left pixel to other pixels */
1282 if (devinfo
->gen
>= 8) {
1283 struct brw_reg src0
= byte_offset(stride(src
, 4, 4, 0), 0 * type_size
);
1284 struct brw_reg src1
= byte_offset(stride(src
, 4, 4, 0), 2 * type_size
);
1286 brw_ADD(p
, dst
, negate(src0
), src1
);
1288 /* On Haswell and earlier, the region used above appears to not work
1289 * correctly for compressed instructions. At least on Haswell and
1290 * Iron Lake, compressed ALIGN16 instructions do work. Since we
1291 * would have to split to SIMD8 no matter which method we choose, we
1292 * may as well use ALIGN16 on all platforms gen7 and earlier.
1294 struct brw_reg src0
= stride(src
, 4, 4, 1);
1295 struct brw_reg src1
= stride(src
, 4, 4, 1);
1296 src0
.swizzle
= BRW_SWIZZLE_XXXX
;
1297 src1
.swizzle
= BRW_SWIZZLE_ZZZZ
;
1299 brw_push_insn_state(p
);
1300 brw_set_default_access_mode(p
, BRW_ALIGN_16
);
1301 brw_ADD(p
, dst
, negate(src0
), src1
);
1302 brw_pop_insn_state(p
);
1308 fs_generator::generate_discard_jump(fs_inst
*)
1310 assert(devinfo
->gen
>= 6);
1312 /* This HALT will be patched up at FB write time to point UIP at the end of
1313 * the program, and at brw_uip_jip() JIP will be set to the end of the
1314 * current block (or the program).
1316 this->discard_halt_patches
.push_tail(new(mem_ctx
) ip_record(p
->nr_insn
));
1321 fs_generator::generate_scratch_write(fs_inst
*inst
, struct brw_reg src
)
1323 /* The 32-wide messages only respect the first 16-wide half of the channel
1324 * enable signals which are replicated identically for the second group of
1325 * 16 channels, so we cannot use them unless the write is marked
1326 * force_writemask_all.
1328 const unsigned lower_size
= inst
->force_writemask_all
? inst
->exec_size
:
1329 MIN2(16, inst
->exec_size
);
1330 const unsigned block_size
= 4 * lower_size
/ REG_SIZE
;
1331 assert(inst
->mlen
!= 0);
1333 brw_push_insn_state(p
);
1334 brw_set_default_exec_size(p
, cvt(lower_size
) - 1);
1335 brw_set_default_compression(p
, lower_size
> 8);
1337 for (unsigned i
= 0; i
< inst
->exec_size
/ lower_size
; i
++) {
1338 brw_set_default_group(p
, inst
->group
+ lower_size
* i
);
1340 brw_MOV(p
, brw_uvec_mrf(lower_size
, inst
->base_mrf
+ 1, 0),
1341 retype(offset(src
, block_size
* i
), BRW_REGISTER_TYPE_UD
));
1343 brw_oword_block_write_scratch(p
, brw_message_reg(inst
->base_mrf
),
1345 inst
->offset
+ block_size
* REG_SIZE
* i
);
1348 brw_pop_insn_state(p
);
1352 fs_generator::generate_scratch_read(fs_inst
*inst
, struct brw_reg dst
)
1354 assert(inst
->exec_size
<= 16 || inst
->force_writemask_all
);
1355 assert(inst
->mlen
!= 0);
1357 brw_oword_block_read_scratch(p
, dst
, brw_message_reg(inst
->base_mrf
),
1358 inst
->exec_size
/ 8, inst
->offset
);
1362 fs_generator::generate_scratch_read_gen7(fs_inst
*inst
, struct brw_reg dst
)
1364 assert(inst
->exec_size
<= 16 || inst
->force_writemask_all
);
1366 gen7_block_read_scratch(p
, dst
, inst
->exec_size
/ 8, inst
->offset
);
1370 fs_generator::generate_uniform_pull_constant_load(fs_inst
*inst
,
1372 struct brw_reg index
,
1373 struct brw_reg offset
)
1375 assert(type_sz(dst
.type
) == 4);
1376 assert(inst
->mlen
!= 0);
1378 assert(index
.file
== BRW_IMMEDIATE_VALUE
&&
1379 index
.type
== BRW_REGISTER_TYPE_UD
);
1380 uint32_t surf_index
= index
.ud
;
1382 assert(offset
.file
== BRW_IMMEDIATE_VALUE
&&
1383 offset
.type
== BRW_REGISTER_TYPE_UD
);
1384 uint32_t read_offset
= offset
.ud
;
1386 brw_oword_block_read(p
, dst
, brw_message_reg(inst
->base_mrf
),
1387 read_offset
, surf_index
);
1391 fs_generator::generate_uniform_pull_constant_load_gen7(fs_inst
*inst
,
1393 struct brw_reg index
,
1394 struct brw_reg payload
)
1396 assert(index
.type
== BRW_REGISTER_TYPE_UD
);
1397 assert(payload
.file
== BRW_GENERAL_REGISTER_FILE
);
1398 assert(type_sz(dst
.type
) == 4);
1400 if (index
.file
== BRW_IMMEDIATE_VALUE
) {
1401 const uint32_t surf_index
= index
.ud
;
1403 brw_push_insn_state(p
);
1404 brw_set_default_mask_control(p
, BRW_MASK_DISABLE
);
1405 brw_inst
*send
= brw_next_insn(p
, BRW_OPCODE_SEND
);
1406 brw_pop_insn_state(p
);
1408 brw_inst_set_sfid(devinfo
, send
, GEN6_SFID_DATAPORT_CONSTANT_CACHE
);
1409 brw_set_dest(p
, send
, retype(dst
, BRW_REGISTER_TYPE_UD
));
1410 brw_set_src0(p
, send
, retype(payload
, BRW_REGISTER_TYPE_UD
));
1411 brw_set_desc(p
, send
,
1412 brw_message_desc(devinfo
, 1, DIV_ROUND_UP(inst
->size_written
,
1414 brw_dp_read_desc(devinfo
, surf_index
,
1415 BRW_DATAPORT_OWORD_BLOCK_DWORDS(inst
->exec_size
),
1416 GEN7_DATAPORT_DC_OWORD_BLOCK_READ
,
1417 BRW_DATAPORT_READ_TARGET_DATA_CACHE
));
1420 struct brw_reg addr
= vec1(retype(brw_address_reg(0), BRW_REGISTER_TYPE_UD
));
1422 brw_push_insn_state(p
);
1423 brw_set_default_mask_control(p
, BRW_MASK_DISABLE
);
1425 /* a0.0 = surf_index & 0xff */
1426 brw_inst
*insn_and
= brw_next_insn(p
, BRW_OPCODE_AND
);
1427 brw_inst_set_exec_size(p
->devinfo
, insn_and
, BRW_EXECUTE_1
);
1428 brw_set_dest(p
, insn_and
, addr
);
1429 brw_set_src0(p
, insn_and
, vec1(retype(index
, BRW_REGISTER_TYPE_UD
)));
1430 brw_set_src1(p
, insn_and
, brw_imm_ud(0x0ff));
1432 /* dst = send(payload, a0.0 | <descriptor>) */
1433 brw_send_indirect_message(
1434 p
, GEN6_SFID_DATAPORT_CONSTANT_CACHE
,
1435 retype(dst
, BRW_REGISTER_TYPE_UD
),
1436 retype(payload
, BRW_REGISTER_TYPE_UD
), addr
,
1437 brw_message_desc(devinfo
, 1,
1438 DIV_ROUND_UP(inst
->size_written
, REG_SIZE
), true) |
1439 brw_dp_read_desc(devinfo
, 0 /* surface */,
1440 BRW_DATAPORT_OWORD_BLOCK_DWORDS(inst
->exec_size
),
1441 GEN7_DATAPORT_DC_OWORD_BLOCK_READ
,
1442 BRW_DATAPORT_READ_TARGET_DATA_CACHE
),
1445 brw_pop_insn_state(p
);
1450 fs_generator::generate_varying_pull_constant_load_gen4(fs_inst
*inst
,
1452 struct brw_reg index
)
1454 assert(devinfo
->gen
< 7); /* Should use the gen7 variant. */
1455 assert(inst
->header_size
!= 0);
1458 assert(index
.file
== BRW_IMMEDIATE_VALUE
&&
1459 index
.type
== BRW_REGISTER_TYPE_UD
);
1460 uint32_t surf_index
= index
.ud
;
1462 uint32_t simd_mode
, rlen
, msg_type
;
1463 if (inst
->exec_size
== 16) {
1464 simd_mode
= BRW_SAMPLER_SIMD_MODE_SIMD16
;
1467 assert(inst
->exec_size
== 8);
1468 simd_mode
= BRW_SAMPLER_SIMD_MODE_SIMD8
;
1472 if (devinfo
->gen
>= 5)
1473 msg_type
= GEN5_SAMPLER_MESSAGE_SAMPLE_LD
;
1475 /* We always use the SIMD16 message so that we only have to load U, and
1478 msg_type
= BRW_SAMPLER_MESSAGE_SIMD16_LD
;
1479 assert(inst
->mlen
== 3);
1480 assert(inst
->size_written
== 8 * REG_SIZE
);
1482 simd_mode
= BRW_SAMPLER_SIMD_MODE_SIMD16
;
1485 struct brw_reg header
= brw_vec8_grf(0, 0);
1486 gen6_resolve_implied_move(p
, &header
, inst
->base_mrf
);
1488 brw_inst
*send
= brw_next_insn(p
, BRW_OPCODE_SEND
);
1489 brw_inst_set_compression(devinfo
, send
, false);
1490 brw_inst_set_sfid(devinfo
, send
, BRW_SFID_SAMPLER
);
1491 brw_set_dest(p
, send
, retype(dst
, BRW_REGISTER_TYPE_UW
));
1492 brw_set_src0(p
, send
, header
);
1493 if (devinfo
->gen
< 6)
1494 brw_inst_set_base_mrf(p
->devinfo
, send
, inst
->base_mrf
);
1496 /* Our surface is set up as floats, regardless of what actual data is
1499 uint32_t return_format
= BRW_SAMPLER_RETURN_FORMAT_FLOAT32
;
1500 brw_set_desc(p
, send
,
1501 brw_message_desc(devinfo
, inst
->mlen
, rlen
, inst
->header_size
) |
1502 brw_sampler_desc(devinfo
, surf_index
,
1503 0, /* sampler (unused) */
1504 msg_type
, simd_mode
, return_format
));
1508 fs_generator::generate_pixel_interpolator_query(fs_inst
*inst
,
1511 struct brw_reg msg_data
,
1514 const bool has_payload
= inst
->src
[0].file
!= BAD_FILE
;
1515 assert(msg_data
.type
== BRW_REGISTER_TYPE_UD
);
1516 assert(inst
->size_written
% REG_SIZE
== 0);
1518 brw_pixel_interpolator_query(p
,
1519 retype(dst
, BRW_REGISTER_TYPE_UW
),
1520 /* If we don't have a payload, what we send doesn't matter */
1521 has_payload
? src
: brw_vec8_grf(0, 0),
1522 inst
->pi_noperspective
,
1525 has_payload
? 2 * inst
->exec_size
/ 8 : 1,
1526 inst
->size_written
/ REG_SIZE
);
1529 /* Sets vstride=1, width=4, hstride=0 of register src1 during
1530 * the ADD instruction.
1533 fs_generator::generate_set_sample_id(fs_inst
*inst
,
1535 struct brw_reg src0
,
1536 struct brw_reg src1
)
1538 assert(dst
.type
== BRW_REGISTER_TYPE_D
||
1539 dst
.type
== BRW_REGISTER_TYPE_UD
);
1540 assert(src0
.type
== BRW_REGISTER_TYPE_D
||
1541 src0
.type
== BRW_REGISTER_TYPE_UD
);
1543 const struct brw_reg reg
= stride(src1
, 1, 4, 0);
1544 const unsigned lower_size
= MIN2(inst
->exec_size
,
1545 devinfo
->gen
>= 8 ? 16 : 8);
1547 for (unsigned i
= 0; i
< inst
->exec_size
/ lower_size
; i
++) {
1548 brw_inst
*insn
= brw_ADD(p
, offset(dst
, i
* lower_size
/ 8),
1549 offset(src0
, (src0
.vstride
== 0 ? 0 : (1 << (src0
.vstride
- 1)) *
1550 (i
* lower_size
/ (1 << src0
.width
))) *
1551 type_sz(src0
.type
) / REG_SIZE
),
1552 suboffset(reg
, i
* lower_size
/ 4));
1553 brw_inst_set_exec_size(devinfo
, insn
, cvt(lower_size
) - 1);
1554 brw_inst_set_group(devinfo
, insn
, inst
->group
+ lower_size
* i
);
1555 brw_inst_set_compression(devinfo
, insn
, lower_size
> 8);
1560 fs_generator::generate_pack_half_2x16_split(fs_inst
*,
1565 assert(devinfo
->gen
>= 7);
1566 assert(dst
.type
== BRW_REGISTER_TYPE_UD
);
1567 assert(x
.type
== BRW_REGISTER_TYPE_F
);
1568 assert(y
.type
== BRW_REGISTER_TYPE_F
);
1570 /* From the Ivybridge PRM, Vol4, Part3, Section 6.27 f32to16:
1572 * Because this instruction does not have a 16-bit floating-point type,
1573 * the destination data type must be Word (W).
1575 * The destination must be DWord-aligned and specify a horizontal stride
1576 * (HorzStride) of 2. The 16-bit result is stored in the lower word of
1577 * each destination channel and the upper word is not modified.
1579 struct brw_reg dst_w
= spread(retype(dst
, BRW_REGISTER_TYPE_W
), 2);
1581 /* Give each 32-bit channel of dst the form below, where "." means
1585 brw_F32TO16(p
, dst_w
, y
);
1590 brw_SHL(p
, dst
, dst
, brw_imm_ud(16u));
1592 /* And, finally the form of packHalf2x16's output:
1595 brw_F32TO16(p
, dst_w
, x
);
1599 fs_generator::generate_shader_time_add(fs_inst
*,
1600 struct brw_reg payload
,
1601 struct brw_reg offset
,
1602 struct brw_reg value
)
1604 assert(devinfo
->gen
>= 7);
1605 brw_push_insn_state(p
);
1606 brw_set_default_mask_control(p
, true);
1608 assert(payload
.file
== BRW_GENERAL_REGISTER_FILE
);
1609 struct brw_reg payload_offset
= retype(brw_vec1_grf(payload
.nr
, 0),
1611 struct brw_reg payload_value
= retype(brw_vec1_grf(payload
.nr
+ 1, 0),
1614 assert(offset
.file
== BRW_IMMEDIATE_VALUE
);
1615 if (value
.file
== BRW_GENERAL_REGISTER_FILE
) {
1616 value
.width
= BRW_WIDTH_1
;
1617 value
.hstride
= BRW_HORIZONTAL_STRIDE_0
;
1618 value
.vstride
= BRW_VERTICAL_STRIDE_0
;
1620 assert(value
.file
== BRW_IMMEDIATE_VALUE
);
1623 /* Trying to deal with setup of the params from the IR is crazy in the FS8
1624 * case, and we don't really care about squeezing every bit of performance
1625 * out of this path, so we just emit the MOVs from here.
1627 brw_MOV(p
, payload_offset
, offset
);
1628 brw_MOV(p
, payload_value
, value
);
1629 brw_shader_time_add(p
, payload
,
1630 prog_data
->binding_table
.shader_time_start
);
1631 brw_pop_insn_state(p
);
1635 fs_generator::enable_debug(const char *shader_name
)
1638 this->shader_name
= shader_name
;
1642 fs_generator::generate_code(const cfg_t
*cfg
, int dispatch_width
,
1643 struct brw_compile_stats
*stats
)
1645 /* align to 64 byte boundary. */
1646 while (p
->next_insn_offset
% 64)
1649 this->dispatch_width
= dispatch_width
;
1651 int start_offset
= p
->next_insn_offset
;
1652 int spill_count
= 0, fill_count
= 0;
1655 struct disasm_info
*disasm_info
= disasm_initialize(devinfo
, cfg
);
1657 foreach_block_and_inst (block
, fs_inst
, inst
, cfg
) {
1658 if (inst
->opcode
== SHADER_OPCODE_UNDEF
)
1661 struct brw_reg src
[4], dst
;
1662 unsigned int last_insn_offset
= p
->next_insn_offset
;
1663 bool multiple_instructions_emitted
= false;
1665 /* From the Broadwell PRM, Volume 7, "3D-Media-GPGPU", in the
1666 * "Register Region Restrictions" section: for BDW, SKL:
1668 * "A POW/FDIV operation must not be followed by an instruction
1669 * that requires two destination registers."
1671 * The documentation is often lacking annotations for Atom parts,
1672 * and empirically this affects CHV as well.
1674 if (devinfo
->gen
>= 8 &&
1675 devinfo
->gen
<= 9 &&
1677 brw_inst_opcode(devinfo
, brw_last_inst
) == BRW_OPCODE_MATH
&&
1678 brw_inst_math_function(devinfo
, brw_last_inst
) == BRW_MATH_FUNCTION_POW
&&
1679 inst
->dst
.component_size(inst
->exec_size
) > REG_SIZE
) {
1681 last_insn_offset
= p
->next_insn_offset
;
1684 if (unlikely(debug_flag
))
1685 disasm_annotate(disasm_info
, inst
, p
->next_insn_offset
);
1687 /* If the instruction writes to more than one register, it needs to be
1688 * explicitly marked as compressed on Gen <= 5. On Gen >= 6 the
1689 * hardware figures out by itself what the right compression mode is,
1690 * but we still need to know whether the instruction is compressed to
1691 * set up the source register regions appropriately.
1693 * XXX - This is wrong for instructions that write a single register but
1694 * read more than one which should strictly speaking be treated as
1695 * compressed. For instructions that don't write any registers it
1696 * relies on the destination being a null register of the correct
1697 * type and regioning so the instruction is considered compressed
1698 * or not accordingly.
1700 const bool compressed
=
1701 inst
->dst
.component_size(inst
->exec_size
) > REG_SIZE
;
1702 brw_set_default_compression(p
, compressed
);
1703 brw_set_default_group(p
, inst
->group
);
1705 for (unsigned int i
= 0; i
< inst
->sources
; i
++) {
1706 src
[i
] = brw_reg_from_fs_reg(devinfo
, inst
,
1707 &inst
->src
[i
], compressed
);
1708 /* The accumulator result appears to get used for the
1709 * conditional modifier generation. When negating a UD
1710 * value, there is a 33rd bit generated for the sign in the
1711 * accumulator value, so now you can't check, for example,
1712 * equality with a 32-bit value. See piglit fs-op-neg-uvec4.
1714 assert(!inst
->conditional_mod
||
1715 inst
->src
[i
].type
!= BRW_REGISTER_TYPE_UD
||
1716 !inst
->src
[i
].negate
);
1718 dst
= brw_reg_from_fs_reg(devinfo
, inst
,
1719 &inst
->dst
, compressed
);
1721 brw_set_default_access_mode(p
, BRW_ALIGN_1
);
1722 brw_set_default_predicate_control(p
, inst
->predicate
);
1723 brw_set_default_predicate_inverse(p
, inst
->predicate_inverse
);
1724 /* On gen7 and above, hardware automatically adds the group onto the
1725 * flag subregister number. On Sandy Bridge and older, we have to do it
1728 const unsigned flag_subreg
= inst
->flag_subreg
+
1729 (devinfo
->gen
>= 7 ? 0 : inst
->group
/ 16);
1730 brw_set_default_flag_reg(p
, flag_subreg
/ 2, flag_subreg
% 2);
1731 brw_set_default_saturate(p
, inst
->saturate
);
1732 brw_set_default_mask_control(p
, inst
->force_writemask_all
);
1733 brw_set_default_acc_write_control(p
, inst
->writes_accumulator
);
1735 unsigned exec_size
= inst
->exec_size
;
1736 if (devinfo
->gen
== 7 && !devinfo
->is_haswell
&&
1737 (get_exec_type_size(inst
) == 8 || type_sz(inst
->dst
.type
) == 8)) {
1741 brw_set_default_exec_size(p
, cvt(exec_size
) - 1);
1743 assert(inst
->force_writemask_all
|| inst
->exec_size
>= 4);
1744 assert(inst
->force_writemask_all
|| inst
->group
% inst
->exec_size
== 0);
1745 assert(inst
->base_mrf
+ inst
->mlen
<= BRW_MAX_MRF(devinfo
->gen
));
1746 assert(inst
->mlen
<= BRW_MAX_MSG_LENGTH
);
1748 switch (inst
->opcode
) {
1749 case BRW_OPCODE_MOV
:
1750 brw_MOV(p
, dst
, src
[0]);
1752 case BRW_OPCODE_ADD
:
1753 brw_ADD(p
, dst
, src
[0], src
[1]);
1755 case BRW_OPCODE_MUL
:
1756 brw_MUL(p
, dst
, src
[0], src
[1]);
1758 case BRW_OPCODE_AVG
:
1759 brw_AVG(p
, dst
, src
[0], src
[1]);
1761 case BRW_OPCODE_MACH
:
1762 brw_MACH(p
, dst
, src
[0], src
[1]);
1765 case BRW_OPCODE_LINE
:
1766 brw_LINE(p
, dst
, src
[0], src
[1]);
1769 case BRW_OPCODE_MAD
:
1770 assert(devinfo
->gen
>= 6);
1771 if (devinfo
->gen
< 10)
1772 brw_set_default_access_mode(p
, BRW_ALIGN_16
);
1773 brw_MAD(p
, dst
, src
[0], src
[1], src
[2]);
1776 case BRW_OPCODE_LRP
:
1777 assert(devinfo
->gen
>= 6 && devinfo
->gen
<= 10);
1778 if (devinfo
->gen
< 10)
1779 brw_set_default_access_mode(p
, BRW_ALIGN_16
);
1780 brw_LRP(p
, dst
, src
[0], src
[1], src
[2]);
1783 case BRW_OPCODE_FRC
:
1784 brw_FRC(p
, dst
, src
[0]);
1786 case BRW_OPCODE_RNDD
:
1787 brw_RNDD(p
, dst
, src
[0]);
1789 case BRW_OPCODE_RNDE
:
1790 brw_RNDE(p
, dst
, src
[0]);
1792 case BRW_OPCODE_RNDZ
:
1793 brw_RNDZ(p
, dst
, src
[0]);
1796 case BRW_OPCODE_AND
:
1797 brw_AND(p
, dst
, src
[0], src
[1]);
1800 brw_OR(p
, dst
, src
[0], src
[1]);
1802 case BRW_OPCODE_XOR
:
1803 brw_XOR(p
, dst
, src
[0], src
[1]);
1805 case BRW_OPCODE_NOT
:
1806 brw_NOT(p
, dst
, src
[0]);
1808 case BRW_OPCODE_ASR
:
1809 brw_ASR(p
, dst
, src
[0], src
[1]);
1811 case BRW_OPCODE_SHR
:
1812 brw_SHR(p
, dst
, src
[0], src
[1]);
1814 case BRW_OPCODE_SHL
:
1815 brw_SHL(p
, dst
, src
[0], src
[1]);
1817 case BRW_OPCODE_ROL
:
1818 assert(devinfo
->gen
>= 11);
1819 assert(src
[0].type
== dst
.type
);
1820 brw_ROL(p
, dst
, src
[0], src
[1]);
1822 case BRW_OPCODE_ROR
:
1823 assert(devinfo
->gen
>= 11);
1824 assert(src
[0].type
== dst
.type
);
1825 brw_ROR(p
, dst
, src
[0], src
[1]);
1827 case BRW_OPCODE_F32TO16
:
1828 assert(devinfo
->gen
>= 7);
1829 brw_F32TO16(p
, dst
, src
[0]);
1831 case BRW_OPCODE_F16TO32
:
1832 assert(devinfo
->gen
>= 7);
1833 brw_F16TO32(p
, dst
, src
[0]);
1835 case BRW_OPCODE_CMP
:
1836 if (inst
->exec_size
>= 16 && devinfo
->gen
== 7 && !devinfo
->is_haswell
&&
1837 dst
.file
== BRW_ARCHITECTURE_REGISTER_FILE
) {
1838 /* For unknown reasons the WaCMPInstFlagDepClearedEarly workaround
1839 * implemented in the compiler is not sufficient. Overriding the
1840 * type when the destination is the null register is necessary but
1841 * not sufficient by itself.
1843 assert(dst
.nr
== BRW_ARF_NULL
);
1844 dst
.type
= BRW_REGISTER_TYPE_D
;
1846 brw_CMP(p
, dst
, inst
->conditional_mod
, src
[0], src
[1]);
1848 case BRW_OPCODE_SEL
:
1849 brw_SEL(p
, dst
, src
[0], src
[1]);
1851 case BRW_OPCODE_CSEL
:
1852 assert(devinfo
->gen
>= 8);
1853 if (devinfo
->gen
< 10)
1854 brw_set_default_access_mode(p
, BRW_ALIGN_16
);
1855 brw_CSEL(p
, dst
, src
[0], src
[1], src
[2]);
1857 case BRW_OPCODE_BFREV
:
1858 assert(devinfo
->gen
>= 7);
1859 brw_BFREV(p
, retype(dst
, BRW_REGISTER_TYPE_UD
),
1860 retype(src
[0], BRW_REGISTER_TYPE_UD
));
1862 case BRW_OPCODE_FBH
:
1863 assert(devinfo
->gen
>= 7);
1864 brw_FBH(p
, retype(dst
, src
[0].type
), src
[0]);
1866 case BRW_OPCODE_FBL
:
1867 assert(devinfo
->gen
>= 7);
1868 brw_FBL(p
, retype(dst
, BRW_REGISTER_TYPE_UD
),
1869 retype(src
[0], BRW_REGISTER_TYPE_UD
));
1871 case BRW_OPCODE_LZD
:
1872 brw_LZD(p
, dst
, src
[0]);
1874 case BRW_OPCODE_CBIT
:
1875 assert(devinfo
->gen
>= 7);
1876 brw_CBIT(p
, retype(dst
, BRW_REGISTER_TYPE_UD
),
1877 retype(src
[0], BRW_REGISTER_TYPE_UD
));
1879 case BRW_OPCODE_ADDC
:
1880 assert(devinfo
->gen
>= 7);
1881 brw_ADDC(p
, dst
, src
[0], src
[1]);
1883 case BRW_OPCODE_SUBB
:
1884 assert(devinfo
->gen
>= 7);
1885 brw_SUBB(p
, dst
, src
[0], src
[1]);
1887 case BRW_OPCODE_MAC
:
1888 brw_MAC(p
, dst
, src
[0], src
[1]);
1891 case BRW_OPCODE_BFE
:
1892 assert(devinfo
->gen
>= 7);
1893 if (devinfo
->gen
< 10)
1894 brw_set_default_access_mode(p
, BRW_ALIGN_16
);
1895 brw_BFE(p
, dst
, src
[0], src
[1], src
[2]);
1898 case BRW_OPCODE_BFI1
:
1899 assert(devinfo
->gen
>= 7);
1900 brw_BFI1(p
, dst
, src
[0], src
[1]);
1902 case BRW_OPCODE_BFI2
:
1903 assert(devinfo
->gen
>= 7);
1904 if (devinfo
->gen
< 10)
1905 brw_set_default_access_mode(p
, BRW_ALIGN_16
);
1906 brw_BFI2(p
, dst
, src
[0], src
[1], src
[2]);
1910 if (inst
->src
[0].file
!= BAD_FILE
) {
1911 /* The instruction has an embedded compare (only allowed on gen6) */
1912 assert(devinfo
->gen
== 6);
1913 gen6_IF(p
, inst
->conditional_mod
, src
[0], src
[1]);
1915 brw_IF(p
, brw_get_default_exec_size(p
));
1919 case BRW_OPCODE_ELSE
:
1922 case BRW_OPCODE_ENDIF
:
1927 brw_DO(p
, brw_get_default_exec_size(p
));
1930 case BRW_OPCODE_BREAK
:
1933 case BRW_OPCODE_CONTINUE
:
1937 case BRW_OPCODE_WHILE
:
1942 case SHADER_OPCODE_RCP
:
1943 case SHADER_OPCODE_RSQ
:
1944 case SHADER_OPCODE_SQRT
:
1945 case SHADER_OPCODE_EXP2
:
1946 case SHADER_OPCODE_LOG2
:
1947 case SHADER_OPCODE_SIN
:
1948 case SHADER_OPCODE_COS
:
1949 assert(inst
->conditional_mod
== BRW_CONDITIONAL_NONE
);
1950 if (devinfo
->gen
>= 6) {
1951 assert(inst
->mlen
== 0);
1952 assert(devinfo
->gen
>= 7 || inst
->exec_size
== 8);
1953 gen6_math(p
, dst
, brw_math_function(inst
->opcode
),
1954 src
[0], brw_null_reg());
1956 assert(inst
->mlen
>= 1);
1957 assert(devinfo
->gen
== 5 || devinfo
->is_g4x
|| inst
->exec_size
== 8);
1959 brw_math_function(inst
->opcode
),
1960 inst
->base_mrf
, src
[0],
1961 BRW_MATH_PRECISION_FULL
);
1964 case SHADER_OPCODE_INT_QUOTIENT
:
1965 case SHADER_OPCODE_INT_REMAINDER
:
1966 case SHADER_OPCODE_POW
:
1967 assert(inst
->conditional_mod
== BRW_CONDITIONAL_NONE
);
1968 if (devinfo
->gen
>= 6) {
1969 assert(inst
->mlen
== 0);
1970 assert((devinfo
->gen
>= 7 && inst
->opcode
== SHADER_OPCODE_POW
) ||
1971 inst
->exec_size
== 8);
1972 gen6_math(p
, dst
, brw_math_function(inst
->opcode
), src
[0], src
[1]);
1974 assert(inst
->mlen
>= 1);
1975 assert(inst
->exec_size
== 8);
1976 gen4_math(p
, dst
, brw_math_function(inst
->opcode
),
1977 inst
->base_mrf
, src
[0],
1978 BRW_MATH_PRECISION_FULL
);
1981 case FS_OPCODE_LINTERP
:
1982 multiple_instructions_emitted
= generate_linterp(inst
, dst
, src
);
1984 case FS_OPCODE_PIXEL_X
:
1985 assert(src
[0].type
== BRW_REGISTER_TYPE_UW
);
1986 src
[0].subnr
= 0 * type_sz(src
[0].type
);
1987 brw_MOV(p
, dst
, stride(src
[0], 8, 4, 1));
1989 case FS_OPCODE_PIXEL_Y
:
1990 assert(src
[0].type
== BRW_REGISTER_TYPE_UW
);
1991 src
[0].subnr
= 4 * type_sz(src
[0].type
);
1992 brw_MOV(p
, dst
, stride(src
[0], 8, 4, 1));
1995 case SHADER_OPCODE_SEND
:
1996 generate_send(inst
, dst
, src
[0], src
[1], src
[2],
1997 inst
->ex_mlen
> 0 ? src
[3] : brw_null_reg());
2000 case SHADER_OPCODE_GET_BUFFER_SIZE
:
2001 generate_get_buffer_size(inst
, dst
, src
[0], src
[1]);
2003 case SHADER_OPCODE_TEX
:
2005 case SHADER_OPCODE_TXD
:
2006 case SHADER_OPCODE_TXF
:
2007 case SHADER_OPCODE_TXF_CMS
:
2008 case SHADER_OPCODE_TXL
:
2009 case SHADER_OPCODE_TXS
:
2010 case SHADER_OPCODE_LOD
:
2011 case SHADER_OPCODE_TG4
:
2012 case SHADER_OPCODE_SAMPLEINFO
:
2013 assert(inst
->src
[0].file
== BAD_FILE
);
2014 generate_tex(inst
, dst
, src
[1], src
[2]);
2017 case FS_OPCODE_DDX_COARSE
:
2018 case FS_OPCODE_DDX_FINE
:
2019 generate_ddx(inst
, dst
, src
[0]);
2021 case FS_OPCODE_DDY_COARSE
:
2022 case FS_OPCODE_DDY_FINE
:
2023 generate_ddy(inst
, dst
, src
[0]);
2026 case SHADER_OPCODE_GEN4_SCRATCH_WRITE
:
2027 generate_scratch_write(inst
, src
[0]);
2031 case SHADER_OPCODE_GEN4_SCRATCH_READ
:
2032 generate_scratch_read(inst
, dst
);
2036 case SHADER_OPCODE_GEN7_SCRATCH_READ
:
2037 generate_scratch_read_gen7(inst
, dst
);
2041 case SHADER_OPCODE_MOV_INDIRECT
:
2042 generate_mov_indirect(inst
, dst
, src
[0], src
[1]);
2045 case SHADER_OPCODE_URB_READ_SIMD8
:
2046 case SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT
:
2047 generate_urb_read(inst
, dst
, src
[0]);
2050 case SHADER_OPCODE_URB_WRITE_SIMD8
:
2051 case SHADER_OPCODE_URB_WRITE_SIMD8_PER_SLOT
:
2052 case SHADER_OPCODE_URB_WRITE_SIMD8_MASKED
:
2053 case SHADER_OPCODE_URB_WRITE_SIMD8_MASKED_PER_SLOT
:
2054 generate_urb_write(inst
, src
[0]);
2057 case FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD
:
2058 assert(inst
->force_writemask_all
);
2059 generate_uniform_pull_constant_load(inst
, dst
, src
[0], src
[1]);
2062 case FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD_GEN7
:
2063 assert(inst
->force_writemask_all
);
2064 generate_uniform_pull_constant_load_gen7(inst
, dst
, src
[0], src
[1]);
2067 case FS_OPCODE_VARYING_PULL_CONSTANT_LOAD_GEN4
:
2068 generate_varying_pull_constant_load_gen4(inst
, dst
, src
[0]);
2071 case FS_OPCODE_REP_FB_WRITE
:
2072 case FS_OPCODE_FB_WRITE
:
2073 generate_fb_write(inst
, src
[0]);
2076 case FS_OPCODE_FB_READ
:
2077 generate_fb_read(inst
, dst
, src
[0]);
2080 case FS_OPCODE_DISCARD_JUMP
:
2081 generate_discard_jump(inst
);
2084 case SHADER_OPCODE_SHADER_TIME_ADD
:
2085 generate_shader_time_add(inst
, src
[0], src
[1], src
[2]);
2088 case SHADER_OPCODE_MEMORY_FENCE
:
2089 assert(src
[1].file
== BRW_IMMEDIATE_VALUE
);
2090 assert(src
[2].file
== BRW_IMMEDIATE_VALUE
);
2091 brw_memory_fence(p
, dst
, src
[0], BRW_OPCODE_SEND
, src
[1].ud
, src
[2].ud
);
2094 case SHADER_OPCODE_INTERLOCK
:
2095 assert(devinfo
->gen
>= 9);
2096 /* The interlock is basically a memory fence issued via sendc */
2097 brw_memory_fence(p
, dst
, src
[0], BRW_OPCODE_SENDC
, false, /* bti */ 0);
2100 case SHADER_OPCODE_FIND_LIVE_CHANNEL
: {
2101 const struct brw_reg mask
=
2102 brw_stage_has_packed_dispatch(devinfo
, stage
,
2103 prog_data
) ? brw_imm_ud(~0u) :
2104 stage
== MESA_SHADER_FRAGMENT
? brw_vmask_reg() :
2106 brw_find_live_channel(p
, dst
, mask
);
2110 case SHADER_OPCODE_BROADCAST
:
2111 assert(inst
->force_writemask_all
);
2112 brw_broadcast(p
, dst
, src
[0], src
[1]);
2115 case SHADER_OPCODE_SHUFFLE
:
2116 generate_shuffle(inst
, dst
, src
[0], src
[1]);
2119 case SHADER_OPCODE_SEL_EXEC
:
2120 assert(inst
->force_writemask_all
);
2121 brw_set_default_mask_control(p
, BRW_MASK_DISABLE
);
2122 brw_MOV(p
, dst
, src
[1]);
2123 brw_set_default_mask_control(p
, BRW_MASK_ENABLE
);
2124 brw_MOV(p
, dst
, src
[0]);
2127 case SHADER_OPCODE_QUAD_SWIZZLE
:
2128 assert(src
[1].file
== BRW_IMMEDIATE_VALUE
);
2129 assert(src
[1].type
== BRW_REGISTER_TYPE_UD
);
2130 generate_quad_swizzle(inst
, dst
, src
[0], src
[1].ud
);
2133 case SHADER_OPCODE_CLUSTER_BROADCAST
: {
2134 assert(src
[0].type
== dst
.type
);
2135 assert(!src
[0].negate
&& !src
[0].abs
);
2136 assert(src
[1].file
== BRW_IMMEDIATE_VALUE
);
2137 assert(src
[1].type
== BRW_REGISTER_TYPE_UD
);
2138 assert(src
[2].file
== BRW_IMMEDIATE_VALUE
);
2139 assert(src
[2].type
== BRW_REGISTER_TYPE_UD
);
2140 const unsigned component
= src
[1].ud
;
2141 const unsigned cluster_size
= src
[2].ud
;
2142 struct brw_reg strided
= stride(suboffset(src
[0], component
),
2143 cluster_size
, cluster_size
, 0);
2144 if (type_sz(src
[0].type
) > 4 &&
2145 (devinfo
->is_cherryview
|| gen_device_info_is_9lp(devinfo
))) {
2146 /* IVB has an issue (which we found empirically) where it reads
2147 * two address register components per channel for indirectly
2148 * addressed 64-bit sources.
2150 * From the Cherryview PRM Vol 7. "Register Region Restrictions":
2152 * "When source or destination datatype is 64b or operation is
2153 * integer DWord multiply, indirect addressing must not be
2156 * To work around both of these, we do two integer MOVs insead of
2157 * one 64-bit MOV. Because no double value should ever cross a
2158 * register boundary, it's safe to use the immediate offset in the
2159 * indirect here to handle adding 4 bytes to the offset and avoid
2160 * the extra ADD to the register file.
2162 brw_MOV(p
, subscript(dst
, BRW_REGISTER_TYPE_D
, 0),
2163 subscript(strided
, BRW_REGISTER_TYPE_D
, 0));
2164 brw_MOV(p
, subscript(dst
, BRW_REGISTER_TYPE_D
, 1),
2165 subscript(strided
, BRW_REGISTER_TYPE_D
, 1));
2167 brw_MOV(p
, dst
, strided
);
2172 case FS_OPCODE_SET_SAMPLE_ID
:
2173 generate_set_sample_id(inst
, dst
, src
[0], src
[1]);
2176 case FS_OPCODE_PACK_HALF_2x16_SPLIT
:
2177 generate_pack_half_2x16_split(inst
, dst
, src
[0], src
[1]);
2180 case FS_OPCODE_PLACEHOLDER_HALT
:
2181 /* This is the place where the final HALT needs to be inserted if
2182 * we've emitted any discards. If not, this will emit no code.
2184 if (!patch_discard_jumps_to_fb_writes()) {
2185 if (unlikely(debug_flag
)) {
2186 disasm_info
->use_tail
= true;
2191 case FS_OPCODE_INTERPOLATE_AT_SAMPLE
:
2192 generate_pixel_interpolator_query(inst
, dst
, src
[0], src
[1],
2193 GEN7_PIXEL_INTERPOLATOR_LOC_SAMPLE
);
2196 case FS_OPCODE_INTERPOLATE_AT_SHARED_OFFSET
:
2197 generate_pixel_interpolator_query(inst
, dst
, src
[0], src
[1],
2198 GEN7_PIXEL_INTERPOLATOR_LOC_SHARED_OFFSET
);
2201 case FS_OPCODE_INTERPOLATE_AT_PER_SLOT_OFFSET
:
2202 generate_pixel_interpolator_query(inst
, dst
, src
[0], src
[1],
2203 GEN7_PIXEL_INTERPOLATOR_LOC_PER_SLOT_OFFSET
);
2206 case CS_OPCODE_CS_TERMINATE
:
2207 generate_cs_terminate(inst
, src
[0]);
2210 case SHADER_OPCODE_BARRIER
:
2211 generate_barrier(inst
, src
[0]);
2214 case BRW_OPCODE_DIM
:
2215 assert(devinfo
->is_haswell
);
2216 assert(src
[0].type
== BRW_REGISTER_TYPE_DF
);
2217 assert(dst
.type
== BRW_REGISTER_TYPE_DF
);
2218 brw_DIM(p
, dst
, retype(src
[0], BRW_REGISTER_TYPE_F
));
2221 case SHADER_OPCODE_RND_MODE
:
2222 assert(src
[0].file
== BRW_IMMEDIATE_VALUE
);
2223 brw_rounding_mode(p
, (brw_rnd_mode
) src
[0].d
);
2227 unreachable("Unsupported opcode");
2229 case SHADER_OPCODE_LOAD_PAYLOAD
:
2230 unreachable("Should be lowered by lower_load_payload()");
2233 if (multiple_instructions_emitted
)
2236 if (inst
->no_dd_clear
|| inst
->no_dd_check
|| inst
->conditional_mod
) {
2237 assert(p
->next_insn_offset
== last_insn_offset
+ 16 ||
2238 !"conditional_mod, no_dd_check, or no_dd_clear set for IR "
2239 "emitting more than 1 instruction");
2241 brw_inst
*last
= &p
->store
[last_insn_offset
/ 16];
2243 if (inst
->conditional_mod
)
2244 brw_inst_set_cond_modifier(p
->devinfo
, last
, inst
->conditional_mod
);
2245 brw_inst_set_no_dd_clear(p
->devinfo
, last
, inst
->no_dd_clear
);
2246 brw_inst_set_no_dd_check(p
->devinfo
, last
, inst
->no_dd_check
);
2250 brw_set_uip_jip(p
, start_offset
);
2252 /* end of program sentinel */
2253 disasm_new_inst_group(disasm_info
, p
->next_insn_offset
);
2258 if (unlikely(debug_flag
))
2260 brw_validate_instructions(devinfo
, p
->store
,
2262 p
->next_insn_offset
,
2265 int before_size
= p
->next_insn_offset
- start_offset
;
2266 brw_compact_instructions(p
, start_offset
, disasm_info
);
2267 int after_size
= p
->next_insn_offset
- start_offset
;
2269 if (unlikely(debug_flag
)) {
2270 unsigned char sha1
[21];
2273 _mesa_sha1_compute(p
->store
+ start_offset
/ sizeof(brw_inst
),
2275 _mesa_sha1_format(sha1buf
, sha1
);
2277 fprintf(stderr
, "Native code for %s (sha1 %s)\n"
2278 "SIMD%d shader: %d instructions. %d loops. %u cycles. "
2279 "%d:%d spills:fills. "
2280 "scheduled with mode %s. "
2281 "Promoted %u constants. "
2282 "Compacted %d to %d bytes (%.0f%%)\n",
2283 shader_name
, sha1buf
,
2284 dispatch_width
, before_size
/ 16,
2285 loop_count
, cfg
->cycle_count
,
2286 spill_count
, fill_count
,
2287 shader_stats
.scheduler_mode
,
2288 shader_stats
.promoted_constants
,
2289 before_size
, after_size
,
2290 100.0f
* (before_size
- after_size
) / before_size
);
2292 /* overriding the shader makes disasm_info invalid */
2293 if (!brw_try_override_assembly(p
, start_offset
, sha1buf
)) {
2294 dump_assembly(p
->store
, disasm_info
);
2296 fprintf(stderr
, "Successfully overrode shader with sha1 %s\n\n", sha1buf
);
2299 ralloc_free(disasm_info
);
2302 compiler
->shader_debug_log(log_data
,
2303 "%s SIMD%d shader: %d inst, %d loops, %u cycles, "
2304 "%d:%d spills:fills, "
2305 "scheduled with mode %s, "
2306 "Promoted %u constants, "
2307 "compacted %d to %d bytes.",
2308 _mesa_shader_stage_to_abbrev(stage
),
2309 dispatch_width
, before_size
/ 16,
2310 loop_count
, cfg
->cycle_count
,
2311 spill_count
, fill_count
,
2312 shader_stats
.scheduler_mode
,
2313 shader_stats
.promoted_constants
,
2314 before_size
, after_size
);
2316 stats
->dispatch_width
= dispatch_width
;
2317 stats
->instructions
= before_size
/ 16;
2318 stats
->loops
= loop_count
;
2319 stats
->cycles
= cfg
->cycle_count
;
2320 stats
->spills
= spill_count
;
2321 stats
->fills
= fill_count
;
2324 return start_offset
;
2328 fs_generator::get_assembly()
2330 return brw_get_program(p
, &prog_data
->program_size
);