2 * Copyright © 2014 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
27 * A representation of i965 EU assembly instructions, with helper methods to
28 * get and set various fields. This is the actual hardware format.
37 #include "brw_eu_defines.h"
38 #include "brw_reg_type.h"
39 #include "dev/gen_device_info.h"
45 /* brw_context.h has a forward declaration of brw_inst, so name the struct. */
46 typedef struct brw_inst
{
50 static inline uint64_t brw_inst_bits(const brw_inst
*inst
,
51 unsigned high
, unsigned low
);
52 static inline void brw_inst_set_bits(brw_inst
*inst
,
53 unsigned high
, unsigned low
,
56 #define FC(name, high, low, assertions) \
58 brw_inst_set_##name(const struct gen_device_info *devinfo, \
59 brw_inst *inst, uint64_t v) \
63 brw_inst_set_bits(inst, high, low, v); \
65 static inline uint64_t \
66 brw_inst_##name(const struct gen_device_info *devinfo, \
67 const brw_inst *inst) \
71 return brw_inst_bits(inst, high, low); \
74 /* A simple macro for fields which stay in the same place on all generations. */
75 #define F(name, high, low) FC(name, high, low, true)
77 #define BOUNDS(hi4, lo4, hi45, lo45, hi5, lo5, hi6, lo6, hi7, lo7, hi8, lo8) \
79 if (devinfo->gen >= 8) { \
80 high = hi8; low = lo8; \
81 } else if (devinfo->gen >= 7) { \
82 high = hi7; low = lo7; \
83 } else if (devinfo->gen >= 6) { \
84 high = hi6; low = lo6; \
85 } else if (devinfo->gen >= 5) { \
86 high = hi5; low = lo5; \
87 } else if (devinfo->is_g4x) { \
88 high = hi45; low = lo45; \
90 high = hi4; low = lo4; \
92 assert(((int) high) != -1 && ((int) low) != -1);
94 /* A general macro for cases where the field has moved to several different
95 * bit locations across generations. GCC appears to combine cases where the
96 * bits are identical, removing some of the inefficiency.
98 #define FF(name, hi4, lo4, hi45, lo45, hi5, lo5, hi6, lo6, hi7, lo7, hi8, lo8)\
100 brw_inst_set_##name(const struct gen_device_info *devinfo, \
101 brw_inst *inst, uint64_t value) \
103 BOUNDS(hi4, lo4, hi45, lo45, hi5, lo5, hi6, lo6, hi7, lo7, hi8, lo8) \
104 brw_inst_set_bits(inst, high, low, value); \
106 static inline uint64_t \
107 brw_inst_##name(const struct gen_device_info *devinfo, const brw_inst *inst) \
109 BOUNDS(hi4, lo4, hi45, lo45, hi5, lo5, hi6, lo6, hi7, lo7, hi8, lo8) \
110 return brw_inst_bits(inst, high, low); \
113 /* A macro for fields which moved as of Gen8+. */
114 #define F8(name, gen4_high, gen4_low, gen8_high, gen8_low) \
116 /* 4: */ gen4_high, gen4_low, \
117 /* 4.5: */ gen4_high, gen4_low, \
118 /* 5: */ gen4_high, gen4_low, \
119 /* 6: */ gen4_high, gen4_low, \
120 /* 7: */ gen4_high, gen4_low, \
121 /* 8: */ gen8_high, gen8_low);
123 F(src1_vstride
, 120, 117)
124 F(src1_width
, 116, 114)
125 F(src1_da16_swiz_w
, 115, 114)
126 F(src1_da16_swiz_z
, 113, 112)
127 F(src1_hstride
, 113, 112)
128 F(src1_address_mode
, 111, 111)
129 /** Src1.SrcMod @{ */
130 F(src1_negate
, 110, 110)
131 F(src1_abs
, 109, 109)
133 F8(src1_ia_subreg_nr
, /* 4+ */ 108, 106, /* 8+ */ 108, 105)
134 F(src1_da_reg_nr
, 108, 101)
135 F(src1_da16_subreg_nr
, 100, 100)
136 F(src1_da1_subreg_nr
, 100, 96)
137 F(src1_da16_swiz_y
, 99, 98)
138 F(src1_da16_swiz_x
, 97, 96)
139 F8(src1_reg_hw_type
, /* 4+ */ 46, 44, /* 8+ */ 94, 91)
140 F8(src1_reg_file
, /* 4+ */ 43, 42, /* 8+ */ 90, 89)
141 F(src0_vstride
, 88, 85)
142 F(src0_width
, 84, 82)
143 F(src0_da16_swiz_w
, 83, 82)
144 F(src0_da16_swiz_z
, 81, 80)
145 F(src0_hstride
, 81, 80)
146 F(src0_address_mode
, 79, 79)
147 /** Src0.SrcMod @{ */
148 F(src0_negate
, 78, 78)
151 F8(src0_ia_subreg_nr
, /* 4+ */ 76, 74, /* 8+ */ 76, 73)
152 F(src0_da_reg_nr
, 76, 69)
153 F(src0_da16_subreg_nr
, 68, 68)
154 F(src0_da1_subreg_nr
, 68, 64)
155 F(src0_da16_swiz_y
, 67, 66)
156 F(src0_da16_swiz_x
, 65, 64)
157 F(dst_address_mode
, 63, 63)
158 F(dst_hstride
, 62, 61)
159 F8(dst_ia_subreg_nr
, /* 4+ */ 60, 58, /* 8+ */ 60, 57)
160 F(dst_da_reg_nr
, 60, 53)
161 F(dst_da16_subreg_nr
, 52, 52)
162 F(dst_da1_subreg_nr
, 52, 48)
163 F(da16_writemask
, 51, 48) /* Dst.ChanEn */
164 F8(src0_reg_hw_type
, /* 4+ */ 41, 39, /* 8+ */ 46, 43)
165 F8(src0_reg_file
, /* 4+ */ 38, 37, /* 8+ */ 42, 41)
166 F8(dst_reg_hw_type
, /* 4+ */ 36, 34, /* 8+ */ 40, 37)
167 F8(dst_reg_file
, /* 4+ */ 33, 32, /* 8+ */ 36, 35)
168 F8(mask_control
, /* 4+ */ 9, 9, /* 8+ */ 34, 34)
170 /* 4-6: doesn't exist */ -1, -1, -1, -1, -1, -1, -1, -1,
173 F8(flag_subreg_nr
, /* 4+ */ 89, 89, /* 8+ */ 32, 32)
175 F(debug_control
, 30, 30)
176 F(cmpt_control
, 29, 29)
177 FC(branch_control
, 28, 28, devinfo
->gen
>= 8)
178 FC(acc_wr_control
, 28, 28, devinfo
->gen
>= 6)
179 FC(mask_control_ex
, 28, 28, devinfo
->is_g4x
|| devinfo
->gen
== 5)
180 F(cond_modifier
, 27, 24)
181 FC(math_function
, 27, 24, devinfo
->gen
>= 6)
184 F(pred_control
, 19, 16)
185 F(thread_control
, 15, 14)
186 F(qtr_control
, 13, 12)
188 /* 4-6: doesn't exist */ -1, -1, -1, -1, -1, -1, -1, -1,
191 F8(no_dd_check
, /* 4+ */ 11, 11, /* 8+ */ 10, 10)
192 F8(no_dd_clear
, /* 4+ */ 10, 10, /* 8+ */ 9, 9)
194 /* Bit 7 is Reserved (for future Opcode expansion) */
198 * Three-source instructions:
201 F(3src_src2_reg_nr
, 125, 118) /* same in align1 */
202 F(3src_a16_src2_subreg_nr
, 117, 115) /* Extra discontiguous bit on CHV? */
203 F(3src_a16_src2_swizzle
, 114, 107)
204 F(3src_a16_src2_rep_ctrl
, 106, 106)
205 F(3src_src1_reg_nr
, 104, 97) /* same in align1 */
206 F(3src_a16_src1_subreg_nr
, 96, 94) /* Extra discontiguous bit on CHV? */
207 F(3src_a16_src1_swizzle
, 93, 86)
208 F(3src_a16_src1_rep_ctrl
, 85, 85)
209 F(3src_src0_reg_nr
, 83, 76) /* same in align1 */
210 F(3src_a16_src0_subreg_nr
, 75, 73) /* Extra discontiguous bit on CHV? */
211 F(3src_a16_src0_swizzle
, 72, 65)
212 F(3src_a16_src0_rep_ctrl
, 64, 64)
213 F(3src_dst_reg_nr
, 63, 56) /* same in align1 */
214 F(3src_a16_dst_subreg_nr
, 55, 53)
215 F(3src_a16_dst_writemask
, 52, 49)
216 F8(3src_a16_nib_ctrl
, 47, 47, 11, 11) /* only exists on IVB+ */
217 F8(3src_a16_dst_hw_type
, 45, 44, 48, 46) /* only exists on IVB+ */
218 F8(3src_a16_src_hw_type
, 43, 42, 45, 43)
219 F8(3src_src2_negate
, 41, 41, 42, 42)
220 F8(3src_src2_abs
, 40, 40, 41, 41)
221 F8(3src_src1_negate
, 39, 39, 40, 40)
222 F8(3src_src1_abs
, 38, 38, 39, 39)
223 F8(3src_src0_negate
, 37, 37, 38, 38)
224 F8(3src_src0_abs
, 36, 36, 37, 37)
225 F8(3src_a16_flag_reg_nr
, 34, 34, 33, 33)
226 F8(3src_a16_flag_subreg_nr
, 33, 33, 32, 32)
227 FF(3src_a16_dst_reg_file
,
228 /* 4-5: doesn't exist - no 3-source instructions */ -1, -1, -1, -1, -1, -1,
230 /* 7-8: doesn't exist - no MRFs */ -1, -1, -1, -1)
231 F(3src_saturate
, 31, 31)
232 F(3src_debug_control
, 30, 30)
233 F(3src_cmpt_control
, 29, 29)
234 F(3src_acc_wr_control
, 28, 28)
235 F(3src_cond_modifier
, 27, 24)
236 F(3src_exec_size
, 23, 21)
237 F(3src_pred_inv
, 20, 20)
238 F(3src_pred_control
, 19, 16)
239 F(3src_thread_control
, 15, 14)
240 F(3src_qtr_control
, 13, 12)
241 F8(3src_no_dd_check
, 11, 11, 10, 10)
242 F8(3src_no_dd_clear
, 10, 10, 9, 9)
243 F8(3src_mask_control
, 9, 9, 34, 34)
244 F(3src_access_mode
, 8, 8)
245 /* Bit 7 is Reserved (for future Opcode expansion) */
249 #define REG_TYPE(reg) \
251 brw_inst_set_3src_a16_##reg##_type(const struct gen_device_info *devinfo, \
252 brw_inst *inst, enum brw_reg_type type) \
254 unsigned hw_type = brw_reg_type_to_a16_hw_3src_type(devinfo, type); \
255 brw_inst_set_3src_a16_##reg##_hw_type(devinfo, inst, hw_type); \
258 static inline enum brw_reg_type \
259 brw_inst_3src_a16_##reg##_type(const struct gen_device_info *devinfo, \
260 const brw_inst *inst) \
262 unsigned hw_type = brw_inst_3src_a16_##reg##_hw_type(devinfo, inst); \
263 return brw_a16_hw_3src_type_to_reg_type(devinfo, hw_type); \
271 * Three-source align1 instructions:
274 /* Reserved 127:126 */
275 /* src2_reg_nr same in align16 */
276 FC(3src_a1_src2_subreg_nr
, 117, 113, devinfo
->gen
>= 10)
277 FC(3src_a1_src2_hstride
, 112, 111, devinfo
->gen
>= 10)
278 /* Reserved 110:109. src2 vstride is an implied parameter */
279 FC(3src_a1_src2_hw_type
, 108, 106, devinfo
->gen
>= 10)
281 /* src1_reg_nr same in align16 */
282 FC(3src_a1_src1_subreg_nr
, 96, 92, devinfo
->gen
>= 10)
283 FC(3src_a1_src1_hstride
, 91, 90, devinfo
->gen
>= 10)
284 FC(3src_a1_src1_vstride
, 89, 88, devinfo
->gen
>= 10)
285 FC(3src_a1_src1_hw_type
, 87, 85, devinfo
->gen
>= 10)
287 /* src0_reg_nr same in align16 */
288 FC(3src_a1_src0_subreg_nr
, 75, 71, devinfo
->gen
>= 10)
289 FC(3src_a1_src0_hstride
, 70, 69, devinfo
->gen
>= 10)
290 FC(3src_a1_src0_vstride
, 68, 67, devinfo
->gen
>= 10)
291 FC(3src_a1_src0_hw_type
, 66, 64, devinfo
->gen
>= 10)
292 /* dst_reg_nr same in align16 */
293 FC(3src_a1_dst_subreg_nr
, 55, 54, devinfo
->gen
>= 10)
294 FC(3src_a1_special_acc
, 55, 52, devinfo
->gen
>= 10) /* aliases dst_subreg_nr */
296 FC(3src_a1_dst_hstride
, 49, 49, devinfo
->gen
>= 10)
297 FC(3src_a1_dst_hw_type
, 48, 46, devinfo
->gen
>= 10)
298 FC(3src_a1_src2_reg_file
, 45, 45, devinfo
->gen
>= 10)
299 FC(3src_a1_src1_reg_file
, 44, 44, devinfo
->gen
>= 10)
300 FC(3src_a1_src0_reg_file
, 43, 43, devinfo
->gen
>= 10)
301 /* Source Modifier fields same in align16 */
302 FC(3src_a1_dst_reg_file
, 36, 36, devinfo
->gen
>= 10)
303 FC(3src_a1_exec_type
, 35, 35, devinfo
->gen
>= 10)
304 /* Fields below this same in align16 */
307 #define REG_TYPE(reg) \
309 brw_inst_set_3src_a1_##reg##_type(const struct gen_device_info *devinfo, \
310 brw_inst *inst, enum brw_reg_type type) \
312 UNUSED enum gen10_align1_3src_exec_type exec_type = \
313 (enum gen10_align1_3src_exec_type) brw_inst_3src_a1_exec_type(devinfo, \
315 if (brw_reg_type_is_floating_point(type)) { \
316 assert(exec_type == BRW_ALIGN1_3SRC_EXEC_TYPE_FLOAT); \
318 assert(exec_type == BRW_ALIGN1_3SRC_EXEC_TYPE_INT); \
320 unsigned hw_type = brw_reg_type_to_a1_hw_3src_type(devinfo, type); \
321 brw_inst_set_3src_a1_##reg##_hw_type(devinfo, inst, hw_type); \
324 static inline enum brw_reg_type \
325 brw_inst_3src_a1_##reg##_type(const struct gen_device_info *devinfo, \
326 const brw_inst *inst) \
328 enum gen10_align1_3src_exec_type exec_type = \
329 (enum gen10_align1_3src_exec_type) brw_inst_3src_a1_exec_type(devinfo, \
331 unsigned hw_type = brw_inst_3src_a1_##reg##_hw_type(devinfo, inst); \
332 return brw_a1_hw_3src_type_to_reg_type(devinfo, hw_type, exec_type); \
342 * Three-source align1 instruction immediates:
345 static inline uint16_t
346 brw_inst_3src_a1_src0_imm(MAYBE_UNUSED
const struct gen_device_info
*devinfo
,
347 const brw_inst
*insn
)
349 assert(devinfo
->gen
>= 10);
350 return brw_inst_bits(insn
, 82, 67);
353 static inline uint16_t
354 brw_inst_3src_a1_src2_imm(MAYBE_UNUSED
const struct gen_device_info
*devinfo
,
355 const brw_inst
*insn
)
357 assert(devinfo
->gen
>= 10);
358 return brw_inst_bits(insn
, 124, 109);
362 brw_inst_set_3src_a1_src0_imm(MAYBE_UNUSED
const struct gen_device_info
*devinfo
,
363 brw_inst
*insn
, uint16_t value
)
365 assert(devinfo
->gen
>= 10);
366 brw_inst_set_bits(insn
, 82, 67, value
);
370 brw_inst_set_3src_a1_src2_imm(MAYBE_UNUSED
const struct gen_device_info
*devinfo
,
371 brw_inst
*insn
, uint16_t value
)
373 assert(devinfo
->gen
>= 10);
374 brw_inst_set_bits(insn
, 124, 109, value
);
379 * Flow control instruction bits:
383 brw_inst_set_uip(const struct gen_device_info
*devinfo
,
384 brw_inst
*inst
, int32_t value
)
386 assert(devinfo
->gen
>= 6);
388 if (devinfo
->gen
>= 8) {
389 brw_inst_set_bits(inst
, 95, 64, (uint32_t)value
);
391 assert(value
<= (1 << 16) - 1);
392 assert(value
> -(1 << 16));
393 brw_inst_set_bits(inst
, 127, 112, (uint16_t)value
);
397 static inline int32_t
398 brw_inst_uip(const struct gen_device_info
*devinfo
, const brw_inst
*inst
)
400 assert(devinfo
->gen
>= 6);
402 if (devinfo
->gen
>= 8) {
403 return brw_inst_bits(inst
, 95, 64);
405 return (int16_t)brw_inst_bits(inst
, 127, 112);
410 brw_inst_set_jip(const struct gen_device_info
*devinfo
,
411 brw_inst
*inst
, int32_t value
)
413 assert(devinfo
->gen
>= 6);
415 if (devinfo
->gen
>= 8) {
416 brw_inst_set_bits(inst
, 127, 96, (uint32_t)value
);
418 assert(value
<= (1 << 15) - 1);
419 assert(value
>= -(1 << 15));
420 brw_inst_set_bits(inst
, 111, 96, (uint16_t)value
);
424 static inline int32_t
425 brw_inst_jip(const struct gen_device_info
*devinfo
, const brw_inst
*inst
)
427 assert(devinfo
->gen
>= 6);
429 if (devinfo
->gen
>= 8) {
430 return brw_inst_bits(inst
, 127, 96);
432 return (int16_t)brw_inst_bits(inst
, 111, 96);
436 /** Like FC, but using int16_t to handle negative jump targets. */
437 #define FJ(name, high, low, assertions) \
439 brw_inst_set_##name(const struct gen_device_info *devinfo, brw_inst *inst, int16_t v) \
441 assert(assertions); \
443 brw_inst_set_bits(inst, high, low, (uint16_t) v); \
445 static inline int16_t \
446 brw_inst_##name(const struct gen_device_info *devinfo, const brw_inst *inst) \
448 assert(assertions); \
450 return brw_inst_bits(inst, high, low); \
453 FJ(gen6_jump_count
, 63, 48, devinfo
->gen
== 6)
454 FJ(gen4_jump_count
, 111, 96, devinfo
->gen
< 6)
455 FC(gen4_pop_count
, 115, 112, devinfo
->gen
< 6)
458 /* Message descriptor bits */
459 #define MD(x) ((x) + 96)
462 * Fields for SEND messages:
481 /* 4: doesn't exist */ -1, -1, -1, -1,
486 F(gateway_notify
, MD(16), MD(15))
494 FF(gateway_subfuncid
,
495 /* 4: */ MD(1), MD(0),
496 /* 4.5: */ MD(1), MD(0),
497 /* 5: */ MD(1), MD(0), /* 2:0, but bit 2 is reserved MBZ */
498 /* 6: */ MD(2), MD(0),
499 /* 7: */ MD(2), MD(0),
500 /* 8: */ MD(2), MD(0))
502 /* 4: */ 123, 120, /* called msg_target */
509 /* 4-7: */ -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
510 /* 8: */ 80, 80) /* actually only Gen11+ */
511 FC(base_mrf
, 27, 24, devinfo
->gen
< 6);
515 * URB message function control bits:
518 FF(urb_per_slot_offset
,
519 /* 4-6: */ -1, -1, -1, -1, -1, -1, -1, -1,
520 /* 7: */ MD(16), MD(16),
521 /* 8: */ MD(17), MD(17))
522 FC(urb_channel_mask_present
, MD(15), MD(15), devinfo
->gen
>= 8)
523 FC(urb_complete
, MD(15), MD(15), devinfo
->gen
< 8)
524 FC(urb_used
, MD(14), MD(14), devinfo
->gen
< 7)
525 FC(urb_allocate
, MD(13), MD(13), devinfo
->gen
< 7)
526 FF(urb_swizzle_control
,
527 /* 4: */ MD(11), MD(10),
528 /* 4.5: */ MD(11), MD(10),
529 /* 5: */ MD(11), MD(10),
530 /* 6: */ MD(11), MD(10),
531 /* 7: */ MD(14), MD(14),
532 /* 8: */ MD(15), MD(15))
533 FF(urb_global_offset
,
534 /* 4: */ MD( 9), MD(4),
535 /* 4.5: */ MD( 9), MD(4),
536 /* 5: */ MD( 9), MD(4),
537 /* 6: */ MD( 9), MD(4),
538 /* 7: */ MD(13), MD(3),
539 /* 8: */ MD(14), MD(4))
541 /* 4: */ MD( 3), MD(0),
542 /* 4.5: */ MD( 3), MD(0),
543 /* 5: */ MD( 3), MD(0),
544 /* 6: */ MD( 3), MD(0),
545 /* 7: */ MD( 2), MD(0),
546 /* 8: */ MD( 3), MD(0))
550 * Gen4-5 math messages:
553 FC(math_msg_data_type
, MD(7), MD(7), devinfo
->gen
< 6)
554 FC(math_msg_saturate
, MD(6), MD(6), devinfo
->gen
< 6)
555 FC(math_msg_precision
, MD(5), MD(5), devinfo
->gen
< 6)
556 FC(math_msg_signed_int
, MD(4), MD(4), devinfo
->gen
< 6)
557 FC(math_msg_function
, MD(3), MD(0), devinfo
->gen
< 6)
561 * Sampler message function control bits:
564 FF(sampler_simd_mode
,
565 /* 4: doesn't exist */ -1, -1, -1, -1,
566 /* 5: */ MD(17), MD(16),
567 /* 6: */ MD(17), MD(16),
568 /* 7: */ MD(18), MD(17),
569 /* 8: */ MD(18), MD(17))
571 /* 4: */ MD(15), MD(14),
572 /* 4.5: */ MD(15), MD(12),
573 /* 5: */ MD(15), MD(12),
574 /* 6: */ MD(15), MD(12),
575 /* 7: */ MD(16), MD(12),
576 /* 8: */ MD(16), MD(12))
577 FC(sampler_return_format
, MD(13), MD(12), devinfo
->gen
== 4 && !devinfo
->is_g4x
)
578 F(sampler
, MD(11), MD(8))
579 F(binding_table_index
, MD( 7), MD(0)) /* also used by other messages */
583 * Data port message function control bits:
586 FC(dp_category
, MD(18), MD(18), devinfo
->gen
>= 7)
588 /* Gen4-5 store fields in different bits for read/write messages. */
590 /* 4: */ MD(13), MD(12),
591 /* 4.5: */ MD(13), MD(11),
592 /* 5: */ MD(13), MD(11),
593 /* 6: */ MD(16), MD(13),
594 /* 7: */ MD(17), MD(14),
595 /* 8: */ MD(17), MD(14))
596 FF(dp_write_msg_type
,
597 /* 4: */ MD(14), MD(12),
598 /* 4.5: */ MD(14), MD(12),
599 /* 5: */ MD(14), MD(12),
600 /* 6: */ MD(16), MD(13),
601 /* 7: */ MD(17), MD(14),
602 /* 8: */ MD(17), MD(14))
603 FF(dp_read_msg_control
,
604 /* 4: */ MD(11), MD( 8),
605 /* 4.5: */ MD(10), MD( 8),
606 /* 5: */ MD(10), MD( 8),
607 /* 6: */ MD(12), MD( 8),
608 /* 7: */ MD(13), MD( 8),
609 /* 8: */ MD(13), MD( 8))
610 FF(dp_write_msg_control
,
611 /* 4: */ MD(11), MD( 8),
612 /* 4.5: */ MD(11), MD( 8),
613 /* 5: */ MD(11), MD( 8),
614 /* 6: */ MD(12), MD( 8),
615 /* 7: */ MD(13), MD( 8),
616 /* 8: */ MD(13), MD( 8))
617 FC(dp_read_target_cache
, MD(15), MD(14), devinfo
->gen
< 6);
620 /* 4: */ MD(15), MD(15),
621 /* 4.5: */ MD(15), MD(15),
622 /* 5: */ MD(15), MD(15),
623 /* 6: */ MD(17), MD(17),
624 /* 7+: does not exist */ -1, -1, -1, -1)
626 /* Gen6+ use the same bit locations for everything. */
628 /* 4-5: use dp_read_msg_type or dp_write_msg_type instead */
629 -1, -1, -1, -1, -1, -1,
630 /* 6: */ MD(16), MD(13),
631 /* 7: */ MD(17), MD(14),
632 /* 8: */ MD(17), MD(14))
634 /* 4: */ MD(11), MD( 8),
635 /* 4.5-5: use dp_read_msg_control or dp_write_msg_control */ -1, -1, -1, -1,
636 /* 6: */ MD(12), MD( 8),
637 /* 7: */ MD(13), MD( 8),
638 /* 8: */ MD(13), MD( 8))
642 * Scratch message bits (Gen7+):
645 FC(scratch_read_write
, MD(17), MD(17), devinfo
->gen
>= 7) /* 0 = read, 1 = write */
646 FC(scratch_type
, MD(16), MD(16), devinfo
->gen
>= 7) /* 0 = OWord, 1 = DWord */
647 FC(scratch_invalidate_after_read
, MD(15), MD(15), devinfo
->gen
>= 7)
648 FC(scratch_block_size
, MD(13), MD(12), devinfo
->gen
>= 7)
649 FC(scratch_addr_offset
, MD(11), MD( 0), devinfo
->gen
>= 7)
653 * Render Target message function control bits:
657 /* 4: */ MD(11), MD(11),
658 /* 4.5: */ MD(11), MD(11),
659 /* 5: */ MD(11), MD(11),
660 /* 6: */ MD(12), MD(12),
661 /* 7: */ MD(12), MD(12),
662 /* 8: */ MD(12), MD(12))
663 FC(rt_slot_group
, MD(11), MD(11), devinfo
->gen
>= 6)
664 F(rt_message_type
, MD(10), MD( 8))
668 * Thread Spawn message function control bits:
671 F(ts_resource_select
, MD( 4), MD( 4))
672 F(ts_request_type
, MD( 1), MD( 1))
673 F(ts_opcode
, MD( 0), MD( 0))
677 * Pixel Interpolator message function control bits:
680 F(pi_simd_mode
, MD(16), MD(16))
681 F(pi_nopersp
, MD(14), MD(14))
682 F(pi_message_type
, MD(13), MD(12))
683 F(pi_slot_group
, MD(11), MD(11))
684 F(pi_message_data
, MD(7), MD(0))
692 brw_inst_imm_d(const struct gen_device_info
*devinfo
, const brw_inst
*insn
)
695 return brw_inst_bits(insn
, 127, 96);
698 static inline unsigned
699 brw_inst_imm_ud(const struct gen_device_info
*devinfo
, const brw_inst
*insn
)
702 return brw_inst_bits(insn
, 127, 96);
705 static inline uint64_t
706 brw_inst_imm_uq(MAYBE_UNUSED
const struct gen_device_info
*devinfo
,
707 const brw_inst
*insn
)
709 assert(devinfo
->gen
>= 8);
710 return brw_inst_bits(insn
, 127, 64);
714 brw_inst_imm_f(const struct gen_device_info
*devinfo
, const brw_inst
*insn
)
721 ft
.u
= brw_inst_bits(insn
, 127, 96);
726 brw_inst_imm_df(const struct gen_device_info
*devinfo
, const brw_inst
*insn
)
733 dt
.u
= brw_inst_bits(insn
, 127, 64);
738 brw_inst_set_imm_d(const struct gen_device_info
*devinfo
,
739 brw_inst
*insn
, int value
)
742 return brw_inst_set_bits(insn
, 127, 96, value
);
746 brw_inst_set_imm_ud(const struct gen_device_info
*devinfo
,
747 brw_inst
*insn
, unsigned value
)
750 return brw_inst_set_bits(insn
, 127, 96, value
);
754 brw_inst_set_imm_f(const struct gen_device_info
*devinfo
,
755 brw_inst
*insn
, float value
)
763 brw_inst_set_bits(insn
, 127, 96, ft
.u
);
767 brw_inst_set_imm_df(const struct gen_device_info
*devinfo
,
768 brw_inst
*insn
, double value
)
776 brw_inst_set_bits(insn
, 127, 64, dt
.u
);
780 brw_inst_set_imm_uq(const struct gen_device_info
*devinfo
,
781 brw_inst
*insn
, uint64_t value
)
784 brw_inst_set_bits(insn
, 127, 64, value
);
789 #define REG_TYPE(reg) \
791 brw_inst_set_##reg##_file_type(const struct gen_device_info *devinfo, \
792 brw_inst *inst, enum brw_reg_file file, \
793 enum brw_reg_type type) \
795 assert(file <= BRW_IMMEDIATE_VALUE); \
796 unsigned hw_type = brw_reg_type_to_hw_type(devinfo, file, type); \
797 brw_inst_set_##reg##_reg_file(devinfo, inst, file); \
798 brw_inst_set_##reg##_reg_hw_type(devinfo, inst, hw_type); \
801 static inline enum brw_reg_type \
802 brw_inst_##reg##_type(const struct gen_device_info *devinfo, \
803 const brw_inst *inst) \
805 unsigned file = __builtin_strcmp("dst", #reg) == 0 ? \
806 (unsigned) BRW_GENERAL_REGISTER_FILE : \
807 brw_inst_##reg##_reg_file(devinfo, inst); \
808 unsigned hw_type = brw_inst_##reg##_reg_hw_type(devinfo, inst); \
809 return brw_hw_type_to_reg_type(devinfo, (enum brw_reg_file)file, hw_type); \
818 /* The AddrImm fields are split into two discontiguous sections on Gen8+ */
819 #define BRW_IA1_ADDR_IMM(reg, g4_high, g4_low, g8_nine, g8_high, g8_low) \
821 brw_inst_set_##reg##_ia1_addr_imm(const struct gen_device_info *devinfo, \
825 assert((value & ~0x3ff) == 0); \
826 if (devinfo->gen >= 8) { \
827 brw_inst_set_bits(inst, g8_high, g8_low, value & 0x1ff); \
828 brw_inst_set_bits(inst, g8_nine, g8_nine, value >> 9); \
830 brw_inst_set_bits(inst, g4_high, g4_low, value); \
833 static inline unsigned \
834 brw_inst_##reg##_ia1_addr_imm(const struct gen_device_info *devinfo, \
835 const brw_inst *inst) \
837 if (devinfo->gen >= 8) { \
838 return brw_inst_bits(inst, g8_high, g8_low) | \
839 (brw_inst_bits(inst, g8_nine, g8_nine) << 9); \
841 return brw_inst_bits(inst, g4_high, g4_low); \
845 /* AddrImm[9:0] for Align1 Indirect Addressing */
846 /* -Gen 4- ----Gen8---- */
847 BRW_IA1_ADDR_IMM(src1
, 105, 96, 121, 104, 96)
848 BRW_IA1_ADDR_IMM(src0
, 73, 64, 95, 72, 64)
849 BRW_IA1_ADDR_IMM(dst
, 57, 48, 47, 56, 48)
851 #define BRW_IA16_ADDR_IMM(reg, g4_high, g4_low, g8_nine, g8_high, g8_low) \
853 brw_inst_set_##reg##_ia16_addr_imm(const struct gen_device_info *devinfo, \
854 brw_inst *inst, unsigned value) \
856 assert((value & ~0x3ff) == 0); \
857 if (devinfo->gen >= 8) { \
858 brw_inst_set_bits(inst, g8_high, g8_low, value & 0x1ff); \
859 brw_inst_set_bits(inst, g8_nine, g8_nine, value >> 9); \
861 brw_inst_set_bits(inst, g4_high, g4_low, value >> 9); \
864 static inline unsigned \
865 brw_inst_##reg##_ia16_addr_imm(const struct gen_device_info *devinfo, \
866 const brw_inst *inst) \
868 if (devinfo->gen >= 8) { \
869 return brw_inst_bits(inst, g8_high, g8_low) | \
870 (brw_inst_bits(inst, g8_nine, g8_nine) << 9); \
872 return brw_inst_bits(inst, g4_high, g4_low); \
876 /* AddrImm[9:0] for Align16 Indirect Addressing:
877 * Compared to Align1, these are missing the low 4 bits.
878 * -Gen 4- ----Gen8----
880 BRW_IA16_ADDR_IMM(src1
, 105, 96, 121, 104, 100)
881 BRW_IA16_ADDR_IMM(src0
, 73, 64, 95, 72, 68)
882 BRW_IA16_ADDR_IMM(dst
, 57, 52, 47, 56, 52)
885 * Fetch a set of contiguous bits from the instruction.
887 * Bits indices range from 0..127; fields may not cross 64-bit boundaries.
889 static inline uint64_t
890 brw_inst_bits(const brw_inst
*inst
, unsigned high
, unsigned low
)
892 /* We assume the field doesn't cross 64-bit boundaries. */
893 const unsigned word
= high
/ 64;
894 assert(word
== low
/ 64);
899 const uint64_t mask
= (~0ull >> (64 - (high
- low
+ 1)));
901 return (inst
->data
[word
] >> low
) & mask
;
905 * Set bits in the instruction, with proper shifting and masking.
907 * Bits indices range from 0..127; fields may not cross 64-bit boundaries.
910 brw_inst_set_bits(brw_inst
*inst
, unsigned high
, unsigned low
, uint64_t value
)
912 const unsigned word
= high
/ 64;
913 assert(word
== low
/ 64);
918 const uint64_t mask
= (~0ull >> (64 - (high
- low
+ 1))) << low
;
920 /* Make sure the supplied value actually fits in the given bitfield. */
921 assert((value
& (mask
>> low
)) == value
);
923 inst
->data
[word
] = (inst
->data
[word
] & ~mask
) | (value
<< low
);
926 #undef BRW_IA16_ADDR_IMM
927 #undef BRW_IA1_ADDR_IMM
940 * Fetch a set of contiguous bits from the compacted instruction.
942 * Bits indices range from 0..63.
944 static inline unsigned
945 brw_compact_inst_bits(const brw_compact_inst
*inst
, unsigned high
, unsigned low
)
947 const uint64_t mask
= (1ull << (high
- low
+ 1)) - 1;
949 return (inst
->data
>> low
) & mask
;
953 * Set bits in the compacted instruction.
955 * Bits indices range from 0..63.
958 brw_compact_inst_set_bits(brw_compact_inst
*inst
, unsigned high
, unsigned low
,
961 const uint64_t mask
= ((1ull << (high
- low
+ 1)) - 1) << low
;
963 /* Make sure the supplied value actually fits in the given bitfield. */
964 assert((value
& (mask
>> low
)) == value
);
966 inst
->data
= (inst
->data
& ~mask
) | (value
<< low
);
969 #define FC(name, high, low, assertions) \
971 brw_compact_inst_set_##name(const struct gen_device_info *devinfo, \
972 brw_compact_inst *inst, unsigned v) \
974 assert(assertions); \
976 brw_compact_inst_set_bits(inst, high, low, v); \
978 static inline unsigned \
979 brw_compact_inst_##name(const struct gen_device_info *devinfo, \
980 const brw_compact_inst *inst) \
982 assert(assertions); \
984 return brw_compact_inst_bits(inst, high, low); \
987 /* A simple macro for fields which stay in the same place on all generations. */
988 #define F(name, high, low) FC(name, high, low, true)
990 F(src1_reg_nr
, 63, 56)
991 F(src0_reg_nr
, 55, 48)
992 F(dst_reg_nr
, 47, 40)
993 F(src1_index
, 39, 35)
994 F(src0_index
, 34, 30)
995 F(cmpt_control
, 29, 29) /* Same location as brw_inst */
996 FC(flag_subreg_nr
, 28, 28, devinfo
->gen
<= 6)
997 F(cond_modifier
, 27, 24) /* Same location as brw_inst */
998 FC(acc_wr_control
, 23, 23, devinfo
->gen
>= 6)
999 FC(mask_control_ex
, 23, 23, devinfo
->is_g4x
|| devinfo
->gen
== 5)
1000 F(subreg_index
, 22, 18)
1001 F(datatype_index
, 17, 13)
1002 F(control_index
, 12, 8)
1003 F(debug_control
, 7, 7)
1004 F(opcode
, 6, 0) /* Same location as brw_inst */
1007 * (Gen8+) Compacted three-source instructions:
1010 FC(3src_src2_reg_nr
, 63, 57, devinfo
->gen
>= 8)
1011 FC(3src_src1_reg_nr
, 56, 50, devinfo
->gen
>= 8)
1012 FC(3src_src0_reg_nr
, 49, 43, devinfo
->gen
>= 8)
1013 FC(3src_src2_subreg_nr
, 42, 40, devinfo
->gen
>= 8)
1014 FC(3src_src1_subreg_nr
, 39, 37, devinfo
->gen
>= 8)
1015 FC(3src_src0_subreg_nr
, 36, 34, devinfo
->gen
>= 8)
1016 FC(3src_src2_rep_ctrl
, 33, 33, devinfo
->gen
>= 8)
1017 FC(3src_src1_rep_ctrl
, 32, 32, devinfo
->gen
>= 8)
1018 FC(3src_saturate
, 31, 31, devinfo
->gen
>= 8)
1019 FC(3src_debug_control
, 30, 30, devinfo
->gen
>= 8)
1020 FC(3src_cmpt_control
, 29, 29, devinfo
->gen
>= 8)
1021 FC(3src_src0_rep_ctrl
, 28, 28, devinfo
->gen
>= 8)
1023 FC(3src_dst_reg_nr
, 18, 12, devinfo
->gen
>= 8)
1024 FC(3src_source_index
, 11, 10, devinfo
->gen
>= 8)
1025 FC(3src_control_index
, 9, 8, devinfo
->gen
>= 8)
1026 /* Bit 7 is Reserved (for future Opcode expansion) */
1027 FC(3src_opcode
, 6, 0, devinfo
->gen
>= 8)