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i965: Rename brw_inst's functions that access the 3src register type
[mesa.git] / src / intel / compiler / brw_inst.h
1 /*
2 * Copyright © 2014 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 */
23
24 /**
25 * @file brw_inst.h
26 *
27 * A representation of i965 EU assembly instructions, with helper methods to
28 * get and set various fields. This is the actual hardware format.
29 */
30
31 #ifndef BRW_INST_H
32 #define BRW_INST_H
33
34 #include <assert.h>
35 #include <stdint.h>
36
37 #include "brw_eu_defines.h"
38 #include "brw_reg_type.h"
39 #include "common/gen_device_info.h"
40
41 #ifdef __cplusplus
42 extern "C" {
43 #endif
44
45 /* brw_context.h has a forward declaration of brw_inst, so name the struct. */
46 typedef struct brw_inst {
47 uint64_t data[2];
48 } brw_inst;
49
50 static inline uint64_t brw_inst_bits(const brw_inst *inst,
51 unsigned high, unsigned low);
52 static inline void brw_inst_set_bits(brw_inst *inst,
53 unsigned high, unsigned low,
54 uint64_t value);
55
56 #define FC(name, high, low, assertions) \
57 static inline void \
58 brw_inst_set_##name(const struct gen_device_info *devinfo, \
59 brw_inst *inst, uint64_t v) \
60 { \
61 assert(assertions); \
62 (void) devinfo; \
63 brw_inst_set_bits(inst, high, low, v); \
64 } \
65 static inline uint64_t \
66 brw_inst_##name(const struct gen_device_info *devinfo, \
67 const brw_inst *inst) \
68 { \
69 assert(assertions); \
70 (void) devinfo; \
71 return brw_inst_bits(inst, high, low); \
72 }
73
74 /* A simple macro for fields which stay in the same place on all generations. */
75 #define F(name, high, low) FC(name, high, low, true)
76
77 #define BOUNDS(hi4, lo4, hi45, lo45, hi5, lo5, hi6, lo6, hi7, lo7, hi8, lo8) \
78 unsigned high, low; \
79 if (devinfo->gen >= 8) { \
80 high = hi8; low = lo8; \
81 } else if (devinfo->gen >= 7) { \
82 high = hi7; low = lo7; \
83 } else if (devinfo->gen >= 6) { \
84 high = hi6; low = lo6; \
85 } else if (devinfo->gen >= 5) { \
86 high = hi5; low = lo5; \
87 } else if (devinfo->is_g4x) { \
88 high = hi45; low = lo45; \
89 } else { \
90 high = hi4; low = lo4; \
91 } \
92 assert(((int) high) != -1 && ((int) low) != -1);
93
94 /* A general macro for cases where the field has moved to several different
95 * bit locations across generations. GCC appears to combine cases where the
96 * bits are identical, removing some of the inefficiency.
97 */
98 #define FF(name, hi4, lo4, hi45, lo45, hi5, lo5, hi6, lo6, hi7, lo7, hi8, lo8)\
99 static inline void \
100 brw_inst_set_##name(const struct gen_device_info *devinfo, \
101 brw_inst *inst, uint64_t value) \
102 { \
103 BOUNDS(hi4, lo4, hi45, lo45, hi5, lo5, hi6, lo6, hi7, lo7, hi8, lo8) \
104 brw_inst_set_bits(inst, high, low, value); \
105 } \
106 static inline uint64_t \
107 brw_inst_##name(const struct gen_device_info *devinfo, const brw_inst *inst) \
108 { \
109 BOUNDS(hi4, lo4, hi45, lo45, hi5, lo5, hi6, lo6, hi7, lo7, hi8, lo8) \
110 return brw_inst_bits(inst, high, low); \
111 }
112
113 /* A macro for fields which moved as of Gen8+. */
114 #define F8(name, gen4_high, gen4_low, gen8_high, gen8_low) \
115 FF(name, \
116 /* 4: */ gen4_high, gen4_low, \
117 /* 4.5: */ gen4_high, gen4_low, \
118 /* 5: */ gen4_high, gen4_low, \
119 /* 6: */ gen4_high, gen4_low, \
120 /* 7: */ gen4_high, gen4_low, \
121 /* 8: */ gen8_high, gen8_low);
122
123 F(src1_vstride, 120, 117)
124 F(src1_width, 116, 114)
125 F(src1_da16_swiz_w, 115, 114)
126 F(src1_da16_swiz_z, 113, 112)
127 F(src1_hstride, 113, 112)
128 F(src1_address_mode, 111, 111)
129 /** Src1.SrcMod @{ */
130 F(src1_negate, 110, 110)
131 F(src1_abs, 109, 109)
132 /** @} */
133 F8(src1_ia_subreg_nr, /* 4+ */ 108, 106, /* 8+ */ 108, 105)
134 F(src1_da_reg_nr, 108, 101)
135 F(src1_da16_subreg_nr, 100, 100)
136 F(src1_da1_subreg_nr, 100, 96)
137 F(src1_da16_swiz_y, 99, 98)
138 F(src1_da16_swiz_x, 97, 96)
139 F8(src1_reg_hw_type, /* 4+ */ 46, 44, /* 8+ */ 94, 91)
140 F8(src1_reg_file, /* 4+ */ 43, 42, /* 8+ */ 90, 89)
141 F(src0_vstride, 88, 85)
142 F(src0_width, 84, 82)
143 F(src0_da16_swiz_w, 83, 82)
144 F(src0_da16_swiz_z, 81, 80)
145 F(src0_hstride, 81, 80)
146 F(src0_address_mode, 79, 79)
147 /** Src0.SrcMod @{ */
148 F(src0_negate, 78, 78)
149 F(src0_abs, 77, 77)
150 /** @} */
151 F8(src0_ia_subreg_nr, /* 4+ */ 76, 74, /* 8+ */ 76, 73)
152 F(src0_da_reg_nr, 76, 69)
153 F(src0_da16_subreg_nr, 68, 68)
154 F(src0_da1_subreg_nr, 68, 64)
155 F(src0_da16_swiz_y, 67, 66)
156 F(src0_da16_swiz_x, 65, 64)
157 F(dst_address_mode, 63, 63)
158 F(dst_hstride, 62, 61)
159 F8(dst_ia_subreg_nr, /* 4+ */ 60, 58, /* 8+ */ 60, 57)
160 F(dst_da_reg_nr, 60, 53)
161 F(dst_da16_subreg_nr, 52, 52)
162 F(dst_da1_subreg_nr, 52, 48)
163 F(da16_writemask, 51, 48) /* Dst.ChanEn */
164 F8(src0_reg_hw_type, /* 4+ */ 41, 39, /* 8+ */ 46, 43)
165 F8(src0_reg_file, /* 4+ */ 38, 37, /* 8+ */ 42, 41)
166 F8(dst_reg_hw_type, /* 4+ */ 36, 34, /* 8+ */ 40, 37)
167 F8(dst_reg_file, /* 4+ */ 33, 32, /* 8+ */ 36, 35)
168 F8(mask_control, /* 4+ */ 9, 9, /* 8+ */ 34, 34)
169 FF(flag_reg_nr,
170 /* 4-6: doesn't exist */ -1, -1, -1, -1, -1, -1, -1, -1,
171 /* 7: */ 90, 90,
172 /* 8: */ 33, 33)
173 F8(flag_subreg_nr, /* 4+ */ 89, 89, /* 8+ */ 32, 32)
174 F(saturate, 31, 31)
175 F(debug_control, 30, 30)
176 F(cmpt_control, 29, 29)
177 FC(branch_control, 28, 28, devinfo->gen >= 8)
178 FC(acc_wr_control, 28, 28, devinfo->gen >= 6)
179 FC(mask_control_ex, 28, 28, devinfo->is_g4x || devinfo->gen == 5)
180 F(cond_modifier, 27, 24)
181 FC(math_function, 27, 24, devinfo->gen >= 6)
182 F(exec_size, 23, 21)
183 F(pred_inv, 20, 20)
184 F(pred_control, 19, 16)
185 F(thread_control, 15, 14)
186 F(qtr_control, 13, 12)
187 FF(nib_control,
188 /* 4-6: doesn't exist */ -1, -1, -1, -1, -1, -1, -1, -1,
189 /* 7: */ 47, 47,
190 /* 8: */ 11, 11)
191 F8(no_dd_check, /* 4+ */ 11, 11, /* 8+ */ 10, 10)
192 F8(no_dd_clear, /* 4+ */ 10, 10, /* 8+ */ 9, 9)
193 F(access_mode, 8, 8)
194 /* Bit 7 is Reserved (for future Opcode expansion) */
195 F(opcode, 6, 0)
196
197 /**
198 * Three-source instructions:
199 * @{
200 */
201 F(3src_src2_reg_nr, 125, 118) /* same in align1 */
202 F(3src_a16_src2_subreg_nr, 117, 115) /* Extra discontiguous bit on CHV? */
203 F(3src_a16_src2_swizzle, 114, 107)
204 F(3src_a16_src2_rep_ctrl, 106, 106)
205 F(3src_src1_reg_nr, 104, 97) /* same in align1 */
206 F(3src_a16_src1_subreg_nr, 96, 94) /* Extra discontiguous bit on CHV? */
207 F(3src_a16_src1_swizzle, 93, 86)
208 F(3src_a16_src1_rep_ctrl, 85, 85)
209 F(3src_src0_reg_nr, 83, 76) /* same in align1 */
210 F(3src_a16_src0_subreg_nr, 75, 73) /* Extra discontiguous bit on CHV? */
211 F(3src_a16_src0_swizzle, 72, 65)
212 F(3src_a16_src0_rep_ctrl, 64, 64)
213 F(3src_dst_reg_nr, 63, 56) /* same in align1 */
214 F(3src_a16_dst_subreg_nr, 55, 53)
215 F(3src_a16_dst_writemask, 52, 49)
216 F8(3src_a16_nib_ctrl, 47, 47, 11, 11) /* only exists on IVB+ */
217 F8(3src_a16_dst_hw_type, 45, 44, 48, 46) /* only exists on IVB+ */
218 F8(3src_a16_src_hw_type, 43, 42, 45, 43)
219 F8(3src_src2_negate, 41, 41, 42, 42)
220 F8(3src_src2_abs, 40, 40, 41, 41)
221 F8(3src_src1_negate, 39, 39, 40, 40)
222 F8(3src_src1_abs, 38, 38, 39, 39)
223 F8(3src_src0_negate, 37, 37, 38, 38)
224 F8(3src_src0_abs, 36, 36, 37, 37)
225 F8(3src_a16_flag_reg_nr, 34, 34, 33, 33)
226 F8(3src_a16_flag_subreg_nr, 33, 33, 32, 32)
227 FF(3src_a16_dst_reg_file,
228 /* 4-5: doesn't exist - no 3-source instructions */ -1, -1, -1, -1, -1, -1,
229 /* 6: */ 32, 32,
230 /* 7-8: doesn't exist - no MRFs */ -1, -1, -1, -1)
231 F(3src_saturate, 31, 31)
232 F(3src_debug_control, 30, 30)
233 F(3src_cmpt_control, 29, 29)
234 F(3src_acc_wr_control, 28, 28)
235 F(3src_cond_modifier, 27, 24)
236 F(3src_exec_size, 23, 21)
237 F(3src_pred_inv, 20, 20)
238 F(3src_pred_control, 19, 16)
239 F(3src_thread_control, 15, 14)
240 F(3src_qtr_control, 13, 12)
241 F8(3src_no_dd_check, 11, 11, 10, 10)
242 F8(3src_no_dd_clear, 10, 10, 9, 9)
243 F8(3src_mask_control, 9, 9, 34, 34)
244 F(3src_access_mode, 8, 8)
245 /* Bit 7 is Reserved (for future Opcode expansion) */
246 F(3src_opcode, 6, 0)
247 /** @} */
248
249 /**
250 * Flow control instruction bits:
251 * @{
252 */
253 static inline void
254 brw_inst_set_uip(const struct gen_device_info *devinfo,
255 brw_inst *inst, int32_t value)
256 {
257 assert(devinfo->gen >= 6);
258
259 if (devinfo->gen >= 8) {
260 brw_inst_set_bits(inst, 95, 64, (uint32_t)value);
261 } else {
262 assert(value <= (1 << 16) - 1);
263 assert(value > -(1 << 16));
264 brw_inst_set_bits(inst, 127, 112, (uint16_t)value);
265 }
266 }
267
268 static inline int32_t
269 brw_inst_uip(const struct gen_device_info *devinfo, const brw_inst *inst)
270 {
271 assert(devinfo->gen >= 6);
272
273 if (devinfo->gen >= 8) {
274 return brw_inst_bits(inst, 95, 64);
275 } else {
276 return (int16_t)brw_inst_bits(inst, 127, 112);
277 }
278 }
279
280 static inline void
281 brw_inst_set_jip(const struct gen_device_info *devinfo,
282 brw_inst *inst, int32_t value)
283 {
284 assert(devinfo->gen >= 6);
285
286 if (devinfo->gen >= 8) {
287 brw_inst_set_bits(inst, 127, 96, (uint32_t)value);
288 } else {
289 assert(value <= (1 << 15) - 1);
290 assert(value >= -(1 << 15));
291 brw_inst_set_bits(inst, 111, 96, (uint16_t)value);
292 }
293 }
294
295 static inline int32_t
296 brw_inst_jip(const struct gen_device_info *devinfo, const brw_inst *inst)
297 {
298 assert(devinfo->gen >= 6);
299
300 if (devinfo->gen >= 8) {
301 return brw_inst_bits(inst, 127, 96);
302 } else {
303 return (int16_t)brw_inst_bits(inst, 111, 96);
304 }
305 }
306
307 /** Like FC, but using int16_t to handle negative jump targets. */
308 #define FJ(name, high, low, assertions) \
309 static inline void \
310 brw_inst_set_##name(const struct gen_device_info *devinfo, brw_inst *inst, int16_t v) \
311 { \
312 assert(assertions); \
313 (void) devinfo; \
314 brw_inst_set_bits(inst, high, low, (uint16_t) v); \
315 } \
316 static inline int16_t \
317 brw_inst_##name(const struct gen_device_info *devinfo, const brw_inst *inst) \
318 { \
319 assert(assertions); \
320 (void) devinfo; \
321 return brw_inst_bits(inst, high, low); \
322 }
323
324 FJ(gen6_jump_count, 63, 48, devinfo->gen == 6)
325 FJ(gen4_jump_count, 111, 96, devinfo->gen < 6)
326 FC(gen4_pop_count, 115, 112, devinfo->gen < 6)
327 /** @} */
328
329 /* Message descriptor bits */
330 #define MD(x) ((x) + 96)
331
332 /**
333 * Fields for SEND messages:
334 * @{
335 */
336 F(eot, 127, 127)
337 FF(mlen,
338 /* 4: */ 119, 116,
339 /* 4.5: */ 119, 116,
340 /* 5: */ 124, 121,
341 /* 6: */ 124, 121,
342 /* 7: */ 124, 121,
343 /* 8: */ 124, 121);
344 FF(rlen,
345 /* 4: */ 115, 112,
346 /* 4.5: */ 115, 112,
347 /* 5: */ 120, 116,
348 /* 6: */ 120, 116,
349 /* 7: */ 120, 116,
350 /* 8: */ 120, 116);
351 FF(header_present,
352 /* 4: doesn't exist */ -1, -1, -1, -1,
353 /* 5: */ 115, 115,
354 /* 6: */ 115, 115,
355 /* 7: */ 115, 115,
356 /* 8: */ 115, 115)
357 F(gateway_notify, MD(16), MD(15))
358 FF(function_control,
359 /* 4: */ 111, 96,
360 /* 4.5: */ 111, 96,
361 /* 5: */ 114, 96,
362 /* 6: */ 114, 96,
363 /* 7: */ 114, 96,
364 /* 8: */ 114, 96)
365 FF(gateway_subfuncid,
366 /* 4: */ MD(1), MD(0),
367 /* 4.5: */ MD(1), MD(0),
368 /* 5: */ MD(1), MD(0), /* 2:0, but bit 2 is reserved MBZ */
369 /* 6: */ MD(2), MD(0),
370 /* 7: */ MD(2), MD(0),
371 /* 8: */ MD(2), MD(0))
372 FF(sfid,
373 /* 4: */ 123, 120, /* called msg_target */
374 /* 4.5 */ 123, 120,
375 /* 5: */ 95, 92,
376 /* 6: */ 27, 24,
377 /* 7: */ 27, 24,
378 /* 8: */ 27, 24)
379 FC(base_mrf, 27, 24, devinfo->gen < 6);
380 /** @} */
381
382 /**
383 * URB message function control bits:
384 * @{
385 */
386 FF(urb_per_slot_offset,
387 /* 4-6: */ -1, -1, -1, -1, -1, -1, -1, -1,
388 /* 7: */ MD(16), MD(16),
389 /* 8: */ MD(17), MD(17))
390 FC(urb_channel_mask_present, MD(15), MD(15), devinfo->gen >= 8)
391 FC(urb_complete, MD(15), MD(15), devinfo->gen < 8)
392 FC(urb_used, MD(14), MD(14), devinfo->gen < 7)
393 FC(urb_allocate, MD(13), MD(13), devinfo->gen < 7)
394 FF(urb_swizzle_control,
395 /* 4: */ MD(11), MD(10),
396 /* 4.5: */ MD(11), MD(10),
397 /* 5: */ MD(11), MD(10),
398 /* 6: */ MD(11), MD(10),
399 /* 7: */ MD(14), MD(14),
400 /* 8: */ MD(15), MD(15))
401 FF(urb_global_offset,
402 /* 4: */ MD( 9), MD(4),
403 /* 4.5: */ MD( 9), MD(4),
404 /* 5: */ MD( 9), MD(4),
405 /* 6: */ MD( 9), MD(4),
406 /* 7: */ MD(13), MD(3),
407 /* 8: */ MD(14), MD(4))
408 FF(urb_opcode,
409 /* 4: */ MD( 3), MD(0),
410 /* 4.5: */ MD( 3), MD(0),
411 /* 5: */ MD( 3), MD(0),
412 /* 6: */ MD( 3), MD(0),
413 /* 7: */ MD( 2), MD(0),
414 /* 8: */ MD( 3), MD(0))
415 /** @} */
416
417 /**
418 * Gen4-5 math messages:
419 * @{
420 */
421 FC(math_msg_data_type, MD(7), MD(7), devinfo->gen < 6)
422 FC(math_msg_saturate, MD(6), MD(6), devinfo->gen < 6)
423 FC(math_msg_precision, MD(5), MD(5), devinfo->gen < 6)
424 FC(math_msg_signed_int, MD(4), MD(4), devinfo->gen < 6)
425 FC(math_msg_function, MD(3), MD(0), devinfo->gen < 6)
426 /** @} */
427
428 /**
429 * Sampler message function control bits:
430 * @{
431 */
432 FF(sampler_simd_mode,
433 /* 4: doesn't exist */ -1, -1, -1, -1,
434 /* 5: */ MD(17), MD(16),
435 /* 6: */ MD(17), MD(16),
436 /* 7: */ MD(18), MD(17),
437 /* 8: */ MD(18), MD(17))
438 FF(sampler_msg_type,
439 /* 4: */ MD(15), MD(14),
440 /* 4.5: */ MD(15), MD(12),
441 /* 5: */ MD(15), MD(12),
442 /* 6: */ MD(15), MD(12),
443 /* 7: */ MD(16), MD(12),
444 /* 8: */ MD(16), MD(12))
445 FC(sampler_return_format, MD(13), MD(12), devinfo->gen == 4 && !devinfo->is_g4x)
446 F(sampler, MD(11), MD(8))
447 F(binding_table_index, MD( 7), MD(0)) /* also used by other messages */
448 /** @} */
449
450 /**
451 * Data port message function control bits:
452 * @{
453 */
454 FC(dp_category, MD(18), MD(18), devinfo->gen >= 7)
455
456 /* Gen4-5 store fields in different bits for read/write messages. */
457 FF(dp_read_msg_type,
458 /* 4: */ MD(13), MD(12),
459 /* 4.5: */ MD(13), MD(11),
460 /* 5: */ MD(13), MD(11),
461 /* 6: */ MD(16), MD(13),
462 /* 7: */ MD(17), MD(14),
463 /* 8: */ MD(17), MD(14))
464 FF(dp_write_msg_type,
465 /* 4: */ MD(14), MD(12),
466 /* 4.5: */ MD(14), MD(12),
467 /* 5: */ MD(14), MD(12),
468 /* 6: */ MD(16), MD(13),
469 /* 7: */ MD(17), MD(14),
470 /* 8: */ MD(17), MD(14))
471 FF(dp_read_msg_control,
472 /* 4: */ MD(11), MD( 8),
473 /* 4.5: */ MD(10), MD( 8),
474 /* 5: */ MD(10), MD( 8),
475 /* 6: */ MD(12), MD( 8),
476 /* 7: */ MD(13), MD( 8),
477 /* 8: */ MD(13), MD( 8))
478 FF(dp_write_msg_control,
479 /* 4: */ MD(11), MD( 8),
480 /* 4.5: */ MD(11), MD( 8),
481 /* 5: */ MD(11), MD( 8),
482 /* 6: */ MD(12), MD( 8),
483 /* 7: */ MD(13), MD( 8),
484 /* 8: */ MD(13), MD( 8))
485 FC(dp_read_target_cache, MD(15), MD(14), devinfo->gen < 6);
486
487 FF(dp_write_commit,
488 /* 4: */ MD(15), MD(15),
489 /* 4.5: */ MD(15), MD(15),
490 /* 5: */ MD(15), MD(15),
491 /* 6: */ MD(17), MD(17),
492 /* 7+: does not exist */ -1, -1, -1, -1)
493
494 /* Gen6+ use the same bit locations for everything. */
495 FF(dp_msg_type,
496 /* 4-5: use dp_read_msg_type or dp_write_msg_type instead */
497 -1, -1, -1, -1, -1, -1,
498 /* 6: */ MD(16), MD(13),
499 /* 7: */ MD(17), MD(14),
500 /* 8: */ MD(17), MD(14))
501 FF(dp_msg_control,
502 /* 4: */ MD(11), MD( 8),
503 /* 4.5-5: use dp_read_msg_control or dp_write_msg_control */ -1, -1, -1, -1,
504 /* 6: */ MD(12), MD( 8),
505 /* 7: */ MD(13), MD( 8),
506 /* 8: */ MD(13), MD( 8))
507 /** @} */
508
509 /**
510 * Scratch message bits (Gen7+):
511 * @{
512 */
513 FC(scratch_read_write, MD(17), MD(17), devinfo->gen >= 7) /* 0 = read, 1 = write */
514 FC(scratch_type, MD(16), MD(16), devinfo->gen >= 7) /* 0 = OWord, 1 = DWord */
515 FC(scratch_invalidate_after_read, MD(15), MD(15), devinfo->gen >= 7)
516 FC(scratch_block_size, MD(13), MD(12), devinfo->gen >= 7)
517 FC(scratch_addr_offset, MD(11), MD( 0), devinfo->gen >= 7)
518 /** @} */
519
520 /**
521 * Render Target message function control bits:
522 * @{
523 */
524 FF(rt_last,
525 /* 4: */ MD(11), MD(11),
526 /* 4.5: */ MD(11), MD(11),
527 /* 5: */ MD(11), MD(11),
528 /* 6: */ MD(12), MD(12),
529 /* 7: */ MD(12), MD(12),
530 /* 8: */ MD(12), MD(12))
531 FC(rt_slot_group, MD(11), MD(11), devinfo->gen >= 6)
532 F(rt_message_type, MD(10), MD( 8))
533 /** @} */
534
535 /**
536 * Thread Spawn message function control bits:
537 * @{
538 */
539 F(ts_resource_select, MD( 4), MD( 4))
540 F(ts_request_type, MD( 1), MD( 1))
541 F(ts_opcode, MD( 0), MD( 0))
542 /** @} */
543
544 /**
545 * Pixel Interpolator message function control bits:
546 * @{
547 */
548 F(pi_simd_mode, MD(16), MD(16))
549 F(pi_nopersp, MD(14), MD(14))
550 F(pi_message_type, MD(13), MD(12))
551 F(pi_slot_group, MD(11), MD(11))
552 F(pi_message_data, MD(7), MD(0))
553 /** @} */
554
555 /**
556 * Immediates:
557 * @{
558 */
559 static inline int
560 brw_inst_imm_d(const struct gen_device_info *devinfo, const brw_inst *insn)
561 {
562 (void) devinfo;
563 return brw_inst_bits(insn, 127, 96);
564 }
565
566 static inline unsigned
567 brw_inst_imm_ud(const struct gen_device_info *devinfo, const brw_inst *insn)
568 {
569 (void) devinfo;
570 return brw_inst_bits(insn, 127, 96);
571 }
572
573 static inline uint64_t
574 brw_inst_imm_uq(const struct gen_device_info *devinfo, const brw_inst *insn)
575 {
576 assert(devinfo->gen >= 8);
577 return brw_inst_bits(insn, 127, 64);
578 }
579
580 static inline float
581 brw_inst_imm_f(const struct gen_device_info *devinfo, const brw_inst *insn)
582 {
583 union {
584 float f;
585 uint32_t u;
586 } ft;
587 (void) devinfo;
588 ft.u = brw_inst_bits(insn, 127, 96);
589 return ft.f;
590 }
591
592 static inline double
593 brw_inst_imm_df(const struct gen_device_info *devinfo, const brw_inst *insn)
594 {
595 union {
596 double d;
597 uint64_t u;
598 } dt;
599 (void) devinfo;
600 dt.u = brw_inst_bits(insn, 127, 64);
601 return dt.d;
602 }
603
604 static inline void
605 brw_inst_set_imm_d(const struct gen_device_info *devinfo,
606 brw_inst *insn, int value)
607 {
608 (void) devinfo;
609 return brw_inst_set_bits(insn, 127, 96, value);
610 }
611
612 static inline void
613 brw_inst_set_imm_ud(const struct gen_device_info *devinfo,
614 brw_inst *insn, unsigned value)
615 {
616 (void) devinfo;
617 return brw_inst_set_bits(insn, 127, 96, value);
618 }
619
620 static inline void
621 brw_inst_set_imm_f(const struct gen_device_info *devinfo,
622 brw_inst *insn, float value)
623 {
624 union {
625 float f;
626 uint32_t u;
627 } ft;
628 (void) devinfo;
629 ft.f = value;
630 brw_inst_set_bits(insn, 127, 96, ft.u);
631 }
632
633 static inline void
634 brw_inst_set_imm_df(const struct gen_device_info *devinfo,
635 brw_inst *insn, double value)
636 {
637 union {
638 double d;
639 uint64_t u;
640 } dt;
641 (void) devinfo;
642 dt.d = value;
643 brw_inst_set_bits(insn, 127, 64, dt.u);
644 }
645
646 static inline void
647 brw_inst_set_imm_uq(const struct gen_device_info *devinfo,
648 brw_inst *insn, uint64_t value)
649 {
650 (void) devinfo;
651 brw_inst_set_bits(insn, 127, 64, value);
652 }
653
654 /** @} */
655
656 #define REG_TYPE(reg) \
657 static inline void \
658 brw_inst_set_##reg##_file_type(const struct gen_device_info *devinfo, \
659 brw_inst *inst, enum brw_reg_file file, \
660 enum brw_reg_type type) \
661 { \
662 assert(file <= BRW_IMMEDIATE_VALUE); \
663 unsigned hw_type = brw_reg_type_to_hw_type(devinfo, file, type); \
664 brw_inst_set_##reg##_reg_file(devinfo, inst, file); \
665 brw_inst_set_##reg##_reg_hw_type(devinfo, inst, hw_type); \
666 } \
667 \
668 static inline enum brw_reg_type \
669 brw_inst_##reg##_type(const struct gen_device_info *devinfo, \
670 const brw_inst *inst) \
671 { \
672 unsigned file = __builtin_strcmp("dst", #reg) == 0 ? \
673 BRW_GENERAL_REGISTER_FILE : \
674 brw_inst_##reg##_reg_file(devinfo, inst); \
675 unsigned hw_type = brw_inst_##reg##_reg_hw_type(devinfo, inst); \
676 return brw_hw_type_to_reg_type(devinfo, (enum brw_reg_file)file, hw_type); \
677 }
678
679 REG_TYPE(dst)
680 REG_TYPE(src0)
681 REG_TYPE(src1)
682 #undef REG_TYPE
683
684
685 /* The AddrImm fields are split into two discontiguous sections on Gen8+ */
686 #define BRW_IA1_ADDR_IMM(reg, g4_high, g4_low, g8_nine, g8_high, g8_low) \
687 static inline void \
688 brw_inst_set_##reg##_ia1_addr_imm(const struct gen_device_info *devinfo, \
689 brw_inst *inst, \
690 unsigned value) \
691 { \
692 assert((value & ~0x3ff) == 0); \
693 if (devinfo->gen >= 8) { \
694 brw_inst_set_bits(inst, g8_high, g8_low, value & 0x1ff); \
695 brw_inst_set_bits(inst, g8_nine, g8_nine, value >> 9); \
696 } else { \
697 brw_inst_set_bits(inst, g4_high, g4_low, value); \
698 } \
699 } \
700 static inline unsigned \
701 brw_inst_##reg##_ia1_addr_imm(const struct gen_device_info *devinfo, \
702 const brw_inst *inst) \
703 { \
704 if (devinfo->gen >= 8) { \
705 return brw_inst_bits(inst, g8_high, g8_low) | \
706 (brw_inst_bits(inst, g8_nine, g8_nine) << 9); \
707 } else { \
708 return brw_inst_bits(inst, g4_high, g4_low); \
709 } \
710 }
711
712 /* AddrImm[9:0] for Align1 Indirect Addressing */
713 /* -Gen 4- ----Gen8---- */
714 BRW_IA1_ADDR_IMM(src1, 105, 96, 121, 104, 96)
715 BRW_IA1_ADDR_IMM(src0, 73, 64, 95, 72, 64)
716 BRW_IA1_ADDR_IMM(dst, 57, 48, 47, 56, 48)
717
718 #define BRW_IA16_ADDR_IMM(reg, g4_high, g4_low, g8_nine, g8_high, g8_low) \
719 static inline void \
720 brw_inst_set_##reg##_ia16_addr_imm(const struct gen_device_info *devinfo, \
721 brw_inst *inst, unsigned value) \
722 { \
723 assert((value & ~0x3ff) == 0); \
724 if (devinfo->gen >= 8) { \
725 brw_inst_set_bits(inst, g8_high, g8_low, value & 0x1ff); \
726 brw_inst_set_bits(inst, g8_nine, g8_nine, value >> 9); \
727 } else { \
728 brw_inst_set_bits(inst, g4_high, g4_low, value >> 9); \
729 } \
730 } \
731 static inline unsigned \
732 brw_inst_##reg##_ia16_addr_imm(const struct gen_device_info *devinfo, \
733 const brw_inst *inst) \
734 { \
735 if (devinfo->gen >= 8) { \
736 return brw_inst_bits(inst, g8_high, g8_low) | \
737 (brw_inst_bits(inst, g8_nine, g8_nine) << 9); \
738 } else { \
739 return brw_inst_bits(inst, g4_high, g4_low); \
740 } \
741 }
742
743 /* AddrImm[9:0] for Align16 Indirect Addressing:
744 * Compared to Align1, these are missing the low 4 bits.
745 * -Gen 4- ----Gen8----
746 */
747 BRW_IA16_ADDR_IMM(src1, 105, 96, 121, 104, 100)
748 BRW_IA16_ADDR_IMM(src0, 73, 64, 95, 72, 68)
749 BRW_IA16_ADDR_IMM(dst, 57, 52, 47, 56, 52)
750
751 /**
752 * Fetch a set of contiguous bits from the instruction.
753 *
754 * Bits indices range from 0..127; fields may not cross 64-bit boundaries.
755 */
756 static inline uint64_t
757 brw_inst_bits(const brw_inst *inst, unsigned high, unsigned low)
758 {
759 /* We assume the field doesn't cross 64-bit boundaries. */
760 const unsigned word = high / 64;
761 assert(word == low / 64);
762
763 high %= 64;
764 low %= 64;
765
766 const uint64_t mask = (~0ull >> (64 - (high - low + 1)));
767
768 return (inst->data[word] >> low) & mask;
769 }
770
771 /**
772 * Set bits in the instruction, with proper shifting and masking.
773 *
774 * Bits indices range from 0..127; fields may not cross 64-bit boundaries.
775 */
776 static inline void
777 brw_inst_set_bits(brw_inst *inst, unsigned high, unsigned low, uint64_t value)
778 {
779 const unsigned word = high / 64;
780 assert(word == low / 64);
781
782 high %= 64;
783 low %= 64;
784
785 const uint64_t mask = (~0ull >> (64 - (high - low + 1))) << low;
786
787 /* Make sure the supplied value actually fits in the given bitfield. */
788 assert((value & (mask >> low)) == value);
789
790 inst->data[word] = (inst->data[word] & ~mask) | (value << low);
791 }
792
793 #undef BRW_IA16_ADDR_IMM
794 #undef BRW_IA1_ADDR_IMM
795 #undef MD
796 #undef F8
797 #undef FF
798 #undef BOUNDS
799 #undef F
800 #undef FC
801
802 typedef struct {
803 uint64_t data;
804 } brw_compact_inst;
805
806 /**
807 * Fetch a set of contiguous bits from the compacted instruction.
808 *
809 * Bits indices range from 0..63.
810 */
811 static inline unsigned
812 brw_compact_inst_bits(const brw_compact_inst *inst, unsigned high, unsigned low)
813 {
814 const uint64_t mask = (1ull << (high - low + 1)) - 1;
815
816 return (inst->data >> low) & mask;
817 }
818
819 /**
820 * Set bits in the compacted instruction.
821 *
822 * Bits indices range from 0..63.
823 */
824 static inline void
825 brw_compact_inst_set_bits(brw_compact_inst *inst, unsigned high, unsigned low,
826 uint64_t value)
827 {
828 const uint64_t mask = ((1ull << (high - low + 1)) - 1) << low;
829
830 /* Make sure the supplied value actually fits in the given bitfield. */
831 assert((value & (mask >> low)) == value);
832
833 inst->data = (inst->data & ~mask) | (value << low);
834 }
835
836 #define FC(name, high, low, assertions) \
837 static inline void \
838 brw_compact_inst_set_##name(const struct gen_device_info *devinfo, \
839 brw_compact_inst *inst, unsigned v) \
840 { \
841 assert(assertions); \
842 (void) devinfo; \
843 brw_compact_inst_set_bits(inst, high, low, v); \
844 } \
845 static inline unsigned \
846 brw_compact_inst_##name(const struct gen_device_info *devinfo, \
847 const brw_compact_inst *inst) \
848 { \
849 assert(assertions); \
850 (void) devinfo; \
851 return brw_compact_inst_bits(inst, high, low); \
852 }
853
854 /* A simple macro for fields which stay in the same place on all generations. */
855 #define F(name, high, low) FC(name, high, low, true)
856
857 F(src1_reg_nr, 63, 56)
858 F(src0_reg_nr, 55, 48)
859 F(dst_reg_nr, 47, 40)
860 F(src1_index, 39, 35)
861 F(src0_index, 34, 30)
862 F(cmpt_control, 29, 29) /* Same location as brw_inst */
863 FC(flag_subreg_nr, 28, 28, devinfo->gen <= 6)
864 F(cond_modifier, 27, 24) /* Same location as brw_inst */
865 FC(acc_wr_control, 23, 23, devinfo->gen >= 6)
866 FC(mask_control_ex, 23, 23, devinfo->is_g4x || devinfo->gen == 5)
867 F(subreg_index, 22, 18)
868 F(datatype_index, 17, 13)
869 F(control_index, 12, 8)
870 F(debug_control, 7, 7)
871 F(opcode, 6, 0) /* Same location as brw_inst */
872
873 /**
874 * (Gen8+) Compacted three-source instructions:
875 * @{
876 */
877 FC(3src_src2_reg_nr, 63, 57, devinfo->gen >= 8)
878 FC(3src_src1_reg_nr, 56, 50, devinfo->gen >= 8)
879 FC(3src_src0_reg_nr, 49, 43, devinfo->gen >= 8)
880 FC(3src_src2_subreg_nr, 42, 40, devinfo->gen >= 8)
881 FC(3src_src1_subreg_nr, 39, 37, devinfo->gen >= 8)
882 FC(3src_src0_subreg_nr, 36, 34, devinfo->gen >= 8)
883 FC(3src_src2_rep_ctrl, 33, 33, devinfo->gen >= 8)
884 FC(3src_src1_rep_ctrl, 32, 32, devinfo->gen >= 8)
885 FC(3src_saturate, 31, 31, devinfo->gen >= 8)
886 FC(3src_debug_control, 30, 30, devinfo->gen >= 8)
887 FC(3src_cmpt_control, 29, 29, devinfo->gen >= 8)
888 FC(3src_src0_rep_ctrl, 28, 28, devinfo->gen >= 8)
889 /* Reserved */
890 FC(3src_dst_reg_nr, 18, 12, devinfo->gen >= 8)
891 FC(3src_source_index, 11, 10, devinfo->gen >= 8)
892 FC(3src_control_index, 9, 8, devinfo->gen >= 8)
893 /* Bit 7 is Reserved (for future Opcode expansion) */
894 FC(3src_opcode, 6, 0, devinfo->gen >= 8)
895 /** @} */
896
897 #undef F
898
899 #ifdef __cplusplus
900 }
901 #endif
902
903 #endif