2 * Copyright © 2010 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * Eric Anholt <eric@anholt.net>
29 #include "brw_fs_live_variables.h"
32 #include "brw_shader.h"
36 /** @file brw_fs_schedule_instructions.cpp
38 * List scheduling of FS instructions.
40 * The basic model of the list scheduler is to take a basic block,
41 * compute a DAG of the dependencies (RAW ordering with latency, WAW
42 * ordering with latency, WAR ordering), and make a list of the DAG heads.
43 * Heuristically pick a DAG head, then put all the children that are
44 * now DAG heads into the list of things to schedule.
46 * The heuristic is the important part. We're trying to be cheap,
47 * since actually computing the optimal scheduling is NP complete.
48 * What we do is track a "current clock". When we schedule a node, we
49 * update the earliest-unblocked clock time of its children, and
50 * increment the clock. Then, when trying to schedule, we just pick
51 * the earliest-unblocked instruction to schedule.
53 * Note that often there will be many things which could execute
54 * immediately, and there are a range of heuristic options to choose
55 * from in picking among those.
58 static bool debug
= false;
60 class instruction_scheduler
;
62 class schedule_node
: public exec_node
65 schedule_node(backend_instruction
*inst
, instruction_scheduler
*sched
);
66 void set_latency_gen4();
67 void set_latency_gen7(bool is_haswell
);
69 backend_instruction
*inst
;
70 schedule_node
**children
;
79 * Which iteration of pushing groups of children onto the candidates list
80 * this node was a part of.
82 unsigned cand_generation
;
85 * This is the sum of the instruction's latency plus the maximum delay of
86 * its children, or just the issue_time if it's a leaf node.
91 * Preferred exit node among the (direct or indirect) successors of this
92 * node. Among the scheduler nodes blocked by this node, this will be the
93 * one that may cause earliest program termination, or NULL if none of the
94 * successors is an exit node.
100 * Lower bound of the scheduling time after which one of the instructions
101 * blocked by this node may lead to program termination.
103 * exit_unblocked_time() determines a strict partial ordering relation '«' on
104 * the set of scheduler nodes as follows:
106 * n « m <-> exit_unblocked_time(n) < exit_unblocked_time(m)
108 * which can be used to heuristically order nodes according to how early they
109 * can unblock an exit node and lead to program termination.
112 exit_unblocked_time(const schedule_node
*n
)
114 return n
->exit
? n
->exit
->unblocked_time
: INT_MAX
;
118 schedule_node::set_latency_gen4()
121 int math_latency
= 22;
123 switch (inst
->opcode
) {
124 case SHADER_OPCODE_RCP
:
125 this->latency
= 1 * chans
* math_latency
;
127 case SHADER_OPCODE_RSQ
:
128 this->latency
= 2 * chans
* math_latency
;
130 case SHADER_OPCODE_INT_QUOTIENT
:
131 case SHADER_OPCODE_SQRT
:
132 case SHADER_OPCODE_LOG2
:
133 /* full precision log. partial is 2. */
134 this->latency
= 3 * chans
* math_latency
;
136 case SHADER_OPCODE_INT_REMAINDER
:
137 case SHADER_OPCODE_EXP2
:
138 /* full precision. partial is 3, same throughput. */
139 this->latency
= 4 * chans
* math_latency
;
141 case SHADER_OPCODE_POW
:
142 this->latency
= 8 * chans
* math_latency
;
144 case SHADER_OPCODE_SIN
:
145 case SHADER_OPCODE_COS
:
146 /* minimum latency, max is 12 rounds. */
147 this->latency
= 5 * chans
* math_latency
;
156 schedule_node::set_latency_gen7(bool is_haswell
)
158 switch (inst
->opcode
) {
161 * (since the last two src operands are in different register banks):
162 * mad(8) g4<1>F g2.2<4,4,1>F.x g2<4,4,1>F.x g3.1<4,4,1>F.x { align16 WE_normal 1Q };
164 * 3 cycles on IVB, 4 on HSW
165 * (since the last two src operands are in the same register bank):
166 * mad(8) g4<1>F g2.2<4,4,1>F.x g2<4,4,1>F.x g2.1<4,4,1>F.x { align16 WE_normal 1Q };
168 * 18 cycles on IVB, 16 on HSW
169 * (since the last two src operands are in different register banks):
170 * mad(8) g4<1>F g2.2<4,4,1>F.x g2<4,4,1>F.x g3.1<4,4,1>F.x { align16 WE_normal 1Q };
171 * mov(8) null g4<4,5,1>F { align16 WE_normal 1Q };
173 * 20 cycles on IVB, 18 on HSW
174 * (since the last two src operands are in the same register bank):
175 * mad(8) g4<1>F g2.2<4,4,1>F.x g2<4,4,1>F.x g2.1<4,4,1>F.x { align16 WE_normal 1Q };
176 * mov(8) null g4<4,4,1>F { align16 WE_normal 1Q };
179 /* Our register allocator doesn't know about register banks, so use the
182 latency
= is_haswell
? 16 : 18;
187 * (since the last two src operands are in different register banks):
188 * lrp(8) g4<1>F g2.2<4,4,1>F.x g2<4,4,1>F.x g3.1<4,4,1>F.x { align16 WE_normal 1Q };
190 * 3 cycles on IVB, 4 on HSW
191 * (since the last two src operands are in the same register bank):
192 * lrp(8) g4<1>F g2.2<4,4,1>F.x g2<4,4,1>F.x g2.1<4,4,1>F.x { align16 WE_normal 1Q };
194 * 16 cycles on IVB, 14 on HSW
195 * (since the last two src operands are in different register banks):
196 * lrp(8) g4<1>F g2.2<4,4,1>F.x g2<4,4,1>F.x g3.1<4,4,1>F.x { align16 WE_normal 1Q };
197 * mov(8) null g4<4,4,1>F { align16 WE_normal 1Q };
200 * (since the last two src operands are in the same register bank):
201 * lrp(8) g4<1>F g2.2<4,4,1>F.x g2<4,4,1>F.x g2.1<4,4,1>F.x { align16 WE_normal 1Q };
202 * mov(8) null g4<4,4,1>F { align16 WE_normal 1Q };
205 /* Our register allocator doesn't know about register banks, so use the
211 case SHADER_OPCODE_RCP
:
212 case SHADER_OPCODE_RSQ
:
213 case SHADER_OPCODE_SQRT
:
214 case SHADER_OPCODE_LOG2
:
215 case SHADER_OPCODE_EXP2
:
216 case SHADER_OPCODE_SIN
:
217 case SHADER_OPCODE_COS
:
219 * math inv(8) g4<1>F g2<0,1,0>F null { align1 WE_normal 1Q };
222 * math inv(8) g4<1>F g2<0,1,0>F null { align1 WE_normal 1Q };
223 * mov(8) null g4<8,8,1>F { align1 WE_normal 1Q };
225 * Same for exp2, log2, rsq, sqrt, sin, cos.
227 latency
= is_haswell
? 14 : 16;
230 case SHADER_OPCODE_POW
:
232 * math pow(8) g4<1>F g2<0,1,0>F g2.1<0,1,0>F { align1 WE_normal 1Q };
235 * math pow(8) g4<1>F g2<0,1,0>F g2.1<0,1,0>F { align1 WE_normal 1Q };
236 * mov(8) null g4<8,8,1>F { align1 WE_normal 1Q };
238 latency
= is_haswell
? 22 : 24;
241 case SHADER_OPCODE_TEX
:
242 case SHADER_OPCODE_TXD
:
243 case SHADER_OPCODE_TXF
:
244 case SHADER_OPCODE_TXF_LZ
:
245 case SHADER_OPCODE_TXL
:
246 case SHADER_OPCODE_TXL_LZ
:
248 * mov(8) g115<1>F 0F { align1 WE_normal 1Q };
249 * mov(8) g114<1>F 0F { align1 WE_normal 1Q };
250 * send(8) g4<1>UW g114<8,8,1>F
251 * sampler (10, 0, 0, 1) mlen 2 rlen 4 { align1 WE_normal 1Q };
253 * 697 +/-49 cycles (min 610, n=26):
254 * mov(8) g115<1>F 0F { align1 WE_normal 1Q };
255 * mov(8) g114<1>F 0F { align1 WE_normal 1Q };
256 * send(8) g4<1>UW g114<8,8,1>F
257 * sampler (10, 0, 0, 1) mlen 2 rlen 4 { align1 WE_normal 1Q };
258 * mov(8) null g4<8,8,1>F { align1 WE_normal 1Q };
260 * So the latency on our first texture load of the batchbuffer takes
261 * ~700 cycles, since the caches are cold at that point.
263 * 840 +/- 92 cycles (min 720, n=25):
264 * mov(8) g115<1>F 0F { align1 WE_normal 1Q };
265 * mov(8) g114<1>F 0F { align1 WE_normal 1Q };
266 * send(8) g4<1>UW g114<8,8,1>F
267 * sampler (10, 0, 0, 1) mlen 2 rlen 4 { align1 WE_normal 1Q };
268 * mov(8) null g4<8,8,1>F { align1 WE_normal 1Q };
269 * send(8) g4<1>UW g114<8,8,1>F
270 * sampler (10, 0, 0, 1) mlen 2 rlen 4 { align1 WE_normal 1Q };
271 * mov(8) null g4<8,8,1>F { align1 WE_normal 1Q };
273 * On the second load, it takes just an extra ~140 cycles, and after
274 * accounting for the 14 cycles of the MOV's latency, that makes ~130.
276 * 683 +/- 49 cycles (min = 602, n=47):
277 * mov(8) g115<1>F 0F { align1 WE_normal 1Q };
278 * mov(8) g114<1>F 0F { align1 WE_normal 1Q };
279 * send(8) g4<1>UW g114<8,8,1>F
280 * sampler (10, 0, 0, 1) mlen 2 rlen 4 { align1 WE_normal 1Q };
281 * send(8) g50<1>UW g114<8,8,1>F
282 * sampler (10, 0, 0, 1) mlen 2 rlen 4 { align1 WE_normal 1Q };
283 * mov(8) null g4<8,8,1>F { align1 WE_normal 1Q };
285 * The unit appears to be pipelined, since this matches up with the
286 * cache-cold case, despite there being two loads here. If you replace
287 * the g4 in the MOV to null with g50, it's still 693 +/- 52 (n=39).
289 * So, take some number between the cache-hot 140 cycles and the
290 * cache-cold 700 cycles. No particular tuning was done on this.
292 * I haven't done significant testing of the non-TEX opcodes. TXL at
293 * least looked about the same as TEX.
298 case SHADER_OPCODE_TXS
:
299 /* Testing textureSize(sampler2D, 0), one load was 420 +/- 41
301 * mov(8) g114<1>UD 0D { align1 WE_normal 1Q };
302 * send(8) g6<1>UW g114<8,8,1>F
303 * sampler (10, 0, 10, 1) mlen 1 rlen 4 { align1 WE_normal 1Q };
304 * mov(16) g6<1>F g6<8,8,1>D { align1 WE_normal 1Q };
307 * Two loads was 535 +/- 30 cycles (n=19):
308 * mov(16) g114<1>UD 0D { align1 WE_normal 1H };
309 * send(16) g6<1>UW g114<8,8,1>F
310 * sampler (10, 0, 10, 2) mlen 2 rlen 8 { align1 WE_normal 1H };
311 * mov(16) g114<1>UD 0D { align1 WE_normal 1H };
312 * mov(16) g6<1>F g6<8,8,1>D { align1 WE_normal 1H };
313 * send(16) g8<1>UW g114<8,8,1>F
314 * sampler (10, 0, 10, 2) mlen 2 rlen 8 { align1 WE_normal 1H };
315 * mov(16) g8<1>F g8<8,8,1>D { align1 WE_normal 1H };
316 * add(16) g6<1>F g6<8,8,1>F g8<8,8,1>F { align1 WE_normal 1H };
318 * Since the only caches that should matter are just the
319 * instruction/state cache containing the surface state, assume that we
320 * always have hot caches.
325 case FS_OPCODE_VARYING_PULL_CONSTANT_LOAD_GEN4
:
326 case FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD
:
327 case FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD_GEN7
:
328 case VS_OPCODE_PULL_CONSTANT_LOAD
:
329 /* testing using varying-index pull constants:
332 * mov(8) g4<1>D g2.1<0,1,0>F { align1 WE_normal 1Q };
333 * send(8) g4<1>F g4<8,8,1>D
334 * data (9, 2, 3) mlen 1 rlen 1 { align1 WE_normal 1Q };
337 * mov(8) g4<1>D g2.1<0,1,0>F { align1 WE_normal 1Q };
338 * send(8) g4<1>F g4<8,8,1>D
339 * data (9, 2, 3) mlen 1 rlen 1 { align1 WE_normal 1Q };
340 * mov(8) null g4<8,8,1>F { align1 WE_normal 1Q };
343 * mov(8) g4<1>D g2.1<0,1,0>F { align1 WE_normal 1Q };
344 * send(8) g4<1>F g4<8,8,1>D
345 * data (9, 2, 3) mlen 1 rlen 1 { align1 WE_normal 1Q };
346 * mov(8) null g4<8,8,1>F { align1 WE_normal 1Q };
347 * send(8) g4<1>F g4<8,8,1>D
348 * data (9, 2, 3) mlen 1 rlen 1 { align1 WE_normal 1Q };
349 * mov(8) null g4<8,8,1>F { align1 WE_normal 1Q };
351 * So, if it's cache-hot, it's about 140. If it's cache cold, it's
352 * about 460. We expect to mostly be cache hot, so pick something more
358 case SHADER_OPCODE_GEN7_SCRATCH_READ
:
359 /* Testing a load from offset 0, that had been previously written:
361 * send(8) g114<1>UW g0<8,8,1>F data (0, 0, 0) mlen 1 rlen 1 { align1 WE_normal 1Q };
362 * mov(8) null g114<8,8,1>F { align1 WE_normal 1Q };
364 * The cycles spent seemed to be grouped around 40-50 (as low as 38),
365 * then around 140. Presumably this is cache hit vs miss.
370 case SHADER_OPCODE_UNTYPED_ATOMIC
:
371 case SHADER_OPCODE_UNTYPED_ATOMIC_FLOAT
:
372 case SHADER_OPCODE_TYPED_ATOMIC
:
374 * mov(8) g112<1>ud 0x00000000ud { align1 WE_all 1Q };
375 * mov(1) g112.7<1>ud g1.7<0,1,0>ud { align1 WE_all };
376 * mov(8) g113<1>ud 0x00000000ud { align1 WE_normal 1Q };
377 * send(8) g4<1>ud g112<8,8,1>ud
378 * data (38, 5, 6) mlen 2 rlen 1 { align1 WE_normal 1Q };
380 * Running it 100 times as fragment shader on a 128x128 quad
381 * gives an average latency of 13867 cycles per atomic op,
382 * standard deviation 3%. Note that this is a rather
383 * pessimistic estimate, the actual latency in cases with few
384 * collisions between threads and favorable pipelining has been
385 * seen to be reduced by a factor of 100.
390 case SHADER_OPCODE_UNTYPED_SURFACE_READ
:
391 case SHADER_OPCODE_UNTYPED_SURFACE_WRITE
:
392 case SHADER_OPCODE_TYPED_SURFACE_READ
:
393 case SHADER_OPCODE_TYPED_SURFACE_WRITE
:
395 * mov(8) g112<1>UD 0x00000000UD { align1 WE_all 1Q };
396 * mov(1) g112.7<1>UD g1.7<0,1,0>UD { align1 WE_all };
397 * mov(8) g113<1>UD 0x00000000UD { align1 WE_normal 1Q };
398 * send(8) g4<1>UD g112<8,8,1>UD
399 * data (38, 6, 5) mlen 2 rlen 1 { align1 WE_normal 1Q };
401 * . [repeats 8 times]
403 * mov(8) g112<1>UD 0x00000000UD { align1 WE_all 1Q };
404 * mov(1) g112.7<1>UD g1.7<0,1,0>UD { align1 WE_all };
405 * mov(8) g113<1>UD 0x00000000UD { align1 WE_normal 1Q };
406 * send(8) g4<1>UD g112<8,8,1>UD
407 * data (38, 6, 5) mlen 2 rlen 1 { align1 WE_normal 1Q };
409 * Running it 100 times as fragment shader on a 128x128 quad
410 * gives an average latency of 583 cycles per surface read,
411 * standard deviation 0.9%.
413 latency
= is_haswell
? 300 : 600;
416 case SHADER_OPCODE_SEND
:
417 switch (inst
->sfid
) {
418 case BRW_SFID_SAMPLER
: {
419 unsigned msg_type
= (inst
->desc
>> 12) & 0x1f;
421 case GEN5_SAMPLER_MESSAGE_SAMPLE_RESINFO
:
422 case GEN6_SAMPLER_MESSAGE_SAMPLE_SAMPLEINFO
:
423 /* See also SHADER_OPCODE_TXS */
428 /* See also SHADER_OPCODE_TEX */
435 case GEN6_SFID_DATAPORT_RENDER_CACHE
:
436 switch ((inst
->desc
>> 14) & 0x1f) {
437 case GEN7_DATAPORT_RC_TYPED_SURFACE_WRITE
:
438 case GEN7_DATAPORT_RC_TYPED_SURFACE_READ
:
439 /* See also SHADER_OPCODE_TYPED_SURFACE_READ */
444 case GEN7_DATAPORT_RC_TYPED_ATOMIC_OP
:
445 /* See also SHADER_OPCODE_TYPED_ATOMIC */
451 unreachable("Unknown render cache message");
455 case GEN7_SFID_DATAPORT_DATA_CACHE
:
456 switch ((inst
->desc
>> 14) & 0x1f) {
457 case HSW_DATAPORT_DC_PORT0_BYTE_SCATTERED_READ
:
458 case HSW_DATAPORT_DC_PORT0_BYTE_SCATTERED_WRITE
:
459 /* We have no data for this but assume it's roughly the same as
460 * untyped surface read/write.
465 case GEN7_DATAPORT_DC_UNTYPED_SURFACE_READ
:
466 case GEN7_DATAPORT_DC_UNTYPED_SURFACE_WRITE
:
467 /* See also SHADER_OPCODE_UNTYPED_SURFACE_READ */
472 case GEN7_DATAPORT_DC_UNTYPED_ATOMIC_OP
:
473 /* See also SHADER_OPCODE_UNTYPED_ATOMIC */
479 unreachable("Unknown data cache message");
483 case HSW_SFID_DATAPORT_DATA_CACHE_1
:
484 switch ((inst
->desc
>> 14) & 0x1f) {
485 case HSW_DATAPORT_DC_PORT1_UNTYPED_SURFACE_READ
:
486 case HSW_DATAPORT_DC_PORT1_UNTYPED_SURFACE_WRITE
:
487 case HSW_DATAPORT_DC_PORT1_TYPED_SURFACE_READ
:
488 case HSW_DATAPORT_DC_PORT1_TYPED_SURFACE_WRITE
:
489 /* See also SHADER_OPCODE_UNTYPED_SURFACE_READ */
493 case HSW_DATAPORT_DC_PORT1_UNTYPED_ATOMIC_OP
:
494 case HSW_DATAPORT_DC_PORT1_UNTYPED_ATOMIC_OP_SIMD4X2
:
495 case HSW_DATAPORT_DC_PORT1_TYPED_ATOMIC_OP_SIMD4X2
:
496 case HSW_DATAPORT_DC_PORT1_TYPED_ATOMIC_OP
:
497 case GEN9_DATAPORT_DC_PORT1_UNTYPED_ATOMIC_FLOAT_OP
:
498 /* See also SHADER_OPCODE_UNTYPED_ATOMIC */
503 unreachable("Unknown data cache message");
508 unreachable("Unknown SFID");
514 * mul(8) g4<1>F g2<0,1,0>F 0.5F { align1 WE_normal 1Q };
517 * mul(8) g4<1>F g2<0,1,0>F 0.5F { align1 WE_normal 1Q };
518 * mov(8) null g4<8,8,1>F { align1 WE_normal 1Q };
525 class instruction_scheduler
{
527 instruction_scheduler(backend_shader
*s
, int grf_count
,
528 unsigned hw_reg_count
, int block_count
,
529 instruction_scheduler_mode mode
)
532 this->mem_ctx
= ralloc_context(NULL
);
533 this->grf_count
= grf_count
;
534 this->hw_reg_count
= hw_reg_count
;
535 this->instructions
.make_empty();
536 this->instructions_to_schedule
= 0;
537 this->post_reg_alloc
= (mode
== SCHEDULE_POST
);
539 if (!post_reg_alloc
) {
540 this->reg_pressure_in
= rzalloc_array(mem_ctx
, int, block_count
);
542 this->livein
= ralloc_array(mem_ctx
, BITSET_WORD
*, block_count
);
543 for (int i
= 0; i
< block_count
; i
++)
544 this->livein
[i
] = rzalloc_array(mem_ctx
, BITSET_WORD
,
545 BITSET_WORDS(grf_count
));
547 this->liveout
= ralloc_array(mem_ctx
, BITSET_WORD
*, block_count
);
548 for (int i
= 0; i
< block_count
; i
++)
549 this->liveout
[i
] = rzalloc_array(mem_ctx
, BITSET_WORD
,
550 BITSET_WORDS(grf_count
));
552 this->hw_liveout
= ralloc_array(mem_ctx
, BITSET_WORD
*, block_count
);
553 for (int i
= 0; i
< block_count
; i
++)
554 this->hw_liveout
[i
] = rzalloc_array(mem_ctx
, BITSET_WORD
,
555 BITSET_WORDS(hw_reg_count
));
557 this->written
= rzalloc_array(mem_ctx
, bool, grf_count
);
559 this->reads_remaining
= rzalloc_array(mem_ctx
, int, grf_count
);
561 this->hw_reads_remaining
= rzalloc_array(mem_ctx
, int, hw_reg_count
);
563 this->reg_pressure_in
= NULL
;
565 this->liveout
= NULL
;
566 this->hw_liveout
= NULL
;
567 this->written
= NULL
;
568 this->reads_remaining
= NULL
;
569 this->hw_reads_remaining
= NULL
;
573 ~instruction_scheduler()
575 ralloc_free(this->mem_ctx
);
577 void add_barrier_deps(schedule_node
*n
);
578 void add_dep(schedule_node
*before
, schedule_node
*after
, int latency
);
579 void add_dep(schedule_node
*before
, schedule_node
*after
);
581 void run(cfg_t
*cfg
);
582 void add_insts_from_block(bblock_t
*block
);
583 void compute_delays();
584 void compute_exits();
585 virtual void calculate_deps() = 0;
586 virtual schedule_node
*choose_instruction_to_schedule() = 0;
589 * Returns how many cycles it takes the instruction to issue.
591 * Instructions in gen hardware are handled one simd4 vector at a time,
592 * with 1 cycle per vector dispatched. Thus SIMD8 pixel shaders take 2
593 * cycles to dispatch and SIMD16 (compressed) instructions take 4.
595 virtual int issue_time(backend_instruction
*inst
) = 0;
597 virtual void count_reads_remaining(backend_instruction
*inst
) = 0;
598 virtual void setup_liveness(cfg_t
*cfg
) = 0;
599 virtual void update_register_pressure(backend_instruction
*inst
) = 0;
600 virtual int get_register_pressure_benefit(backend_instruction
*inst
) = 0;
602 void schedule_instructions(bblock_t
*block
);
607 int instructions_to_schedule
;
609 unsigned hw_reg_count
;
612 exec_list instructions
;
615 instruction_scheduler_mode mode
;
618 * The register pressure at the beginning of each basic block.
621 int *reg_pressure_in
;
624 * The virtual GRF's whose range overlaps the beginning of each basic block.
627 BITSET_WORD
**livein
;
630 * The virtual GRF's whose range overlaps the end of each basic block.
633 BITSET_WORD
**liveout
;
636 * The hardware GRF's whose range overlaps the end of each basic block.
639 BITSET_WORD
**hw_liveout
;
642 * Whether we've scheduled a write for this virtual GRF yet.
648 * How many reads we haven't scheduled for this virtual GRF yet.
651 int *reads_remaining
;
654 * How many reads we haven't scheduled for this hardware GRF yet.
657 int *hw_reads_remaining
;
660 class fs_instruction_scheduler
: public instruction_scheduler
663 fs_instruction_scheduler(fs_visitor
*v
, int grf_count
, int hw_reg_count
,
665 instruction_scheduler_mode mode
);
666 void calculate_deps();
667 bool is_compressed(fs_inst
*inst
);
668 schedule_node
*choose_instruction_to_schedule();
669 int issue_time(backend_instruction
*inst
);
672 void count_reads_remaining(backend_instruction
*inst
);
673 void setup_liveness(cfg_t
*cfg
);
674 void update_register_pressure(backend_instruction
*inst
);
675 int get_register_pressure_benefit(backend_instruction
*inst
);
678 fs_instruction_scheduler::fs_instruction_scheduler(fs_visitor
*v
,
679 int grf_count
, int hw_reg_count
,
681 instruction_scheduler_mode mode
)
682 : instruction_scheduler(v
, grf_count
, hw_reg_count
, block_count
, mode
),
688 is_src_duplicate(fs_inst
*inst
, int src
)
690 for (int i
= 0; i
< src
; i
++)
691 if (inst
->src
[i
].equals(inst
->src
[src
]))
698 fs_instruction_scheduler::count_reads_remaining(backend_instruction
*be
)
700 fs_inst
*inst
= (fs_inst
*)be
;
702 if (!reads_remaining
)
705 for (int i
= 0; i
< inst
->sources
; i
++) {
706 if (is_src_duplicate(inst
, i
))
709 if (inst
->src
[i
].file
== VGRF
) {
710 reads_remaining
[inst
->src
[i
].nr
]++;
711 } else if (inst
->src
[i
].file
== FIXED_GRF
) {
712 if (inst
->src
[i
].nr
>= hw_reg_count
)
715 for (unsigned j
= 0; j
< regs_read(inst
, i
); j
++)
716 hw_reads_remaining
[inst
->src
[i
].nr
+ j
]++;
722 fs_instruction_scheduler::setup_liveness(cfg_t
*cfg
)
724 /* First, compute liveness on a per-GRF level using the in/out sets from
725 * liveness calculation.
727 for (int block
= 0; block
< cfg
->num_blocks
; block
++) {
728 for (int i
= 0; i
< v
->live_intervals
->num_vars
; i
++) {
729 if (BITSET_TEST(v
->live_intervals
->block_data
[block
].livein
, i
)) {
730 int vgrf
= v
->live_intervals
->vgrf_from_var
[i
];
731 if (!BITSET_TEST(livein
[block
], vgrf
)) {
732 reg_pressure_in
[block
] += v
->alloc
.sizes
[vgrf
];
733 BITSET_SET(livein
[block
], vgrf
);
737 if (BITSET_TEST(v
->live_intervals
->block_data
[block
].liveout
, i
))
738 BITSET_SET(liveout
[block
], v
->live_intervals
->vgrf_from_var
[i
]);
742 /* Now, extend the live in/live out sets for when a range crosses a block
743 * boundary, which matches what our register allocator/interference code
744 * does to account for force_writemask_all and incompatible exec_mask's.
746 for (int block
= 0; block
< cfg
->num_blocks
- 1; block
++) {
747 for (int i
= 0; i
< grf_count
; i
++) {
748 if (v
->virtual_grf_start
[i
] <= cfg
->blocks
[block
]->end_ip
&&
749 v
->virtual_grf_end
[i
] >= cfg
->blocks
[block
+ 1]->start_ip
) {
750 if (!BITSET_TEST(livein
[block
+ 1], i
)) {
751 reg_pressure_in
[block
+ 1] += v
->alloc
.sizes
[i
];
752 BITSET_SET(livein
[block
+ 1], i
);
755 BITSET_SET(liveout
[block
], i
);
760 int payload_last_use_ip
[hw_reg_count
];
761 v
->calculate_payload_ranges(hw_reg_count
, payload_last_use_ip
);
763 for (unsigned i
= 0; i
< hw_reg_count
; i
++) {
764 if (payload_last_use_ip
[i
] == -1)
767 for (int block
= 0; block
< cfg
->num_blocks
; block
++) {
768 if (cfg
->blocks
[block
]->start_ip
<= payload_last_use_ip
[i
])
769 reg_pressure_in
[block
]++;
771 if (cfg
->blocks
[block
]->end_ip
<= payload_last_use_ip
[i
])
772 BITSET_SET(hw_liveout
[block
], i
);
778 fs_instruction_scheduler::update_register_pressure(backend_instruction
*be
)
780 fs_inst
*inst
= (fs_inst
*)be
;
782 if (!reads_remaining
)
785 if (inst
->dst
.file
== VGRF
) {
786 written
[inst
->dst
.nr
] = true;
789 for (int i
= 0; i
< inst
->sources
; i
++) {
790 if (is_src_duplicate(inst
, i
))
793 if (inst
->src
[i
].file
== VGRF
) {
794 reads_remaining
[inst
->src
[i
].nr
]--;
795 } else if (inst
->src
[i
].file
== FIXED_GRF
&&
796 inst
->src
[i
].nr
< hw_reg_count
) {
797 for (unsigned off
= 0; off
< regs_read(inst
, i
); off
++)
798 hw_reads_remaining
[inst
->src
[i
].nr
+ off
]--;
804 fs_instruction_scheduler::get_register_pressure_benefit(backend_instruction
*be
)
806 fs_inst
*inst
= (fs_inst
*)be
;
809 if (inst
->dst
.file
== VGRF
) {
810 if (!BITSET_TEST(livein
[block_idx
], inst
->dst
.nr
) &&
811 !written
[inst
->dst
.nr
])
812 benefit
-= v
->alloc
.sizes
[inst
->dst
.nr
];
815 for (int i
= 0; i
< inst
->sources
; i
++) {
816 if (is_src_duplicate(inst
, i
))
819 if (inst
->src
[i
].file
== VGRF
&&
820 !BITSET_TEST(liveout
[block_idx
], inst
->src
[i
].nr
) &&
821 reads_remaining
[inst
->src
[i
].nr
] == 1)
822 benefit
+= v
->alloc
.sizes
[inst
->src
[i
].nr
];
824 if (inst
->src
[i
].file
== FIXED_GRF
&&
825 inst
->src
[i
].nr
< hw_reg_count
) {
826 for (unsigned off
= 0; off
< regs_read(inst
, i
); off
++) {
827 int reg
= inst
->src
[i
].nr
+ off
;
828 if (!BITSET_TEST(hw_liveout
[block_idx
], reg
) &&
829 hw_reads_remaining
[reg
] == 1) {
839 class vec4_instruction_scheduler
: public instruction_scheduler
842 vec4_instruction_scheduler(vec4_visitor
*v
, int grf_count
);
843 void calculate_deps();
844 schedule_node
*choose_instruction_to_schedule();
845 int issue_time(backend_instruction
*inst
);
848 void count_reads_remaining(backend_instruction
*inst
);
849 void setup_liveness(cfg_t
*cfg
);
850 void update_register_pressure(backend_instruction
*inst
);
851 int get_register_pressure_benefit(backend_instruction
*inst
);
854 vec4_instruction_scheduler::vec4_instruction_scheduler(vec4_visitor
*v
,
856 : instruction_scheduler(v
, grf_count
, 0, 0, SCHEDULE_POST
),
862 vec4_instruction_scheduler::count_reads_remaining(backend_instruction
*)
867 vec4_instruction_scheduler::setup_liveness(cfg_t
*)
872 vec4_instruction_scheduler::update_register_pressure(backend_instruction
*)
877 vec4_instruction_scheduler::get_register_pressure_benefit(backend_instruction
*)
882 schedule_node::schedule_node(backend_instruction
*inst
,
883 instruction_scheduler
*sched
)
885 const struct gen_device_info
*devinfo
= sched
->bs
->devinfo
;
888 this->child_array_size
= 0;
889 this->children
= NULL
;
890 this->child_latency
= NULL
;
891 this->child_count
= 0;
892 this->parent_count
= 0;
893 this->unblocked_time
= 0;
894 this->cand_generation
= 0;
898 /* We can't measure Gen6 timings directly but expect them to be much
899 * closer to Gen7 than Gen4.
901 if (!sched
->post_reg_alloc
)
903 else if (devinfo
->gen
>= 6)
904 set_latency_gen7(devinfo
->is_haswell
);
910 instruction_scheduler::add_insts_from_block(bblock_t
*block
)
912 foreach_inst_in_block(backend_instruction
, inst
, block
) {
913 schedule_node
*n
= new(mem_ctx
) schedule_node(inst
, this);
915 instructions
.push_tail(n
);
918 this->instructions_to_schedule
= block
->end_ip
- block
->start_ip
+ 1;
921 /** Computation of the delay member of each node. */
923 instruction_scheduler::compute_delays()
925 foreach_in_list_reverse(schedule_node
, n
, &instructions
) {
926 if (!n
->child_count
) {
927 n
->delay
= issue_time(n
->inst
);
929 for (int i
= 0; i
< n
->child_count
; i
++) {
930 assert(n
->children
[i
]->delay
);
931 n
->delay
= MAX2(n
->delay
, n
->latency
+ n
->children
[i
]->delay
);
938 instruction_scheduler::compute_exits()
940 /* Calculate a lower bound of the scheduling time of each node in the
941 * graph. This is analogous to the node's critical path but calculated
942 * from the top instead of from the bottom of the block.
944 foreach_in_list(schedule_node
, n
, &instructions
) {
945 for (int i
= 0; i
< n
->child_count
; i
++) {
946 n
->children
[i
]->unblocked_time
=
947 MAX2(n
->children
[i
]->unblocked_time
,
948 n
->unblocked_time
+ issue_time(n
->inst
) + n
->child_latency
[i
]);
952 /* Calculate the exit of each node by induction based on the exit nodes of
953 * its children. The preferred exit of a node is the one among the exit
954 * nodes of its children which can be unblocked first according to the
955 * optimistic unblocked time estimate calculated above.
957 foreach_in_list_reverse(schedule_node
, n
, &instructions
) {
958 n
->exit
= (n
->inst
->opcode
== FS_OPCODE_DISCARD_JUMP
? n
: NULL
);
960 for (int i
= 0; i
< n
->child_count
; i
++) {
961 if (exit_unblocked_time(n
->children
[i
]) < exit_unblocked_time(n
))
962 n
->exit
= n
->children
[i
]->exit
;
968 * Add a dependency between two instruction nodes.
970 * The @after node will be scheduled after @before. We will try to
971 * schedule it @latency cycles after @before, but no guarantees there.
974 instruction_scheduler::add_dep(schedule_node
*before
, schedule_node
*after
,
977 if (!before
|| !after
)
980 assert(before
!= after
);
982 for (int i
= 0; i
< before
->child_count
; i
++) {
983 if (before
->children
[i
] == after
) {
984 before
->child_latency
[i
] = MAX2(before
->child_latency
[i
], latency
);
989 if (before
->child_array_size
<= before
->child_count
) {
990 if (before
->child_array_size
< 16)
991 before
->child_array_size
= 16;
993 before
->child_array_size
*= 2;
995 before
->children
= reralloc(mem_ctx
, before
->children
,
997 before
->child_array_size
);
998 before
->child_latency
= reralloc(mem_ctx
, before
->child_latency
,
999 int, before
->child_array_size
);
1002 before
->children
[before
->child_count
] = after
;
1003 before
->child_latency
[before
->child_count
] = latency
;
1004 before
->child_count
++;
1005 after
->parent_count
++;
1009 instruction_scheduler::add_dep(schedule_node
*before
, schedule_node
*after
)
1014 add_dep(before
, after
, before
->latency
);
1018 is_scheduling_barrier(const backend_instruction
*inst
)
1020 return inst
->opcode
== FS_OPCODE_PLACEHOLDER_HALT
||
1021 inst
->is_control_flow() ||
1022 inst
->has_side_effects();
1026 * Sometimes we really want this node to execute after everything that
1027 * was before it and before everything that followed it. This adds
1028 * the deps to do so.
1031 instruction_scheduler::add_barrier_deps(schedule_node
*n
)
1033 schedule_node
*prev
= (schedule_node
*)n
->prev
;
1034 schedule_node
*next
= (schedule_node
*)n
->next
;
1037 while (!prev
->is_head_sentinel()) {
1038 add_dep(prev
, n
, 0);
1039 if (is_scheduling_barrier(prev
->inst
))
1041 prev
= (schedule_node
*)prev
->prev
;
1046 while (!next
->is_tail_sentinel()) {
1047 add_dep(n
, next
, 0);
1048 if (is_scheduling_barrier(next
->inst
))
1050 next
= (schedule_node
*)next
->next
;
1055 /* instruction scheduling needs to be aware of when an MRF write
1056 * actually writes 2 MRFs.
1059 fs_instruction_scheduler::is_compressed(fs_inst
*inst
)
1061 return inst
->exec_size
== 16;
1065 fs_instruction_scheduler::calculate_deps()
1067 /* Pre-register-allocation, this tracks the last write per VGRF offset.
1068 * After register allocation, reg_offsets are gone and we track individual
1071 schedule_node
**last_grf_write
;
1072 schedule_node
*last_mrf_write
[BRW_MAX_MRF(v
->devinfo
->gen
)];
1073 schedule_node
*last_conditional_mod
[8] = {};
1074 schedule_node
*last_accumulator_write
= NULL
;
1075 /* Fixed HW registers are assumed to be separate from the virtual
1076 * GRFs, so they can be tracked separately. We don't really write
1077 * to fixed GRFs much, so don't bother tracking them on a more
1080 schedule_node
*last_fixed_grf_write
= NULL
;
1082 last_grf_write
= (schedule_node
**)calloc(sizeof(schedule_node
*), grf_count
* 16);
1083 memset(last_mrf_write
, 0, sizeof(last_mrf_write
));
1085 /* top-to-bottom dependencies: RAW and WAW. */
1086 foreach_in_list(schedule_node
, n
, &instructions
) {
1087 fs_inst
*inst
= (fs_inst
*)n
->inst
;
1089 if (is_scheduling_barrier(inst
))
1090 add_barrier_deps(n
);
1092 /* read-after-write deps. */
1093 for (int i
= 0; i
< inst
->sources
; i
++) {
1094 if (inst
->src
[i
].file
== VGRF
) {
1095 if (post_reg_alloc
) {
1096 for (unsigned r
= 0; r
< regs_read(inst
, i
); r
++)
1097 add_dep(last_grf_write
[inst
->src
[i
].nr
+ r
], n
);
1099 for (unsigned r
= 0; r
< regs_read(inst
, i
); r
++) {
1100 add_dep(last_grf_write
[inst
->src
[i
].nr
* 16 +
1101 inst
->src
[i
].offset
/ REG_SIZE
+ r
], n
);
1104 } else if (inst
->src
[i
].file
== FIXED_GRF
) {
1105 if (post_reg_alloc
) {
1106 for (unsigned r
= 0; r
< regs_read(inst
, i
); r
++)
1107 add_dep(last_grf_write
[inst
->src
[i
].nr
+ r
], n
);
1109 add_dep(last_fixed_grf_write
, n
);
1111 } else if (inst
->src
[i
].is_accumulator()) {
1112 add_dep(last_accumulator_write
, n
);
1113 } else if (inst
->src
[i
].file
== ARF
) {
1114 add_barrier_deps(n
);
1118 if (inst
->base_mrf
!= -1) {
1119 for (int i
= 0; i
< inst
->mlen
; i
++) {
1120 /* It looks like the MRF regs are released in the send
1121 * instruction once it's sent, not when the result comes
1124 add_dep(last_mrf_write
[inst
->base_mrf
+ i
], n
);
1128 if (const unsigned mask
= inst
->flags_read(v
->devinfo
)) {
1129 assert(mask
< (1 << ARRAY_SIZE(last_conditional_mod
)));
1131 for (unsigned i
= 0; i
< ARRAY_SIZE(last_conditional_mod
); i
++) {
1132 if (mask
& (1 << i
))
1133 add_dep(last_conditional_mod
[i
], n
);
1137 if (inst
->reads_accumulator_implicitly()) {
1138 add_dep(last_accumulator_write
, n
);
1141 /* write-after-write deps. */
1142 if (inst
->dst
.file
== VGRF
) {
1143 if (post_reg_alloc
) {
1144 for (unsigned r
= 0; r
< regs_written(inst
); r
++) {
1145 add_dep(last_grf_write
[inst
->dst
.nr
+ r
], n
);
1146 last_grf_write
[inst
->dst
.nr
+ r
] = n
;
1149 for (unsigned r
= 0; r
< regs_written(inst
); r
++) {
1150 add_dep(last_grf_write
[inst
->dst
.nr
* 16 +
1151 inst
->dst
.offset
/ REG_SIZE
+ r
], n
);
1152 last_grf_write
[inst
->dst
.nr
* 16 +
1153 inst
->dst
.offset
/ REG_SIZE
+ r
] = n
;
1156 } else if (inst
->dst
.file
== MRF
) {
1157 int reg
= inst
->dst
.nr
& ~BRW_MRF_COMPR4
;
1159 add_dep(last_mrf_write
[reg
], n
);
1160 last_mrf_write
[reg
] = n
;
1161 if (is_compressed(inst
)) {
1162 if (inst
->dst
.nr
& BRW_MRF_COMPR4
)
1166 add_dep(last_mrf_write
[reg
], n
);
1167 last_mrf_write
[reg
] = n
;
1169 } else if (inst
->dst
.file
== FIXED_GRF
) {
1170 if (post_reg_alloc
) {
1171 for (unsigned r
= 0; r
< regs_written(inst
); r
++)
1172 last_grf_write
[inst
->dst
.nr
+ r
] = n
;
1174 last_fixed_grf_write
= n
;
1176 } else if (inst
->dst
.is_accumulator()) {
1177 add_dep(last_accumulator_write
, n
);
1178 last_accumulator_write
= n
;
1179 } else if (inst
->dst
.file
== ARF
&& !inst
->dst
.is_null()) {
1180 add_barrier_deps(n
);
1183 if (inst
->mlen
> 0 && inst
->base_mrf
!= -1) {
1184 for (int i
= 0; i
< v
->implied_mrf_writes(inst
); i
++) {
1185 add_dep(last_mrf_write
[inst
->base_mrf
+ i
], n
);
1186 last_mrf_write
[inst
->base_mrf
+ i
] = n
;
1190 if (const unsigned mask
= inst
->flags_written()) {
1191 assert(mask
< (1 << ARRAY_SIZE(last_conditional_mod
)));
1193 for (unsigned i
= 0; i
< ARRAY_SIZE(last_conditional_mod
); i
++) {
1194 if (mask
& (1 << i
)) {
1195 add_dep(last_conditional_mod
[i
], n
, 0);
1196 last_conditional_mod
[i
] = n
;
1201 if (inst
->writes_accumulator_implicitly(v
->devinfo
) &&
1202 !inst
->dst
.is_accumulator()) {
1203 add_dep(last_accumulator_write
, n
);
1204 last_accumulator_write
= n
;
1208 /* bottom-to-top dependencies: WAR */
1209 memset(last_grf_write
, 0, sizeof(schedule_node
*) * grf_count
* 16);
1210 memset(last_mrf_write
, 0, sizeof(last_mrf_write
));
1211 memset(last_conditional_mod
, 0, sizeof(last_conditional_mod
));
1212 last_accumulator_write
= NULL
;
1213 last_fixed_grf_write
= NULL
;
1215 foreach_in_list_reverse_safe(schedule_node
, n
, &instructions
) {
1216 fs_inst
*inst
= (fs_inst
*)n
->inst
;
1218 /* write-after-read deps. */
1219 for (int i
= 0; i
< inst
->sources
; i
++) {
1220 if (inst
->src
[i
].file
== VGRF
) {
1221 if (post_reg_alloc
) {
1222 for (unsigned r
= 0; r
< regs_read(inst
, i
); r
++)
1223 add_dep(n
, last_grf_write
[inst
->src
[i
].nr
+ r
], 0);
1225 for (unsigned r
= 0; r
< regs_read(inst
, i
); r
++) {
1226 add_dep(n
, last_grf_write
[inst
->src
[i
].nr
* 16 +
1227 inst
->src
[i
].offset
/ REG_SIZE
+ r
], 0);
1230 } else if (inst
->src
[i
].file
== FIXED_GRF
) {
1231 if (post_reg_alloc
) {
1232 for (unsigned r
= 0; r
< regs_read(inst
, i
); r
++)
1233 add_dep(n
, last_grf_write
[inst
->src
[i
].nr
+ r
], 0);
1235 add_dep(n
, last_fixed_grf_write
, 0);
1237 } else if (inst
->src
[i
].is_accumulator()) {
1238 add_dep(n
, last_accumulator_write
, 0);
1239 } else if (inst
->src
[i
].file
== ARF
) {
1240 add_barrier_deps(n
);
1244 if (inst
->base_mrf
!= -1) {
1245 for (int i
= 0; i
< inst
->mlen
; i
++) {
1246 /* It looks like the MRF regs are released in the send
1247 * instruction once it's sent, not when the result comes
1250 add_dep(n
, last_mrf_write
[inst
->base_mrf
+ i
], 2);
1254 if (const unsigned mask
= inst
->flags_read(v
->devinfo
)) {
1255 assert(mask
< (1 << ARRAY_SIZE(last_conditional_mod
)));
1257 for (unsigned i
= 0; i
< ARRAY_SIZE(last_conditional_mod
); i
++) {
1258 if (mask
& (1 << i
))
1259 add_dep(n
, last_conditional_mod
[i
]);
1263 if (inst
->reads_accumulator_implicitly()) {
1264 add_dep(n
, last_accumulator_write
);
1267 /* Update the things this instruction wrote, so earlier reads
1268 * can mark this as WAR dependency.
1270 if (inst
->dst
.file
== VGRF
) {
1271 if (post_reg_alloc
) {
1272 for (unsigned r
= 0; r
< regs_written(inst
); r
++)
1273 last_grf_write
[inst
->dst
.nr
+ r
] = n
;
1275 for (unsigned r
= 0; r
< regs_written(inst
); r
++) {
1276 last_grf_write
[inst
->dst
.nr
* 16 +
1277 inst
->dst
.offset
/ REG_SIZE
+ r
] = n
;
1280 } else if (inst
->dst
.file
== MRF
) {
1281 int reg
= inst
->dst
.nr
& ~BRW_MRF_COMPR4
;
1283 last_mrf_write
[reg
] = n
;
1285 if (is_compressed(inst
)) {
1286 if (inst
->dst
.nr
& BRW_MRF_COMPR4
)
1291 last_mrf_write
[reg
] = n
;
1293 } else if (inst
->dst
.file
== FIXED_GRF
) {
1294 if (post_reg_alloc
) {
1295 for (unsigned r
= 0; r
< regs_written(inst
); r
++)
1296 last_grf_write
[inst
->dst
.nr
+ r
] = n
;
1298 last_fixed_grf_write
= n
;
1300 } else if (inst
->dst
.is_accumulator()) {
1301 last_accumulator_write
= n
;
1302 } else if (inst
->dst
.file
== ARF
&& !inst
->dst
.is_null()) {
1303 add_barrier_deps(n
);
1306 if (inst
->mlen
> 0 && inst
->base_mrf
!= -1) {
1307 for (int i
= 0; i
< v
->implied_mrf_writes(inst
); i
++) {
1308 last_mrf_write
[inst
->base_mrf
+ i
] = n
;
1312 if (const unsigned mask
= inst
->flags_written()) {
1313 assert(mask
< (1 << ARRAY_SIZE(last_conditional_mod
)));
1315 for (unsigned i
= 0; i
< ARRAY_SIZE(last_conditional_mod
); i
++) {
1316 if (mask
& (1 << i
))
1317 last_conditional_mod
[i
] = n
;
1321 if (inst
->writes_accumulator_implicitly(v
->devinfo
)) {
1322 last_accumulator_write
= n
;
1326 free(last_grf_write
);
1330 vec4_instruction_scheduler::calculate_deps()
1332 schedule_node
*last_grf_write
[grf_count
];
1333 schedule_node
*last_mrf_write
[BRW_MAX_MRF(v
->devinfo
->gen
)];
1334 schedule_node
*last_conditional_mod
= NULL
;
1335 schedule_node
*last_accumulator_write
= NULL
;
1336 /* Fixed HW registers are assumed to be separate from the virtual
1337 * GRFs, so they can be tracked separately. We don't really write
1338 * to fixed GRFs much, so don't bother tracking them on a more
1341 schedule_node
*last_fixed_grf_write
= NULL
;
1343 memset(last_grf_write
, 0, sizeof(last_grf_write
));
1344 memset(last_mrf_write
, 0, sizeof(last_mrf_write
));
1346 /* top-to-bottom dependencies: RAW and WAW. */
1347 foreach_in_list(schedule_node
, n
, &instructions
) {
1348 vec4_instruction
*inst
= (vec4_instruction
*)n
->inst
;
1350 if (is_scheduling_barrier(inst
))
1351 add_barrier_deps(n
);
1353 /* read-after-write deps. */
1354 for (int i
= 0; i
< 3; i
++) {
1355 if (inst
->src
[i
].file
== VGRF
) {
1356 for (unsigned j
= 0; j
< regs_read(inst
, i
); ++j
)
1357 add_dep(last_grf_write
[inst
->src
[i
].nr
+ j
], n
);
1358 } else if (inst
->src
[i
].file
== FIXED_GRF
) {
1359 add_dep(last_fixed_grf_write
, n
);
1360 } else if (inst
->src
[i
].is_accumulator()) {
1361 assert(last_accumulator_write
);
1362 add_dep(last_accumulator_write
, n
);
1363 } else if (inst
->src
[i
].file
== ARF
) {
1364 add_barrier_deps(n
);
1368 if (inst
->reads_g0_implicitly())
1369 add_dep(last_fixed_grf_write
, n
);
1371 if (!inst
->is_send_from_grf()) {
1372 for (int i
= 0; i
< inst
->mlen
; i
++) {
1373 /* It looks like the MRF regs are released in the send
1374 * instruction once it's sent, not when the result comes
1377 add_dep(last_mrf_write
[inst
->base_mrf
+ i
], n
);
1381 if (inst
->reads_flag()) {
1382 assert(last_conditional_mod
);
1383 add_dep(last_conditional_mod
, n
);
1386 if (inst
->reads_accumulator_implicitly()) {
1387 assert(last_accumulator_write
);
1388 add_dep(last_accumulator_write
, n
);
1391 /* write-after-write deps. */
1392 if (inst
->dst
.file
== VGRF
) {
1393 for (unsigned j
= 0; j
< regs_written(inst
); ++j
) {
1394 add_dep(last_grf_write
[inst
->dst
.nr
+ j
], n
);
1395 last_grf_write
[inst
->dst
.nr
+ j
] = n
;
1397 } else if (inst
->dst
.file
== MRF
) {
1398 add_dep(last_mrf_write
[inst
->dst
.nr
], n
);
1399 last_mrf_write
[inst
->dst
.nr
] = n
;
1400 } else if (inst
->dst
.file
== FIXED_GRF
) {
1401 last_fixed_grf_write
= n
;
1402 } else if (inst
->dst
.is_accumulator()) {
1403 add_dep(last_accumulator_write
, n
);
1404 last_accumulator_write
= n
;
1405 } else if (inst
->dst
.file
== ARF
&& !inst
->dst
.is_null()) {
1406 add_barrier_deps(n
);
1409 if (inst
->mlen
> 0 && !inst
->is_send_from_grf()) {
1410 for (int i
= 0; i
< v
->implied_mrf_writes(inst
); i
++) {
1411 add_dep(last_mrf_write
[inst
->base_mrf
+ i
], n
);
1412 last_mrf_write
[inst
->base_mrf
+ i
] = n
;
1416 if (inst
->writes_flag()) {
1417 add_dep(last_conditional_mod
, n
, 0);
1418 last_conditional_mod
= n
;
1421 if (inst
->writes_accumulator_implicitly(v
->devinfo
) &&
1422 !inst
->dst
.is_accumulator()) {
1423 add_dep(last_accumulator_write
, n
);
1424 last_accumulator_write
= n
;
1428 /* bottom-to-top dependencies: WAR */
1429 memset(last_grf_write
, 0, sizeof(last_grf_write
));
1430 memset(last_mrf_write
, 0, sizeof(last_mrf_write
));
1431 last_conditional_mod
= NULL
;
1432 last_accumulator_write
= NULL
;
1433 last_fixed_grf_write
= NULL
;
1435 foreach_in_list_reverse_safe(schedule_node
, n
, &instructions
) {
1436 vec4_instruction
*inst
= (vec4_instruction
*)n
->inst
;
1438 /* write-after-read deps. */
1439 for (int i
= 0; i
< 3; i
++) {
1440 if (inst
->src
[i
].file
== VGRF
) {
1441 for (unsigned j
= 0; j
< regs_read(inst
, i
); ++j
)
1442 add_dep(n
, last_grf_write
[inst
->src
[i
].nr
+ j
]);
1443 } else if (inst
->src
[i
].file
== FIXED_GRF
) {
1444 add_dep(n
, last_fixed_grf_write
);
1445 } else if (inst
->src
[i
].is_accumulator()) {
1446 add_dep(n
, last_accumulator_write
);
1447 } else if (inst
->src
[i
].file
== ARF
) {
1448 add_barrier_deps(n
);
1452 if (!inst
->is_send_from_grf()) {
1453 for (int i
= 0; i
< inst
->mlen
; i
++) {
1454 /* It looks like the MRF regs are released in the send
1455 * instruction once it's sent, not when the result comes
1458 add_dep(n
, last_mrf_write
[inst
->base_mrf
+ i
], 2);
1462 if (inst
->reads_flag()) {
1463 add_dep(n
, last_conditional_mod
);
1466 if (inst
->reads_accumulator_implicitly()) {
1467 add_dep(n
, last_accumulator_write
);
1470 /* Update the things this instruction wrote, so earlier reads
1471 * can mark this as WAR dependency.
1473 if (inst
->dst
.file
== VGRF
) {
1474 for (unsigned j
= 0; j
< regs_written(inst
); ++j
)
1475 last_grf_write
[inst
->dst
.nr
+ j
] = n
;
1476 } else if (inst
->dst
.file
== MRF
) {
1477 last_mrf_write
[inst
->dst
.nr
] = n
;
1478 } else if (inst
->dst
.file
== FIXED_GRF
) {
1479 last_fixed_grf_write
= n
;
1480 } else if (inst
->dst
.is_accumulator()) {
1481 last_accumulator_write
= n
;
1482 } else if (inst
->dst
.file
== ARF
&& !inst
->dst
.is_null()) {
1483 add_barrier_deps(n
);
1486 if (inst
->mlen
> 0 && !inst
->is_send_from_grf()) {
1487 for (int i
= 0; i
< v
->implied_mrf_writes(inst
); i
++) {
1488 last_mrf_write
[inst
->base_mrf
+ i
] = n
;
1492 if (inst
->writes_flag()) {
1493 last_conditional_mod
= n
;
1496 if (inst
->writes_accumulator_implicitly(v
->devinfo
)) {
1497 last_accumulator_write
= n
;
1503 fs_instruction_scheduler::choose_instruction_to_schedule()
1505 schedule_node
*chosen
= NULL
;
1507 if (mode
== SCHEDULE_PRE
|| mode
== SCHEDULE_POST
) {
1508 int chosen_time
= 0;
1510 /* Of the instructions ready to execute or the closest to being ready,
1511 * choose the one most likely to unblock an early program exit, or
1512 * otherwise the oldest one.
1514 foreach_in_list(schedule_node
, n
, &instructions
) {
1516 exit_unblocked_time(n
) < exit_unblocked_time(chosen
) ||
1517 (exit_unblocked_time(n
) == exit_unblocked_time(chosen
) &&
1518 n
->unblocked_time
< chosen_time
)) {
1520 chosen_time
= n
->unblocked_time
;
1524 /* Before register allocation, we don't care about the latencies of
1525 * instructions. All we care about is reducing live intervals of
1526 * variables so that we can avoid register spilling, or get SIMD16
1527 * shaders which naturally do a better job of hiding instruction
1530 foreach_in_list(schedule_node
, n
, &instructions
) {
1531 fs_inst
*inst
= (fs_inst
*)n
->inst
;
1538 /* Most important: If we can definitely reduce register pressure, do
1541 int register_pressure_benefit
= get_register_pressure_benefit(n
->inst
);
1542 int chosen_register_pressure_benefit
=
1543 get_register_pressure_benefit(chosen
->inst
);
1545 if (register_pressure_benefit
> 0 &&
1546 register_pressure_benefit
> chosen_register_pressure_benefit
) {
1549 } else if (chosen_register_pressure_benefit
> 0 &&
1550 (register_pressure_benefit
<
1551 chosen_register_pressure_benefit
)) {
1555 if (mode
== SCHEDULE_PRE_LIFO
) {
1556 /* Prefer instructions that recently became available for
1557 * scheduling. These are the things that are most likely to
1558 * (eventually) make a variable dead and reduce register pressure.
1559 * Typical register pressure estimates don't work for us because
1560 * most of our pressure comes from texturing, where no single
1561 * instruction to schedule will make a vec4 value dead.
1563 if (n
->cand_generation
> chosen
->cand_generation
) {
1566 } else if (n
->cand_generation
< chosen
->cand_generation
) {
1570 /* On MRF-using chips, prefer non-SEND instructions. If we don't
1571 * do this, then because we prefer instructions that just became
1572 * candidates, we'll end up in a pattern of scheduling a SEND,
1573 * then the MRFs for the next SEND, then the next SEND, then the
1574 * MRFs, etc., without ever consuming the results of a send.
1576 if (v
->devinfo
->gen
< 7) {
1577 fs_inst
*chosen_inst
= (fs_inst
*)chosen
->inst
;
1579 /* We use size_written > 4 * exec_size as our test for the kind
1580 * of send instruction to avoid -- only sends generate many
1581 * regs, and a single-result send is probably actually reducing
1582 * register pressure.
1584 if (inst
->size_written
<= 4 * inst
->exec_size
&&
1585 chosen_inst
->size_written
> 4 * chosen_inst
->exec_size
) {
1588 } else if (inst
->size_written
> chosen_inst
->size_written
) {
1594 /* For instructions pushed on the cands list at the same time, prefer
1595 * the one with the highest delay to the end of the program. This is
1596 * most likely to have its values able to be consumed first (such as
1597 * for a large tree of lowered ubo loads, which appear reversed in
1598 * the instruction stream with respect to when they can be consumed).
1600 if (n
->delay
> chosen
->delay
) {
1603 } else if (n
->delay
< chosen
->delay
) {
1607 /* Prefer the node most likely to unblock an early program exit.
1609 if (exit_unblocked_time(n
) < exit_unblocked_time(chosen
)) {
1612 } else if (exit_unblocked_time(n
) > exit_unblocked_time(chosen
)) {
1616 /* If all other metrics are equal, we prefer the first instruction in
1617 * the list (program execution).
1626 vec4_instruction_scheduler::choose_instruction_to_schedule()
1628 schedule_node
*chosen
= NULL
;
1629 int chosen_time
= 0;
1631 /* Of the instructions ready to execute or the closest to being ready,
1632 * choose the oldest one.
1634 foreach_in_list(schedule_node
, n
, &instructions
) {
1635 if (!chosen
|| n
->unblocked_time
< chosen_time
) {
1637 chosen_time
= n
->unblocked_time
;
1645 fs_instruction_scheduler::issue_time(backend_instruction
*inst
)
1647 const unsigned overhead
= v
->bank_conflict_cycles((fs_inst
*)inst
);
1648 if (is_compressed((fs_inst
*)inst
))
1649 return 4 + overhead
;
1651 return 2 + overhead
;
1655 vec4_instruction_scheduler::issue_time(backend_instruction
*)
1657 /* We always execute as two vec4s in parallel. */
1662 instruction_scheduler::schedule_instructions(bblock_t
*block
)
1664 const struct gen_device_info
*devinfo
= bs
->devinfo
;
1666 if (!post_reg_alloc
)
1667 reg_pressure
= reg_pressure_in
[block
->num
];
1668 block_idx
= block
->num
;
1670 /* Remove non-DAG heads from the list. */
1671 foreach_in_list_safe(schedule_node
, n
, &instructions
) {
1672 if (n
->parent_count
!= 0)
1676 unsigned cand_generation
= 1;
1677 while (!instructions
.is_empty()) {
1678 schedule_node
*chosen
= choose_instruction_to_schedule();
1680 /* Schedule this instruction. */
1683 chosen
->inst
->exec_node::remove();
1684 block
->instructions
.push_tail(chosen
->inst
);
1685 instructions_to_schedule
--;
1687 if (!post_reg_alloc
) {
1688 reg_pressure
-= get_register_pressure_benefit(chosen
->inst
);
1689 update_register_pressure(chosen
->inst
);
1692 /* If we expected a delay for scheduling, then bump the clock to reflect
1693 * that. In reality, the hardware will switch to another hyperthread
1694 * and may not return to dispatching our thread for a while even after
1695 * we're unblocked. After this, we have the time when the chosen
1696 * instruction will start executing.
1698 time
= MAX2(time
, chosen
->unblocked_time
);
1700 /* Update the clock for how soon an instruction could start after the
1703 time
+= issue_time(chosen
->inst
);
1706 fprintf(stderr
, "clock %4d, scheduled: ", time
);
1707 bs
->dump_instruction(chosen
->inst
);
1708 if (!post_reg_alloc
)
1709 fprintf(stderr
, "(register pressure %d)\n", reg_pressure
);
1712 /* Now that we've scheduled a new instruction, some of its
1713 * children can be promoted to the list of instructions ready to
1714 * be scheduled. Update the children's unblocked time for this
1715 * DAG edge as we do so.
1717 for (int i
= chosen
->child_count
- 1; i
>= 0; i
--) {
1718 schedule_node
*child
= chosen
->children
[i
];
1720 child
->unblocked_time
= MAX2(child
->unblocked_time
,
1721 time
+ chosen
->child_latency
[i
]);
1724 fprintf(stderr
, "\tchild %d, %d parents: ", i
, child
->parent_count
);
1725 bs
->dump_instruction(child
->inst
);
1728 child
->cand_generation
= cand_generation
;
1729 child
->parent_count
--;
1730 if (child
->parent_count
== 0) {
1732 fprintf(stderr
, "\t\tnow available\n");
1734 instructions
.push_head(child
);
1739 /* Shared resource: the mathbox. There's one mathbox per EU on Gen6+
1740 * but it's more limited pre-gen6, so if we send something off to it then
1741 * the next math instruction isn't going to make progress until the first
1744 if (devinfo
->gen
< 6 && chosen
->inst
->is_math()) {
1745 foreach_in_list(schedule_node
, n
, &instructions
) {
1746 if (n
->inst
->is_math())
1747 n
->unblocked_time
= MAX2(n
->unblocked_time
,
1748 time
+ chosen
->latency
);
1753 assert(instructions_to_schedule
== 0);
1755 block
->cycle_count
= time
;
1758 static unsigned get_cycle_count(cfg_t
*cfg
)
1760 unsigned count
= 0, multiplier
= 1;
1761 foreach_block(block
, cfg
) {
1762 if (block
->start()->opcode
== BRW_OPCODE_DO
)
1763 multiplier
*= 10; /* assume that loops execute ~10 times */
1765 count
+= block
->cycle_count
* multiplier
;
1767 if (block
->end()->opcode
== BRW_OPCODE_WHILE
)
1775 instruction_scheduler::run(cfg_t
*cfg
)
1777 if (debug
&& !post_reg_alloc
) {
1778 fprintf(stderr
, "\nInstructions before scheduling (reg_alloc %d)\n",
1780 bs
->dump_instructions();
1783 if (!post_reg_alloc
)
1784 setup_liveness(cfg
);
1786 foreach_block(block
, cfg
) {
1787 if (reads_remaining
) {
1788 memset(reads_remaining
, 0,
1789 grf_count
* sizeof(*reads_remaining
));
1790 memset(hw_reads_remaining
, 0,
1791 hw_reg_count
* sizeof(*hw_reads_remaining
));
1792 memset(written
, 0, grf_count
* sizeof(*written
));
1794 foreach_inst_in_block(fs_inst
, inst
, block
)
1795 count_reads_remaining(inst
);
1798 add_insts_from_block(block
);
1805 schedule_instructions(block
);
1808 if (debug
&& !post_reg_alloc
) {
1809 fprintf(stderr
, "\nInstructions after scheduling (reg_alloc %d)\n",
1811 bs
->dump_instructions();
1814 cfg
->cycle_count
= get_cycle_count(cfg
);
1818 fs_visitor::schedule_instructions(instruction_scheduler_mode mode
)
1820 if (mode
!= SCHEDULE_POST
)
1821 calculate_live_intervals();
1824 if (mode
== SCHEDULE_POST
)
1825 grf_count
= grf_used
;
1827 grf_count
= alloc
.count
;
1829 fs_instruction_scheduler
sched(this, grf_count
, first_non_payload_grf
,
1830 cfg
->num_blocks
, mode
);
1833 invalidate_live_intervals();
1837 vec4_visitor::opt_schedule_instructions()
1839 vec4_instruction_scheduler
sched(this, prog_data
->total_grf
);
1842 invalidate_live_intervals();