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isl: Add support for multisample compression surfaces
[mesa.git] / src / intel / isl / isl.h
1 /*
2 * Copyright 2015 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 */
23
24 /**
25 * @file
26 * @brief Intel Surface Layout
27 *
28 * Header Layout
29 * -------------
30 * The header is ordered as:
31 * - forward declarations
32 * - macros that may be overridden at compile-time for specific gens
33 * - enums and constants
34 * - structs and unions
35 * - functions
36 */
37
38 #pragma once
39
40 #include <assert.h>
41 #include <stdbool.h>
42 #include <stdint.h>
43
44 #include "c99_compat.h"
45 #include "util/macros.h"
46
47 #ifdef __cplusplus
48 extern "C" {
49 #endif
50
51 struct brw_device_info;
52 struct brw_image_param;
53
54 #ifndef ISL_DEV_GEN
55 /**
56 * @brief Get the hardware generation of isl_device.
57 *
58 * You can define this as a compile-time constant in the CFLAGS. For example,
59 * `gcc -DISL_DEV_GEN(dev)=9 ...`.
60 */
61 #define ISL_DEV_GEN(__dev) ((__dev)->info->gen)
62 #define ISL_DEV_GEN_SANITIZE(__dev)
63 #else
64 #define ISL_DEV_GEN_SANITIZE(__dev) \
65 (assert(ISL_DEV_GEN(__dev) == (__dev)->info->gen))
66 #endif
67
68 #ifndef ISL_DEV_IS_HASWELL
69 /**
70 * @brief Get the hardware generation of isl_device.
71 *
72 * You can define this as a compile-time constant in the CFLAGS. For example,
73 * `gcc -DISL_DEV_GEN(dev)=9 ...`.
74 */
75 #define ISL_DEV_IS_HASWELL(__dev) ((__dev)->info->is_haswell)
76 #endif
77
78 #ifndef ISL_DEV_USE_SEPARATE_STENCIL
79 /**
80 * You can define this as a compile-time constant in the CFLAGS. For example,
81 * `gcc -DISL_DEV_USE_SEPARATE_STENCIL(dev)=1 ...`.
82 */
83 #define ISL_DEV_USE_SEPARATE_STENCIL(__dev) ((__dev)->use_separate_stencil)
84 #define ISL_DEV_USE_SEPARATE_STENCIL_SANITIZE(__dev)
85 #else
86 #define ISL_DEV_USE_SEPARATE_STENCIL_SANITIZE(__dev) \
87 (assert(ISL_DEV_USE_SEPARATE_STENCIL(__dev) == (__dev)->use_separate_stencil))
88 #endif
89
90 /**
91 * Hardware enumeration SURFACE_FORMAT.
92 *
93 * For the official list, see Broadwell PRM: Volume 2b: Command Reference:
94 * Enumerations: SURFACE_FORMAT.
95 */
96 enum isl_format {
97 ISL_FORMAT_R32G32B32A32_FLOAT = 0,
98 ISL_FORMAT_R32G32B32A32_SINT = 1,
99 ISL_FORMAT_R32G32B32A32_UINT = 2,
100 ISL_FORMAT_R32G32B32A32_UNORM = 3,
101 ISL_FORMAT_R32G32B32A32_SNORM = 4,
102 ISL_FORMAT_R64G64_FLOAT = 5,
103 ISL_FORMAT_R32G32B32X32_FLOAT = 6,
104 ISL_FORMAT_R32G32B32A32_SSCALED = 7,
105 ISL_FORMAT_R32G32B32A32_USCALED = 8,
106 ISL_FORMAT_R32G32B32A32_SFIXED = 32,
107 ISL_FORMAT_R64G64_PASSTHRU = 33,
108 ISL_FORMAT_R32G32B32_FLOAT = 64,
109 ISL_FORMAT_R32G32B32_SINT = 65,
110 ISL_FORMAT_R32G32B32_UINT = 66,
111 ISL_FORMAT_R32G32B32_UNORM = 67,
112 ISL_FORMAT_R32G32B32_SNORM = 68,
113 ISL_FORMAT_R32G32B32_SSCALED = 69,
114 ISL_FORMAT_R32G32B32_USCALED = 70,
115 ISL_FORMAT_R32G32B32_SFIXED = 80,
116 ISL_FORMAT_R16G16B16A16_UNORM = 128,
117 ISL_FORMAT_R16G16B16A16_SNORM = 129,
118 ISL_FORMAT_R16G16B16A16_SINT = 130,
119 ISL_FORMAT_R16G16B16A16_UINT = 131,
120 ISL_FORMAT_R16G16B16A16_FLOAT = 132,
121 ISL_FORMAT_R32G32_FLOAT = 133,
122 ISL_FORMAT_R32G32_SINT = 134,
123 ISL_FORMAT_R32G32_UINT = 135,
124 ISL_FORMAT_R32_FLOAT_X8X24_TYPELESS = 136,
125 ISL_FORMAT_X32_TYPELESS_G8X24_UINT = 137,
126 ISL_FORMAT_L32A32_FLOAT = 138,
127 ISL_FORMAT_R32G32_UNORM = 139,
128 ISL_FORMAT_R32G32_SNORM = 140,
129 ISL_FORMAT_R64_FLOAT = 141,
130 ISL_FORMAT_R16G16B16X16_UNORM = 142,
131 ISL_FORMAT_R16G16B16X16_FLOAT = 143,
132 ISL_FORMAT_A32X32_FLOAT = 144,
133 ISL_FORMAT_L32X32_FLOAT = 145,
134 ISL_FORMAT_I32X32_FLOAT = 146,
135 ISL_FORMAT_R16G16B16A16_SSCALED = 147,
136 ISL_FORMAT_R16G16B16A16_USCALED = 148,
137 ISL_FORMAT_R32G32_SSCALED = 149,
138 ISL_FORMAT_R32G32_USCALED = 150,
139 ISL_FORMAT_R32G32_FLOAT_LD = 151,
140 ISL_FORMAT_R32G32_SFIXED = 160,
141 ISL_FORMAT_R64_PASSTHRU = 161,
142 ISL_FORMAT_B8G8R8A8_UNORM = 192,
143 ISL_FORMAT_B8G8R8A8_UNORM_SRGB = 193,
144 ISL_FORMAT_R10G10B10A2_UNORM = 194,
145 ISL_FORMAT_R10G10B10A2_UNORM_SRGB = 195,
146 ISL_FORMAT_R10G10B10A2_UINT = 196,
147 ISL_FORMAT_R10G10B10_SNORM_A2_UNORM = 197,
148 ISL_FORMAT_R8G8B8A8_UNORM = 199,
149 ISL_FORMAT_R8G8B8A8_UNORM_SRGB = 200,
150 ISL_FORMAT_R8G8B8A8_SNORM = 201,
151 ISL_FORMAT_R8G8B8A8_SINT = 202,
152 ISL_FORMAT_R8G8B8A8_UINT = 203,
153 ISL_FORMAT_R16G16_UNORM = 204,
154 ISL_FORMAT_R16G16_SNORM = 205,
155 ISL_FORMAT_R16G16_SINT = 206,
156 ISL_FORMAT_R16G16_UINT = 207,
157 ISL_FORMAT_R16G16_FLOAT = 208,
158 ISL_FORMAT_B10G10R10A2_UNORM = 209,
159 ISL_FORMAT_B10G10R10A2_UNORM_SRGB = 210,
160 ISL_FORMAT_R11G11B10_FLOAT = 211,
161 ISL_FORMAT_R32_SINT = 214,
162 ISL_FORMAT_R32_UINT = 215,
163 ISL_FORMAT_R32_FLOAT = 216,
164 ISL_FORMAT_R24_UNORM_X8_TYPELESS = 217,
165 ISL_FORMAT_X24_TYPELESS_G8_UINT = 218,
166 ISL_FORMAT_L32_UNORM = 221,
167 ISL_FORMAT_A32_UNORM = 222,
168 ISL_FORMAT_L16A16_UNORM = 223,
169 ISL_FORMAT_I24X8_UNORM = 224,
170 ISL_FORMAT_L24X8_UNORM = 225,
171 ISL_FORMAT_A24X8_UNORM = 226,
172 ISL_FORMAT_I32_FLOAT = 227,
173 ISL_FORMAT_L32_FLOAT = 228,
174 ISL_FORMAT_A32_FLOAT = 229,
175 ISL_FORMAT_X8B8_UNORM_G8R8_SNORM = 230,
176 ISL_FORMAT_A8X8_UNORM_G8R8_SNORM = 231,
177 ISL_FORMAT_B8X8_UNORM_G8R8_SNORM = 232,
178 ISL_FORMAT_B8G8R8X8_UNORM = 233,
179 ISL_FORMAT_B8G8R8X8_UNORM_SRGB = 234,
180 ISL_FORMAT_R8G8B8X8_UNORM = 235,
181 ISL_FORMAT_R8G8B8X8_UNORM_SRGB = 236,
182 ISL_FORMAT_R9G9B9E5_SHAREDEXP = 237,
183 ISL_FORMAT_B10G10R10X2_UNORM = 238,
184 ISL_FORMAT_L16A16_FLOAT = 240,
185 ISL_FORMAT_R32_UNORM = 241,
186 ISL_FORMAT_R32_SNORM = 242,
187 ISL_FORMAT_R10G10B10X2_USCALED = 243,
188 ISL_FORMAT_R8G8B8A8_SSCALED = 244,
189 ISL_FORMAT_R8G8B8A8_USCALED = 245,
190 ISL_FORMAT_R16G16_SSCALED = 246,
191 ISL_FORMAT_R16G16_USCALED = 247,
192 ISL_FORMAT_R32_SSCALED = 248,
193 ISL_FORMAT_R32_USCALED = 249,
194 ISL_FORMAT_B5G6R5_UNORM = 256,
195 ISL_FORMAT_B5G6R5_UNORM_SRGB = 257,
196 ISL_FORMAT_B5G5R5A1_UNORM = 258,
197 ISL_FORMAT_B5G5R5A1_UNORM_SRGB = 259,
198 ISL_FORMAT_B4G4R4A4_UNORM = 260,
199 ISL_FORMAT_B4G4R4A4_UNORM_SRGB = 261,
200 ISL_FORMAT_R8G8_UNORM = 262,
201 ISL_FORMAT_R8G8_SNORM = 263,
202 ISL_FORMAT_R8G8_SINT = 264,
203 ISL_FORMAT_R8G8_UINT = 265,
204 ISL_FORMAT_R16_UNORM = 266,
205 ISL_FORMAT_R16_SNORM = 267,
206 ISL_FORMAT_R16_SINT = 268,
207 ISL_FORMAT_R16_UINT = 269,
208 ISL_FORMAT_R16_FLOAT = 270,
209 ISL_FORMAT_A8P8_UNORM_PALETTE0 = 271,
210 ISL_FORMAT_A8P8_UNORM_PALETTE1 = 272,
211 ISL_FORMAT_I16_UNORM = 273,
212 ISL_FORMAT_L16_UNORM = 274,
213 ISL_FORMAT_A16_UNORM = 275,
214 ISL_FORMAT_L8A8_UNORM = 276,
215 ISL_FORMAT_I16_FLOAT = 277,
216 ISL_FORMAT_L16_FLOAT = 278,
217 ISL_FORMAT_A16_FLOAT = 279,
218 ISL_FORMAT_L8A8_UNORM_SRGB = 280,
219 ISL_FORMAT_R5G5_SNORM_B6_UNORM = 281,
220 ISL_FORMAT_B5G5R5X1_UNORM = 282,
221 ISL_FORMAT_B5G5R5X1_UNORM_SRGB = 283,
222 ISL_FORMAT_R8G8_SSCALED = 284,
223 ISL_FORMAT_R8G8_USCALED = 285,
224 ISL_FORMAT_R16_SSCALED = 286,
225 ISL_FORMAT_R16_USCALED = 287,
226 ISL_FORMAT_P8A8_UNORM_PALETTE0 = 290,
227 ISL_FORMAT_P8A8_UNORM_PALETTE1 = 291,
228 ISL_FORMAT_A1B5G5R5_UNORM = 292,
229 ISL_FORMAT_A4B4G4R4_UNORM = 293,
230 ISL_FORMAT_L8A8_UINT = 294,
231 ISL_FORMAT_L8A8_SINT = 295,
232 ISL_FORMAT_R8_UNORM = 320,
233 ISL_FORMAT_R8_SNORM = 321,
234 ISL_FORMAT_R8_SINT = 322,
235 ISL_FORMAT_R8_UINT = 323,
236 ISL_FORMAT_A8_UNORM = 324,
237 ISL_FORMAT_I8_UNORM = 325,
238 ISL_FORMAT_L8_UNORM = 326,
239 ISL_FORMAT_P4A4_UNORM_PALETTE0 = 327,
240 ISL_FORMAT_A4P4_UNORM_PALETTE0 = 328,
241 ISL_FORMAT_R8_SSCALED = 329,
242 ISL_FORMAT_R8_USCALED = 330,
243 ISL_FORMAT_P8_UNORM_PALETTE0 = 331,
244 ISL_FORMAT_L8_UNORM_SRGB = 332,
245 ISL_FORMAT_P8_UNORM_PALETTE1 = 333,
246 ISL_FORMAT_P4A4_UNORM_PALETTE1 = 334,
247 ISL_FORMAT_A4P4_UNORM_PALETTE1 = 335,
248 ISL_FORMAT_Y8_UNORM = 336,
249 ISL_FORMAT_L8_UINT = 338,
250 ISL_FORMAT_L8_SINT = 339,
251 ISL_FORMAT_I8_UINT = 340,
252 ISL_FORMAT_I8_SINT = 341,
253 ISL_FORMAT_DXT1_RGB_SRGB = 384,
254 ISL_FORMAT_R1_UNORM = 385,
255 ISL_FORMAT_YCRCB_NORMAL = 386,
256 ISL_FORMAT_YCRCB_SWAPUVY = 387,
257 ISL_FORMAT_P2_UNORM_PALETTE0 = 388,
258 ISL_FORMAT_P2_UNORM_PALETTE1 = 389,
259 ISL_FORMAT_BC1_UNORM = 390,
260 ISL_FORMAT_BC2_UNORM = 391,
261 ISL_FORMAT_BC3_UNORM = 392,
262 ISL_FORMAT_BC4_UNORM = 393,
263 ISL_FORMAT_BC5_UNORM = 394,
264 ISL_FORMAT_BC1_UNORM_SRGB = 395,
265 ISL_FORMAT_BC2_UNORM_SRGB = 396,
266 ISL_FORMAT_BC3_UNORM_SRGB = 397,
267 ISL_FORMAT_MONO8 = 398,
268 ISL_FORMAT_YCRCB_SWAPUV = 399,
269 ISL_FORMAT_YCRCB_SWAPY = 400,
270 ISL_FORMAT_DXT1_RGB = 401,
271 ISL_FORMAT_FXT1 = 402,
272 ISL_FORMAT_R8G8B8_UNORM = 403,
273 ISL_FORMAT_R8G8B8_SNORM = 404,
274 ISL_FORMAT_R8G8B8_SSCALED = 405,
275 ISL_FORMAT_R8G8B8_USCALED = 406,
276 ISL_FORMAT_R64G64B64A64_FLOAT = 407,
277 ISL_FORMAT_R64G64B64_FLOAT = 408,
278 ISL_FORMAT_BC4_SNORM = 409,
279 ISL_FORMAT_BC5_SNORM = 410,
280 ISL_FORMAT_R16G16B16_FLOAT = 411,
281 ISL_FORMAT_R16G16B16_UNORM = 412,
282 ISL_FORMAT_R16G16B16_SNORM = 413,
283 ISL_FORMAT_R16G16B16_SSCALED = 414,
284 ISL_FORMAT_R16G16B16_USCALED = 415,
285 ISL_FORMAT_BC6H_SF16 = 417,
286 ISL_FORMAT_BC7_UNORM = 418,
287 ISL_FORMAT_BC7_UNORM_SRGB = 419,
288 ISL_FORMAT_BC6H_UF16 = 420,
289 ISL_FORMAT_PLANAR_420_8 = 421,
290 ISL_FORMAT_R8G8B8_UNORM_SRGB = 424,
291 ISL_FORMAT_ETC1_RGB8 = 425,
292 ISL_FORMAT_ETC2_RGB8 = 426,
293 ISL_FORMAT_EAC_R11 = 427,
294 ISL_FORMAT_EAC_RG11 = 428,
295 ISL_FORMAT_EAC_SIGNED_R11 = 429,
296 ISL_FORMAT_EAC_SIGNED_RG11 = 430,
297 ISL_FORMAT_ETC2_SRGB8 = 431,
298 ISL_FORMAT_R16G16B16_UINT = 432,
299 ISL_FORMAT_R16G16B16_SINT = 433,
300 ISL_FORMAT_R32_SFIXED = 434,
301 ISL_FORMAT_R10G10B10A2_SNORM = 435,
302 ISL_FORMAT_R10G10B10A2_USCALED = 436,
303 ISL_FORMAT_R10G10B10A2_SSCALED = 437,
304 ISL_FORMAT_R10G10B10A2_SINT = 438,
305 ISL_FORMAT_B10G10R10A2_SNORM = 439,
306 ISL_FORMAT_B10G10R10A2_USCALED = 440,
307 ISL_FORMAT_B10G10R10A2_SSCALED = 441,
308 ISL_FORMAT_B10G10R10A2_UINT = 442,
309 ISL_FORMAT_B10G10R10A2_SINT = 443,
310 ISL_FORMAT_R64G64B64A64_PASSTHRU = 444,
311 ISL_FORMAT_R64G64B64_PASSTHRU = 445,
312 ISL_FORMAT_ETC2_RGB8_PTA = 448,
313 ISL_FORMAT_ETC2_SRGB8_PTA = 449,
314 ISL_FORMAT_ETC2_EAC_RGBA8 = 450,
315 ISL_FORMAT_ETC2_EAC_SRGB8_A8 = 451,
316 ISL_FORMAT_R8G8B8_UINT = 456,
317 ISL_FORMAT_R8G8B8_SINT = 457,
318 ISL_FORMAT_RAW = 511,
319 ISL_FORMAT_ASTC_LDR_2D_4X4_U8SRGB = 512,
320 ISL_FORMAT_ASTC_LDR_2D_5X4_U8SRGB = 520,
321 ISL_FORMAT_ASTC_LDR_2D_5X5_U8SRGB = 521,
322 ISL_FORMAT_ASTC_LDR_2D_6X5_U8SRGB = 529,
323 ISL_FORMAT_ASTC_LDR_2D_6X6_U8SRGB = 530,
324 ISL_FORMAT_ASTC_LDR_2D_8X5_U8SRGB = 545,
325 ISL_FORMAT_ASTC_LDR_2D_8X6_U8SRGB = 546,
326 ISL_FORMAT_ASTC_LDR_2D_8X8_U8SRGB = 548,
327 ISL_FORMAT_ASTC_LDR_2D_10X5_U8SRGB = 561,
328 ISL_FORMAT_ASTC_LDR_2D_10X6_U8SRGB = 562,
329 ISL_FORMAT_ASTC_LDR_2D_10X8_U8SRGB = 564,
330 ISL_FORMAT_ASTC_LDR_2D_10X10_U8SRGB = 566,
331 ISL_FORMAT_ASTC_LDR_2D_12X10_U8SRGB = 574,
332 ISL_FORMAT_ASTC_LDR_2D_12X12_U8SRGB = 575,
333 ISL_FORMAT_ASTC_LDR_2D_4X4_FLT16 = 576,
334 ISL_FORMAT_ASTC_LDR_2D_5X4_FLT16 = 584,
335 ISL_FORMAT_ASTC_LDR_2D_5X5_FLT16 = 585,
336 ISL_FORMAT_ASTC_LDR_2D_6X5_FLT16 = 593,
337 ISL_FORMAT_ASTC_LDR_2D_6X6_FLT16 = 594,
338 ISL_FORMAT_ASTC_LDR_2D_8X5_FLT16 = 609,
339 ISL_FORMAT_ASTC_LDR_2D_8X6_FLT16 = 610,
340 ISL_FORMAT_ASTC_LDR_2D_8X8_FLT16 = 612,
341 ISL_FORMAT_ASTC_LDR_2D_10X5_FLT16 = 625,
342 ISL_FORMAT_ASTC_LDR_2D_10X6_FLT16 = 626,
343 ISL_FORMAT_ASTC_LDR_2D_10X8_FLT16 = 628,
344 ISL_FORMAT_ASTC_LDR_2D_10X10_FLT16 = 630,
345 ISL_FORMAT_ASTC_LDR_2D_12X10_FLT16 = 638,
346 ISL_FORMAT_ASTC_LDR_2D_12X12_FLT16 = 639,
347
348 /* The formats that follow are internal to ISL and as such don't have an
349 * explicit number. We'll just let the C compiler assign it for us. Any
350 * actual hardware formats *must* come before these in the list.
351 */
352
353 /* Formats for color compression surfaces */
354 ISL_FORMAT_HIZ,
355 ISL_FORMAT_MCS_2X,
356 ISL_FORMAT_MCS_4X,
357 ISL_FORMAT_MCS_8X,
358 ISL_FORMAT_MCS_16X,
359
360 /* Hardware doesn't understand this out-of-band value */
361 ISL_FORMAT_UNSUPPORTED = UINT16_MAX,
362 };
363
364 /**
365 * Numerical base type for channels of isl_format.
366 */
367 enum isl_base_type {
368 ISL_VOID,
369 ISL_RAW,
370 ISL_UNORM,
371 ISL_SNORM,
372 ISL_UFLOAT,
373 ISL_SFLOAT,
374 ISL_UFIXED,
375 ISL_SFIXED,
376 ISL_UINT,
377 ISL_SINT,
378 ISL_USCALED,
379 ISL_SSCALED,
380 };
381
382 /**
383 * Colorspace of isl_format.
384 */
385 enum isl_colorspace {
386 ISL_COLORSPACE_NONE = 0,
387 ISL_COLORSPACE_LINEAR,
388 ISL_COLORSPACE_SRGB,
389 ISL_COLORSPACE_YUV,
390 };
391
392 /**
393 * Texture compression mode of isl_format.
394 */
395 enum isl_txc {
396 ISL_TXC_NONE = 0,
397 ISL_TXC_DXT1,
398 ISL_TXC_DXT3,
399 ISL_TXC_DXT5,
400 ISL_TXC_FXT1,
401 ISL_TXC_RGTC1,
402 ISL_TXC_RGTC2,
403 ISL_TXC_BPTC,
404 ISL_TXC_ETC1,
405 ISL_TXC_ETC2,
406 ISL_TXC_ASTC,
407
408 /* Used for auxiliary surface formats */
409 ISL_TXC_HIZ,
410 ISL_TXC_MCS,
411 };
412
413 /**
414 * @brief Hardware tile mode
415 *
416 * WARNING: These values differ from the hardware enum values, which are
417 * unstable across hardware generations.
418 *
419 * Note that legacy Y tiling is ISL_TILING_Y0 instead of ISL_TILING_Y, to
420 * clearly distinguish it from Yf and Ys.
421 */
422 enum isl_tiling {
423 ISL_TILING_LINEAR = 0,
424 ISL_TILING_W,
425 ISL_TILING_X,
426 ISL_TILING_Y0, /**< Legacy Y tiling */
427 ISL_TILING_Yf, /**< Standard 4K tiling. The 'f' means "four". */
428 ISL_TILING_Ys, /**< Standard 64K tiling. The 's' means "sixty-four". */
429 ISL_TILING_HIZ, /**< Tiling format for HiZ surfaces */
430 };
431
432 /**
433 * @defgroup Tiling Flags
434 * @{
435 */
436 typedef uint32_t isl_tiling_flags_t;
437 #define ISL_TILING_LINEAR_BIT (1u << ISL_TILING_LINEAR)
438 #define ISL_TILING_W_BIT (1u << ISL_TILING_W)
439 #define ISL_TILING_X_BIT (1u << ISL_TILING_X)
440 #define ISL_TILING_Y0_BIT (1u << ISL_TILING_Y0)
441 #define ISL_TILING_Yf_BIT (1u << ISL_TILING_Yf)
442 #define ISL_TILING_Ys_BIT (1u << ISL_TILING_Ys)
443 #define ISL_TILING_HIZ_BIT (1u << ISL_TILING_HIZ)
444 #define ISL_TILING_ANY_MASK (~0u)
445 #define ISL_TILING_NON_LINEAR_MASK (~ISL_TILING_LINEAR_BIT)
446
447 /** Any Y tiling, including legacy Y tiling. */
448 #define ISL_TILING_ANY_Y_MASK (ISL_TILING_Y0_BIT | \
449 ISL_TILING_Yf_BIT | \
450 ISL_TILING_Ys_BIT)
451
452 /** The Skylake BSpec refers to Yf and Ys as "standard tiling formats". */
453 #define ISL_TILING_STD_Y_MASK (ISL_TILING_Yf_BIT | \
454 ISL_TILING_Ys_BIT)
455 /** @} */
456
457 /**
458 * @brief Logical dimension of surface.
459 *
460 * Note: There is no dimension for cube map surfaces. ISL interprets cube maps
461 * as 2D array surfaces.
462 */
463 enum isl_surf_dim {
464 ISL_SURF_DIM_1D,
465 ISL_SURF_DIM_2D,
466 ISL_SURF_DIM_3D,
467 };
468
469 /**
470 * @brief Physical layout of the surface's dimensions.
471 */
472 enum isl_dim_layout {
473 /**
474 * For details, see the G35 PRM >> Volume 1: Graphics Core >> Section
475 * 6.17.3: 2D Surfaces.
476 *
477 * On many gens, 1D surfaces share the same layout as 2D surfaces. From
478 * the G35 PRM >> Volume 1: Graphics Core >> Section 6.17.2: 1D Surfaces:
479 *
480 * One-dimensional surfaces are identical to 2D surfaces with height of
481 * one.
482 *
483 * @invariant isl_surf::phys_level0_sa::depth == 1
484 */
485 ISL_DIM_LAYOUT_GEN4_2D,
486
487 /**
488 * For details, see the G35 PRM >> Volume 1: Graphics Core >> Section
489 * 6.17.5: 3D Surfaces.
490 *
491 * @invariant isl_surf::phys_level0_sa::array_len == 1
492 */
493 ISL_DIM_LAYOUT_GEN4_3D,
494
495 /**
496 * For details, see the Skylake BSpec >> Memory Views >> Common Surface
497 * Formats >> Surface Layout and Tiling >> » 1D Surfaces.
498 */
499 ISL_DIM_LAYOUT_GEN9_1D,
500 };
501
502 /* TODO(chadv): Explain */
503 enum isl_array_pitch_span {
504 ISL_ARRAY_PITCH_SPAN_FULL,
505 ISL_ARRAY_PITCH_SPAN_COMPACT,
506 };
507
508 /**
509 * @defgroup Surface Usage
510 * @{
511 */
512 typedef uint64_t isl_surf_usage_flags_t;
513 #define ISL_SURF_USAGE_RENDER_TARGET_BIT (1u << 0)
514 #define ISL_SURF_USAGE_DEPTH_BIT (1u << 1)
515 #define ISL_SURF_USAGE_STENCIL_BIT (1u << 2)
516 #define ISL_SURF_USAGE_TEXTURE_BIT (1u << 3)
517 #define ISL_SURF_USAGE_CUBE_BIT (1u << 4)
518 #define ISL_SURF_USAGE_DISABLE_AUX_BIT (1u << 5)
519 #define ISL_SURF_USAGE_DISPLAY_BIT (1u << 6)
520 #define ISL_SURF_USAGE_DISPLAY_ROTATE_90_BIT (1u << 7)
521 #define ISL_SURF_USAGE_DISPLAY_ROTATE_180_BIT (1u << 8)
522 #define ISL_SURF_USAGE_DISPLAY_ROTATE_270_BIT (1u << 9)
523 #define ISL_SURF_USAGE_DISPLAY_FLIP_X_BIT (1u << 10)
524 #define ISL_SURF_USAGE_DISPLAY_FLIP_Y_BIT (1u << 11)
525 #define ISL_SURF_USAGE_STORAGE_BIT (1u << 12)
526 #define ISL_SURF_USAGE_HIZ_BIT (1u << 13)
527 #define ISL_SURF_USAGE_MCS_BIT (1u << 14)
528 /** @} */
529
530 /**
531 * @brief A channel select (also known as texture swizzle) value
532 */
533 enum isl_channel_select {
534 ISL_CHANNEL_SELECT_ZERO = 0,
535 ISL_CHANNEL_SELECT_ONE = 1,
536 ISL_CHANNEL_SELECT_RED = 4,
537 ISL_CHANNEL_SELECT_GREEN = 5,
538 ISL_CHANNEL_SELECT_BLUE = 6,
539 ISL_CHANNEL_SELECT_ALPHA = 7,
540 };
541
542 /**
543 * Identical to VkSampleCountFlagBits.
544 */
545 enum isl_sample_count {
546 ISL_SAMPLE_COUNT_1_BIT = 1u,
547 ISL_SAMPLE_COUNT_2_BIT = 2u,
548 ISL_SAMPLE_COUNT_4_BIT = 4u,
549 ISL_SAMPLE_COUNT_8_BIT = 8u,
550 ISL_SAMPLE_COUNT_16_BIT = 16u,
551 };
552 typedef uint32_t isl_sample_count_mask_t;
553
554 /**
555 * @brief Multisample Format
556 */
557 enum isl_msaa_layout {
558 /**
559 * @brief Suface is single-sampled.
560 */
561 ISL_MSAA_LAYOUT_NONE,
562
563 /**
564 * @brief [SNB+] Interleaved Multisample Format
565 *
566 * In this format, multiple samples are interleaved into each cacheline.
567 * In other words, the sample index is swizzled into the low 6 bits of the
568 * surface's virtual address space.
569 *
570 * For example, suppose the surface is legacy Y tiled, is 4x multisampled,
571 * and its pixel format is 32bpp. Then the first cacheline is arranged
572 * thus:
573 *
574 * (0,0,0) (0,1,0) (0,0,1) (1,0,1)
575 * (1,0,0) (1,1,0) (0,1,1) (1,1,1)
576 *
577 * (0,0,2) (1,0,2) (0,0,3) (1,0,3)
578 * (0,1,2) (1,1,2) (0,1,3) (1,1,3)
579 *
580 * The hardware docs refer to this format with multiple terms. In
581 * Sandybridge, this is the only multisample format; so no term is used.
582 * The Ivybridge docs refer to surfaces in this format as IMS (Interleaved
583 * Multisample Surface). Later hardware docs additionally refer to this
584 * format as MSFMT_DEPTH_STENCIL (because the format is deprecated for
585 * color surfaces).
586 *
587 * See the Sandybridge PRM, Volume 4, Part 1, Section 2.7 "Multisampled
588 * Surface Behavior".
589 *
590 * See the Ivybridge PRM, Volume 1, Part 1, Section 6.18.4.1 "Interleaved
591 * Multisampled Surfaces".
592 */
593 ISL_MSAA_LAYOUT_INTERLEAVED,
594
595 /**
596 * @brief [IVB+] Array Multisample Format
597 *
598 * In this format, the surface's physical layout resembles that of a
599 * 2D array surface.
600 *
601 * Suppose the multisample surface's logical extent is (w, h) and its
602 * sample count is N. Then surface's physical extent is the same as
603 * a singlesample 2D surface whose logical extent is (w, h) and array
604 * length is N. Array slice `i` contains the pixel values for sample
605 * index `i`.
606 *
607 * The Ivybridge docs refer to surfaces in this format as UMS
608 * (Uncompressed Multsample Layout) and CMS (Compressed Multisample
609 * Surface). The Broadwell docs additionally refer to this format as
610 * MSFMT_MSS (MSS=Multisample Surface Storage).
611 *
612 * See the Broadwell PRM, Volume 5 "Memory Views", Section "Uncompressed
613 * Multisample Surfaces".
614 *
615 * See the Broadwell PRM, Volume 5 "Memory Views", Section "Compressed
616 * Multisample Surfaces".
617 */
618 ISL_MSAA_LAYOUT_ARRAY,
619 };
620
621
622 struct isl_device {
623 const struct brw_device_info *info;
624 bool use_separate_stencil;
625 bool has_bit6_swizzling;
626 };
627
628 struct isl_extent2d {
629 union { uint32_t w, width; };
630 union { uint32_t h, height; };
631 };
632
633 struct isl_extent3d {
634 union { uint32_t w, width; };
635 union { uint32_t h, height; };
636 union { uint32_t d, depth; };
637 };
638
639 struct isl_extent4d {
640 union { uint32_t w, width; };
641 union { uint32_t h, height; };
642 union { uint32_t d, depth; };
643 union { uint32_t a, array_len; };
644 };
645
646 struct isl_channel_layout {
647 enum isl_base_type type;
648 uint8_t bits; /**< Size in bits */
649 };
650
651 /**
652 * Each format has 3D block extent (width, height, depth). The block extent of
653 * compressed formats is that of the format's compression block. For example,
654 * the block extent of ISL_FORMAT_ETC2_RGB8 is (w=4, h=4, d=1). The block
655 * extent of uncompressed pixel formats, such as ISL_FORMAT_R8G8B8A8_UNORM, is
656 * is (w=1, h=1, d=1).
657 */
658 struct isl_format_layout {
659 enum isl_format format;
660 const char *name;
661
662 uint16_t bpb; /**< Bits per block */
663 uint8_t bw; /**< Block width, in pixels */
664 uint8_t bh; /**< Block height, in pixels */
665 uint8_t bd; /**< Block depth, in pixels */
666
667 struct {
668 struct isl_channel_layout r; /**< Red channel */
669 struct isl_channel_layout g; /**< Green channel */
670 struct isl_channel_layout b; /**< Blue channel */
671 struct isl_channel_layout a; /**< Alpha channel */
672 struct isl_channel_layout l; /**< Luminance channel */
673 struct isl_channel_layout i; /**< Intensity channel */
674 struct isl_channel_layout p; /**< Palette channel */
675 } channels;
676
677 enum isl_colorspace colorspace;
678 enum isl_txc txc;
679 };
680
681 struct isl_tile_info {
682 enum isl_tiling tiling;
683
684 /** The logical size of the tile in units of surface elements
685 *
686 * This field determines how a given surface is cut up into tiles. It is
687 * used to compute the size of a surface in tiles and can be used to
688 * determine the location of the tile containing any given surface element.
689 * The exact value of this field depends heavily on the bits-per-block of
690 * the format being used.
691 */
692 struct isl_extent2d logical_extent_el;
693
694 /** The physical size of the tile in bytes and rows of bytes
695 *
696 * This field determines how the tiles of a surface are physically layed
697 * out in memory. The logical and physical tile extent are frequently the
698 * same but this is not always the case. For instance, a W-tile (which is
699 * always used with ISL_FORMAT_R8) has a logical size of 64el x 64el but
700 * its physical size is 128B x 32rows, the same as a Y-tile.
701 *
702 * @see isl_surf::row_pitch
703 */
704 struct isl_extent2d phys_extent_B;
705 };
706
707 /**
708 * @brief Input to surface initialization
709 *
710 * @invariant width >= 1
711 * @invariant height >= 1
712 * @invariant depth >= 1
713 * @invariant levels >= 1
714 * @invariant samples >= 1
715 * @invariant array_len >= 1
716 *
717 * @invariant if 1D then height == 1 and depth == 1 and samples == 1
718 * @invariant if 2D then depth == 1
719 * @invariant if 3D then array_len == 1 and samples == 1
720 */
721 struct isl_surf_init_info {
722 enum isl_surf_dim dim;
723 enum isl_format format;
724
725 uint32_t width;
726 uint32_t height;
727 uint32_t depth;
728 uint32_t levels;
729 uint32_t array_len;
730 uint32_t samples;
731
732 /** Lower bound for isl_surf::alignment, in bytes. */
733 uint32_t min_alignment;
734
735 /** Lower bound for isl_surf::pitch, in bytes. */
736 uint32_t min_pitch;
737
738 isl_surf_usage_flags_t usage;
739
740 /** Flags that alter how ISL selects isl_surf::tiling. */
741 isl_tiling_flags_t tiling_flags;
742 };
743
744 struct isl_surf {
745 enum isl_surf_dim dim;
746 enum isl_dim_layout dim_layout;
747 enum isl_msaa_layout msaa_layout;
748 enum isl_tiling tiling;
749 enum isl_format format;
750
751 /**
752 * Alignment of the upper-left sample of each subimage, in units of surface
753 * elements.
754 */
755 struct isl_extent3d image_alignment_el;
756
757 /**
758 * Logical extent of the surface's base level, in units of pixels. This is
759 * identical to the extent defined in isl_surf_init_info.
760 */
761 struct isl_extent4d logical_level0_px;
762
763 /**
764 * Physical extent of the surface's base level, in units of physical
765 * surface samples and aligned to the format's compression block.
766 *
767 * Consider isl_dim_layout as an operator that transforms a logical surface
768 * layout to a physical surface layout. Then
769 *
770 * logical_layout := (isl_surf::dim, isl_surf::logical_level0_px)
771 * isl_surf::phys_level0_sa := isl_surf::dim_layout * logical_layout
772 */
773 struct isl_extent4d phys_level0_sa;
774
775 uint32_t levels;
776 uint32_t samples;
777
778 /** Total size of the surface, in bytes. */
779 uint32_t size;
780
781 /** Required alignment for the surface's base address. */
782 uint32_t alignment;
783
784 /**
785 * The interpretation of this field depends on the value of
786 * isl_tile_info::physical_extent_B. In particular, the width of the
787 * surface in tiles is row_pitch / isl_tile_info::physical_extent_B.width
788 * and the distance in bytes between vertically adjacent tiles in the image
789 * is given by row_pitch * isl_tile_info::physical_extent_B.height.
790 *
791 * For linear images where isl_tile_info::physical_extent_B.height == 1,
792 * this cleanly reduces to being the distance, in bytes, between vertically
793 * adjacent surface elements.
794 *
795 * @see isl_tile_info::phys_extent_B;
796 */
797 uint32_t row_pitch;
798
799 /**
800 * Pitch between physical array slices, in rows of surface elements.
801 */
802 uint32_t array_pitch_el_rows;
803
804 enum isl_array_pitch_span array_pitch_span;
805
806 /** Copy of isl_surf_init_info::usage. */
807 isl_surf_usage_flags_t usage;
808 };
809
810 struct isl_view {
811 /**
812 * Indicates the usage of the particular view
813 *
814 * Normally, this is one bit. However, for a cube map texture, it
815 * should be ISL_SURF_USAGE_TEXTURE_BIT | ISL_SURF_USAGE_CUBE_BIT.
816 */
817 isl_surf_usage_flags_t usage;
818
819 /**
820 * The format to use in the view
821 *
822 * This may differ from the format of the actual isl_surf but must have
823 * the same block size.
824 */
825 enum isl_format format;
826
827 uint32_t base_level;
828 uint32_t levels;
829
830 /**
831 * Base array layer
832 *
833 * For cube maps, both base_array_layer and array_len should be
834 * specified in terms of 2-D layers and must be a multiple of 6.
835 */
836 uint32_t base_array_layer;
837 uint32_t array_len;
838
839 enum isl_channel_select channel_select[4];
840 };
841
842 union isl_color_value {
843 float f32[4];
844 uint32_t u32[4];
845 int32_t i32[4];
846 };
847
848 struct isl_surf_fill_state_info {
849 const struct isl_surf *surf;
850 const struct isl_view *view;
851
852 /**
853 * The address of the surface in GPU memory.
854 */
855 uint64_t address;
856
857 /**
858 * The Memory Object Control state for the filled surface state.
859 *
860 * The exact format of this value depends on hardware generation.
861 */
862 uint32_t mocs;
863
864 /**
865 * The clear color for this surface
866 *
867 * Valid values depend on hardware generation.
868 */
869 union isl_color_value clear_color;
870 };
871
872 struct isl_buffer_fill_state_info {
873 /**
874 * The address of the surface in GPU memory.
875 */
876 uint64_t address;
877
878 /**
879 * The size of the buffer
880 */
881 uint64_t size;
882
883 /**
884 * The Memory Object Control state for the filled surface state.
885 *
886 * The exact format of this value depends on hardware generation.
887 */
888 uint32_t mocs;
889
890 /**
891 * The format to use in the surface state
892 *
893 * This may differ from the format of the actual isl_surf but have the
894 * same block size.
895 */
896 enum isl_format format;
897
898 uint32_t stride;
899 };
900
901 extern const struct isl_format_layout isl_format_layouts[];
902
903 void
904 isl_device_init(struct isl_device *dev,
905 const struct brw_device_info *info,
906 bool has_bit6_swizzling);
907
908 isl_sample_count_mask_t ATTRIBUTE_CONST
909 isl_device_get_sample_counts(struct isl_device *dev);
910
911 static inline const struct isl_format_layout * ATTRIBUTE_CONST
912 isl_format_get_layout(enum isl_format fmt)
913 {
914 return &isl_format_layouts[fmt];
915 }
916
917 static inline const char * ATTRIBUTE_CONST
918 isl_format_get_name(enum isl_format fmt)
919 {
920 return isl_format_layouts[fmt].name;
921 }
922
923 bool isl_format_supports_rendering(const struct brw_device_info *devinfo,
924 enum isl_format format);
925 bool isl_format_supports_alpha_blending(const struct brw_device_info *devinfo,
926 enum isl_format format);
927 bool isl_format_supports_sampling(const struct brw_device_info *devinfo,
928 enum isl_format format);
929 bool isl_format_supports_filtering(const struct brw_device_info *devinfo,
930 enum isl_format format);
931 bool isl_format_supports_vertex_fetch(const struct brw_device_info *devinfo,
932 enum isl_format format);
933 bool isl_format_supports_lossless_compression(const struct brw_device_info *devinfo,
934 enum isl_format format);
935
936 bool isl_format_has_unorm_channel(enum isl_format fmt) ATTRIBUTE_CONST;
937 bool isl_format_has_snorm_channel(enum isl_format fmt) ATTRIBUTE_CONST;
938 bool isl_format_has_ufloat_channel(enum isl_format fmt) ATTRIBUTE_CONST;
939 bool isl_format_has_sfloat_channel(enum isl_format fmt) ATTRIBUTE_CONST;
940 bool isl_format_has_uint_channel(enum isl_format fmt) ATTRIBUTE_CONST;
941 bool isl_format_has_sint_channel(enum isl_format fmt) ATTRIBUTE_CONST;
942
943 static inline bool
944 isl_format_has_normalized_channel(enum isl_format fmt)
945 {
946 return isl_format_has_unorm_channel(fmt) ||
947 isl_format_has_snorm_channel(fmt);
948 }
949
950 static inline bool
951 isl_format_has_float_channel(enum isl_format fmt)
952 {
953 return isl_format_has_ufloat_channel(fmt) ||
954 isl_format_has_sfloat_channel(fmt);
955 }
956
957 static inline bool
958 isl_format_has_int_channel(enum isl_format fmt)
959 {
960 return isl_format_has_uint_channel(fmt) ||
961 isl_format_has_sint_channel(fmt);
962 }
963
964 unsigned isl_format_get_num_channels(enum isl_format fmt);
965
966 static inline bool
967 isl_format_is_compressed(enum isl_format fmt)
968 {
969 const struct isl_format_layout *fmtl = isl_format_get_layout(fmt);
970
971 return fmtl->txc != ISL_TXC_NONE;
972 }
973
974 static inline bool
975 isl_format_has_bc_compression(enum isl_format fmt)
976 {
977 switch (isl_format_get_layout(fmt)->txc) {
978 case ISL_TXC_DXT1:
979 case ISL_TXC_DXT3:
980 case ISL_TXC_DXT5:
981 return true;
982 case ISL_TXC_NONE:
983 case ISL_TXC_FXT1:
984 case ISL_TXC_RGTC1:
985 case ISL_TXC_RGTC2:
986 case ISL_TXC_BPTC:
987 case ISL_TXC_ETC1:
988 case ISL_TXC_ETC2:
989 case ISL_TXC_ASTC:
990 return false;
991
992 case ISL_TXC_HIZ:
993 case ISL_TXC_MCS:
994 unreachable("Should not be called on an aux surface");
995 }
996
997 unreachable("bad texture compression mode");
998 return false;
999 }
1000
1001 static inline bool
1002 isl_format_is_yuv(enum isl_format fmt)
1003 {
1004 const struct isl_format_layout *fmtl = isl_format_get_layout(fmt);
1005
1006 return fmtl->colorspace == ISL_COLORSPACE_YUV;
1007 }
1008
1009 static inline bool
1010 isl_format_block_is_1x1x1(enum isl_format fmt)
1011 {
1012 const struct isl_format_layout *fmtl = isl_format_get_layout(fmt);
1013
1014 return fmtl->bw == 1 && fmtl->bh == 1 && fmtl->bd == 1;
1015 }
1016
1017 static inline bool
1018 isl_format_is_rgb(enum isl_format fmt)
1019 {
1020 return isl_format_layouts[fmt].channels.r.bits > 0 &&
1021 isl_format_layouts[fmt].channels.g.bits > 0 &&
1022 isl_format_layouts[fmt].channels.b.bits > 0 &&
1023 isl_format_layouts[fmt].channels.a.bits == 0;
1024 }
1025
1026 enum isl_format isl_format_rgb_to_rgba(enum isl_format rgb) ATTRIBUTE_CONST;
1027 enum isl_format isl_format_rgb_to_rgbx(enum isl_format rgb) ATTRIBUTE_CONST;
1028
1029 bool isl_is_storage_image_format(enum isl_format fmt);
1030
1031 enum isl_format
1032 isl_lower_storage_image_format(const struct brw_device_info *devinfo,
1033 enum isl_format fmt);
1034
1035 /* Returns true if this hardware supports typed load/store on a format with
1036 * the same size as the given format.
1037 */
1038 bool
1039 isl_has_matching_typed_storage_image_format(const struct brw_device_info *devinfo,
1040 enum isl_format fmt);
1041
1042 static inline bool
1043 isl_tiling_is_any_y(enum isl_tiling tiling)
1044 {
1045 return (1u << tiling) & ISL_TILING_ANY_MASK;
1046 }
1047
1048 static inline bool
1049 isl_tiling_is_std_y(enum isl_tiling tiling)
1050 {
1051 return (1u << tiling) & ISL_TILING_STD_Y_MASK;
1052 }
1053
1054 bool
1055 isl_tiling_get_info(const struct isl_device *dev,
1056 enum isl_tiling tiling,
1057 uint32_t format_bpb,
1058 struct isl_tile_info *info);
1059 bool
1060 isl_surf_choose_tiling(const struct isl_device *dev,
1061 const struct isl_surf_init_info *restrict info,
1062 enum isl_tiling *tiling);
1063
1064 static inline bool
1065 isl_surf_usage_is_display(isl_surf_usage_flags_t usage)
1066 {
1067 return usage & ISL_SURF_USAGE_DISPLAY_BIT;
1068 }
1069
1070 static inline bool
1071 isl_surf_usage_is_depth(isl_surf_usage_flags_t usage)
1072 {
1073 return usage & ISL_SURF_USAGE_DEPTH_BIT;
1074 }
1075
1076 static inline bool
1077 isl_surf_usage_is_stencil(isl_surf_usage_flags_t usage)
1078 {
1079 return usage & ISL_SURF_USAGE_STENCIL_BIT;
1080 }
1081
1082 static inline bool
1083 isl_surf_usage_is_depth_and_stencil(isl_surf_usage_flags_t usage)
1084 {
1085 return (usage & ISL_SURF_USAGE_DEPTH_BIT) &&
1086 (usage & ISL_SURF_USAGE_STENCIL_BIT);
1087 }
1088
1089 static inline bool
1090 isl_surf_usage_is_depth_or_stencil(isl_surf_usage_flags_t usage)
1091 {
1092 return usage & (ISL_SURF_USAGE_DEPTH_BIT | ISL_SURF_USAGE_STENCIL_BIT);
1093 }
1094
1095 static inline bool
1096 isl_surf_info_is_z16(const struct isl_surf_init_info *info)
1097 {
1098 return (info->usage & ISL_SURF_USAGE_DEPTH_BIT) &&
1099 (info->format == ISL_FORMAT_R16_UNORM);
1100 }
1101
1102 static inline bool
1103 isl_surf_info_is_z32_float(const struct isl_surf_init_info *info)
1104 {
1105 return (info->usage & ISL_SURF_USAGE_DEPTH_BIT) &&
1106 (info->format == ISL_FORMAT_R32_FLOAT);
1107 }
1108
1109 static inline struct isl_extent2d
1110 isl_extent2d(uint32_t width, uint32_t height)
1111 {
1112 struct isl_extent2d e = { { 0 } };
1113
1114 e.width = width;
1115 e.height = height;
1116
1117 return e;
1118 }
1119
1120 static inline struct isl_extent3d
1121 isl_extent3d(uint32_t width, uint32_t height, uint32_t depth)
1122 {
1123 struct isl_extent3d e = { { 0 } };
1124
1125 e.width = width;
1126 e.height = height;
1127 e.depth = depth;
1128
1129 return e;
1130 }
1131
1132 static inline struct isl_extent4d
1133 isl_extent4d(uint32_t width, uint32_t height, uint32_t depth,
1134 uint32_t array_len)
1135 {
1136 struct isl_extent4d e = { { 0 } };
1137
1138 e.width = width;
1139 e.height = height;
1140 e.depth = depth;
1141 e.array_len = array_len;
1142
1143 return e;
1144 }
1145
1146 #define isl_surf_init(dev, surf, ...) \
1147 isl_surf_init_s((dev), (surf), \
1148 &(struct isl_surf_init_info) { __VA_ARGS__ });
1149
1150 bool
1151 isl_surf_init_s(const struct isl_device *dev,
1152 struct isl_surf *surf,
1153 const struct isl_surf_init_info *restrict info);
1154
1155 void
1156 isl_surf_get_tile_info(const struct isl_device *dev,
1157 const struct isl_surf *surf,
1158 struct isl_tile_info *tile_info);
1159
1160 #define isl_surf_fill_state(dev, state, ...) \
1161 isl_surf_fill_state_s((dev), (state), \
1162 &(struct isl_surf_fill_state_info) { __VA_ARGS__ });
1163
1164 void
1165 isl_surf_fill_state_s(const struct isl_device *dev, void *state,
1166 const struct isl_surf_fill_state_info *restrict info);
1167
1168 #define isl_buffer_fill_state(dev, state, ...) \
1169 isl_buffer_fill_state_s((dev), (state), \
1170 &(struct isl_buffer_fill_state_info) { __VA_ARGS__ });
1171
1172 void
1173 isl_buffer_fill_state_s(const struct isl_device *dev, void *state,
1174 const struct isl_buffer_fill_state_info *restrict info);
1175
1176 void
1177 isl_surf_fill_image_param(const struct isl_device *dev,
1178 struct brw_image_param *param,
1179 const struct isl_surf *surf,
1180 const struct isl_view *view);
1181
1182 void
1183 isl_buffer_fill_image_param(const struct isl_device *dev,
1184 struct brw_image_param *param,
1185 enum isl_format format,
1186 uint64_t size);
1187
1188 /**
1189 * Alignment of the upper-left sample of each subimage, in units of surface
1190 * elements.
1191 */
1192 static inline struct isl_extent3d
1193 isl_surf_get_image_alignment_el(const struct isl_surf *surf)
1194 {
1195 return surf->image_alignment_el;
1196 }
1197
1198 /**
1199 * Alignment of the upper-left sample of each subimage, in units of surface
1200 * samples.
1201 */
1202 static inline struct isl_extent3d
1203 isl_surf_get_image_alignment_sa(const struct isl_surf *surf)
1204 {
1205 const struct isl_format_layout *fmtl = isl_format_get_layout(surf->format);
1206
1207 return isl_extent3d(fmtl->bw * surf->image_alignment_el.w,
1208 fmtl->bh * surf->image_alignment_el.h,
1209 fmtl->bd * surf->image_alignment_el.d);
1210 }
1211
1212 /**
1213 * Pitch between vertically adjacent surface elements, in bytes.
1214 */
1215 static inline uint32_t
1216 isl_surf_get_row_pitch(const struct isl_surf *surf)
1217 {
1218 return surf->row_pitch;
1219 }
1220
1221 /**
1222 * Pitch between vertically adjacent surface elements, in units of surface elements.
1223 */
1224 static inline uint32_t
1225 isl_surf_get_row_pitch_el(const struct isl_surf *surf)
1226 {
1227 const struct isl_format_layout *fmtl = isl_format_get_layout(surf->format);
1228
1229 assert(surf->row_pitch % (fmtl->bpb / 8) == 0);
1230 return surf->row_pitch / (fmtl->bpb / 8);
1231 }
1232
1233 /**
1234 * Pitch between physical array slices, in rows of surface elements.
1235 */
1236 static inline uint32_t
1237 isl_surf_get_array_pitch_el_rows(const struct isl_surf *surf)
1238 {
1239 return surf->array_pitch_el_rows;
1240 }
1241
1242 /**
1243 * Pitch between physical array slices, in units of surface elements.
1244 */
1245 static inline uint32_t
1246 isl_surf_get_array_pitch_el(const struct isl_surf *surf)
1247 {
1248 return isl_surf_get_array_pitch_el_rows(surf) *
1249 isl_surf_get_row_pitch_el(surf);
1250 }
1251
1252 /**
1253 * Pitch between physical array slices, in rows of surface samples.
1254 */
1255 static inline uint32_t
1256 isl_surf_get_array_pitch_sa_rows(const struct isl_surf *surf)
1257 {
1258 const struct isl_format_layout *fmtl = isl_format_get_layout(surf->format);
1259 return fmtl->bh * isl_surf_get_array_pitch_el_rows(surf);
1260 }
1261
1262 /**
1263 * Pitch between physical array slices, in bytes.
1264 */
1265 static inline uint32_t
1266 isl_surf_get_array_pitch(const struct isl_surf *surf)
1267 {
1268 return isl_surf_get_array_pitch_sa_rows(surf) * surf->row_pitch;
1269 }
1270
1271 /**
1272 * Calculate the offset, in units of surface elements, to a subimage in the
1273 * surface.
1274 *
1275 * @invariant level < surface levels
1276 * @invariant logical_array_layer < logical array length of surface
1277 * @invariant logical_z_offset_px < logical depth of surface at level
1278 */
1279 void
1280 isl_surf_get_image_offset_el(const struct isl_surf *surf,
1281 uint32_t level,
1282 uint32_t logical_array_layer,
1283 uint32_t logical_z_offset_px,
1284 uint32_t *x_offset_el,
1285 uint32_t *y_offset_el);
1286
1287 /**
1288 * @brief Calculate the intratile offsets to a surface.
1289 *
1290 * In @a base_address_offset return the offset from the base of the surface to
1291 * the base address of the first tile of the subimage. In @a x_offset_B and
1292 * @a y_offset_rows, return the offset, in units of bytes and rows, from the
1293 * tile's base to the subimage's first surface element. The x and y offsets
1294 * are intratile offsets; that is, they do not exceed the boundary of the
1295 * surface's tiling format.
1296 */
1297 void
1298 isl_tiling_get_intratile_offset_el(const struct isl_device *dev,
1299 enum isl_tiling tiling,
1300 uint8_t bs,
1301 uint32_t row_pitch,
1302 uint32_t total_x_offset_B,
1303 uint32_t total_y_offset_rows,
1304 uint32_t *base_address_offset,
1305 uint32_t *x_offset_B,
1306 uint32_t *y_offset_rows);
1307
1308 /**
1309 * @brief Get value of 3DSTATE_DEPTH_BUFFER.SurfaceFormat
1310 *
1311 * @pre surf->usage has ISL_SURF_USAGE_DEPTH_BIT
1312 * @pre surf->format must be a valid format for depth surfaces
1313 */
1314 uint32_t
1315 isl_surf_get_depth_format(const struct isl_device *dev,
1316 const struct isl_surf *surf);
1317
1318 #ifdef __cplusplus
1319 }
1320 #endif