3 * Copyright © 2018 Intel Corporation
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
21 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
31 #define YYLTYPE YYLTYPE
32 typedef struct YYLTYPE
48 message(enum message_level level, YYLTYPE *location,
51 static const char *level_str[] = { "warning", "error" };
55 fprintf(stderr, "%s:%d:%d: %s: ", input_filename,
57 location->first_column, level_str[level]);
59 fprintf(stderr, "%s:%s: ", input_filename, level_str[level]);
62 vfprintf(stderr, fmt, args);
66 #define warn(flag, l, fmt, ...) \
68 if (warning_flags & WARN_ ## flag) \
69 message(WARN, l, fmt, ## __VA_ARGS__); \
72 #define error(l, fmt, ...) \
74 message(ERROR, l, fmt, ## __VA_ARGS__); \
78 isPowerofTwo(unsigned int x)
80 return x && (!(x & (x - 1)));
84 set_direct_src_operand(struct brw_reg *reg, int type)
86 return brw_reg(reg->file,
100 i965_asm_unary_instruction(int opcode, struct brw_codegen *p,
101 struct brw_reg dest, struct brw_reg src0)
104 case BRW_OPCODE_BFREV:
105 brw_BFREV(p, dest, src0);
107 case BRW_OPCODE_CBIT:
108 brw_CBIT(p, dest, src0);
110 case BRW_OPCODE_F32TO16:
111 brw_F32TO16(p, dest, src0);
113 case BRW_OPCODE_F16TO32:
114 brw_F16TO32(p, dest, src0);
117 brw_MOV(p, dest, src0);
120 brw_FBL(p, dest, src0);
123 brw_FRC(p, dest, src0);
126 brw_FBH(p, dest, src0);
129 brw_NOT(p, dest, src0);
131 case BRW_OPCODE_RNDE:
132 brw_RNDE(p, dest, src0);
134 case BRW_OPCODE_RNDZ:
135 brw_RNDZ(p, dest, src0);
137 case BRW_OPCODE_RNDD:
138 brw_RNDD(p, dest, src0);
141 brw_LZD(p, dest, src0);
144 brw_DIM(p, dest, src0);
146 case BRW_OPCODE_RNDU:
147 fprintf(stderr, "Opcode BRW_OPCODE_RNDU unhandled\n");
150 fprintf(stderr, "Unsupported unary opcode\n");
155 i965_asm_binary_instruction(int opcode,
156 struct brw_codegen *p,
162 case BRW_OPCODE_ADDC:
163 brw_ADDC(p, dest, src0, src1);
165 case BRW_OPCODE_BFI1:
166 brw_BFI1(p, dest, src0, src1);
169 brw_DP2(p, dest, src0, src1);
172 brw_DP3(p, dest, src0, src1);
175 brw_DP4(p, dest, src0, src1);
178 brw_DPH(p, dest, src0, src1);
180 case BRW_OPCODE_LINE:
181 brw_LINE(p, dest, src0, src1);
184 brw_MAC(p, dest, src0, src1);
186 case BRW_OPCODE_MACH:
187 brw_MACH(p, dest, src0, src1);
190 brw_PLN(p, dest, src0, src1);
193 brw_ROL(p, dest, src0, src1);
196 brw_ROR(p, dest, src0, src1);
198 case BRW_OPCODE_SAD2:
199 fprintf(stderr, "Opcode BRW_OPCODE_SAD2 unhandled\n");
201 case BRW_OPCODE_SADA2:
202 fprintf(stderr, "Opcode BRW_OPCODE_SADA2 unhandled\n");
204 case BRW_OPCODE_SUBB:
205 brw_SUBB(p, dest, src0, src1);
208 brw_ADD(p, dest, src0, src1);
211 /* Third parameter is conditional modifier
212 * which gets updated later
214 brw_CMP(p, dest, 0, src0, src1);
217 brw_AND(p, dest, src0, src1);
220 brw_ASR(p, dest, src0, src1);
223 brw_AVG(p, dest, src0, src1);
226 brw_OR(p, dest, src0, src1);
229 brw_SEL(p, dest, src0, src1);
232 brw_SHL(p, dest, src0, src1);
235 brw_SHR(p, dest, src0, src1);
238 brw_XOR(p, dest, src0, src1);
241 brw_MUL(p, dest, src0, src1);
244 fprintf(stderr, "Unsupported binary opcode\n");
249 i965_asm_ternary_instruction(int opcode,
250 struct brw_codegen *p,
258 brw_MAD(p, dest, src0, src1, src2);
260 case BRW_OPCODE_CSEL:
261 brw_CSEL(p, dest, src0, src1, src2);
264 brw_LRP(p, dest, src0, src1, src2);
267 brw_BFE(p, dest, src0, src1, src2);
269 case BRW_OPCODE_BFI2:
270 brw_BFI2(p, dest, src0, src1, src2);
273 fprintf(stderr, "Unsupported ternary opcode\n");
278 i965_asm_set_instruction_options(struct brw_codegen *p,
279 struct options options)
281 brw_inst_set_access_mode(p->devinfo, brw_last_inst,
282 options.access_mode);
283 brw_inst_set_mask_control(p->devinfo, brw_last_inst,
284 options.mask_control);
285 brw_inst_set_thread_control(p->devinfo, brw_last_inst,
286 options.thread_control);
287 brw_inst_set_no_dd_check(p->devinfo, brw_last_inst,
288 options.no_dd_check);
289 brw_inst_set_no_dd_clear(p->devinfo, brw_last_inst,
290 options.no_dd_clear);
291 brw_inst_set_debug_control(p->devinfo, brw_last_inst,
292 options.debug_control);
293 if (p->devinfo->gen >= 6)
294 brw_inst_set_acc_wr_control(p->devinfo, brw_last_inst,
295 options.acc_wr_control);
296 brw_inst_set_cmpt_control(p->devinfo, brw_last_inst,
301 i965_asm_set_dst_nr(struct brw_codegen *p,
303 struct options options)
305 if (p->devinfo->gen <= 6) {
306 if (reg->file == BRW_MESSAGE_REGISTER_FILE &&
307 options.qtr_ctrl == BRW_COMPRESSION_COMPRESSED &&
309 reg->nr |= BRW_MRF_COMPR4;
322 unsigned long long int llint;
324 enum brw_reg_type reg_type;
325 struct brw_codegen *program;
326 struct predicate predicate;
327 struct condition condition;
328 struct options options;
329 brw_inst *instruction;
339 %token LSQUARE RSQUARE
344 %token <integer> TYPE_B TYPE_UB
345 %token <integer> TYPE_W TYPE_UW
346 %token <integer> TYPE_D TYPE_UD
347 %token <integer> TYPE_Q TYPE_UQ
348 %token <integer> TYPE_V TYPE_UV
349 %token <integer> TYPE_F TYPE_HF
350 %token <integer> TYPE_DF TYPE_NF
351 %token <integer> TYPE_VF
354 %token <integer> ADD ADD3 ADDC AND ASR AVG
355 %token <integer> BFE BFI1 BFI2 BFB BFREV BRC BRD BREAK
356 %token <integer> CALL CALLA CASE CBIT CMP CMPN CONT CSEL
357 %token <integer> DIM DO DPAS DPASW DP2 DP3 DP4 DP4A DPH
358 %token <integer> ELSE ENDIF F16TO32 F32TO16 FBH FBL FORK FRC
359 %token <integer> GOTO
360 %token <integer> HALT
361 %token <integer> IF IFF ILLEGAL
362 %token <integer> JMPI JOIN
363 %token <integer> LINE LRP LZD
364 %token <integer> MAC MACH MAD MADM MOV MOVI MUL MREST MSAVE
365 %token <integer> NENOP NOP NOT
367 %token <integer> PLN POP PUSH
368 %token <integer> RET RNDD RNDE RNDU RNDZ ROL ROR
369 %token <integer> SAD2 SADA2 SEL SEND SENDC SENDS SENDSC SHL SHR SMOV SUBB SYNC
370 %token <integer> WAIT WHILE
373 /* extended math functions */
374 %token <integer> COS EXP FDIV INV INVM INTDIV INTDIVMOD INTMOD LOG POW RSQ
375 %token <integer> RSQRTM SIN SINCOS SQRT
377 /* shared functions for send */
378 %token CONST CRE DATA DP_DATA_1 GATEWAY MATH PIXEL_INTERP READ RENDER SAMPLER
379 %token THREAD_SPAWNER URB VME WRITE DP_SAMPLER
381 /* Conditional modifiers */
382 %token <integer> EQUAL GREATER GREATER_EQUAL LESS LESS_EQUAL NOT_EQUAL
383 %token <integer> NOT_ZERO OVERFLOW UNORDERED ZERO
385 /* register Access Modes */
386 %token ALIGN1 ALIGN16
388 /* accumulator write control */
391 /* compaction control */
394 /* compression control */
395 %token COMPR COMPR4 SECHALF
397 /* mask control (WeCtrl) */
403 /* dependency control */
404 %token NODDCLR NODDCHK
412 /* predicate control */
413 %token <integer> ANYV ALLV ANY2H ALL2H ANY4H ALL4H ANY8H ALL8H ANY16H ALL16H
414 %token <integer> ANY32H ALL32H
416 /* round instructions */
417 %token <integer> ROUND_INCREMENT
426 %token QTR_2Q QTR_3Q QTR_4Q QTR_2H QTR_2N QTR_3N QTR_4N QTR_5N
427 %token QTR_6N QTR_7N QTR_8N
430 %token <integer> X Y Z W
433 %token GENREGFILE MSGREGFILE
435 /* vertical stride in register region */
439 %token <integer> GENREG MSGREG ADDRREG ACCREG FLAGREG NOTIFYREG STATEREG
440 %token <integer> CONTROLREG IPREG PERFORMANCEREG THREADREG CHANNELENABLEREG
441 %token <integer> MASKREG
443 %token <integer> INTEGER
447 %precedence SUBREGNUM
450 %precedence EMPTYEXECSIZE
453 %type <integer> execsize simple_int exp
456 /* predicate control */
457 %type <integer> predctrl predstate
458 %type <predicate> predicate
460 /* conditional modifier */
461 %type <condition> cond_mod
462 %type <integer> condModifiers
464 /* instruction options */
465 %type <options> instoptions instoption_list
466 %type <integer> instoption
469 %type <integer> writemask_x writemask_y writemask_z writemask_w
470 %type <integer> writemask
473 %type <reg> dst dstoperand dstoperandex dstoperandex_typed dstreg
474 %type <integer> dstregion
476 %type <integer> saturate relativelocation rellocation
477 %type <reg> relativelocation2
480 %type <reg> directsrcoperand directsrcaccoperand indirectsrcoperand srcacc
481 %type <reg> srcarcoperandex srcaccimm srcarcoperandex_typed srcimm
482 %type <reg> indirectgenreg indirectregion
483 %type <reg> immreg src reg32 payload directgenreg_list addrparam region
484 %type <reg> region_wh directgenreg directmsgreg indirectmsgreg
485 %type <integer> swizzle
488 %type <reg> accreg addrreg channelenablereg controlreg flagreg ipreg
489 %type <reg> notifyreg nullreg performancereg threadcontrolreg statereg maskreg
490 %type <integer> subregnum
493 %type <reg_type> reg_type imm_type
495 /* immediate values */
498 /* instruction opcodes */
499 %type <integer> unaryopcodes binaryopcodes binaryaccopcodes ternaryopcodes
500 %type <integer> sendop
501 %type <instruction> sendopcode
503 %type <integer> negate abs chansel math_function sharedfunction
508 add_instruction_option(struct options *options, int option)
512 options->access_mode = BRW_ALIGN_1;
515 options->access_mode = BRW_ALIGN_16;
518 options->qtr_ctrl |= BRW_COMPRESSION_2NDHALF;
521 options->qtr_ctrl |= BRW_COMPRESSION_COMPRESSED;
522 options->is_compr = true;
525 options->qtr_ctrl |= BRW_COMPRESSION_COMPRESSED;
528 options->thread_control |= BRW_THREAD_SWITCH;
531 options->thread_control |= BRW_THREAD_ATOMIC;
534 options->no_dd_check = true;
537 options->no_dd_clear = BRW_DEPENDENCY_NOTCLEARED;
540 options->mask_control |= BRW_MASK_DISABLE;
543 options->debug_control = BRW_DEBUG_BREAKPOINT;
546 options->mask_control |= BRW_WE_ALL;
549 options->compaction = true;
552 options->acc_wr_control = true;
555 options->end_of_thread = true;
557 /* TODO : Figure out how to set instruction group and get rid of
561 options->qtr_ctrl = BRW_COMPRESSION_2NDHALF;
564 options->qtr_ctrl = BRW_COMPRESSION_COMPRESSED;
567 options->qtr_ctrl = 3;
570 options->qtr_ctrl = BRW_COMPRESSION_COMPRESSED;
573 options->qtr_ctrl = BRW_COMPRESSION_NONE;
574 options->nib_ctrl = true;
577 options->qtr_ctrl = BRW_COMPRESSION_2NDHALF;
580 options->qtr_ctrl = BRW_COMPRESSION_2NDHALF;
581 options->nib_ctrl = true;
584 options->qtr_ctrl = BRW_COMPRESSION_COMPRESSED;
587 options->qtr_ctrl = BRW_COMPRESSION_COMPRESSED;
588 options->nib_ctrl = true;
591 options->qtr_ctrl = 3;
594 options->qtr_ctrl = 3;
595 options->nib_ctrl = true;
607 instrseq instruction SEMICOLON
608 | instrseq relocatableinstruction SEMICOLON
609 | instruction SEMICOLON
610 | relocatableinstruction SEMICOLON
613 /* Instruction Group */
617 | binaryaccinstruction
626 relocatableinstruction:
634 ILLEGAL execsize instoptions
636 brw_next_insn(p, $1);
637 brw_inst_set_exec_size(p->devinfo, brw_last_inst, $2);
638 i965_asm_set_instruction_options(p, $3);
642 /* Unary instruction */
644 predicate unaryopcodes saturate cond_mod execsize dst srcaccimm instoptions
646 i965_asm_set_dst_nr(p, &$6, $8);
647 brw_set_default_access_mode(p, $8.access_mode);
648 i965_asm_unary_instruction($2, p, $6, $7);
649 brw_pop_insn_state(p);
650 i965_asm_set_instruction_options(p, $8);
651 brw_inst_set_cond_modifier(p->devinfo, brw_last_inst,
654 if (p->devinfo->gen >= 7) {
655 if ($2 != BRW_OPCODE_DIM) {
656 brw_inst_set_flag_reg_nr(p->devinfo,
659 brw_inst_set_flag_subreg_nr(p->devinfo,
665 if ($7.file != BRW_IMMEDIATE_VALUE) {
666 brw_inst_set_src0_vstride(p->devinfo, brw_last_inst,
669 brw_inst_set_saturate(p->devinfo, brw_last_inst, $3);
670 brw_inst_set_exec_size(p->devinfo, brw_last_inst, $5);
671 // TODO: set instruction group instead of qtr and nib ctrl
672 brw_inst_set_qtr_control(p->devinfo, brw_last_inst,
675 if (p->devinfo->gen >= 7)
676 brw_inst_set_nib_control(p->devinfo, brw_last_inst,
699 /* Binary instruction */
701 predicate binaryopcodes saturate cond_mod execsize dst srcimm srcimm instoptions
703 i965_asm_set_dst_nr(p, &$6, $9);
704 brw_set_default_access_mode(p, $9.access_mode);
705 i965_asm_binary_instruction($2, p, $6, $7, $8);
706 i965_asm_set_instruction_options(p, $9);
707 brw_inst_set_cond_modifier(p->devinfo, brw_last_inst,
710 if (p->devinfo->gen >= 7) {
711 brw_inst_set_flag_reg_nr(p->devinfo, brw_last_inst,
713 brw_inst_set_flag_subreg_nr(p->devinfo, brw_last_inst,
717 brw_inst_set_saturate(p->devinfo, brw_last_inst, $3);
718 brw_inst_set_exec_size(p->devinfo, brw_last_inst, $5);
719 // TODO: set instruction group instead of qtr and nib ctrl
720 brw_inst_set_qtr_control(p->devinfo, brw_last_inst,
723 if (p->devinfo->gen >= 7)
724 brw_inst_set_nib_control(p->devinfo, brw_last_inst,
727 brw_pop_insn_state(p);
750 /* Binary acc instruction */
751 binaryaccinstruction:
752 predicate binaryaccopcodes saturate cond_mod execsize dst srcacc srcimm instoptions
754 i965_asm_set_dst_nr(p, &$6, $9);
755 brw_set_default_access_mode(p, $9.access_mode);
756 i965_asm_binary_instruction($2, p, $6, $7, $8);
757 brw_pop_insn_state(p);
758 i965_asm_set_instruction_options(p, $9);
759 brw_inst_set_cond_modifier(p->devinfo, brw_last_inst,
762 if (p->devinfo->gen >= 7) {
763 if (!brw_inst_flag_reg_nr(p->devinfo, brw_last_inst)) {
764 brw_inst_set_flag_reg_nr(p->devinfo,
767 brw_inst_set_flag_subreg_nr(p->devinfo,
773 brw_inst_set_saturate(p->devinfo, brw_last_inst, $3);
774 brw_inst_set_exec_size(p->devinfo, brw_last_inst, $5);
775 // TODO: set instruction group instead of qtr and nib ctrl
776 brw_inst_set_qtr_control(p->devinfo, brw_last_inst,
779 if (p->devinfo->gen >= 7)
780 brw_inst_set_nib_control(p->devinfo, brw_last_inst,
799 /* Math instruction */
801 predicate MATH saturate math_function execsize dst src srcimm instoptions
803 brw_set_default_access_mode(p, $9.access_mode);
804 gen6_math(p, $6, $4, $7, $8);
805 i965_asm_set_instruction_options(p, $9);
806 brw_inst_set_exec_size(p->devinfo, brw_last_inst, $5);
807 brw_inst_set_saturate(p->devinfo, brw_last_inst, $3);
808 // TODO: set instruction group instead
809 brw_inst_set_qtr_control(p->devinfo, brw_last_inst,
812 if (p->devinfo->gen >= 7)
813 brw_inst_set_nib_control(p->devinfo, brw_last_inst,
816 brw_pop_insn_state(p);
838 /* NOP instruction */
846 /* Ternary operand instruction */
848 predicate ternaryopcodes saturate cond_mod execsize dst src src src instoptions
850 brw_set_default_access_mode(p, $10.access_mode);
851 i965_asm_ternary_instruction($2, p, $6, $7, $8, $9);
852 brw_pop_insn_state(p);
853 i965_asm_set_instruction_options(p, $10);
854 brw_inst_set_cond_modifier(p->devinfo, brw_last_inst,
857 if (p->devinfo->gen >= 7) {
858 brw_inst_set_3src_a16_flag_reg_nr(p->devinfo, brw_last_inst,
860 brw_inst_set_3src_a16_flag_subreg_nr(p->devinfo, brw_last_inst,
864 brw_inst_set_saturate(p->devinfo, brw_last_inst, $3);
865 brw_inst_set_exec_size(p->devinfo, brw_last_inst, $5);
866 // TODO: set instruction group instead of qtr and nib ctrl
867 brw_inst_set_qtr_control(p->devinfo, brw_last_inst,
870 if (p->devinfo->gen >= 7)
871 brw_inst_set_nib_control(p->devinfo, brw_last_inst,
884 /* Sync instruction */
886 WAIT execsize dst instoptions
888 brw_next_insn(p, $1);
889 i965_asm_set_instruction_options(p, $4);
890 brw_inst_set_exec_size(p->devinfo, brw_last_inst, $2);
891 brw_set_default_access_mode(p, $4.access_mode);
892 struct brw_reg dest = $3;
893 dest.swizzle = brw_swizzle_for_mask(dest.writemask);
894 if (dest.file != ARF || dest.nr != BRW_ARF_NOTIFICATION_COUNT)
895 error(&@1, "WAIT must use the notification register\n");
896 brw_set_dest(p, brw_last_inst, dest);
897 brw_set_src0(p, brw_last_inst, dest);
898 brw_set_src1(p, brw_last_inst, brw_null_reg());
899 brw_inst_set_mask_control(p->devinfo, brw_last_inst, BRW_MASK_DISABLE);
903 /* Send instruction */
905 predicate sendopcode execsize dst payload exp2 sharedfunction instoptions
907 i965_asm_set_instruction_options(p, $8);
908 brw_inst_set_exec_size(p->devinfo, brw_last_inst, $3);
909 brw_set_dest(p, brw_last_inst, $4);
910 brw_set_src0(p, brw_last_inst, $5);
911 brw_inst_set_bits(brw_last_inst, 127, 96, $6);
912 brw_inst_set_src1_file_type(p->devinfo, brw_last_inst,
914 BRW_REGISTER_TYPE_UD);
915 brw_inst_set_sfid(p->devinfo, brw_last_inst, $7);
916 brw_inst_set_eot(p->devinfo, brw_last_inst, $8.end_of_thread);
917 // TODO: set instruction group instead of qtr and nib ctrl
918 brw_inst_set_qtr_control(p->devinfo, brw_last_inst,
921 if (p->devinfo->gen >= 7)
922 brw_inst_set_nib_control(p->devinfo, brw_last_inst,
925 brw_pop_insn_state(p);
927 | predicate sendopcode execsize exp dst payload exp2 sharedfunction instoptions
929 i965_asm_set_instruction_options(p, $9);
930 brw_inst_set_exec_size(p->devinfo, brw_last_inst, $3);
931 brw_inst_set_base_mrf(p->devinfo, brw_last_inst, $4);
932 brw_set_dest(p, brw_last_inst, $5);
933 brw_set_src0(p, brw_last_inst, $6);
934 brw_inst_set_bits(brw_last_inst, 127, 96, $7);
935 brw_inst_set_src1_file_type(p->devinfo, brw_last_inst,
937 BRW_REGISTER_TYPE_UD);
938 brw_inst_set_sfid(p->devinfo, brw_last_inst, $8);
939 brw_inst_set_eot(p->devinfo, brw_last_inst, $9.end_of_thread);
940 // TODO: set instruction group instead of qtr and nib ctrl
941 brw_inst_set_qtr_control(p->devinfo, brw_last_inst,
944 if (p->devinfo->gen >= 7)
945 brw_inst_set_nib_control(p->devinfo, brw_last_inst,
948 brw_pop_insn_state(p);
950 | predicate sendopcode execsize dst payload payload exp2 sharedfunction instoptions
952 i965_asm_set_instruction_options(p, $9);
953 brw_inst_set_exec_size(p->devinfo, brw_last_inst, $3);
954 brw_set_dest(p, brw_last_inst, $4);
955 brw_set_src0(p, brw_last_inst, $5);
956 brw_inst_set_bits(brw_last_inst, 127, 96, $7);
957 brw_inst_set_sfid(p->devinfo, brw_last_inst, $8);
958 brw_inst_set_eot(p->devinfo, brw_last_inst, $9.end_of_thread);
959 // TODO: set instruction group instead of qtr and nib ctrl
960 brw_inst_set_qtr_control(p->devinfo, brw_last_inst,
963 if (p->devinfo->gen >= 7)
964 brw_inst_set_nib_control(p->devinfo, brw_last_inst,
967 brw_pop_insn_state(p);
969 | predicate SENDS execsize dst payload payload exp2 exp2 sharedfunction instoptions
971 brw_next_insn(p, $2);
972 i965_asm_set_instruction_options(p, $10);
973 brw_inst_set_exec_size(p->devinfo, brw_last_inst, $3);
974 brw_set_dest(p, brw_last_inst, $4);
975 brw_set_src0(p, brw_last_inst, $5);
976 brw_set_src1(p, brw_last_inst, $6);
978 if (brw_inst_send_sel_reg32_ex_desc(p->devinfo, brw_last_inst)) {
979 brw_inst_set_send_ex_desc_ia_subreg_nr(p->devinfo, brw_last_inst, $5.subnr);
981 brw_inst_set_sends_ex_desc(p->devinfo, brw_last_inst, $8);
984 brw_inst_set_bits(brw_last_inst, 127, 96, $7);
985 brw_inst_set_sfid(p->devinfo, brw_last_inst, $9);
986 brw_inst_set_eot(p->devinfo, brw_last_inst, $10.end_of_thread);
987 // TODO: set instruction group instead of qtr and nib ctrl
988 brw_inst_set_qtr_control(p->devinfo, brw_last_inst,
991 if (p->devinfo->gen >= 7)
992 brw_inst_set_nib_control(p->devinfo, brw_last_inst,
995 brw_pop_insn_state(p);
997 | predicate SENDS execsize dst payload payload src exp2 sharedfunction instoptions
999 brw_next_insn(p, $2);
1000 i965_asm_set_instruction_options(p, $10);
1001 brw_inst_set_exec_size(p->devinfo, brw_last_inst, $3);
1002 brw_set_dest(p, brw_last_inst, $4);
1003 brw_set_src0(p, brw_last_inst, $5);
1004 brw_set_src1(p, brw_last_inst, $6);
1006 brw_inst_set_send_sel_reg32_desc(p->devinfo, brw_last_inst, 1);
1007 brw_inst_set_sends_ex_desc(p->devinfo, brw_last_inst, $8);
1009 brw_inst_set_sfid(p->devinfo, brw_last_inst, $9);
1010 brw_inst_set_eot(p->devinfo, brw_last_inst, $10.end_of_thread);
1011 // TODO: set instruction group instead of qtr and nib ctrl
1012 brw_inst_set_qtr_control(p->devinfo, brw_last_inst,
1015 if (p->devinfo->gen >= 7)
1016 brw_inst_set_nib_control(p->devinfo, brw_last_inst,
1019 brw_pop_insn_state(p);
1029 sendop { $$ = brw_next_insn(p, $1); }
1033 NULL_TOKEN { $$ = BRW_SFID_NULL; }
1034 | MATH { $$ = BRW_SFID_MATH; }
1035 | GATEWAY { $$ = BRW_SFID_MESSAGE_GATEWAY; }
1036 | READ { $$ = BRW_SFID_DATAPORT_READ; }
1037 | WRITE { $$ = BRW_SFID_DATAPORT_WRITE; }
1038 | URB { $$ = BRW_SFID_URB; }
1039 | THREAD_SPAWNER { $$ = BRW_SFID_THREAD_SPAWNER; }
1040 | VME { $$ = BRW_SFID_VME; }
1041 | RENDER { $$ = GEN6_SFID_DATAPORT_RENDER_CACHE; }
1042 | CONST { $$ = GEN6_SFID_DATAPORT_CONSTANT_CACHE; }
1043 | DATA { $$ = GEN7_SFID_DATAPORT_DATA_CACHE; }
1044 | PIXEL_INTERP { $$ = GEN7_SFID_PIXEL_INTERPOLATOR; }
1045 | DP_DATA_1 { $$ = HSW_SFID_DATAPORT_DATA_CACHE_1; }
1046 | CRE { $$ = HSW_SFID_CRE; }
1047 | SAMPLER { $$ = BRW_SFID_SAMPLER; }
1048 | DP_SAMPLER { $$ = GEN6_SFID_DATAPORT_SAMPLER_CACHE; }
1053 | MINUS LONG { $$ = -$2; }
1056 /* Jump instruction */
1058 predicate JMPI execsize relativelocation2 instoptions
1060 brw_next_insn(p, $2);
1061 i965_asm_set_instruction_options(p, $5);
1062 brw_inst_set_exec_size(p->devinfo, brw_last_inst, $3);
1063 brw_set_dest(p, brw_last_inst, brw_ip_reg());
1064 brw_set_src0(p, brw_last_inst, brw_ip_reg());
1065 brw_set_src1(p, brw_last_inst, $4);
1066 brw_inst_set_pred_control(p->devinfo, brw_last_inst,
1067 brw_inst_pred_control(p->devinfo,
1069 brw_pop_insn_state(p);
1073 /* branch instruction */
1075 predicate ENDIF execsize relativelocation instoptions
1077 brw_next_insn(p, $2);
1078 i965_asm_set_instruction_options(p, $5);
1079 brw_inst_set_exec_size(p->devinfo, brw_last_inst, $3);
1081 if (p->devinfo->gen < 6) {
1082 brw_set_dest(p, brw_last_inst, retype(brw_null_reg(),
1083 BRW_REGISTER_TYPE_D));
1084 brw_set_src0(p, brw_last_inst, retype(brw_null_reg(),
1085 BRW_REGISTER_TYPE_D));
1086 brw_set_src1(p, brw_last_inst, brw_imm_d(0x0));
1087 brw_inst_set_gen4_pop_count(p->devinfo, brw_last_inst,
1089 } else if (p->devinfo->gen == 6) {
1090 brw_set_dest(p, brw_last_inst, brw_imm_w(0x0));
1091 brw_inst_set_gen6_jump_count(p->devinfo, brw_last_inst,
1093 brw_set_src0(p, brw_last_inst, retype(brw_null_reg(),
1094 BRW_REGISTER_TYPE_D));
1095 brw_set_src1(p, brw_last_inst, retype(brw_null_reg(),
1096 BRW_REGISTER_TYPE_D));
1097 } else if (p->devinfo->gen == 7) {
1098 brw_set_dest(p, brw_last_inst, retype(brw_null_reg(),
1099 BRW_REGISTER_TYPE_D));
1100 brw_set_src0(p, brw_last_inst, retype(brw_null_reg(),
1101 BRW_REGISTER_TYPE_D));
1102 brw_set_src1(p, brw_last_inst, brw_imm_w(0x0));
1103 brw_inst_set_jip(p->devinfo, brw_last_inst, $4);
1105 brw_set_src0(p, brw_last_inst, brw_imm_d($4));
1108 if (p->devinfo->gen < 6)
1109 brw_inst_set_thread_control(p->devinfo, brw_last_inst,
1111 brw_pop_insn_state(p);
1113 | ELSE execsize relativelocation rellocation instoptions
1115 brw_next_insn(p, $1);
1116 i965_asm_set_instruction_options(p, $5);
1117 brw_inst_set_exec_size(p->devinfo, brw_last_inst, $2);
1119 if (p->devinfo->gen < 6) {
1120 brw_set_dest(p, brw_last_inst, brw_ip_reg());
1121 brw_set_src0(p, brw_last_inst, brw_ip_reg());
1122 brw_set_src1(p, brw_last_inst, brw_imm_d(0x0));
1123 brw_inst_set_gen4_jump_count(p->devinfo, brw_last_inst,
1125 brw_inst_set_gen4_pop_count(p->devinfo, brw_last_inst,
1127 } else if (p->devinfo->gen == 6) {
1128 brw_set_dest(p, brw_last_inst, brw_imm_w(0x0));
1129 brw_inst_set_gen6_jump_count(p->devinfo, brw_last_inst,
1131 brw_set_src0(p, brw_last_inst, retype(brw_null_reg(),
1132 BRW_REGISTER_TYPE_D));
1133 brw_set_src1(p, brw_last_inst, retype(brw_null_reg(),
1134 BRW_REGISTER_TYPE_D));
1135 } else if (p->devinfo->gen == 7) {
1136 brw_set_dest(p, brw_last_inst, retype(brw_null_reg(),
1137 BRW_REGISTER_TYPE_D));
1138 brw_set_src0(p, brw_last_inst, retype(brw_null_reg(),
1139 BRW_REGISTER_TYPE_D));
1140 brw_set_src1(p, brw_last_inst, brw_imm_w($3));
1141 brw_inst_set_jip(p->devinfo, brw_last_inst, $3);
1142 brw_inst_set_uip(p->devinfo, brw_last_inst, $4);
1144 brw_set_dest(p, brw_last_inst, retype(brw_null_reg(),
1145 BRW_REGISTER_TYPE_D));
1146 brw_set_src0(p, brw_last_inst, brw_imm_d($3));
1147 brw_inst_set_jip(p->devinfo, brw_last_inst, $3);
1148 brw_inst_set_uip(p->devinfo, brw_last_inst, $4);
1151 if (!p->single_program_flow && p->devinfo->gen < 6)
1152 brw_inst_set_thread_control(p->devinfo, brw_last_inst,
1155 | predicate IF execsize relativelocation rellocation instoptions
1157 brw_next_insn(p, $2);
1158 i965_asm_set_instruction_options(p, $6);
1159 brw_inst_set_exec_size(p->devinfo, brw_last_inst, $3);
1161 if (p->devinfo->gen < 6) {
1162 brw_set_dest(p, brw_last_inst, brw_ip_reg());
1163 brw_set_src0(p, brw_last_inst, brw_ip_reg());
1164 brw_set_src1(p, brw_last_inst, brw_imm_d(0x0));
1165 brw_inst_set_gen4_jump_count(p->devinfo, brw_last_inst,
1167 brw_inst_set_gen4_pop_count(p->devinfo, brw_last_inst,
1169 } else if (p->devinfo->gen == 6) {
1170 brw_set_dest(p, brw_last_inst, brw_imm_w(0x0));
1171 brw_inst_set_gen6_jump_count(p->devinfo, brw_last_inst,
1173 brw_set_src0(p, brw_last_inst,
1174 vec1(retype(brw_null_reg(),
1175 BRW_REGISTER_TYPE_D)));
1176 brw_set_src1(p, brw_last_inst,
1177 vec1(retype(brw_null_reg(),
1178 BRW_REGISTER_TYPE_D)));
1179 } else if (p->devinfo->gen == 7) {
1180 brw_set_dest(p, brw_last_inst,
1181 vec1(retype(brw_null_reg(),
1182 BRW_REGISTER_TYPE_D)));
1183 brw_set_src0(p, brw_last_inst,
1184 vec1(retype(brw_null_reg(),
1185 BRW_REGISTER_TYPE_D)));
1186 brw_set_src1(p, brw_last_inst, brw_imm_w($4));
1187 brw_inst_set_jip(p->devinfo, brw_last_inst, $4);
1188 brw_inst_set_uip(p->devinfo, brw_last_inst, $5);
1190 brw_set_dest(p, brw_last_inst,
1191 vec1(retype(brw_null_reg(),
1192 BRW_REGISTER_TYPE_D)));
1193 brw_set_src0(p, brw_last_inst, brw_imm_d($4));
1194 brw_inst_set_jip(p->devinfo, brw_last_inst, $4);
1195 brw_inst_set_uip(p->devinfo, brw_last_inst, $5);
1198 if (!p->single_program_flow && p->devinfo->gen < 6)
1199 brw_inst_set_thread_control(p->devinfo, brw_last_inst,
1202 brw_pop_insn_state(p);
1204 | predicate IFF execsize relativelocation instoptions
1206 brw_next_insn(p, $2);
1207 i965_asm_set_instruction_options(p, $5);
1208 brw_inst_set_exec_size(p->devinfo, brw_last_inst, $3);
1210 if (p->devinfo->gen < 6) {
1211 brw_set_dest(p, brw_last_inst, brw_ip_reg());
1212 brw_set_src0(p, brw_last_inst, brw_ip_reg());
1213 brw_inst_set_gen4_jump_count(p->devinfo, brw_last_inst,
1215 brw_set_src1(p, brw_last_inst, brw_imm_d($4));
1216 } else if (p->devinfo->gen == 6) {
1217 brw_set_dest(p, brw_last_inst, brw_imm_w($4));
1218 brw_inst_set_gen6_jump_count(p->devinfo, brw_last_inst,
1220 brw_set_src0(p, brw_last_inst,
1221 vec1(retype(brw_null_reg(),
1222 BRW_REGISTER_TYPE_D)));
1223 brw_set_src1(p, brw_last_inst,
1224 vec1(retype(brw_null_reg(),
1225 BRW_REGISTER_TYPE_D)));
1226 } else if (p->devinfo->gen == 7) {
1227 brw_set_dest(p, brw_last_inst,
1228 vec1(retype(brw_null_reg(),
1229 BRW_REGISTER_TYPE_D)));
1230 brw_set_src0(p, brw_last_inst,
1231 vec1(retype(brw_null_reg(),
1232 BRW_REGISTER_TYPE_D)));
1233 brw_set_src1(p, brw_last_inst, brw_imm_w($4));
1234 brw_inst_set_jip(p->devinfo, brw_last_inst, $4);
1236 brw_set_dest(p, brw_last_inst,
1237 vec1(retype(brw_null_reg(),
1238 BRW_REGISTER_TYPE_D)));
1239 brw_set_src0(p, brw_last_inst, brw_imm_d($4));
1240 brw_inst_set_jip(p->devinfo, brw_last_inst, $4);
1243 if (!p->single_program_flow && p->devinfo->gen < 6)
1244 brw_inst_set_thread_control(p->devinfo, brw_last_inst,
1247 brw_pop_insn_state(p);
1251 /* break instruction */
1253 predicate BREAK execsize relativelocation relativelocation instoptions
1255 brw_next_insn(p, $2);
1256 i965_asm_set_instruction_options(p, $6);
1257 brw_inst_set_exec_size(p->devinfo, brw_last_inst, $3);
1259 if (p->devinfo->gen >= 8) {
1260 brw_set_dest(p, brw_last_inst, retype(brw_null_reg(),
1261 BRW_REGISTER_TYPE_D));
1262 brw_set_src0(p, brw_last_inst, brw_imm_d($4));
1263 brw_inst_set_uip(p->devinfo, brw_last_inst, $5);
1264 } else if (p->devinfo->gen >= 6) {
1265 brw_set_dest(p, brw_last_inst, retype(brw_null_reg(),
1266 BRW_REGISTER_TYPE_D));
1267 brw_set_src0(p, brw_last_inst, retype(brw_null_reg(),
1268 BRW_REGISTER_TYPE_D));
1269 brw_set_src1(p, brw_last_inst, brw_imm_d(0x0));
1270 brw_inst_set_jip(p->devinfo, brw_last_inst, $4);
1271 brw_inst_set_uip(p->devinfo, brw_last_inst, $5);
1273 brw_set_dest(p, brw_last_inst, brw_ip_reg());
1274 brw_set_src0(p, brw_last_inst, brw_ip_reg());
1275 brw_set_src1(p, brw_last_inst, brw_imm_d(0x0));
1276 brw_inst_set_gen4_jump_count(p->devinfo, brw_last_inst,
1278 brw_inst_set_gen4_pop_count(p->devinfo, brw_last_inst,
1282 brw_pop_insn_state(p);
1284 | predicate HALT execsize relativelocation relativelocation instoptions
1286 brw_next_insn(p, $2);
1287 i965_asm_set_instruction_options(p, $6);
1288 brw_inst_set_exec_size(p->devinfo, brw_last_inst, $3);
1289 brw_set_dest(p, brw_last_inst, retype(brw_null_reg(),
1290 BRW_REGISTER_TYPE_D));
1292 if (p->devinfo->gen >= 8) {
1293 brw_set_src0(p, brw_last_inst, brw_imm_d($4));
1294 brw_inst_set_uip(p->devinfo, brw_last_inst, $5);
1296 brw_set_src0(p, brw_last_inst, retype(brw_null_reg(),
1297 BRW_REGISTER_TYPE_D));
1298 brw_set_src1(p, brw_last_inst, brw_imm_d($5));
1301 brw_inst_set_jip(p->devinfo, brw_last_inst, $4);
1302 brw_inst_set_uip(p->devinfo, brw_last_inst, $5);
1303 brw_pop_insn_state(p);
1305 | predicate CONT execsize relativelocation relativelocation instoptions
1307 brw_next_insn(p, $2);
1308 i965_asm_set_instruction_options(p, $6);
1309 brw_inst_set_exec_size(p->devinfo, brw_last_inst, $3);
1310 brw_set_dest(p, brw_last_inst, brw_ip_reg());
1312 if (p->devinfo->gen >= 8) {
1313 brw_set_src0(p, brw_last_inst, brw_imm_d(0x0));
1314 brw_inst_set_jip(p->devinfo, brw_last_inst, $4);
1315 brw_inst_set_uip(p->devinfo, brw_last_inst, $5);
1317 brw_set_src0(p, brw_last_inst, brw_ip_reg());
1318 brw_set_src1(p, brw_last_inst, brw_imm_d(0x0));
1319 if (p->devinfo->gen >= 6) {
1320 brw_inst_set_jip(p->devinfo, brw_last_inst, $4);
1321 brw_inst_set_uip(p->devinfo, brw_last_inst, $5);
1323 brw_inst_set_gen4_jump_count(p->devinfo, brw_last_inst,
1325 brw_inst_set_gen4_pop_count(p->devinfo, brw_last_inst,
1330 brw_pop_insn_state(p);
1334 /* loop instruction */
1336 predicate WHILE execsize relativelocation instoptions
1338 brw_next_insn(p, $2);
1339 i965_asm_set_instruction_options(p, $5);
1340 brw_inst_set_exec_size(p->devinfo, brw_last_inst, $3);
1342 if (p->devinfo->gen >= 6) {
1343 if (p->devinfo->gen >= 8) {
1344 brw_set_dest(p, brw_last_inst,
1345 retype(brw_null_reg(),
1346 BRW_REGISTER_TYPE_D));
1347 brw_set_src0(p, brw_last_inst, brw_imm_d($4));
1348 } else if (p->devinfo->gen == 7) {
1349 brw_set_dest(p, brw_last_inst,
1350 retype(brw_null_reg(),
1351 BRW_REGISTER_TYPE_D));
1352 brw_set_src0(p, brw_last_inst,
1353 retype(brw_null_reg(),
1354 BRW_REGISTER_TYPE_D));
1355 brw_set_src1(p, brw_last_inst,
1357 brw_inst_set_jip(p->devinfo, brw_last_inst,
1360 brw_set_dest(p, brw_last_inst, brw_imm_w(0x0));
1361 brw_inst_set_gen6_jump_count(p->devinfo,
1364 brw_set_src0(p, brw_last_inst,
1365 retype(brw_null_reg(),
1366 BRW_REGISTER_TYPE_D));
1367 brw_set_src1(p, brw_last_inst,
1368 retype(brw_null_reg(),
1369 BRW_REGISTER_TYPE_D));
1372 brw_set_dest(p, brw_last_inst, brw_ip_reg());
1373 brw_set_src0(p, brw_last_inst, brw_ip_reg());
1374 brw_set_src1(p, brw_last_inst, brw_imm_d(0x0));
1375 brw_inst_set_gen4_jump_count(p->devinfo, brw_last_inst,
1377 brw_inst_set_gen4_pop_count(p->devinfo, brw_last_inst,
1380 brw_pop_insn_state(p);
1382 | DO execsize instoptions
1384 brw_next_insn(p, $1);
1385 if (p->devinfo->gen < 6) {
1386 brw_inst_set_exec_size(p->devinfo, brw_last_inst, $2);
1387 i965_asm_set_instruction_options(p, $3);
1388 brw_set_dest(p, brw_last_inst, brw_null_reg());
1389 brw_set_src0(p, brw_last_inst, brw_null_reg());
1390 brw_set_src1(p, brw_last_inst, brw_null_reg());
1392 brw_inst_set_qtr_control(p->devinfo, brw_last_inst, BRW_COMPRESSION_NONE);
1397 /* Relative location */
1404 INTEGER { $$ = $1; }
1405 | MINUS INTEGER { $$ = -$2; }
1407 | MINUS LONG { $$ = -$2; }
1412 | %empty { $$ = 0; }
1422 /* Destination register */
1429 dstreg dstregion writemask reg_type
1432 $$.vstride = BRW_VERTICAL_STRIDE_1;
1433 $$.width = BRW_WIDTH_1;
1437 $$.swizzle = BRW_SWIZZLE_NOOP;
1438 $$.subnr = $$.subnr * brw_reg_type_to_size($4);
1443 dstoperandex_typed dstregion writemask reg_type
1449 $$.subnr = $$.subnr * brw_reg_type_to_size($4);
1451 /* BSpec says "When the conditional modifier is present, updates
1452 * to the selected flag register also occur. In this case, the
1453 * register region fields of the ‘null’ operand are valid."
1455 | nullreg dstregion writemask reg_type
1458 $$.vstride = BRW_VERTICAL_STRIDE_1;
1459 $$.width = BRW_WIDTH_1;
1468 $$.type = BRW_REGISTER_TYPE_UW;
1489 $$.address_mode = BRW_ADDRESS_DIRECT;
1494 $$.address_mode = BRW_ADDRESS_REGISTER_INDIRECT_REGISTER;
1499 $$.address_mode = BRW_ADDRESS_DIRECT;
1504 $$.address_mode = BRW_ADDRESS_REGISTER_INDIRECT_REGISTER;
1508 /* Source register */
1518 case BRW_REGISTER_TYPE_UD:
1519 $$ = brw_imm_ud($1);
1521 case BRW_REGISTER_TYPE_D:
1524 case BRW_REGISTER_TYPE_UW:
1525 $$ = brw_imm_uw($1 | ($1 << 16));
1527 case BRW_REGISTER_TYPE_W:
1530 case BRW_REGISTER_TYPE_F:
1531 $$ = brw_imm_reg(BRW_REGISTER_TYPE_F);
1532 /* Set u64 instead of ud since DIM uses a 64-bit F-typed imm */
1535 case BRW_REGISTER_TYPE_V:
1538 case BRW_REGISTER_TYPE_UV:
1539 $$ = brw_imm_uv($1);
1541 case BRW_REGISTER_TYPE_VF:
1542 $$ = brw_imm_vf($1);
1544 case BRW_REGISTER_TYPE_Q:
1547 case BRW_REGISTER_TYPE_UQ:
1548 $$ = brw_imm_uq($1);
1550 case BRW_REGISTER_TYPE_DF:
1551 $$ = brw_imm_reg(BRW_REGISTER_TYPE_DF);
1555 error(&@2, "Unknown immediate type %s\n",
1556 brw_reg_type_to_letters($2));
1562 directgenreg region reg_type
1564 $$ = set_direct_src_operand(&$1, $3);
1565 $$ = stride($$, $2.vstride, $2.width, $2.hstride);
1575 | indirectsrcoperand
1580 | indirectsrcoperand
1585 | indirectsrcoperand
1589 directsrcaccoperand:
1591 | accreg region reg_type
1593 $$ = set_direct_src_operand(&$1, $3);
1594 $$.vstride = $2.vstride;
1595 $$.width = $2.width;
1596 $$.hstride = $2.hstride;
1601 srcarcoperandex_typed region reg_type
1603 $$ = brw_reg($1.file,
1615 | nullreg region reg_type
1617 $$ = set_direct_src_operand(&$1, $3);
1618 $$.vstride = $2.vstride;
1619 $$.width = $2.width;
1620 $$.hstride = $2.hstride;
1624 $$ = set_direct_src_operand(&$1, BRW_REGISTER_TYPE_UW);
1628 srcarcoperandex_typed:
1638 negate abs indirectgenreg indirectregion swizzle reg_type
1640 $$ = brw_reg($3.file,
1652 $$.address_mode = BRW_ADDRESS_REGISTER_INDIRECT_REGISTER;
1653 // brw_reg set indirect_offset to 0 so set it to valid value
1654 $$.indirect_offset = $3.indirect_offset;
1667 negate abs directgenreg_list region swizzle reg_type
1669 $$ = brw_reg($3.file,
1684 /* Address register */
1688 memset(&$$, '\0', sizeof($$));
1689 $$.subnr = $1.subnr;
1690 $$.indirect_offset = $2;
1695 /* Register files and register numbers */
1697 INTEGER { $$ = $1; }
1702 DOT exp { $$ = $2; }
1703 | %empty %prec SUBREGNUM { $$ = 0; }
1709 memset(&$$, '\0', sizeof($$));
1710 $$.file = BRW_GENERAL_REGISTER_FILE;
1717 GENREGFILE LSQUARE addrparam RSQUARE
1719 memset(&$$, '\0', sizeof($$));
1720 $$.file = BRW_GENERAL_REGISTER_FILE;
1721 $$.subnr = $3.subnr;
1722 $$.indirect_offset = $3.indirect_offset;
1729 $$.file = BRW_MESSAGE_REGISTER_FILE;
1736 MSGREGFILE LSQUARE addrparam RSQUARE
1738 memset(&$$, '\0', sizeof($$));
1739 $$.file = BRW_MESSAGE_REGISTER_FILE;
1740 $$.subnr = $3.subnr;
1741 $$.indirect_offset = $3.indirect_offset;
1748 int subnr = (p->devinfo->gen >= 8) ? 16 : 8;
1751 error(&@2, "Address sub register number %d"
1752 "out of range\n", $2);
1754 $$.file = BRW_ARCHITECTURE_REGISTER_FILE;
1755 $$.nr = BRW_ARF_ADDRESS;
1764 if (p->devinfo->gen < 8)
1770 error(&@1, "Accumulator register number %d"
1771 " out of range\n", $1);
1773 memset(&$$, '\0', sizeof($$));
1774 $$.file = BRW_ARCHITECTURE_REGISTER_FILE;
1775 $$.nr = BRW_ARF_ACCUMULATOR;
1783 // SNB = 1 flag reg and IVB+ = 2 flag reg
1784 int nr_reg = (p->devinfo->gen >= 7) ? 2 : 1;
1788 error(&@1, "Flag register number %d"
1789 " out of range \n", $1);
1791 error(&@2, "Flag subregister number %d"
1792 " out of range\n", $2);
1794 $$.file = BRW_ARCHITECTURE_REGISTER_FILE;
1795 $$.nr = BRW_ARF_FLAG | $1;
1804 error(&@1, "Mask register number %d"
1805 " out of range\n", $1);
1807 $$.file = BRW_ARCHITECTURE_REGISTER_FILE;
1808 $$.nr = BRW_ARF_MASK;
1817 error(&@1, "Notification register number %d"
1818 " out of range\n", $1);
1820 int subnr = (p->devinfo->gen >= 11) ? 2 : 3;
1822 error(&@2, "Notification sub register number %d"
1823 " out of range\n", $2);
1825 $$.file = BRW_ARCHITECTURE_REGISTER_FILE;
1826 $$.nr = BRW_ARF_NOTIFICATION_COUNT;
1835 error(&@1, "State register number %d"
1836 " out of range\n", $1);
1839 error(&@2, "State sub register number %d"
1840 " out of range\n", $2);
1842 $$.file = BRW_ARCHITECTURE_REGISTER_FILE;
1843 $$.nr = BRW_ARF_STATE;
1849 CONTROLREG subregnum
1852 error(&@2, "control sub register number %d"
1853 " out of range\n", $2);
1855 $$.file = BRW_ARCHITECTURE_REGISTER_FILE;
1856 $$.nr = BRW_ARF_CONTROL;
1862 IPREG { $$ = brw_ip_reg(); }
1866 NULL_TOKEN { $$ = brw_null_reg(); }
1873 error(&@2, "Thread control sub register number %d"
1874 " out of range\n", $2);
1876 $$.file = BRW_ARCHITECTURE_REGISTER_FILE;
1877 $$.nr = BRW_ARF_TDR;
1883 PERFORMANCEREG subregnum
1886 if (p->devinfo->gen >= 10)
1888 else if (p->devinfo->gen <= 8)
1894 error(&@2, "Performance sub register number %d"
1895 " out of range\n", $2);
1897 $$.file = BRW_ARCHITECTURE_REGISTER_FILE;
1898 $$.nr = BRW_ARF_TIMESTAMP;
1904 CHANNELENABLEREG subregnum
1907 error(&@1, "Channel enable register number %d"
1908 " out of range\n", $1);
1910 $$.file = BRW_ARCHITECTURE_REGISTER_FILE;
1911 $$.nr = BRW_ARF_MASK;
1916 /* Immediate values */
1922 | LSQUARE exp2 COMMA exp2 COMMA exp2 COMMA exp2 RSQUARE
1924 $$ = ($2 << 0) | ($4 << 8) | ($6 << 16) | ($8 << 24);
1932 $$ = BRW_HORIZONTAL_STRIDE_1;
1936 if ($2 != 0 && ($2 > 4 || !isPowerofTwo($2)))
1937 error(&@2, "Invalid Horizontal stride %d\n", $2);
1951 $$ = stride($$, 0, 1, 0);
1955 if ($2 != 0 && ($2 > 32 || !isPowerofTwo($2)))
1956 error(&@2, "Invalid VertStride %d\n", $2);
1958 $$ = stride($$, $2, 1, 0);
1960 | LANGLE exp COMMA exp COMMA exp RANGLE
1963 if ($2 != 0 && ($2 > 32 || !isPowerofTwo($2)))
1964 error(&@2, "Invalid VertStride %d\n", $2);
1966 if ($4 > 16 || !isPowerofTwo($4))
1967 error(&@4, "Invalid width %d\n", $4);
1969 if ($6 != 0 && ($6 > 4 || !isPowerofTwo($6)))
1970 error(&@6, "Invalid Horizontal stride in"
1971 " region_wh %d\n", $6);
1973 $$ = stride($$, $2, $4, $6);
1975 | LANGLE exp SEMICOLON exp COMMA exp RANGLE
1977 if ($2 != 0 && ($2 > 32 || !isPowerofTwo($2)))
1978 error(&@2, "Invalid VertStride %d\n", $2);
1980 if ($4 > 16 || !isPowerofTwo($4))
1981 error(&@4, "Invalid width %d\n", $4);
1983 if ($6 != 0 && ($6 > 4 || !isPowerofTwo($6)))
1984 error(&@6, "Invalid Horizontal stride in"
1985 " region_wh %d\n", $6);
1987 $$ = stride($$, $2, $4, $6);
1989 | LANGLE VxH COMMA exp COMMA exp RANGLE
1991 if ($4 > 16 || !isPowerofTwo($4))
1992 error(&@4, "Invalid width %d\n", $4);
1994 if ($6 != 0 && ($6 > 4 || !isPowerofTwo($6)))
1995 error(&@6, "Invalid Horizontal stride in"
1996 " region_wh %d\n", $6);
1998 $$ = brw_VxH_indirect(0, 0);
2003 LANGLE exp COMMA exp RANGLE
2005 if ($2 > 16 || !isPowerofTwo($2))
2006 error(&@2, "Invalid width %d\n", $2);
2008 if ($4 != 0 && ($4 > 4 || !isPowerofTwo($4)))
2009 error(&@4, "Invalid Horizontal stride in"
2010 " region_wh %d\n", $4);
2012 $$ = stride($$, 0, $2, $4);
2013 $$.vstride = BRW_VERTICAL_STRIDE_ONE_DIMENSIONAL;
2018 TYPE_F { $$ = BRW_REGISTER_TYPE_F; }
2019 | TYPE_UD { $$ = BRW_REGISTER_TYPE_UD; }
2020 | TYPE_D { $$ = BRW_REGISTER_TYPE_D; }
2021 | TYPE_UW { $$ = BRW_REGISTER_TYPE_UW; }
2022 | TYPE_W { $$ = BRW_REGISTER_TYPE_W; }
2023 | TYPE_UB { $$ = BRW_REGISTER_TYPE_UB; }
2024 | TYPE_B { $$ = BRW_REGISTER_TYPE_B; }
2025 | TYPE_DF { $$ = BRW_REGISTER_TYPE_DF; }
2026 | TYPE_UQ { $$ = BRW_REGISTER_TYPE_UQ; }
2027 | TYPE_Q { $$ = BRW_REGISTER_TYPE_Q; }
2028 | TYPE_HF { $$ = BRW_REGISTER_TYPE_HF; }
2029 | TYPE_NF { $$ = BRW_REGISTER_TYPE_NF; }
2033 reg_type { $$ = $1; }
2034 | TYPE_V { $$ = BRW_REGISTER_TYPE_V; }
2035 | TYPE_VF { $$ = BRW_REGISTER_TYPE_VF; }
2036 | TYPE_UV { $$ = BRW_REGISTER_TYPE_UV; }
2042 $$ = WRITEMASK_XYZW;
2044 | DOT writemask_x writemask_y writemask_z writemask_w
2046 $$ = $2 | $3 | $4 | $5;
2052 | X { $$ = 1 << BRW_CHANNEL_X; }
2057 | Y { $$ = 1 << BRW_CHANNEL_Y; }
2062 | Z { $$ = 1 << BRW_CHANNEL_Z; }
2067 | W { $$ = 1 << BRW_CHANNEL_W; }
2073 $$ = BRW_SWIZZLE_NOOP;
2077 $$ = BRW_SWIZZLE4($2, $2, $2, $2);
2079 | DOT chansel chansel chansel chansel
2081 $$ = BRW_SWIZZLE4($2, $3, $4, $5);
2092 /* Instruction prediction and modifiers */
2096 brw_push_insn_state(p);
2097 brw_set_default_predicate_control(p, BRW_PREDICATE_NONE);
2098 brw_set_default_flag_reg(p, 0, 0);
2099 brw_set_default_predicate_inverse(p, false);
2101 | LPAREN predstate flagreg predctrl RPAREN
2103 brw_push_insn_state(p);
2104 brw_set_default_predicate_inverse(p, $2);
2105 brw_set_default_flag_reg(p, $3.nr, $3.subnr);
2106 brw_set_default_predicate_control(p, $4);
2117 %empty { $$ = BRW_PREDICATE_NORMAL; }
2118 | DOT X { $$ = BRW_PREDICATE_ALIGN16_REPLICATE_X; }
2119 | DOT Y { $$ = BRW_PREDICATE_ALIGN16_REPLICATE_Y; }
2120 | DOT Z { $$ = BRW_PREDICATE_ALIGN16_REPLICATE_Z; }
2121 | DOT W { $$ = BRW_PREDICATE_ALIGN16_REPLICATE_W; }
2136 /* Source Modification */
2147 /* Flag (Conditional) Modifier */
2151 $$.cond_modifier = $1;
2153 $$.flag_subreg_nr = 0;
2155 | condModifiers DOT flagreg
2157 $$.cond_modifier = $1;
2158 $$.flag_reg_nr = $3.nr;
2159 $$.flag_subreg_nr = $3.subnr;
2164 %empty { $$ = BRW_CONDITIONAL_NONE; }
2179 %empty { $$ = BRW_INSTRUCTION_NORMAL; }
2180 | SATURATE { $$ = BRW_INSTRUCTION_SATURATE; }
2183 /* Execution size */
2185 %empty %prec EMPTYEXECSIZE
2189 | LPAREN exp2 RPAREN
2191 if ($2 > 32 || !isPowerofTwo($2))
2192 error(&@2, "Invalid execution size %d\n", $2);
2198 /* Instruction options */
2202 memset(&$$, 0, sizeof($$));
2204 | LCURLY instoption_list RCURLY
2206 memset(&$$, 0, sizeof($$));
2212 instoption_list COMMA instoption
2214 memset(&$$, 0, sizeof($$));
2216 add_instruction_option(&$$, $3);
2218 | instoption_list instoption
2220 memset(&$$, 0, sizeof($$));
2222 add_instruction_option(&$$, $2);
2226 memset(&$$, 0, sizeof($$));
2231 ALIGN1 { $$ = ALIGN1;}
2232 | ALIGN16 { $$ = ALIGN16; }
2233 | ACCWREN { $$ = ACCWREN; }
2234 | SECHALF { $$ = SECHALF; }
2235 | COMPR { $$ = COMPR; }
2236 | COMPR4 { $$ = COMPR4; }
2237 | BREAKPOINT { $$ = BREAKPOINT; }
2238 | NODDCLR { $$ = NODDCLR; }
2239 | NODDCHK { $$ = NODDCHK; }
2240 | MASK_DISABLE { $$ = MASK_DISABLE; }
2242 | SWITCH { $$ = SWITCH; }
2243 | ATOMIC { $$ = ATOMIC; }
2244 | CMPTCTRL { $$ = CMPTCTRL; }
2245 | WECTRL { $$ = WECTRL; }
2246 | QTR_2Q { $$ = QTR_2Q; }
2247 | QTR_3Q { $$ = QTR_3Q; }
2248 | QTR_4Q { $$ = QTR_4Q; }
2249 | QTR_2H { $$ = QTR_2H; }
2250 | QTR_2N { $$ = QTR_2N; }
2251 | QTR_3N { $$ = QTR_3N; }
2252 | QTR_4N { $$ = QTR_4N; }
2253 | QTR_5N { $$ = QTR_5N; }
2254 | QTR_6N { $$ = QTR_6N; }
2255 | QTR_7N { $$ = QTR_7N; }
2256 | QTR_8N { $$ = QTR_8N; }
2261 extern int yylineno;
2266 fprintf(stderr, "%s: %d: %s at \"%s\"\n",
2267 input_filename, yylineno, msg, lex_text());