3 * Copyright © 2018 Intel Corporation
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
21 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
31 #define YYLTYPE YYLTYPE
32 typedef struct YYLTYPE
48 message(enum message_level level, YYLTYPE *location,
51 static const char *level_str[] = { "warning", "error" };
55 fprintf(stderr, "%s:%d:%d: %s: ", input_filename,
57 location->first_column, level_str[level]);
59 fprintf(stderr, "%s:%s: ", input_filename, level_str[level]);
62 vfprintf(stderr, fmt, args);
66 #define warn(flag, l, fmt, ...) \
68 if (warning_flags & WARN_ ## flag) \
69 message(WARN, l, fmt, ## __VA_ARGS__); \
72 #define error(l, fmt, ...) \
74 message(ERROR, l, fmt, ## __VA_ARGS__); \
78 isPowerofTwo(unsigned int x)
80 return x && (!(x & (x - 1)));
84 set_direct_src_operand(struct brw_reg *reg, int type)
86 return brw_reg(reg->file,
100 i965_asm_unary_instruction(int opcode, struct brw_codegen *p,
101 struct brw_reg dest, struct brw_reg src0)
104 case BRW_OPCODE_BFREV:
105 brw_BFREV(p, dest, src0);
107 case BRW_OPCODE_CBIT:
108 brw_CBIT(p, dest, src0);
110 case BRW_OPCODE_F32TO16:
111 brw_F32TO16(p, dest, src0);
113 case BRW_OPCODE_F16TO32:
114 brw_F16TO32(p, dest, src0);
117 brw_MOV(p, dest, src0);
120 brw_FBL(p, dest, src0);
123 brw_FRC(p, dest, src0);
126 brw_FBH(p, dest, src0);
129 brw_NOT(p, dest, src0);
131 case BRW_OPCODE_RNDE:
132 brw_RNDE(p, dest, src0);
134 case BRW_OPCODE_RNDZ:
135 brw_RNDZ(p, dest, src0);
137 case BRW_OPCODE_RNDD:
138 brw_RNDD(p, dest, src0);
141 brw_LZD(p, dest, src0);
144 brw_DIM(p, dest, src0);
146 case BRW_OPCODE_RNDU:
147 fprintf(stderr, "Opcode BRW_OPCODE_RNDU unhandled\n");
150 fprintf(stderr, "Unsupported unary opcode\n");
155 i965_asm_binary_instruction(int opcode,
156 struct brw_codegen *p,
162 case BRW_OPCODE_ADDC:
163 brw_ADDC(p, dest, src0, src1);
165 case BRW_OPCODE_BFI1:
166 brw_BFI1(p, dest, src0, src1);
169 brw_DP2(p, dest, src0, src1);
172 brw_DP3(p, dest, src0, src1);
175 brw_DP4(p, dest, src0, src1);
178 brw_DPH(p, dest, src0, src1);
180 case BRW_OPCODE_LINE:
181 brw_LINE(p, dest, src0, src1);
184 brw_MAC(p, dest, src0, src1);
186 case BRW_OPCODE_MACH:
187 brw_MACH(p, dest, src0, src1);
190 brw_PLN(p, dest, src0, src1);
193 brw_ROL(p, dest, src0, src1);
196 brw_ROR(p, dest, src0, src1);
198 case BRW_OPCODE_SAD2:
199 fprintf(stderr, "Opcode BRW_OPCODE_SAD2 unhandled\n");
201 case BRW_OPCODE_SADA2:
202 fprintf(stderr, "Opcode BRW_OPCODE_SADA2 unhandled\n");
204 case BRW_OPCODE_SUBB:
205 brw_SUBB(p, dest, src0, src1);
208 brw_ADD(p, dest, src0, src1);
211 /* Third parameter is conditional modifier
212 * which gets updated later
214 brw_CMP(p, dest, 0, src0, src1);
217 brw_AND(p, dest, src0, src1);
220 brw_ASR(p, dest, src0, src1);
223 brw_AVG(p, dest, src0, src1);
226 brw_OR(p, dest, src0, src1);
229 brw_SEL(p, dest, src0, src1);
232 brw_SHL(p, dest, src0, src1);
235 brw_SHR(p, dest, src0, src1);
238 brw_XOR(p, dest, src0, src1);
241 brw_MUL(p, dest, src0, src1);
244 fprintf(stderr, "Unsupported binary opcode\n");
249 i965_asm_ternary_instruction(int opcode,
250 struct brw_codegen *p,
258 brw_MAD(p, dest, src0, src1, src2);
260 case BRW_OPCODE_CSEL:
261 brw_CSEL(p, dest, src0, src1, src2);
264 brw_LRP(p, dest, src0, src1, src2);
267 brw_BFE(p, dest, src0, src1, src2);
269 case BRW_OPCODE_BFI2:
270 brw_BFI2(p, dest, src0, src1, src2);
273 fprintf(stderr, "Unsupported ternary opcode\n");
278 i965_asm_set_instruction_options(struct brw_codegen *p,
279 struct options options)
281 brw_inst_set_access_mode(p->devinfo, brw_last_inst,
282 options.access_mode);
283 brw_inst_set_mask_control(p->devinfo, brw_last_inst,
284 options.mask_control);
285 brw_inst_set_thread_control(p->devinfo, brw_last_inst,
286 options.thread_control);
287 brw_inst_set_no_dd_check(p->devinfo, brw_last_inst,
288 options.no_dd_check);
289 brw_inst_set_no_dd_clear(p->devinfo, brw_last_inst,
290 options.no_dd_clear);
291 brw_inst_set_debug_control(p->devinfo, brw_last_inst,
292 options.debug_control);
293 if (p->devinfo->gen >= 6)
294 brw_inst_set_acc_wr_control(p->devinfo, brw_last_inst,
295 options.acc_wr_control);
296 brw_inst_set_cmpt_control(p->devinfo, brw_last_inst,
301 i965_asm_set_dst_nr(struct brw_codegen *p,
303 struct options options)
305 if (p->devinfo->gen <= 6) {
306 if (reg->file == BRW_MESSAGE_REGISTER_FILE &&
307 options.qtr_ctrl == BRW_COMPRESSION_COMPRESSED &&
309 reg->nr |= BRW_MRF_COMPR4;
322 unsigned long long int llint;
324 struct brw_codegen *program;
325 struct predicate predicate;
326 struct condition condition;
327 struct options options;
328 brw_inst *instruction;
338 %token LSQUARE RSQUARE
343 %token <integer> TYPE_B TYPE_UB
344 %token <integer> TYPE_W TYPE_UW
345 %token <integer> TYPE_D TYPE_UD
346 %token <integer> TYPE_Q TYPE_UQ
347 %token <integer> TYPE_V TYPE_UV
348 %token <integer> TYPE_F TYPE_HF
349 %token <integer> TYPE_DF TYPE_NF
350 %token <integer> TYPE_VF
353 %token <integer> ADD ADD3 ADDC AND ASR AVG
354 %token <integer> BFE BFI1 BFI2 BFB BFREV BRC BRD BREAK
355 %token <integer> CALL CALLA CASE CBIT CMP CMPN CONT CSEL
356 %token <integer> DIM DO DPAS DPASW DP2 DP3 DP4 DP4A DPH
357 %token <integer> ELSE ENDIF F16TO32 F32TO16 FBH FBL FORK FRC
358 %token <integer> GOTO
359 %token <integer> HALT
360 %token <integer> IF IFF ILLEGAL
361 %token <integer> JMPI JOIN
362 %token <integer> LINE LRP LZD
363 %token <integer> MAC MACH MAD MADM MOV MOVI MUL MREST MSAVE
364 %token <integer> NENOP NOP NOT
366 %token <integer> PLN POP PUSH
367 %token <integer> RET RNDD RNDE RNDU RNDZ ROL ROR
368 %token <integer> SAD2 SADA2 SEL SEND SENDC SENDS SENDSC SHL SHR SMOV SUBB SYNC
369 %token <integer> WAIT WHILE
372 /* extended math functions */
373 %token <integer> COS EXP FDIV INV INVM INTDIV INTDIVMOD INTMOD LOG POW RSQ
374 %token <integer> RSQRTM SIN SINCOS SQRT
376 /* shared functions for send */
377 %token CONST CRE DATA DP_DATA_1 GATEWAY MATH PIXEL_INTERP READ RENDER SAMPLER
378 %token THREAD_SPAWNER URB VME WRITE DP_SAMPLER
380 /* Conditional modifiers */
381 %token <integer> EQUAL GREATER GREATER_EQUAL LESS LESS_EQUAL NOT_EQUAL
382 %token <integer> NOT_ZERO OVERFLOW UNORDERED ZERO
384 /* register Access Modes */
385 %token ALIGN1 ALIGN16
387 /* accumulator write control */
390 /* compaction control */
393 /* compression control */
394 %token COMPR COMPR4 SECHALF
396 /* mask control (WeCtrl) */
402 /* dependency control */
403 %token NODDCLR NODDCHK
411 /* predicate control */
412 %token <integer> ANYV ALLV ANY2H ALL2H ANY4H ALL4H ANY8H ALL8H ANY16H ALL16H
413 %token <integer> ANY32H ALL32H
415 /* round instructions */
416 %token <integer> ROUND_INCREMENT
425 %token QTR_2Q QTR_3Q QTR_4Q QTR_2H QTR_2N QTR_3N QTR_4N QTR_5N
426 %token QTR_6N QTR_7N QTR_8N
429 %token <integer> X Y Z W
432 %token GENREGFILE MSGREGFILE
434 /* vertical stride in register region */
438 %token <integer> GENREG MSGREG ADDRREG ACCREG FLAGREG NOTIFYREG STATEREG
439 %token <integer> CONTROLREG IPREG PERFORMANCEREG THREADREG CHANNELENABLEREG
440 %token <integer> MASKREG
442 %token <integer> INTEGER
446 %precedence SUBREGNUM
449 %precedence EMPTYEXECSIZE
452 %type <integer> execsize simple_int exp
455 /* predicate control */
456 %type <integer> predctrl predstate
457 %type <predicate> predicate
459 /* conditional modifier */
460 %type <condition> cond_mod
461 %type <integer> condModifiers
463 /* instruction options */
464 %type <options> instoptions instoption_list
465 %type <integer> instoption
468 %type <integer> writemask_x writemask_y writemask_z writemask_w
469 %type <reg> writemask
472 %type <reg> dst dstoperand dstoperandex dstoperandex_typed dstreg dsttype
473 %type <integer> dstregion
475 %type <integer> saturate relativelocation rellocation
476 %type <reg> relativelocation2
479 %type <reg> directsrcoperand directsrcaccoperand indirectsrcoperand srcacc
480 %type <reg> srcarcoperandex srcaccimm srcarcoperandex_typed srctype srcimm
481 %type <reg> srcimmtype indirectgenreg indirectregion
482 %type <reg> immreg src reg32 payload directgenreg_list addrparam region
483 %type <reg> region_wh swizzle directgenreg directmsgreg indirectmsgreg
486 %type <reg> accreg addrreg channelenablereg controlreg flagreg ipreg
487 %type <reg> notifyreg nullreg performancereg threadcontrolreg statereg maskreg
488 %type <integer> subregnum
490 /* immediate values */
493 /* instruction opcodes */
494 %type <integer> unaryopcodes binaryopcodes binaryaccopcodes ternaryopcodes
495 %type <integer> sendop
496 %type <instruction> sendopcode
498 %type <integer> negate abs chansel math_function sharedfunction
503 add_instruction_option(struct options *options, int option)
507 options->access_mode = BRW_ALIGN_1;
510 options->access_mode = BRW_ALIGN_16;
513 options->qtr_ctrl |= BRW_COMPRESSION_2NDHALF;
516 options->qtr_ctrl |= BRW_COMPRESSION_COMPRESSED;
517 options->is_compr = true;
520 options->qtr_ctrl |= BRW_COMPRESSION_COMPRESSED;
523 options->thread_control |= BRW_THREAD_SWITCH;
526 options->thread_control |= BRW_THREAD_ATOMIC;
529 options->no_dd_check = true;
532 options->no_dd_clear = BRW_DEPENDENCY_NOTCLEARED;
535 options->mask_control |= BRW_MASK_DISABLE;
538 options->debug_control = BRW_DEBUG_BREAKPOINT;
541 options->mask_control |= BRW_WE_ALL;
544 options->compaction = true;
547 options->acc_wr_control = true;
550 options->end_of_thread = true;
552 /* TODO : Figure out how to set instruction group and get rid of
556 options->qtr_ctrl = BRW_COMPRESSION_2NDHALF;
559 options->qtr_ctrl = BRW_COMPRESSION_COMPRESSED;
562 options->qtr_ctrl = 3;
565 options->qtr_ctrl = BRW_COMPRESSION_COMPRESSED;
568 options->qtr_ctrl = BRW_COMPRESSION_NONE;
569 options->nib_ctrl = true;
572 options->qtr_ctrl = BRW_COMPRESSION_2NDHALF;
575 options->qtr_ctrl = BRW_COMPRESSION_2NDHALF;
576 options->nib_ctrl = true;
579 options->qtr_ctrl = BRW_COMPRESSION_COMPRESSED;
582 options->qtr_ctrl = BRW_COMPRESSION_COMPRESSED;
583 options->nib_ctrl = true;
586 options->qtr_ctrl = 3;
589 options->qtr_ctrl = 3;
590 options->nib_ctrl = true;
602 instrseq instruction SEMICOLON
603 | instrseq relocatableinstruction SEMICOLON
604 | instruction SEMICOLON
605 | relocatableinstruction SEMICOLON
608 /* Instruction Group */
612 | binaryaccinstruction
621 relocatableinstruction:
629 ILLEGAL execsize instoptions
631 brw_next_insn(p, $1);
632 brw_inst_set_exec_size(p->devinfo, brw_last_inst, $2);
633 i965_asm_set_instruction_options(p, $3);
637 /* Unary instruction */
639 predicate unaryopcodes saturate cond_mod execsize dst srcaccimm instoptions
641 i965_asm_set_dst_nr(p, &$6, $8);
642 brw_set_default_access_mode(p, $8.access_mode);
643 i965_asm_unary_instruction($2, p, $6, $7);
644 brw_pop_insn_state(p);
645 i965_asm_set_instruction_options(p, $8);
646 brw_inst_set_cond_modifier(p->devinfo, brw_last_inst,
649 if (p->devinfo->gen >= 7) {
650 if ($2 != BRW_OPCODE_DIM) {
651 brw_inst_set_flag_reg_nr(p->devinfo,
654 brw_inst_set_flag_subreg_nr(p->devinfo,
660 if ($7.file != BRW_IMMEDIATE_VALUE) {
661 brw_inst_set_src0_vstride(p->devinfo, brw_last_inst,
664 brw_inst_set_saturate(p->devinfo, brw_last_inst, $3);
665 brw_inst_set_exec_size(p->devinfo, brw_last_inst, $5);
666 // TODO: set instruction group instead of qtr and nib ctrl
667 brw_inst_set_qtr_control(p->devinfo, brw_last_inst,
670 if (p->devinfo->gen >= 7)
671 brw_inst_set_nib_control(p->devinfo, brw_last_inst,
694 /* Binary instruction */
696 predicate binaryopcodes saturate cond_mod execsize dst srcimm srcimm instoptions
698 i965_asm_set_dst_nr(p, &$6, $9);
699 brw_set_default_access_mode(p, $9.access_mode);
700 i965_asm_binary_instruction($2, p, $6, $7, $8);
701 i965_asm_set_instruction_options(p, $9);
702 brw_inst_set_cond_modifier(p->devinfo, brw_last_inst,
705 if (p->devinfo->gen >= 7) {
706 brw_inst_set_flag_reg_nr(p->devinfo, brw_last_inst,
708 brw_inst_set_flag_subreg_nr(p->devinfo, brw_last_inst,
712 brw_inst_set_saturate(p->devinfo, brw_last_inst, $3);
713 brw_inst_set_exec_size(p->devinfo, brw_last_inst, $5);
714 // TODO: set instruction group instead of qtr and nib ctrl
715 brw_inst_set_qtr_control(p->devinfo, brw_last_inst,
718 if (p->devinfo->gen >= 7)
719 brw_inst_set_nib_control(p->devinfo, brw_last_inst,
722 brw_pop_insn_state(p);
745 /* Binary acc instruction */
746 binaryaccinstruction:
747 predicate binaryaccopcodes saturate cond_mod execsize dst srcacc srcimm instoptions
749 i965_asm_set_dst_nr(p, &$6, $9);
750 brw_set_default_access_mode(p, $9.access_mode);
751 i965_asm_binary_instruction($2, p, $6, $7, $8);
752 brw_pop_insn_state(p);
753 i965_asm_set_instruction_options(p, $9);
754 brw_inst_set_cond_modifier(p->devinfo, brw_last_inst,
757 if (p->devinfo->gen >= 7) {
758 if (!brw_inst_flag_reg_nr(p->devinfo, brw_last_inst)) {
759 brw_inst_set_flag_reg_nr(p->devinfo,
762 brw_inst_set_flag_subreg_nr(p->devinfo,
768 brw_inst_set_saturate(p->devinfo, brw_last_inst, $3);
769 brw_inst_set_exec_size(p->devinfo, brw_last_inst, $5);
770 // TODO: set instruction group instead of qtr and nib ctrl
771 brw_inst_set_qtr_control(p->devinfo, brw_last_inst,
774 if (p->devinfo->gen >= 7)
775 brw_inst_set_nib_control(p->devinfo, brw_last_inst,
795 /* Math instruction */
797 predicate MATH saturate math_function execsize dst src srcimm instoptions
799 brw_set_default_access_mode(p, $9.access_mode);
800 gen6_math(p, $6, $4, $7, $8);
801 i965_asm_set_instruction_options(p, $9);
802 brw_inst_set_exec_size(p->devinfo, brw_last_inst, $5);
803 brw_inst_set_saturate(p->devinfo, brw_last_inst, $3);
804 // TODO: set instruction group instead
805 brw_inst_set_qtr_control(p->devinfo, brw_last_inst,
808 if (p->devinfo->gen >= 7)
809 brw_inst_set_nib_control(p->devinfo, brw_last_inst,
812 brw_pop_insn_state(p);
834 /* NOP instruction */
842 /* Ternary operand instruction */
844 predicate ternaryopcodes saturate cond_mod execsize dst src src src instoptions
846 brw_set_default_access_mode(p, $10.access_mode);
847 i965_asm_ternary_instruction($2, p, $6, $7, $8, $9);
848 brw_pop_insn_state(p);
849 i965_asm_set_instruction_options(p, $10);
850 brw_inst_set_cond_modifier(p->devinfo, brw_last_inst,
853 if (p->devinfo->gen >= 7) {
854 brw_inst_set_3src_a16_flag_reg_nr(p->devinfo, brw_last_inst,
856 brw_inst_set_3src_a16_flag_subreg_nr(p->devinfo, brw_last_inst,
860 brw_inst_set_saturate(p->devinfo, brw_last_inst, $3);
861 brw_inst_set_exec_size(p->devinfo, brw_last_inst, $5);
862 // TODO: set instruction group instead of qtr and nib ctrl
863 brw_inst_set_qtr_control(p->devinfo, brw_last_inst,
866 if (p->devinfo->gen >= 7)
867 brw_inst_set_nib_control(p->devinfo, brw_last_inst,
880 /* Sync instruction */
882 WAIT execsize src instoptions
884 brw_next_insn(p, $1);
885 i965_asm_set_instruction_options(p, $4);
886 brw_inst_set_exec_size(p->devinfo, brw_last_inst, $2);
887 brw_set_default_access_mode(p, $4.access_mode);
888 struct brw_reg src = brw_notification_reg();
889 brw_set_dest(p, brw_last_inst, src);
890 brw_set_src0(p, brw_last_inst, src);
891 brw_set_src1(p, brw_last_inst, brw_null_reg());
892 brw_inst_set_mask_control(p->devinfo, brw_last_inst, BRW_MASK_DISABLE);
896 /* Send instruction */
898 predicate sendopcode execsize dst payload exp2 sharedfunction instoptions
900 i965_asm_set_instruction_options(p, $8);
901 brw_inst_set_exec_size(p->devinfo, brw_last_inst, $3);
902 brw_set_dest(p, brw_last_inst, $4);
903 brw_set_src0(p, brw_last_inst, $5);
904 brw_inst_set_bits(brw_last_inst, 127, 96, $6);
905 brw_inst_set_src1_file_type(p->devinfo, brw_last_inst,
907 BRW_REGISTER_TYPE_UD);
908 brw_inst_set_sfid(p->devinfo, brw_last_inst, $7);
909 brw_inst_set_eot(p->devinfo, brw_last_inst, $8.end_of_thread);
910 // TODO: set instruction group instead of qtr and nib ctrl
911 brw_inst_set_qtr_control(p->devinfo, brw_last_inst,
914 if (p->devinfo->gen >= 7)
915 brw_inst_set_nib_control(p->devinfo, brw_last_inst,
918 brw_pop_insn_state(p);
920 | predicate sendopcode execsize exp dst payload exp2 sharedfunction instoptions
922 i965_asm_set_instruction_options(p, $9);
923 brw_inst_set_exec_size(p->devinfo, brw_last_inst, $3);
924 brw_inst_set_base_mrf(p->devinfo, brw_last_inst, $4);
925 brw_set_dest(p, brw_last_inst, $5);
926 brw_set_src0(p, brw_last_inst, $6);
927 brw_inst_set_bits(brw_last_inst, 127, 96, $7);
928 brw_inst_set_src1_file_type(p->devinfo, brw_last_inst,
930 BRW_REGISTER_TYPE_UD);
931 brw_inst_set_sfid(p->devinfo, brw_last_inst, $8);
932 brw_inst_set_eot(p->devinfo, brw_last_inst, $9.end_of_thread);
933 // TODO: set instruction group instead of qtr and nib ctrl
934 brw_inst_set_qtr_control(p->devinfo, brw_last_inst,
937 if (p->devinfo->gen >= 7)
938 brw_inst_set_nib_control(p->devinfo, brw_last_inst,
941 brw_pop_insn_state(p);
943 | predicate sendopcode execsize dst payload payload exp2 sharedfunction instoptions
945 i965_asm_set_instruction_options(p, $9);
946 brw_inst_set_exec_size(p->devinfo, brw_last_inst, $3);
947 brw_set_dest(p, brw_last_inst, $4);
948 brw_set_src0(p, brw_last_inst, $5);
949 brw_inst_set_bits(brw_last_inst, 127, 96, $7);
950 brw_inst_set_sfid(p->devinfo, brw_last_inst, $8);
951 brw_inst_set_eot(p->devinfo, brw_last_inst, $9.end_of_thread);
952 // TODO: set instruction group instead of qtr and nib ctrl
953 brw_inst_set_qtr_control(p->devinfo, brw_last_inst,
956 if (p->devinfo->gen >= 7)
957 brw_inst_set_nib_control(p->devinfo, brw_last_inst,
960 brw_pop_insn_state(p);
962 | predicate SENDS execsize dst payload payload exp2 exp2 sharedfunction instoptions
964 brw_next_insn(p, $2);
965 i965_asm_set_instruction_options(p, $10);
966 brw_inst_set_exec_size(p->devinfo, brw_last_inst, $3);
967 brw_set_dest(p, brw_last_inst, $4);
968 brw_set_src0(p, brw_last_inst, $5);
969 brw_set_src1(p, brw_last_inst, $6);
971 if (brw_inst_send_sel_reg32_ex_desc(p->devinfo, brw_last_inst)) {
972 brw_inst_set_send_ex_desc_ia_subreg_nr(p->devinfo, brw_last_inst, $5.subnr);
974 brw_inst_set_sends_ex_desc(p->devinfo, brw_last_inst, $8);
977 brw_inst_set_bits(brw_last_inst, 127, 96, $7);
978 brw_inst_set_sfid(p->devinfo, brw_last_inst, $9);
979 brw_inst_set_eot(p->devinfo, brw_last_inst, $10.end_of_thread);
980 // TODO: set instruction group instead of qtr and nib ctrl
981 brw_inst_set_qtr_control(p->devinfo, brw_last_inst,
984 if (p->devinfo->gen >= 7)
985 brw_inst_set_nib_control(p->devinfo, brw_last_inst,
988 brw_pop_insn_state(p);
990 | predicate SENDS execsize dst payload payload src exp2 sharedfunction instoptions
992 brw_next_insn(p, $2);
993 i965_asm_set_instruction_options(p, $10);
994 brw_inst_set_exec_size(p->devinfo, brw_last_inst, $3);
995 brw_set_dest(p, brw_last_inst, $4);
996 brw_set_src0(p, brw_last_inst, $5);
997 brw_set_src1(p, brw_last_inst, $6);
999 brw_inst_set_send_sel_reg32_desc(p->devinfo, brw_last_inst, 1);
1000 brw_inst_set_sends_ex_desc(p->devinfo, brw_last_inst, $8);
1002 brw_inst_set_sfid(p->devinfo, brw_last_inst, $9);
1003 brw_inst_set_eot(p->devinfo, brw_last_inst, $10.end_of_thread);
1004 // TODO: set instruction group instead of qtr and nib ctrl
1005 brw_inst_set_qtr_control(p->devinfo, brw_last_inst,
1008 if (p->devinfo->gen >= 7)
1009 brw_inst_set_nib_control(p->devinfo, brw_last_inst,
1012 brw_pop_insn_state(p);
1022 sendop { $$ = brw_next_insn(p, $1); }
1026 NULL_TOKEN { $$ = BRW_SFID_NULL; }
1027 | MATH { $$ = BRW_SFID_MATH; }
1028 | GATEWAY { $$ = BRW_SFID_MESSAGE_GATEWAY; }
1029 | READ { $$ = BRW_SFID_DATAPORT_READ; }
1030 | WRITE { $$ = BRW_SFID_DATAPORT_WRITE; }
1031 | URB { $$ = BRW_SFID_URB; }
1032 | THREAD_SPAWNER { $$ = BRW_SFID_THREAD_SPAWNER; }
1033 | VME { $$ = BRW_SFID_VME; }
1034 | RENDER { $$ = GEN6_SFID_DATAPORT_RENDER_CACHE; }
1035 | CONST { $$ = GEN6_SFID_DATAPORT_CONSTANT_CACHE; }
1036 | DATA { $$ = GEN7_SFID_DATAPORT_DATA_CACHE; }
1037 | PIXEL_INTERP { $$ = GEN7_SFID_PIXEL_INTERPOLATOR; }
1038 | DP_DATA_1 { $$ = HSW_SFID_DATAPORT_DATA_CACHE_1; }
1039 | CRE { $$ = HSW_SFID_CRE; }
1040 | SAMPLER { $$ = BRW_SFID_SAMPLER; }
1041 | DP_SAMPLER { $$ = GEN6_SFID_DATAPORT_SAMPLER_CACHE; }
1046 | MINUS LONG { $$ = -$2; }
1049 /* Jump instruction */
1051 predicate JMPI execsize relativelocation2 instoptions
1053 brw_next_insn(p, $2);
1054 i965_asm_set_instruction_options(p, $5);
1055 brw_inst_set_exec_size(p->devinfo, brw_last_inst, $3);
1056 brw_set_dest(p, brw_last_inst, brw_ip_reg());
1057 brw_set_src0(p, brw_last_inst, brw_ip_reg());
1058 brw_set_src1(p, brw_last_inst, $4);
1059 brw_inst_set_pred_control(p->devinfo, brw_last_inst,
1060 brw_inst_pred_control(p->devinfo,
1062 brw_pop_insn_state(p);
1066 /* branch instruction */
1068 predicate ENDIF execsize relativelocation instoptions
1070 brw_next_insn(p, $2);
1071 i965_asm_set_instruction_options(p, $5);
1072 brw_inst_set_exec_size(p->devinfo, brw_last_inst, $3);
1074 if (p->devinfo->gen < 6) {
1075 brw_set_dest(p, brw_last_inst, retype(brw_null_reg(),
1076 BRW_REGISTER_TYPE_D));
1077 brw_set_src0(p, brw_last_inst, retype(brw_null_reg(),
1078 BRW_REGISTER_TYPE_D));
1079 brw_set_src1(p, brw_last_inst, brw_imm_d(0x0));
1080 brw_inst_set_gen4_pop_count(p->devinfo, brw_last_inst,
1082 } else if (p->devinfo->gen == 6) {
1083 brw_set_dest(p, brw_last_inst, brw_imm_w(0x0));
1084 brw_inst_set_gen6_jump_count(p->devinfo, brw_last_inst,
1086 brw_set_src0(p, brw_last_inst, retype(brw_null_reg(),
1087 BRW_REGISTER_TYPE_D));
1088 brw_set_src1(p, brw_last_inst, retype(brw_null_reg(),
1089 BRW_REGISTER_TYPE_D));
1090 } else if (p->devinfo->gen == 7) {
1091 brw_set_dest(p, brw_last_inst, retype(brw_null_reg(),
1092 BRW_REGISTER_TYPE_D));
1093 brw_set_src0(p, brw_last_inst, retype(brw_null_reg(),
1094 BRW_REGISTER_TYPE_D));
1095 brw_set_src1(p, brw_last_inst, brw_imm_w(0x0));
1096 brw_inst_set_jip(p->devinfo, brw_last_inst, $4);
1098 brw_set_src0(p, brw_last_inst, brw_imm_d($4));
1101 if (p->devinfo->gen < 6)
1102 brw_inst_set_thread_control(p->devinfo, brw_last_inst,
1104 brw_pop_insn_state(p);
1106 | ELSE execsize relativelocation rellocation instoptions
1108 brw_next_insn(p, $1);
1109 i965_asm_set_instruction_options(p, $5);
1110 brw_inst_set_exec_size(p->devinfo, brw_last_inst, $2);
1112 if (p->devinfo->gen < 6) {
1113 brw_set_dest(p, brw_last_inst, brw_ip_reg());
1114 brw_set_src0(p, brw_last_inst, brw_ip_reg());
1115 brw_set_src1(p, brw_last_inst, brw_imm_d(0x0));
1116 brw_inst_set_gen4_jump_count(p->devinfo, brw_last_inst,
1118 brw_inst_set_gen4_pop_count(p->devinfo, brw_last_inst,
1120 } else if (p->devinfo->gen == 6) {
1121 brw_set_dest(p, brw_last_inst, brw_imm_w(0x0));
1122 brw_inst_set_gen6_jump_count(p->devinfo, brw_last_inst,
1124 brw_set_src0(p, brw_last_inst, retype(brw_null_reg(),
1125 BRW_REGISTER_TYPE_D));
1126 brw_set_src1(p, brw_last_inst, retype(brw_null_reg(),
1127 BRW_REGISTER_TYPE_D));
1128 } else if (p->devinfo->gen == 7) {
1129 brw_set_dest(p, brw_last_inst, retype(brw_null_reg(),
1130 BRW_REGISTER_TYPE_D));
1131 brw_set_src0(p, brw_last_inst, retype(brw_null_reg(),
1132 BRW_REGISTER_TYPE_D));
1133 brw_set_src1(p, brw_last_inst, brw_imm_w($3));
1134 brw_inst_set_jip(p->devinfo, brw_last_inst, $3);
1135 brw_inst_set_uip(p->devinfo, brw_last_inst, $4);
1137 brw_set_dest(p, brw_last_inst, retype(brw_null_reg(),
1138 BRW_REGISTER_TYPE_D));
1139 brw_set_src0(p, brw_last_inst, brw_imm_d($3));
1140 brw_inst_set_jip(p->devinfo, brw_last_inst, $3);
1141 brw_inst_set_uip(p->devinfo, brw_last_inst, $4);
1144 if (!p->single_program_flow && p->devinfo->gen < 6)
1145 brw_inst_set_thread_control(p->devinfo, brw_last_inst,
1148 | predicate IF execsize relativelocation rellocation instoptions
1150 brw_next_insn(p, $2);
1151 i965_asm_set_instruction_options(p, $6);
1152 brw_inst_set_exec_size(p->devinfo, brw_last_inst, $3);
1154 if (p->devinfo->gen < 6) {
1155 brw_set_dest(p, brw_last_inst, brw_ip_reg());
1156 brw_set_src0(p, brw_last_inst, brw_ip_reg());
1157 brw_set_src1(p, brw_last_inst, brw_imm_d(0x0));
1158 brw_inst_set_gen4_jump_count(p->devinfo, brw_last_inst,
1160 brw_inst_set_gen4_pop_count(p->devinfo, brw_last_inst,
1162 } else if (p->devinfo->gen == 6) {
1163 brw_set_dest(p, brw_last_inst, brw_imm_w(0x0));
1164 brw_inst_set_gen6_jump_count(p->devinfo, brw_last_inst,
1166 brw_set_src0(p, brw_last_inst,
1167 vec1(retype(brw_null_reg(),
1168 BRW_REGISTER_TYPE_D)));
1169 brw_set_src1(p, brw_last_inst,
1170 vec1(retype(brw_null_reg(),
1171 BRW_REGISTER_TYPE_D)));
1172 } else if (p->devinfo->gen == 7) {
1173 brw_set_dest(p, brw_last_inst,
1174 vec1(retype(brw_null_reg(),
1175 BRW_REGISTER_TYPE_D)));
1176 brw_set_src0(p, brw_last_inst,
1177 vec1(retype(brw_null_reg(),
1178 BRW_REGISTER_TYPE_D)));
1179 brw_set_src1(p, brw_last_inst, brw_imm_w($4));
1180 brw_inst_set_jip(p->devinfo, brw_last_inst, $4);
1181 brw_inst_set_uip(p->devinfo, brw_last_inst, $5);
1183 brw_set_dest(p, brw_last_inst,
1184 vec1(retype(brw_null_reg(),
1185 BRW_REGISTER_TYPE_D)));
1186 brw_set_src0(p, brw_last_inst, brw_imm_d($4));
1187 brw_inst_set_jip(p->devinfo, brw_last_inst, $4);
1188 brw_inst_set_uip(p->devinfo, brw_last_inst, $5);
1191 if (!p->single_program_flow && p->devinfo->gen < 6)
1192 brw_inst_set_thread_control(p->devinfo, brw_last_inst,
1195 brw_pop_insn_state(p);
1197 | predicate IFF execsize relativelocation instoptions
1199 brw_next_insn(p, $2);
1200 i965_asm_set_instruction_options(p, $5);
1201 brw_inst_set_exec_size(p->devinfo, brw_last_inst, $3);
1203 if (p->devinfo->gen < 6) {
1204 brw_set_dest(p, brw_last_inst, brw_ip_reg());
1205 brw_set_src0(p, brw_last_inst, brw_ip_reg());
1206 brw_inst_set_gen4_jump_count(p->devinfo, brw_last_inst,
1208 brw_set_src1(p, brw_last_inst, brw_imm_d($4));
1209 } else if (p->devinfo->gen == 6) {
1210 brw_set_dest(p, brw_last_inst, brw_imm_w($4));
1211 brw_inst_set_gen6_jump_count(p->devinfo, brw_last_inst,
1213 brw_set_src0(p, brw_last_inst,
1214 vec1(retype(brw_null_reg(),
1215 BRW_REGISTER_TYPE_D)));
1216 brw_set_src1(p, brw_last_inst,
1217 vec1(retype(brw_null_reg(),
1218 BRW_REGISTER_TYPE_D)));
1219 } else if (p->devinfo->gen == 7) {
1220 brw_set_dest(p, brw_last_inst,
1221 vec1(retype(brw_null_reg(),
1222 BRW_REGISTER_TYPE_D)));
1223 brw_set_src0(p, brw_last_inst,
1224 vec1(retype(brw_null_reg(),
1225 BRW_REGISTER_TYPE_D)));
1226 brw_set_src1(p, brw_last_inst, brw_imm_w($4));
1227 brw_inst_set_jip(p->devinfo, brw_last_inst, $4);
1229 brw_set_dest(p, brw_last_inst,
1230 vec1(retype(brw_null_reg(),
1231 BRW_REGISTER_TYPE_D)));
1232 brw_set_src0(p, brw_last_inst, brw_imm_d($4));
1233 brw_inst_set_jip(p->devinfo, brw_last_inst, $4);
1236 if (!p->single_program_flow && p->devinfo->gen < 6)
1237 brw_inst_set_thread_control(p->devinfo, brw_last_inst,
1240 brw_pop_insn_state(p);
1244 /* break instruction */
1246 predicate BREAK execsize relativelocation relativelocation instoptions
1248 brw_next_insn(p, $2);
1249 i965_asm_set_instruction_options(p, $6);
1250 brw_inst_set_exec_size(p->devinfo, brw_last_inst, $3);
1252 if (p->devinfo->gen >= 8) {
1253 brw_set_dest(p, brw_last_inst, retype(brw_null_reg(),
1254 BRW_REGISTER_TYPE_D));
1255 brw_set_src0(p, brw_last_inst, brw_imm_d($4));
1256 brw_inst_set_uip(p->devinfo, brw_last_inst, $5);
1257 } else if (p->devinfo->gen >= 6) {
1258 brw_set_dest(p, brw_last_inst, retype(brw_null_reg(),
1259 BRW_REGISTER_TYPE_D));
1260 brw_set_src0(p, brw_last_inst, retype(brw_null_reg(),
1261 BRW_REGISTER_TYPE_D));
1262 brw_set_src1(p, brw_last_inst, brw_imm_d(0x0));
1263 brw_inst_set_jip(p->devinfo, brw_last_inst, $4);
1264 brw_inst_set_uip(p->devinfo, brw_last_inst, $5);
1266 brw_set_dest(p, brw_last_inst, brw_ip_reg());
1267 brw_set_src0(p, brw_last_inst, brw_ip_reg());
1268 brw_set_src1(p, brw_last_inst, brw_imm_d(0x0));
1269 brw_inst_set_gen4_jump_count(p->devinfo, brw_last_inst,
1271 brw_inst_set_gen4_pop_count(p->devinfo, brw_last_inst,
1275 brw_pop_insn_state(p);
1277 | predicate HALT execsize relativelocation relativelocation instoptions
1279 brw_next_insn(p, $2);
1280 i965_asm_set_instruction_options(p, $6);
1281 brw_inst_set_exec_size(p->devinfo, brw_last_inst, $3);
1282 brw_set_dest(p, brw_last_inst, retype(brw_null_reg(),
1283 BRW_REGISTER_TYPE_D));
1285 if (p->devinfo->gen >= 8) {
1286 brw_set_src0(p, brw_last_inst, brw_imm_d($4));
1287 brw_inst_set_uip(p->devinfo, brw_last_inst, $5);
1289 brw_set_src0(p, brw_last_inst, retype(brw_null_reg(),
1290 BRW_REGISTER_TYPE_D));
1291 brw_set_src1(p, brw_last_inst, brw_imm_d($5));
1294 brw_inst_set_jip(p->devinfo, brw_last_inst, $4);
1295 brw_inst_set_uip(p->devinfo, brw_last_inst, $5);
1296 brw_pop_insn_state(p);
1298 | predicate CONT execsize relativelocation relativelocation instoptions
1300 brw_next_insn(p, $2);
1301 i965_asm_set_instruction_options(p, $6);
1302 brw_inst_set_exec_size(p->devinfo, brw_last_inst, $3);
1303 brw_set_dest(p, brw_last_inst, brw_ip_reg());
1305 if (p->devinfo->gen >= 8) {
1306 brw_set_src0(p, brw_last_inst, brw_imm_d(0x0));
1307 brw_inst_set_jip(p->devinfo, brw_last_inst, $4);
1308 brw_inst_set_uip(p->devinfo, brw_last_inst, $5);
1310 brw_set_src0(p, brw_last_inst, brw_ip_reg());
1311 brw_set_src1(p, brw_last_inst, brw_imm_d(0x0));
1312 if (p->devinfo->gen >= 6) {
1313 brw_inst_set_jip(p->devinfo, brw_last_inst, $4);
1314 brw_inst_set_uip(p->devinfo, brw_last_inst, $5);
1316 brw_inst_set_gen4_jump_count(p->devinfo, brw_last_inst,
1318 brw_inst_set_gen4_pop_count(p->devinfo, brw_last_inst,
1323 brw_pop_insn_state(p);
1327 /* loop instruction */
1329 predicate WHILE execsize relativelocation instoptions
1331 brw_next_insn(p, $2);
1332 i965_asm_set_instruction_options(p, $5);
1333 brw_inst_set_exec_size(p->devinfo, brw_last_inst, $3);
1335 if (p->devinfo->gen >= 6) {
1336 if (p->devinfo->gen >= 8) {
1337 brw_set_dest(p, brw_last_inst,
1338 retype(brw_null_reg(),
1339 BRW_REGISTER_TYPE_D));
1340 brw_set_src0(p, brw_last_inst, brw_imm_d($4));
1341 } else if (p->devinfo->gen == 7) {
1342 brw_set_dest(p, brw_last_inst,
1343 retype(brw_null_reg(),
1344 BRW_REGISTER_TYPE_D));
1345 brw_set_src0(p, brw_last_inst,
1346 retype(brw_null_reg(),
1347 BRW_REGISTER_TYPE_D));
1348 brw_set_src1(p, brw_last_inst,
1350 brw_inst_set_jip(p->devinfo, brw_last_inst,
1353 brw_set_dest(p, brw_last_inst, brw_imm_w(0x0));
1354 brw_inst_set_gen6_jump_count(p->devinfo,
1357 brw_set_src0(p, brw_last_inst,
1358 retype(brw_null_reg(),
1359 BRW_REGISTER_TYPE_D));
1360 brw_set_src1(p, brw_last_inst,
1361 retype(brw_null_reg(),
1362 BRW_REGISTER_TYPE_D));
1365 brw_set_dest(p, brw_last_inst, brw_ip_reg());
1366 brw_set_src0(p, brw_last_inst, brw_ip_reg());
1367 brw_set_src1(p, brw_last_inst, brw_imm_d(0x0));
1368 brw_inst_set_gen4_jump_count(p->devinfo, brw_last_inst,
1370 brw_inst_set_gen4_pop_count(p->devinfo, brw_last_inst,
1373 brw_pop_insn_state(p);
1375 | DO execsize instoptions
1377 brw_next_insn(p, $1);
1378 if (p->devinfo->gen < 6) {
1379 brw_inst_set_exec_size(p->devinfo, brw_last_inst, $2);
1380 i965_asm_set_instruction_options(p, $3);
1381 brw_set_dest(p, brw_last_inst, brw_null_reg());
1382 brw_set_src0(p, brw_last_inst, brw_null_reg());
1383 brw_set_src1(p, brw_last_inst, brw_null_reg());
1385 brw_inst_set_qtr_control(p->devinfo, brw_last_inst, BRW_COMPRESSION_NONE);
1390 /* Relative location */
1397 INTEGER { $$ = $1; }
1398 | MINUS INTEGER { $$ = -$2; }
1400 | MINUS LONG { $$ = -$2; }
1405 | %empty { $$ = 0; }
1415 /* Destination register */
1422 dstreg dstregion writemask dsttype
1427 $$.hstride = BRW_HORIZONTAL_STRIDE_1;
1428 $$.vstride = BRW_VERTICAL_STRIDE_1;
1429 $$.width = BRW_WIDTH_1;
1434 $$.writemask = $3.writemask;
1435 $$.swizzle = BRW_SWIZZLE_NOOP;
1436 $$.subnr = $$.subnr * brw_reg_type_to_size($4.type);
1441 dstoperandex_typed dstregion writemask dsttype
1446 $$.writemask = $3.writemask;
1447 $$.subnr = $$.subnr * brw_reg_type_to_size($4.type);
1449 /* BSpec says "When the conditional modifier is present, updates
1450 * to the selected flag register also occur. In this case, the
1451 * register region fields of the ‘null’ operand are valid."
1453 | nullreg dstregion writemask dsttype
1457 $$.hstride = BRW_HORIZONTAL_STRIDE_1;
1458 $$.vstride = BRW_VERTICAL_STRIDE_1;
1459 $$.width = BRW_WIDTH_1;
1463 $$.writemask = $3.writemask;
1470 $$.type = BRW_REGISTER_TYPE_UW;
1490 $$.address_mode = BRW_ADDRESS_DIRECT;
1495 $$.address_mode = BRW_ADDRESS_REGISTER_INDIRECT_REGISTER;
1500 $$.address_mode = BRW_ADDRESS_DIRECT;
1505 $$.address_mode = BRW_ADDRESS_REGISTER_INDIRECT_REGISTER;
1509 /* Source register */
1521 case BRW_REGISTER_TYPE_UD:
1523 $$ = brw_imm_ud(u32);
1525 case BRW_REGISTER_TYPE_D:
1528 case BRW_REGISTER_TYPE_UW:
1529 u32 = $1 | ($1 << 16);
1530 $$ = brw_imm_uw(u32);
1532 case BRW_REGISTER_TYPE_W:
1534 $$ = brw_imm_w(u32);
1536 case BRW_REGISTER_TYPE_F:
1537 $$ = brw_imm_reg(BRW_REGISTER_TYPE_F);
1541 case BRW_REGISTER_TYPE_V:
1544 case BRW_REGISTER_TYPE_UV:
1545 $$ = brw_imm_uv($1);
1547 case BRW_REGISTER_TYPE_VF:
1548 $$ = brw_imm_reg(BRW_REGISTER_TYPE_VF);
1551 case BRW_REGISTER_TYPE_Q:
1553 $$ = brw_imm_q(u64);
1555 case BRW_REGISTER_TYPE_UQ:
1557 $$ = brw_imm_uq(u64);
1559 case BRW_REGISTER_TYPE_DF:
1560 $$ = brw_imm_reg(BRW_REGISTER_TYPE_DF);
1564 error(&@2, "Unknown immediate type %s\n",
1565 brw_reg_type_to_letters($2.type));
1571 directgenreg region srctype
1573 $$ = set_direct_src_operand(&$1, $3.type);
1574 $$ = stride($$, $2.vstride, $2.width, $2.hstride);
1584 | indirectsrcoperand
1589 | indirectsrcoperand
1594 | indirectsrcoperand
1598 directsrcaccoperand:
1600 | accreg region srctype
1602 $$ = set_direct_src_operand(&$1, $3.type);
1603 $$.vstride = $2.vstride;
1604 $$.width = $2.width;
1605 $$.hstride = $2.hstride;
1610 srcarcoperandex_typed region srctype
1612 $$ = brw_reg($1.file,
1624 | nullreg region srctype
1626 $$ = set_direct_src_operand(&$1, $3.type);
1627 $$.vstride = $2.vstride;
1628 $$.width = $2.width;
1629 $$.hstride = $2.hstride;
1633 $$ = set_direct_src_operand(&$1, BRW_REGISTER_TYPE_UW);
1637 srcarcoperandex_typed:
1647 negate abs indirectgenreg indirectregion swizzle srctype
1649 $$ = brw_reg($3.file,
1661 $$.address_mode = BRW_ADDRESS_REGISTER_INDIRECT_REGISTER;
1662 // brw_reg set indirect_offset to 0 so set it to valid value
1663 $$.indirect_offset = $3.indirect_offset;
1676 negate abs directgenreg_list region swizzle srctype
1678 $$ = brw_reg($3.file,
1693 /* Address register */
1697 memset(&$$, '\0', sizeof($$));
1698 $$.subnr = $1.subnr;
1699 $$.indirect_offset = $2;
1704 /* Register files and register numbers */
1706 INTEGER { $$ = $1; }
1711 DOT exp { $$ = $2; }
1712 | %empty %prec SUBREGNUM { $$ = 0; }
1718 memset(&$$, '\0', sizeof($$));
1719 $$.file = BRW_GENERAL_REGISTER_FILE;
1726 GENREGFILE LSQUARE addrparam RSQUARE
1728 memset(&$$, '\0', sizeof($$));
1729 $$.file = BRW_GENERAL_REGISTER_FILE;
1730 $$.subnr = $3.subnr;
1731 $$.indirect_offset = $3.indirect_offset;
1738 $$ = brw_message_reg($1);
1744 MSGREGFILE LSQUARE addrparam RSQUARE
1746 memset(&$$, '\0', sizeof($$));
1747 $$.file = BRW_MESSAGE_REGISTER_FILE;
1748 $$.subnr = $3.subnr;
1749 $$.indirect_offset = $3.indirect_offset;
1756 int subnr = (p->devinfo->gen >= 8) ? 16 : 8;
1759 error(&@2, "Address sub register number %d"
1760 "out of range\n", $2);
1762 $$.file = BRW_ARCHITECTURE_REGISTER_FILE;
1763 $$.nr = BRW_ARF_ADDRESS;
1772 if (p->devinfo->gen < 8)
1778 error(&@1, "Accumulator register number %d"
1779 " out of range\n", $1);
1781 memset(&$$, '\0', sizeof($$));
1782 $$.file = BRW_ARCHITECTURE_REGISTER_FILE;
1783 $$.nr = BRW_ARF_ACCUMULATOR;
1791 // SNB = 1 flag reg and IVB+ = 2 flag reg
1792 int nr_reg = (p->devinfo->gen >= 7) ? 2 : 1;
1796 error(&@1, "Flag register number %d"
1797 " out of range \n", $1);
1799 error(&@2, "Flag subregister number %d"
1800 " out of range\n", $2);
1802 $$.file = BRW_ARCHITECTURE_REGISTER_FILE;
1803 $$.nr = BRW_ARF_FLAG | $1;
1812 error(&@1, "Mask register number %d"
1813 " out of range\n", $1);
1815 $$ = brw_mask_reg($2);
1823 error(&@1, "Notification register number %d"
1824 " out of range\n", $1);
1826 int subnr = (p->devinfo->gen >= 11) ? 2 : 3;
1828 error(&@2, "Notification sub register number %d"
1829 " out of range\n", $2);
1831 $$ = brw_notification_reg();
1840 error(&@1, "State register number %d"
1841 " out of range\n", $1);
1844 error(&@2, "State sub register number %d"
1845 " out of range\n", $2);
1847 $$.file = BRW_ARCHITECTURE_REGISTER_FILE;
1848 $$.nr = BRW_ARF_STATE;
1854 CONTROLREG subregnum
1857 error(&@2, "control sub register number %d"
1858 " out of range\n", $2);
1860 $$ = brw_cr0_reg($2);
1865 IPREG { $$ = brw_ip_reg(); }
1869 NULL_TOKEN { $$ = brw_null_reg(); }
1876 error(&@1, "Thread control register number %d"
1877 " out of range\n", $1);
1880 error(&@2, "Thread control sub register number %d"
1881 " out of range\n", $2);
1889 PERFORMANCEREG subregnum
1892 if (p->devinfo->gen >= 10)
1894 else if (p->devinfo->gen <= 8)
1900 error(&@2, "Performance sub register number %d"
1901 " out of range\n", $2);
1903 $$.file = BRW_ARCHITECTURE_REGISTER_FILE;
1904 $$.nr = BRW_ARF_TIMESTAMP;
1909 CHANNELENABLEREG subregnum
1912 error(&@1, "Channel enable register number %d"
1913 " out of range\n", $1);
1915 $$ = brw_mask_reg($2);
1919 /* Immediate values */
1925 | LSQUARE exp2 COMMA exp2 COMMA exp2 COMMA exp2 RSQUARE
1927 $$ = ($2 << 0) | ($4 << 8) | ($6 << 16) | ($8 << 24);
1936 if ($2 != 0 && ($2 > 4 || !isPowerofTwo($2)))
1937 error(&@2, "Invalid Horizontal stride %d\n", $2);
1951 $$ = stride($$, BRW_VERTICAL_STRIDE_1, BRW_WIDTH_2, BRW_HORIZONTAL_STRIDE_1);
1955 if ($2 != 0 && ($2 > 32 || !isPowerofTwo($2)))
1956 error(&@2, "Invalid VertStride %d\n", $2);
1958 $$ = stride($$, $2, BRW_WIDTH_1, 0);
1960 | LANGLE exp COMMA exp COMMA exp RANGLE
1963 if ($2 != 0 && ($2 > 32 || !isPowerofTwo($2)))
1964 error(&@2, "Invalid VertStride %d\n", $2);
1966 if ($4 > 16 || !isPowerofTwo($4))
1967 error(&@4, "Invalid width %d\n", $4);
1969 if ($6 != 0 && ($6 > 4 || !isPowerofTwo($6)))
1970 error(&@6, "Invalid Horizontal stride in"
1971 " region_wh %d\n", $6);
1973 $$ = stride($$, $2, $4, $6);
1975 | LANGLE exp SEMICOLON exp COMMA exp RANGLE
1977 if ($2 != 0 && ($2 > 32 || !isPowerofTwo($2)))
1978 error(&@2, "Invalid VertStride %d\n", $2);
1980 if ($4 > 16 || !isPowerofTwo($4))
1981 error(&@4, "Invalid width %d\n", $4);
1983 if ($6 != 0 && ($6 > 4 || !isPowerofTwo($6)))
1984 error(&@6, "Invalid Horizontal stride in"
1985 " region_wh %d\n", $6);
1987 $$ = stride($$, $2, $4, $6);
1989 | LANGLE VxH COMMA exp COMMA exp RANGLE
1991 if ($4 > 16 || !isPowerofTwo($4))
1992 error(&@4, "Invalid width %d\n", $4);
1994 if ($6 != 0 && ($6 > 4 || !isPowerofTwo($6)))
1995 error(&@6, "Invalid Horizontal stride in"
1996 " region_wh %d\n", $6);
1998 $$ = brw_VxH_indirect(0, 0);
2003 LANGLE exp COMMA exp RANGLE
2005 if ($2 > 16 || !isPowerofTwo($2))
2006 error(&@2, "Invalid width %d\n", $2);
2008 if ($4 != 0 && ($4 > 4 || !isPowerofTwo($4)))
2009 error(&@4, "Invalid Horizontal stride in"
2010 " region_wh %d\n", $4);
2012 $$ = stride($$, BRW_VERTICAL_STRIDE_ONE_DIMENSIONAL, $2, $4);
2017 %empty { $$ = retype($$, BRW_REGISTER_TYPE_F); }
2018 | TYPE_F { $$ = retype($$, BRW_REGISTER_TYPE_F); }
2019 | TYPE_UD { $$ = retype($$, BRW_REGISTER_TYPE_UD); }
2020 | TYPE_D { $$ = retype($$, BRW_REGISTER_TYPE_D); }
2021 | TYPE_UW { $$ = retype($$, BRW_REGISTER_TYPE_UW); }
2022 | TYPE_W { $$ = retype($$, BRW_REGISTER_TYPE_W); }
2023 | TYPE_UB { $$ = retype($$, BRW_REGISTER_TYPE_UB); }
2024 | TYPE_B { $$ = retype($$, BRW_REGISTER_TYPE_B); }
2025 | TYPE_DF { $$ = retype($$, BRW_REGISTER_TYPE_DF); }
2026 | TYPE_UQ { $$ = retype($$, BRW_REGISTER_TYPE_UQ); }
2027 | TYPE_Q { $$ = retype($$, BRW_REGISTER_TYPE_Q); }
2028 | TYPE_HF { $$ = retype($$, BRW_REGISTER_TYPE_HF); }
2029 | TYPE_NF { $$ = retype($$, BRW_REGISTER_TYPE_NF); }
2033 srctype { $$ = $1; }
2034 | TYPE_V { $$ = retype($$, BRW_REGISTER_TYPE_V); }
2035 | TYPE_VF { $$ = retype($$, BRW_REGISTER_TYPE_VF); }
2036 | TYPE_UV { $$ = retype($$, BRW_REGISTER_TYPE_UV); }
2040 srctype { $$ = $1; }
2046 $$= brw_set_writemask($$, WRITEMASK_XYZW);
2048 | DOT writemask_x writemask_y writemask_z writemask_w
2050 $$ = brw_set_writemask($$, $2 | $3 | $4 | $5);
2056 | X { $$ = 1 << BRW_CHANNEL_X; }
2061 | Y { $$ = 1 << BRW_CHANNEL_Y; }
2066 | Z { $$ = 1 << BRW_CHANNEL_Z; }
2071 | W { $$ = 1 << BRW_CHANNEL_W; }
2077 $$.swizzle = BRW_SWIZZLE_NOOP;
2081 $$.swizzle = BRW_SWIZZLE4($2, $2, $2, $2);
2083 | DOT chansel chansel chansel chansel
2085 $$.swizzle = BRW_SWIZZLE4($2, $3, $4, $5);
2096 /* Instruction prediction and modifiers */
2100 brw_push_insn_state(p);
2101 brw_set_default_predicate_control(p, BRW_PREDICATE_NONE);
2102 brw_set_default_flag_reg(p, 0, 0);
2103 brw_set_default_predicate_inverse(p, false);
2105 | LPAREN predstate flagreg predctrl RPAREN
2107 brw_push_insn_state(p);
2108 brw_set_default_predicate_inverse(p, $2);
2109 brw_set_default_flag_reg(p, $3.nr, $3.subnr);
2110 brw_set_default_predicate_control(p, $4);
2121 %empty { $$ = BRW_PREDICATE_NORMAL; }
2122 | DOT X { $$ = BRW_PREDICATE_ALIGN16_REPLICATE_X; }
2123 | DOT Y { $$ = BRW_PREDICATE_ALIGN16_REPLICATE_Y; }
2124 | DOT Z { $$ = BRW_PREDICATE_ALIGN16_REPLICATE_Z; }
2125 | DOT W { $$ = BRW_PREDICATE_ALIGN16_REPLICATE_W; }
2140 /* Source Modification */
2151 /* Flag (Conditional) Modifier */
2155 $$.cond_modifier = $1;
2157 $$.flag_subreg_nr = 0;
2159 | condModifiers DOT flagreg
2161 $$.cond_modifier = $1;
2162 $$.flag_reg_nr = $3.nr;
2163 $$.flag_subreg_nr = $3.subnr;
2168 %empty { $$ = BRW_CONDITIONAL_NONE; }
2183 %empty { $$ = BRW_INSTRUCTION_NORMAL; }
2184 | SATURATE { $$ = BRW_INSTRUCTION_SATURATE; }
2187 /* Execution size */
2189 %empty %prec EMPTYEXECSIZE
2193 | LPAREN exp2 RPAREN
2195 if ($2 > 32 || !isPowerofTwo($2))
2196 error(&@2, "Invalid execution size %d\n", $2);
2202 /* Instruction options */
2206 memset(&$$, 0, sizeof($$));
2208 | LCURLY instoption_list RCURLY
2210 memset(&$$, 0, sizeof($$));
2216 instoption_list COMMA instoption
2218 memset(&$$, 0, sizeof($$));
2220 add_instruction_option(&$$, $3);
2222 | instoption_list instoption
2224 memset(&$$, 0, sizeof($$));
2226 add_instruction_option(&$$, $2);
2230 memset(&$$, 0, sizeof($$));
2235 ALIGN1 { $$ = ALIGN1;}
2236 | ALIGN16 { $$ = ALIGN16; }
2237 | ACCWREN { $$ = ACCWREN; }
2238 | SECHALF { $$ = SECHALF; }
2239 | COMPR { $$ = COMPR; }
2240 | COMPR4 { $$ = COMPR4; }
2241 | BREAKPOINT { $$ = BREAKPOINT; }
2242 | NODDCLR { $$ = NODDCLR; }
2243 | NODDCHK { $$ = NODDCHK; }
2244 | MASK_DISABLE { $$ = MASK_DISABLE; }
2246 | SWITCH { $$ = SWITCH; }
2247 | ATOMIC { $$ = ATOMIC; }
2248 | CMPTCTRL { $$ = CMPTCTRL; }
2249 | WECTRL { $$ = WECTRL; }
2250 | QTR_2Q { $$ = QTR_2Q; }
2251 | QTR_3Q { $$ = QTR_3Q; }
2252 | QTR_4Q { $$ = QTR_4Q; }
2253 | QTR_2H { $$ = QTR_2H; }
2254 | QTR_2N { $$ = QTR_2N; }
2255 | QTR_3N { $$ = QTR_3N; }
2256 | QTR_4N { $$ = QTR_4N; }
2257 | QTR_5N { $$ = QTR_5N; }
2258 | QTR_6N { $$ = QTR_6N; }
2259 | QTR_7N { $$ = QTR_7N; }
2260 | QTR_8N { $$ = QTR_8N; }
2265 extern int yylineno;
2270 fprintf(stderr, "%s: %d: %s at \"%s\"\n",
2271 input_filename, yylineno, msg, lex_text());