3 * Copyright © 2018 Intel Corporation
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
21 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
31 #define YYLTYPE YYLTYPE
32 typedef struct YYLTYPE
48 message(enum message_level level, YYLTYPE *location,
51 static const char *level_str[] = { "warning", "error" };
55 fprintf(stderr, "%s:%d:%d: %s: ", input_filename,
57 location->first_column, level_str[level]);
59 fprintf(stderr, "%s:%s: ", input_filename, level_str[level]);
62 vfprintf(stderr, fmt, args);
66 #define warn(flag, l, fmt, ...) \
68 if (warning_flags & WARN_ ## flag) \
69 message(WARN, l, fmt, ## __VA_ARGS__); \
72 #define error(l, fmt, ...) \
74 message(ERROR, l, fmt, ## __VA_ARGS__); \
78 isPowerofTwo(unsigned int x)
80 return x && (!(x & (x - 1)));
84 set_direct_src_operand(struct brw_reg *reg, int type)
86 return brw_reg(reg->file,
100 i965_asm_unary_instruction(int opcode, struct brw_codegen *p,
101 struct brw_reg dest, struct brw_reg src0)
104 case BRW_OPCODE_BFREV:
105 brw_BFREV(p, dest, src0);
107 case BRW_OPCODE_CBIT:
108 brw_CBIT(p, dest, src0);
110 case BRW_OPCODE_F32TO16:
111 brw_F32TO16(p, dest, src0);
113 case BRW_OPCODE_F16TO32:
114 brw_F16TO32(p, dest, src0);
117 brw_MOV(p, dest, src0);
120 brw_FBL(p, dest, src0);
123 brw_FRC(p, dest, src0);
126 brw_FBH(p, dest, src0);
129 brw_NOT(p, dest, src0);
131 case BRW_OPCODE_RNDE:
132 brw_RNDE(p, dest, src0);
134 case BRW_OPCODE_RNDZ:
135 brw_RNDZ(p, dest, src0);
137 case BRW_OPCODE_RNDD:
138 brw_RNDD(p, dest, src0);
141 brw_LZD(p, dest, src0);
144 brw_DIM(p, dest, src0);
146 case BRW_OPCODE_RNDU:
147 fprintf(stderr, "Opcode BRW_OPCODE_RNDU unhandled\n");
150 fprintf(stderr, "Unsupported unary opcode\n");
155 i965_asm_binary_instruction(int opcode,
156 struct brw_codegen *p,
162 case BRW_OPCODE_ADDC:
163 brw_ADDC(p, dest, src0, src1);
165 case BRW_OPCODE_BFI1:
166 brw_BFI1(p, dest, src0, src1);
169 brw_DP2(p, dest, src0, src1);
172 brw_DP3(p, dest, src0, src1);
175 brw_DP4(p, dest, src0, src1);
178 brw_DPH(p, dest, src0, src1);
180 case BRW_OPCODE_LINE:
181 brw_LINE(p, dest, src0, src1);
184 brw_MAC(p, dest, src0, src1);
186 case BRW_OPCODE_MACH:
187 brw_MACH(p, dest, src0, src1);
190 brw_PLN(p, dest, src0, src1);
193 brw_ROL(p, dest, src0, src1);
196 brw_ROR(p, dest, src0, src1);
198 case BRW_OPCODE_SAD2:
199 fprintf(stderr, "Opcode BRW_OPCODE_SAD2 unhandled\n");
201 case BRW_OPCODE_SADA2:
202 fprintf(stderr, "Opcode BRW_OPCODE_SADA2 unhandled\n");
204 case BRW_OPCODE_SUBB:
205 brw_SUBB(p, dest, src0, src1);
208 brw_ADD(p, dest, src0, src1);
211 /* Third parameter is conditional modifier
212 * which gets updated later
214 brw_CMP(p, dest, 0, src0, src1);
217 brw_AND(p, dest, src0, src1);
220 brw_ASR(p, dest, src0, src1);
223 brw_AVG(p, dest, src0, src1);
226 brw_OR(p, dest, src0, src1);
229 brw_SEL(p, dest, src0, src1);
232 brw_SHL(p, dest, src0, src1);
235 brw_SHR(p, dest, src0, src1);
238 brw_XOR(p, dest, src0, src1);
241 brw_MUL(p, dest, src0, src1);
244 fprintf(stderr, "Unsupported binary opcode\n");
249 i965_asm_ternary_instruction(int opcode,
250 struct brw_codegen *p,
258 brw_MAD(p, dest, src0, src1, src2);
260 case BRW_OPCODE_CSEL:
261 brw_CSEL(p, dest, src0, src1, src2);
264 brw_LRP(p, dest, src0, src1, src2);
267 brw_BFE(p, dest, src0, src1, src2);
269 case BRW_OPCODE_BFI2:
270 brw_BFI2(p, dest, src0, src1, src2);
273 fprintf(stderr, "Unsupported ternary opcode\n");
278 i965_asm_set_instruction_options(struct brw_codegen *p,
279 struct options options)
281 brw_inst_set_access_mode(p->devinfo, brw_last_inst,
282 options.access_mode);
283 brw_inst_set_mask_control(p->devinfo, brw_last_inst,
284 options.mask_control);
285 brw_inst_set_thread_control(p->devinfo, brw_last_inst,
286 options.thread_control);
287 brw_inst_set_no_dd_check(p->devinfo, brw_last_inst,
288 options.no_dd_check);
289 brw_inst_set_no_dd_clear(p->devinfo, brw_last_inst,
290 options.no_dd_clear);
291 brw_inst_set_debug_control(p->devinfo, brw_last_inst,
292 options.debug_control);
293 if (p->devinfo->gen >= 6)
294 brw_inst_set_acc_wr_control(p->devinfo, brw_last_inst,
295 options.acc_wr_control);
296 brw_inst_set_cmpt_control(p->devinfo, brw_last_inst,
301 i965_asm_set_dst_nr(struct brw_codegen *p,
303 struct options options)
305 if (p->devinfo->gen <= 6) {
306 if (reg->file == BRW_MESSAGE_REGISTER_FILE &&
307 options.qtr_ctrl == BRW_COMPRESSION_COMPRESSED &&
309 reg->nr |= BRW_MRF_COMPR4;
322 unsigned long long int llint;
324 struct brw_codegen *program;
325 struct predicate predicate;
326 struct condition condition;
327 struct options options;
328 brw_inst *instruction;
338 %token LSQUARE RSQUARE
343 %token <integer> TYPE_B TYPE_UB
344 %token <integer> TYPE_W TYPE_UW
345 %token <integer> TYPE_D TYPE_UD
346 %token <integer> TYPE_Q TYPE_UQ
347 %token <integer> TYPE_V TYPE_UV
348 %token <integer> TYPE_F TYPE_HF
349 %token <integer> TYPE_DF TYPE_NF
350 %token <integer> TYPE_VF
353 %token <integer> ADD ADD3 ADDC AND ASR AVG
354 %token <integer> BFE BFI1 BFI2 BFB BFREV BRC BRD BREAK
355 %token <integer> CALL CALLA CASE CBIT CMP CMPN CONT CSEL
356 %token <integer> DIM DO DPAS DPASW DP2 DP3 DP4 DP4A DPH
357 %token <integer> ELSE ENDIF F16TO32 F32TO16 FBH FBL FORK FRC
358 %token <integer> GOTO
359 %token <integer> HALT
360 %token <integer> IF IFF ILLEGAL
361 %token <integer> JMPI JOIN
362 %token <integer> LINE LRP LZD
363 %token <integer> MAC MACH MAD MADM MOV MOVI MUL MREST MSAVE
364 %token <integer> NENOP NOP NOT
366 %token <integer> PLN POP PUSH
367 %token <integer> RET RNDD RNDE RNDU RNDZ ROL ROR
368 %token <integer> SAD2 SADA2 SEL SEND SENDC SENDS SENDSC SHL SHR SMOV SUBB SYNC
369 %token <integer> WAIT WHILE
372 /* extended math functions */
373 %token <integer> COS EXP FDIV INV INVM INTDIV INTDIVMOD INTMOD LOG POW RSQ
374 %token <integer> RSQRTM SIN SINCOS SQRT
376 /* shared functions for send */
377 %token CONST CRE DATA DP_DATA_1 GATEWAY MATH PIXEL_INTERP READ RENDER SAMPLER
378 %token THREAD_SPAWNER URB VME WRITE DP_SAMPLER
380 /* Conditional modifiers */
381 %token <integer> EQUAL GREATER GREATER_EQUAL LESS LESS_EQUAL NOT_EQUAL
382 %token <integer> NOT_ZERO OVERFLOW UNORDERED ZERO
384 /* register Access Modes */
385 %token ALIGN1 ALIGN16
387 /* accumulator write control */
390 /* compaction control */
393 /* compression control */
394 %token COMPR COMPR4 SECHALF
396 /* mask control (WeCtrl) */
402 /* dependency control */
403 %token NODDCLR NODDCHK
411 /* predicate control */
412 %token <integer> ANYV ALLV ANY2H ALL2H ANY4H ALL4H ANY8H ALL8H ANY16H ALL16H
413 %token <integer> ANY32H ALL32H
415 /* round instructions */
416 %token <integer> ROUND_INCREMENT
425 %token QTR_2Q QTR_3Q QTR_4Q QTR_2H QTR_2N QTR_3N QTR_4N QTR_5N
426 %token QTR_6N QTR_7N QTR_8N
429 %token <integer> X Y Z W
432 %token GENREGFILE MSGREGFILE
434 /* vertical stride in register region */
438 %token <integer> GENREG MSGREG ADDRREG ACCREG FLAGREG NOTIFYREG STATEREG
439 %token <integer> CONTROLREG IPREG PERFORMANCEREG THREADREG CHANNELENABLEREG
440 %token <integer> MASKREG
442 %token <integer> INTEGER
446 %precedence SUBREGNUM
449 %precedence EMPTYEXECSIZE
452 %type <integer> execsize simple_int exp
455 /* predicate control */
456 %type <integer> predctrl predstate
457 %type <predicate> predicate
459 /* conditional modifier */
460 %type <condition> cond_mod
461 %type <integer> condModifiers
463 /* instruction options */
464 %type <options> instoptions instoption_list
465 %type <integer> instoption
468 %type <integer> writemask_x writemask_y writemask_z writemask_w
469 %type <reg> writemask
472 %type <reg> dst dstoperand dstoperandex dstoperandex_typed dstreg dsttype
473 %type <reg> dstoperandex_ud_typed
474 %type <integer> dstregion
476 %type <integer> saturate relativelocation rellocation
477 %type <reg> relativelocation2
480 %type <reg> directsrcoperand directsrcaccoperand indirectsrcoperand srcacc
481 %type <reg> srcarcoperandex srcaccimm srcarcoperandex_typed srctype srcimm
482 %type <reg> srcarcoperandex_ud_typed srcimmtype indirectgenreg indirectregion
483 %type <reg> immreg src reg32 payload directgenreg_list addrparam region
484 %type <reg> region_wh swizzle directgenreg directmsgreg indirectmsgreg
487 %type <reg> accreg addrreg channelenablereg controlreg flagreg ipreg
488 %type <reg> notifyreg nullreg performancereg threadcontrolreg statereg maskreg
489 %type <integer> subregnum
491 /* immediate values */
494 /* instruction opcodes */
495 %type <integer> unaryopcodes binaryopcodes binaryaccopcodes ternaryopcodes
496 %type <integer> sendop
497 %type <instruction> sendopcode
499 %type <integer> negate abs chansel math_function sharedfunction
504 add_instruction_option(struct options *options, int option)
508 options->access_mode = BRW_ALIGN_1;
511 options->access_mode = BRW_ALIGN_16;
514 options->qtr_ctrl |= BRW_COMPRESSION_2NDHALF;
517 options->qtr_ctrl |= BRW_COMPRESSION_COMPRESSED;
518 options->is_compr = true;
521 options->qtr_ctrl |= BRW_COMPRESSION_COMPRESSED;
524 options->thread_control |= BRW_THREAD_SWITCH;
527 options->thread_control |= BRW_THREAD_ATOMIC;
530 options->no_dd_check = true;
533 options->no_dd_clear = BRW_DEPENDENCY_NOTCLEARED;
536 options->mask_control |= BRW_MASK_DISABLE;
539 options->debug_control = BRW_DEBUG_BREAKPOINT;
542 options->mask_control |= BRW_WE_ALL;
545 options->compaction = true;
548 options->acc_wr_control = true;
551 options->end_of_thread = true;
553 /* TODO : Figure out how to set instruction group and get rid of
557 options->qtr_ctrl = BRW_COMPRESSION_2NDHALF;
560 options->qtr_ctrl = BRW_COMPRESSION_COMPRESSED;
563 options->qtr_ctrl = 3;
566 options->qtr_ctrl = BRW_COMPRESSION_COMPRESSED;
569 options->qtr_ctrl = BRW_COMPRESSION_NONE;
570 options->nib_ctrl = true;
573 options->qtr_ctrl = BRW_COMPRESSION_2NDHALF;
576 options->qtr_ctrl = BRW_COMPRESSION_2NDHALF;
577 options->nib_ctrl = true;
580 options->qtr_ctrl = BRW_COMPRESSION_COMPRESSED;
583 options->qtr_ctrl = BRW_COMPRESSION_COMPRESSED;
584 options->nib_ctrl = true;
587 options->qtr_ctrl = 3;
590 options->qtr_ctrl = 3;
591 options->nib_ctrl = true;
603 instrseq instruction SEMICOLON
604 | instrseq relocatableinstruction SEMICOLON
605 | instruction SEMICOLON
606 | relocatableinstruction SEMICOLON
609 /* Instruction Group */
613 | binaryaccinstruction
622 relocatableinstruction:
630 ILLEGAL execsize instoptions
632 brw_next_insn(p, $1);
633 brw_inst_set_exec_size(p->devinfo, brw_last_inst, $2);
634 i965_asm_set_instruction_options(p, $3);
638 /* Unary instruction */
640 predicate unaryopcodes saturate cond_mod execsize dst srcaccimm instoptions
642 i965_asm_set_dst_nr(p, &$6, $8);
643 brw_set_default_access_mode(p, $8.access_mode);
644 i965_asm_unary_instruction($2, p, $6, $7);
645 brw_pop_insn_state(p);
646 i965_asm_set_instruction_options(p, $8);
647 brw_inst_set_cond_modifier(p->devinfo, brw_last_inst,
650 if (p->devinfo->gen >= 7) {
651 if ($2 != BRW_OPCODE_DIM) {
652 brw_inst_set_flag_reg_nr(p->devinfo,
655 brw_inst_set_flag_subreg_nr(p->devinfo,
661 if ($7.file != BRW_IMMEDIATE_VALUE) {
662 brw_inst_set_src0_vstride(p->devinfo, brw_last_inst,
665 brw_inst_set_saturate(p->devinfo, brw_last_inst, $3);
666 brw_inst_set_exec_size(p->devinfo, brw_last_inst, $5);
667 // TODO: set instruction group instead of qtr and nib ctrl
668 brw_inst_set_qtr_control(p->devinfo, brw_last_inst,
671 if (p->devinfo->gen >= 7)
672 brw_inst_set_nib_control(p->devinfo, brw_last_inst,
695 /* Binary instruction */
697 predicate binaryopcodes saturate cond_mod execsize dst srcimm srcimm instoptions
699 i965_asm_set_dst_nr(p, &$6, $9);
700 brw_set_default_access_mode(p, $9.access_mode);
701 i965_asm_binary_instruction($2, p, $6, $7, $8);
702 i965_asm_set_instruction_options(p, $9);
703 brw_inst_set_cond_modifier(p->devinfo, brw_last_inst,
706 if (p->devinfo->gen >= 7) {
707 brw_inst_set_flag_reg_nr(p->devinfo, brw_last_inst,
709 brw_inst_set_flag_subreg_nr(p->devinfo, brw_last_inst,
713 brw_inst_set_saturate(p->devinfo, brw_last_inst, $3);
714 brw_inst_set_exec_size(p->devinfo, brw_last_inst, $5);
715 // TODO: set instruction group instead of qtr and nib ctrl
716 brw_inst_set_qtr_control(p->devinfo, brw_last_inst,
719 if (p->devinfo->gen >= 7)
720 brw_inst_set_nib_control(p->devinfo, brw_last_inst,
723 brw_pop_insn_state(p);
746 /* Binary acc instruction */
747 binaryaccinstruction:
748 predicate binaryaccopcodes saturate cond_mod execsize dst srcacc srcimm instoptions
750 i965_asm_set_dst_nr(p, &$6, $9);
751 brw_set_default_access_mode(p, $9.access_mode);
752 i965_asm_binary_instruction($2, p, $6, $7, $8);
753 brw_pop_insn_state(p);
754 i965_asm_set_instruction_options(p, $9);
755 brw_inst_set_cond_modifier(p->devinfo, brw_last_inst,
758 if (p->devinfo->gen >= 7) {
759 if (!brw_inst_flag_reg_nr(p->devinfo, brw_last_inst)) {
760 brw_inst_set_flag_reg_nr(p->devinfo,
763 brw_inst_set_flag_subreg_nr(p->devinfo,
769 brw_inst_set_saturate(p->devinfo, brw_last_inst, $3);
770 brw_inst_set_exec_size(p->devinfo, brw_last_inst, $5);
771 // TODO: set instruction group instead of qtr and nib ctrl
772 brw_inst_set_qtr_control(p->devinfo, brw_last_inst,
775 if (p->devinfo->gen >= 7)
776 brw_inst_set_nib_control(p->devinfo, brw_last_inst,
796 /* Math instruction */
798 predicate MATH saturate math_function execsize dst src srcimm instoptions
800 brw_set_default_access_mode(p, $9.access_mode);
801 gen6_math(p, $6, $4, $7, $8);
802 i965_asm_set_instruction_options(p, $9);
803 brw_inst_set_exec_size(p->devinfo, brw_last_inst, $5);
804 brw_inst_set_saturate(p->devinfo, brw_last_inst, $3);
805 // TODO: set instruction group instead
806 brw_inst_set_qtr_control(p->devinfo, brw_last_inst,
809 if (p->devinfo->gen >= 7)
810 brw_inst_set_nib_control(p->devinfo, brw_last_inst,
813 brw_pop_insn_state(p);
835 /* NOP instruction */
843 /* Ternary operand instruction */
845 predicate ternaryopcodes saturate cond_mod execsize dst src src src instoptions
847 brw_set_default_access_mode(p, $10.access_mode);
848 i965_asm_ternary_instruction($2, p, $6, $7, $8, $9);
849 brw_pop_insn_state(p);
850 i965_asm_set_instruction_options(p, $10);
851 brw_inst_set_cond_modifier(p->devinfo, brw_last_inst,
854 if (p->devinfo->gen >= 7) {
855 brw_inst_set_3src_a16_flag_reg_nr(p->devinfo, brw_last_inst,
857 brw_inst_set_3src_a16_flag_subreg_nr(p->devinfo, brw_last_inst,
861 brw_inst_set_saturate(p->devinfo, brw_last_inst, $3);
862 brw_inst_set_exec_size(p->devinfo, brw_last_inst, $5);
863 // TODO: set instruction group instead of qtr and nib ctrl
864 brw_inst_set_qtr_control(p->devinfo, brw_last_inst,
867 if (p->devinfo->gen >= 7)
868 brw_inst_set_nib_control(p->devinfo, brw_last_inst,
881 /* Sync instruction */
883 WAIT execsize src instoptions
885 brw_next_insn(p, $1);
886 i965_asm_set_instruction_options(p, $4);
887 brw_inst_set_exec_size(p->devinfo, brw_last_inst, $2);
888 brw_set_default_access_mode(p, $4.access_mode);
889 struct brw_reg src = brw_notification_reg();
890 brw_set_dest(p, brw_last_inst, src);
891 brw_set_src0(p, brw_last_inst, src);
892 brw_set_src1(p, brw_last_inst, brw_null_reg());
893 brw_inst_set_mask_control(p->devinfo, brw_last_inst, BRW_MASK_DISABLE);
897 /* Send instruction */
899 predicate sendopcode execsize dst payload exp2 sharedfunction instoptions
901 i965_asm_set_instruction_options(p, $8);
902 brw_inst_set_exec_size(p->devinfo, brw_last_inst, $3);
903 brw_set_dest(p, brw_last_inst, $4);
904 brw_set_src0(p, brw_last_inst, $5);
905 brw_inst_set_bits(brw_last_inst, 127, 96, $6);
906 brw_inst_set_src1_file_type(p->devinfo, brw_last_inst,
908 BRW_REGISTER_TYPE_UD);
909 brw_inst_set_sfid(p->devinfo, brw_last_inst, $7);
910 brw_inst_set_eot(p->devinfo, brw_last_inst, $8.end_of_thread);
911 // TODO: set instruction group instead of qtr and nib ctrl
912 brw_inst_set_qtr_control(p->devinfo, brw_last_inst,
915 if (p->devinfo->gen >= 7)
916 brw_inst_set_nib_control(p->devinfo, brw_last_inst,
919 brw_pop_insn_state(p);
921 | predicate sendopcode execsize exp dst payload exp2 sharedfunction instoptions
923 i965_asm_set_instruction_options(p, $9);
924 brw_inst_set_exec_size(p->devinfo, brw_last_inst, $3);
925 brw_inst_set_base_mrf(p->devinfo, brw_last_inst, $4);
926 brw_set_dest(p, brw_last_inst, $5);
927 brw_set_src0(p, brw_last_inst, $6);
928 brw_inst_set_bits(brw_last_inst, 127, 96, $7);
929 brw_inst_set_src1_file_type(p->devinfo, brw_last_inst,
931 BRW_REGISTER_TYPE_UD);
932 brw_inst_set_sfid(p->devinfo, brw_last_inst, $8);
933 brw_inst_set_eot(p->devinfo, brw_last_inst, $9.end_of_thread);
934 // TODO: set instruction group instead of qtr and nib ctrl
935 brw_inst_set_qtr_control(p->devinfo, brw_last_inst,
938 if (p->devinfo->gen >= 7)
939 brw_inst_set_nib_control(p->devinfo, brw_last_inst,
942 brw_pop_insn_state(p);
944 | predicate sendopcode execsize dst payload payload exp2 sharedfunction instoptions
946 i965_asm_set_instruction_options(p, $9);
947 brw_inst_set_exec_size(p->devinfo, brw_last_inst, $3);
948 brw_set_dest(p, brw_last_inst, $4);
949 brw_set_src0(p, brw_last_inst, $5);
950 brw_inst_set_bits(brw_last_inst, 127, 96, $7);
951 brw_inst_set_sfid(p->devinfo, brw_last_inst, $8);
952 brw_inst_set_eot(p->devinfo, brw_last_inst, $9.end_of_thread);
953 // TODO: set instruction group instead of qtr and nib ctrl
954 brw_inst_set_qtr_control(p->devinfo, brw_last_inst,
957 if (p->devinfo->gen >= 7)
958 brw_inst_set_nib_control(p->devinfo, brw_last_inst,
961 brw_pop_insn_state(p);
963 | predicate SENDS execsize dst payload payload exp2 exp2 sharedfunction instoptions
965 brw_next_insn(p, $2);
966 i965_asm_set_instruction_options(p, $10);
967 brw_inst_set_exec_size(p->devinfo, brw_last_inst, $3);
968 brw_set_dest(p, brw_last_inst, $4);
969 brw_set_src0(p, brw_last_inst, $5);
970 brw_set_src1(p, brw_last_inst, $6);
972 if (brw_inst_send_sel_reg32_ex_desc(p->devinfo, brw_last_inst)) {
973 brw_inst_set_send_ex_desc_ia_subreg_nr(p->devinfo, brw_last_inst, $5.subnr);
975 brw_inst_set_sends_ex_desc(p->devinfo, brw_last_inst, $8);
978 brw_inst_set_bits(brw_last_inst, 127, 96, $7);
979 brw_inst_set_sfid(p->devinfo, brw_last_inst, $9);
980 brw_inst_set_eot(p->devinfo, brw_last_inst, $10.end_of_thread);
981 // TODO: set instruction group instead of qtr and nib ctrl
982 brw_inst_set_qtr_control(p->devinfo, brw_last_inst,
985 if (p->devinfo->gen >= 7)
986 brw_inst_set_nib_control(p->devinfo, brw_last_inst,
989 brw_pop_insn_state(p);
991 | predicate SENDS execsize dst payload payload src exp2 sharedfunction instoptions
993 brw_next_insn(p, $2);
994 i965_asm_set_instruction_options(p, $10);
995 brw_inst_set_exec_size(p->devinfo, brw_last_inst, $3);
996 brw_set_dest(p, brw_last_inst, $4);
997 brw_set_src0(p, brw_last_inst, $5);
998 brw_set_src1(p, brw_last_inst, $6);
1000 brw_inst_set_send_sel_reg32_desc(p->devinfo, brw_last_inst, 1);
1001 brw_inst_set_sends_ex_desc(p->devinfo, brw_last_inst, $8);
1003 brw_inst_set_sfid(p->devinfo, brw_last_inst, $9);
1004 brw_inst_set_eot(p->devinfo, brw_last_inst, $10.end_of_thread);
1005 // TODO: set instruction group instead of qtr and nib ctrl
1006 brw_inst_set_qtr_control(p->devinfo, brw_last_inst,
1009 if (p->devinfo->gen >= 7)
1010 brw_inst_set_nib_control(p->devinfo, brw_last_inst,
1013 brw_pop_insn_state(p);
1023 sendop { $$ = brw_next_insn(p, $1); }
1027 NULL_TOKEN { $$ = BRW_SFID_NULL; }
1028 | MATH { $$ = BRW_SFID_MATH; }
1029 | GATEWAY { $$ = BRW_SFID_MESSAGE_GATEWAY; }
1030 | READ { $$ = BRW_SFID_DATAPORT_READ; }
1031 | WRITE { $$ = BRW_SFID_DATAPORT_WRITE; }
1032 | URB { $$ = BRW_SFID_URB; }
1033 | THREAD_SPAWNER { $$ = BRW_SFID_THREAD_SPAWNER; }
1034 | VME { $$ = BRW_SFID_VME; }
1035 | RENDER { $$ = GEN6_SFID_DATAPORT_RENDER_CACHE; }
1036 | CONST { $$ = GEN6_SFID_DATAPORT_CONSTANT_CACHE; }
1037 | DATA { $$ = GEN7_SFID_DATAPORT_DATA_CACHE; }
1038 | PIXEL_INTERP { $$ = GEN7_SFID_PIXEL_INTERPOLATOR; }
1039 | DP_DATA_1 { $$ = HSW_SFID_DATAPORT_DATA_CACHE_1; }
1040 | CRE { $$ = HSW_SFID_CRE; }
1041 | SAMPLER { $$ = BRW_SFID_SAMPLER; }
1042 | DP_SAMPLER { $$ = GEN6_SFID_DATAPORT_SAMPLER_CACHE; }
1047 | MINUS LONG { $$ = -$2; }
1050 /* Jump instruction */
1052 predicate JMPI execsize relativelocation2 instoptions
1054 brw_next_insn(p, $2);
1055 i965_asm_set_instruction_options(p, $5);
1056 brw_inst_set_exec_size(p->devinfo, brw_last_inst, $3);
1057 brw_set_dest(p, brw_last_inst, brw_ip_reg());
1058 brw_set_src0(p, brw_last_inst, brw_ip_reg());
1059 brw_set_src1(p, brw_last_inst, $4);
1060 brw_inst_set_pred_control(p->devinfo, brw_last_inst,
1061 brw_inst_pred_control(p->devinfo,
1063 brw_pop_insn_state(p);
1067 /* branch instruction */
1069 predicate ENDIF execsize relativelocation instoptions
1071 brw_next_insn(p, $2);
1072 i965_asm_set_instruction_options(p, $5);
1073 brw_inst_set_exec_size(p->devinfo, brw_last_inst, $3);
1075 if (p->devinfo->gen < 6) {
1076 brw_set_dest(p, brw_last_inst, retype(brw_null_reg(),
1077 BRW_REGISTER_TYPE_D));
1078 brw_set_src0(p, brw_last_inst, retype(brw_null_reg(),
1079 BRW_REGISTER_TYPE_D));
1080 brw_set_src1(p, brw_last_inst, brw_imm_d(0x0));
1081 brw_inst_set_gen4_pop_count(p->devinfo, brw_last_inst,
1083 } else if (p->devinfo->gen == 6) {
1084 brw_set_dest(p, brw_last_inst, brw_imm_w(0x0));
1085 brw_inst_set_gen6_jump_count(p->devinfo, brw_last_inst,
1087 brw_set_src0(p, brw_last_inst, retype(brw_null_reg(),
1088 BRW_REGISTER_TYPE_D));
1089 brw_set_src1(p, brw_last_inst, retype(brw_null_reg(),
1090 BRW_REGISTER_TYPE_D));
1091 } else if (p->devinfo->gen == 7) {
1092 brw_set_dest(p, brw_last_inst, retype(brw_null_reg(),
1093 BRW_REGISTER_TYPE_D));
1094 brw_set_src0(p, brw_last_inst, retype(brw_null_reg(),
1095 BRW_REGISTER_TYPE_D));
1096 brw_set_src1(p, brw_last_inst, brw_imm_w(0x0));
1097 brw_inst_set_jip(p->devinfo, brw_last_inst, $4);
1099 brw_set_src0(p, brw_last_inst, brw_imm_d($4));
1102 if (p->devinfo->gen < 6)
1103 brw_inst_set_thread_control(p->devinfo, brw_last_inst,
1105 brw_pop_insn_state(p);
1107 | ELSE execsize relativelocation rellocation instoptions
1109 brw_next_insn(p, $1);
1110 i965_asm_set_instruction_options(p, $5);
1111 brw_inst_set_exec_size(p->devinfo, brw_last_inst, $2);
1113 if (p->devinfo->gen < 6) {
1114 brw_set_dest(p, brw_last_inst, brw_ip_reg());
1115 brw_set_src0(p, brw_last_inst, brw_ip_reg());
1116 brw_set_src1(p, brw_last_inst, brw_imm_d(0x0));
1117 brw_inst_set_gen4_jump_count(p->devinfo, brw_last_inst,
1119 brw_inst_set_gen4_pop_count(p->devinfo, brw_last_inst,
1121 } else if (p->devinfo->gen == 6) {
1122 brw_set_dest(p, brw_last_inst, brw_imm_w(0x0));
1123 brw_inst_set_gen6_jump_count(p->devinfo, brw_last_inst,
1125 brw_set_src0(p, brw_last_inst, retype(brw_null_reg(),
1126 BRW_REGISTER_TYPE_D));
1127 brw_set_src1(p, brw_last_inst, retype(brw_null_reg(),
1128 BRW_REGISTER_TYPE_D));
1129 } else if (p->devinfo->gen == 7) {
1130 brw_set_dest(p, brw_last_inst, retype(brw_null_reg(),
1131 BRW_REGISTER_TYPE_D));
1132 brw_set_src0(p, brw_last_inst, retype(brw_null_reg(),
1133 BRW_REGISTER_TYPE_D));
1134 brw_set_src1(p, brw_last_inst, brw_imm_w($3));
1135 brw_inst_set_jip(p->devinfo, brw_last_inst, $3);
1136 brw_inst_set_uip(p->devinfo, brw_last_inst, $4);
1138 brw_set_dest(p, brw_last_inst, retype(brw_null_reg(),
1139 BRW_REGISTER_TYPE_D));
1140 brw_set_src0(p, brw_last_inst, brw_imm_d($3));
1141 brw_inst_set_jip(p->devinfo, brw_last_inst, $3);
1142 brw_inst_set_uip(p->devinfo, brw_last_inst, $4);
1145 if (!p->single_program_flow && p->devinfo->gen < 6)
1146 brw_inst_set_thread_control(p->devinfo, brw_last_inst,
1149 | predicate IF execsize relativelocation rellocation instoptions
1151 brw_next_insn(p, $2);
1152 i965_asm_set_instruction_options(p, $6);
1153 brw_inst_set_exec_size(p->devinfo, brw_last_inst, $3);
1155 if (p->devinfo->gen < 6) {
1156 brw_set_dest(p, brw_last_inst, brw_ip_reg());
1157 brw_set_src0(p, brw_last_inst, brw_ip_reg());
1158 brw_set_src1(p, brw_last_inst, brw_imm_d(0x0));
1159 brw_inst_set_gen4_jump_count(p->devinfo, brw_last_inst,
1161 brw_inst_set_gen4_pop_count(p->devinfo, brw_last_inst,
1163 } else if (p->devinfo->gen == 6) {
1164 brw_set_dest(p, brw_last_inst, brw_imm_w(0x0));
1165 brw_inst_set_gen6_jump_count(p->devinfo, brw_last_inst,
1167 brw_set_src0(p, brw_last_inst,
1168 vec1(retype(brw_null_reg(),
1169 BRW_REGISTER_TYPE_D)));
1170 brw_set_src1(p, brw_last_inst,
1171 vec1(retype(brw_null_reg(),
1172 BRW_REGISTER_TYPE_D)));
1173 } else if (p->devinfo->gen == 7) {
1174 brw_set_dest(p, brw_last_inst,
1175 vec1(retype(brw_null_reg(),
1176 BRW_REGISTER_TYPE_D)));
1177 brw_set_src0(p, brw_last_inst,
1178 vec1(retype(brw_null_reg(),
1179 BRW_REGISTER_TYPE_D)));
1180 brw_set_src1(p, brw_last_inst, brw_imm_w($4));
1181 brw_inst_set_jip(p->devinfo, brw_last_inst, $4);
1182 brw_inst_set_uip(p->devinfo, brw_last_inst, $5);
1184 brw_set_dest(p, brw_last_inst,
1185 vec1(retype(brw_null_reg(),
1186 BRW_REGISTER_TYPE_D)));
1187 brw_set_src0(p, brw_last_inst, brw_imm_d($4));
1188 brw_inst_set_jip(p->devinfo, brw_last_inst, $4);
1189 brw_inst_set_uip(p->devinfo, brw_last_inst, $5);
1192 if (!p->single_program_flow && p->devinfo->gen < 6)
1193 brw_inst_set_thread_control(p->devinfo, brw_last_inst,
1196 brw_pop_insn_state(p);
1198 | predicate IFF execsize relativelocation instoptions
1200 brw_next_insn(p, $2);
1201 i965_asm_set_instruction_options(p, $5);
1202 brw_inst_set_exec_size(p->devinfo, brw_last_inst, $3);
1204 if (p->devinfo->gen < 6) {
1205 brw_set_dest(p, brw_last_inst, brw_ip_reg());
1206 brw_set_src0(p, brw_last_inst, brw_ip_reg());
1207 brw_inst_set_gen4_jump_count(p->devinfo, brw_last_inst,
1209 brw_set_src1(p, brw_last_inst, brw_imm_d($4));
1210 } else if (p->devinfo->gen == 6) {
1211 brw_set_dest(p, brw_last_inst, brw_imm_w($4));
1212 brw_inst_set_gen6_jump_count(p->devinfo, brw_last_inst,
1214 brw_set_src0(p, brw_last_inst,
1215 vec1(retype(brw_null_reg(),
1216 BRW_REGISTER_TYPE_D)));
1217 brw_set_src1(p, brw_last_inst,
1218 vec1(retype(brw_null_reg(),
1219 BRW_REGISTER_TYPE_D)));
1220 } else if (p->devinfo->gen == 7) {
1221 brw_set_dest(p, brw_last_inst,
1222 vec1(retype(brw_null_reg(),
1223 BRW_REGISTER_TYPE_D)));
1224 brw_set_src0(p, brw_last_inst,
1225 vec1(retype(brw_null_reg(),
1226 BRW_REGISTER_TYPE_D)));
1227 brw_set_src1(p, brw_last_inst, brw_imm_w($4));
1228 brw_inst_set_jip(p->devinfo, brw_last_inst, $4);
1230 brw_set_dest(p, brw_last_inst,
1231 vec1(retype(brw_null_reg(),
1232 BRW_REGISTER_TYPE_D)));
1233 brw_set_src0(p, brw_last_inst, brw_imm_d($4));
1234 brw_inst_set_jip(p->devinfo, brw_last_inst, $4);
1237 if (!p->single_program_flow && p->devinfo->gen < 6)
1238 brw_inst_set_thread_control(p->devinfo, brw_last_inst,
1241 brw_pop_insn_state(p);
1245 /* break instruction */
1247 predicate BREAK execsize relativelocation relativelocation instoptions
1249 brw_next_insn(p, $2);
1250 i965_asm_set_instruction_options(p, $6);
1251 brw_inst_set_exec_size(p->devinfo, brw_last_inst, $3);
1253 if (p->devinfo->gen >= 8) {
1254 brw_set_dest(p, brw_last_inst, retype(brw_null_reg(),
1255 BRW_REGISTER_TYPE_D));
1256 brw_set_src0(p, brw_last_inst, brw_imm_d($4));
1257 brw_inst_set_uip(p->devinfo, brw_last_inst, $5);
1258 } else if (p->devinfo->gen >= 6) {
1259 brw_set_dest(p, brw_last_inst, retype(brw_null_reg(),
1260 BRW_REGISTER_TYPE_D));
1261 brw_set_src0(p, brw_last_inst, retype(brw_null_reg(),
1262 BRW_REGISTER_TYPE_D));
1263 brw_set_src1(p, brw_last_inst, brw_imm_d(0x0));
1264 brw_inst_set_jip(p->devinfo, brw_last_inst, $4);
1265 brw_inst_set_uip(p->devinfo, brw_last_inst, $5);
1267 brw_set_dest(p, brw_last_inst, brw_ip_reg());
1268 brw_set_src0(p, brw_last_inst, brw_ip_reg());
1269 brw_set_src1(p, brw_last_inst, brw_imm_d(0x0));
1270 brw_inst_set_gen4_jump_count(p->devinfo, brw_last_inst,
1272 brw_inst_set_gen4_pop_count(p->devinfo, brw_last_inst,
1276 brw_pop_insn_state(p);
1278 | predicate HALT execsize relativelocation relativelocation instoptions
1280 brw_next_insn(p, $2);
1281 i965_asm_set_instruction_options(p, $6);
1282 brw_inst_set_exec_size(p->devinfo, brw_last_inst, $3);
1283 brw_set_dest(p, brw_last_inst, retype(brw_null_reg(),
1284 BRW_REGISTER_TYPE_D));
1286 if (p->devinfo->gen >= 8) {
1287 brw_set_src0(p, brw_last_inst, brw_imm_d($4));
1288 brw_inst_set_uip(p->devinfo, brw_last_inst, $5);
1290 brw_set_src0(p, brw_last_inst, retype(brw_null_reg(),
1291 BRW_REGISTER_TYPE_D));
1292 brw_set_src1(p, brw_last_inst, brw_imm_d($5));
1295 brw_inst_set_jip(p->devinfo, brw_last_inst, $4);
1296 brw_inst_set_uip(p->devinfo, brw_last_inst, $5);
1297 brw_pop_insn_state(p);
1299 | predicate CONT execsize relativelocation relativelocation instoptions
1301 brw_next_insn(p, $2);
1302 i965_asm_set_instruction_options(p, $6);
1303 brw_inst_set_exec_size(p->devinfo, brw_last_inst, $3);
1304 brw_set_dest(p, brw_last_inst, brw_ip_reg());
1306 if (p->devinfo->gen >= 8) {
1307 brw_set_src0(p, brw_last_inst, brw_imm_d(0x0));
1308 brw_inst_set_jip(p->devinfo, brw_last_inst, $4);
1309 brw_inst_set_uip(p->devinfo, brw_last_inst, $5);
1311 brw_set_src0(p, brw_last_inst, brw_ip_reg());
1312 brw_set_src1(p, brw_last_inst, brw_imm_d(0x0));
1313 if (p->devinfo->gen >= 6) {
1314 brw_inst_set_jip(p->devinfo, brw_last_inst, $4);
1315 brw_inst_set_uip(p->devinfo, brw_last_inst, $5);
1317 brw_inst_set_gen4_jump_count(p->devinfo, brw_last_inst,
1319 brw_inst_set_gen4_pop_count(p->devinfo, brw_last_inst,
1324 brw_pop_insn_state(p);
1328 /* loop instruction */
1330 predicate WHILE execsize relativelocation instoptions
1332 brw_next_insn(p, $2);
1333 i965_asm_set_instruction_options(p, $5);
1334 brw_inst_set_exec_size(p->devinfo, brw_last_inst, $3);
1336 if (p->devinfo->gen >= 6) {
1337 if (p->devinfo->gen >= 8) {
1338 brw_set_dest(p, brw_last_inst,
1339 retype(brw_null_reg(),
1340 BRW_REGISTER_TYPE_D));
1341 brw_set_src0(p, brw_last_inst, brw_imm_d($4));
1342 } else if (p->devinfo->gen == 7) {
1343 brw_set_dest(p, brw_last_inst,
1344 retype(brw_null_reg(),
1345 BRW_REGISTER_TYPE_D));
1346 brw_set_src0(p, brw_last_inst,
1347 retype(brw_null_reg(),
1348 BRW_REGISTER_TYPE_D));
1349 brw_set_src1(p, brw_last_inst,
1351 brw_inst_set_jip(p->devinfo, brw_last_inst,
1354 brw_set_dest(p, brw_last_inst, brw_imm_w(0x0));
1355 brw_inst_set_gen6_jump_count(p->devinfo,
1358 brw_set_src0(p, brw_last_inst,
1359 retype(brw_null_reg(),
1360 BRW_REGISTER_TYPE_D));
1361 brw_set_src1(p, brw_last_inst,
1362 retype(brw_null_reg(),
1363 BRW_REGISTER_TYPE_D));
1366 brw_set_dest(p, brw_last_inst, brw_ip_reg());
1367 brw_set_src0(p, brw_last_inst, brw_ip_reg());
1368 brw_set_src1(p, brw_last_inst, brw_imm_d(0x0));
1369 brw_inst_set_gen4_jump_count(p->devinfo, brw_last_inst,
1371 brw_inst_set_gen4_pop_count(p->devinfo, brw_last_inst,
1374 brw_pop_insn_state(p);
1376 | DO execsize instoptions
1378 brw_next_insn(p, $1);
1379 if (p->devinfo->gen < 6) {
1380 brw_inst_set_exec_size(p->devinfo, brw_last_inst, $2);
1381 i965_asm_set_instruction_options(p, $3);
1382 brw_set_dest(p, brw_last_inst, brw_null_reg());
1383 brw_set_src0(p, brw_last_inst, brw_null_reg());
1384 brw_set_src1(p, brw_last_inst, brw_null_reg());
1386 brw_inst_set_qtr_control(p->devinfo, brw_last_inst, BRW_COMPRESSION_NONE);
1391 /* Relative location */
1398 INTEGER { $$ = $1; }
1399 | MINUS INTEGER { $$ = -$2; }
1401 | MINUS LONG { $$ = -$2; }
1406 | %empty { $$ = 0; }
1416 /* Destination register */
1423 dstreg dstregion writemask dsttype
1428 $$.hstride = BRW_HORIZONTAL_STRIDE_1;
1429 $$.vstride = BRW_VERTICAL_STRIDE_1;
1430 $$.width = BRW_WIDTH_1;
1435 $$.writemask = $3.writemask;
1436 $$.swizzle = BRW_SWIZZLE_NOOP;
1437 $$.subnr = $$.subnr * brw_reg_type_to_size($4.type);
1442 dstoperandex_typed dstregion writemask dsttype
1447 $$.writemask = $3.writemask;
1448 $$.subnr = $$.subnr * brw_reg_type_to_size($4.type);
1450 | dstoperandex_ud_typed
1454 $$.type = BRW_REGISTER_TYPE_UD;
1456 /* BSpec says "When the conditional modifier is present, updates
1457 * to the selected flag register also occur. In this case, the
1458 * register region fields of the ‘null’ operand are valid."
1460 | nullreg dstregion writemask dsttype
1464 $$.hstride = BRW_HORIZONTAL_STRIDE_1;
1465 $$.vstride = BRW_VERTICAL_STRIDE_1;
1466 $$.width = BRW_WIDTH_1;
1470 $$.writemask = $3.writemask;
1477 $$.type = BRW_REGISTER_TYPE_UW;
1481 dstoperandex_ud_typed:
1500 $$.address_mode = BRW_ADDRESS_DIRECT;
1505 $$.address_mode = BRW_ADDRESS_REGISTER_INDIRECT_REGISTER;
1510 $$.address_mode = BRW_ADDRESS_DIRECT;
1515 $$.address_mode = BRW_ADDRESS_REGISTER_INDIRECT_REGISTER;
1519 /* Source register */
1531 case BRW_REGISTER_TYPE_UD:
1533 $$ = brw_imm_ud(u32);
1535 case BRW_REGISTER_TYPE_D:
1538 case BRW_REGISTER_TYPE_UW:
1539 u32 = $1 | ($1 << 16);
1540 $$ = brw_imm_uw(u32);
1542 case BRW_REGISTER_TYPE_W:
1544 $$ = brw_imm_w(u32);
1546 case BRW_REGISTER_TYPE_F:
1547 $$ = brw_imm_reg(BRW_REGISTER_TYPE_F);
1551 case BRW_REGISTER_TYPE_V:
1554 case BRW_REGISTER_TYPE_UV:
1555 $$ = brw_imm_uv($1);
1557 case BRW_REGISTER_TYPE_VF:
1558 $$ = brw_imm_reg(BRW_REGISTER_TYPE_VF);
1561 case BRW_REGISTER_TYPE_Q:
1563 $$ = brw_imm_q(u64);
1565 case BRW_REGISTER_TYPE_UQ:
1567 $$ = brw_imm_uq(u64);
1569 case BRW_REGISTER_TYPE_DF:
1570 $$ = brw_imm_reg(BRW_REGISTER_TYPE_DF);
1574 error(&@2, "Unkown immdediate type %s\n",
1575 brw_reg_type_to_letters($2.type));
1581 directgenreg region srctype
1583 $$ = set_direct_src_operand(&$1, $3.type);
1584 $$ = stride($$, $2.vstride, $2.width, $2.hstride);
1594 | indirectsrcoperand
1599 | indirectsrcoperand
1604 | indirectsrcoperand
1608 directsrcaccoperand:
1610 | accreg region srctype
1612 $$ = set_direct_src_operand(&$1, $3.type);
1613 $$.vstride = $2.vstride;
1614 $$.width = $2.width;
1615 $$.hstride = $2.hstride;
1620 srcarcoperandex_typed region srctype
1622 $$ = brw_reg($1.file,
1634 | srcarcoperandex_ud_typed
1636 $$ = set_direct_src_operand(&$1, BRW_REGISTER_TYPE_UD);
1638 | nullreg region srctype
1640 $$ = set_direct_src_operand(&$1, $3.type);
1641 $$.vstride = $2.vstride;
1642 $$.width = $2.width;
1643 $$.hstride = $2.hstride;
1647 $$ = set_direct_src_operand(&$1, BRW_REGISTER_TYPE_UW);
1651 srcarcoperandex_ud_typed:
1658 srcarcoperandex_typed:
1665 negate abs indirectgenreg indirectregion swizzle srctype
1667 $$ = brw_reg($3.file,
1679 $$.address_mode = BRW_ADDRESS_REGISTER_INDIRECT_REGISTER;
1680 // brw_reg set indirect_offset to 0 so set it to valid value
1681 $$.indirect_offset = $3.indirect_offset;
1694 negate abs directgenreg_list region swizzle srctype
1696 $$ = brw_reg($3.file,
1711 /* Address register */
1715 memset(&$$, '\0', sizeof($$));
1716 $$.subnr = $1.subnr;
1717 $$.indirect_offset = $2;
1722 /* Register files and register numbers */
1724 INTEGER { $$ = $1; }
1729 DOT exp { $$ = $2; }
1730 | %empty %prec SUBREGNUM { $$ = 0; }
1736 memset(&$$, '\0', sizeof($$));
1737 $$.file = BRW_GENERAL_REGISTER_FILE;
1744 GENREGFILE LSQUARE addrparam RSQUARE
1746 memset(&$$, '\0', sizeof($$));
1747 $$.file = BRW_GENERAL_REGISTER_FILE;
1748 $$.subnr = $3.subnr;
1749 $$.indirect_offset = $3.indirect_offset;
1756 $$ = brw_message_reg($1);
1762 MSGREGFILE LSQUARE addrparam RSQUARE
1764 memset(&$$, '\0', sizeof($$));
1765 $$.file = BRW_MESSAGE_REGISTER_FILE;
1766 $$.subnr = $3.subnr;
1767 $$.indirect_offset = $3.indirect_offset;
1775 error(&@1, "Address register number %d"
1776 "out of range\n", $1);
1778 int subnr = (p->devinfo->gen >= 8) ? 16 : 8;
1781 error(&@2, "Address sub resgister number %d"
1782 "out of range\n", $2);
1784 $$.file = BRW_ARCHITECTURE_REGISTER_FILE;
1785 $$.nr = BRW_ARF_ADDRESS;
1794 if (p->devinfo->gen < 8)
1800 error(&@1, "Accumulator register number %d"
1801 " out of range\n", $1);
1803 memset(&$$, '\0', sizeof($$));
1804 $$.file = BRW_ARCHITECTURE_REGISTER_FILE;
1805 $$.nr = BRW_ARF_ACCUMULATOR;
1813 // SNB = 1 flag reg and IVB+ = 2 flag reg
1814 int nr_reg = (p->devinfo->gen >= 7) ? 2 : 1;
1818 error(&@1, "Flag register number %d"
1819 " out of range \n", $1);
1821 error(&@2, "Flag subregister number %d"
1822 " out of range\n", $2);
1824 $$.file = BRW_ARCHITECTURE_REGISTER_FILE;
1825 $$.nr = BRW_ARF_FLAG | $1;
1834 error(&@1, "Mask register number %d"
1835 " out of range\n", $1);
1837 $$ = brw_mask_reg($2);
1845 error(&@1, "Notification register number %d"
1846 " out of range\n", $1);
1848 int subnr = (p->devinfo->gen >= 11) ? 2 : 3;
1850 error(&@2, "Notification sub register number %d"
1851 " out of range\n", $2);
1853 $$ = brw_notification_reg();
1862 error(&@1, "State register number %d"
1863 " out of range\n", $1);
1866 error(&@2, "State sub register number %d"
1867 " out of range\n", $2);
1869 $$.file = BRW_ARCHITECTURE_REGISTER_FILE;
1870 $$.nr = BRW_ARF_STATE;
1876 CONTROLREG subregnum
1879 error(&@1, "Control register number %d"
1880 " out of range\n", $1);
1883 error(&@2, "control sub register number %d"
1884 " out of range\n", $2);
1886 $$ = brw_cr0_reg($2);
1892 IPREG srctype { $$ = brw_ip_reg(); }
1896 NULL_TOKEN { $$ = brw_null_reg(); }
1903 error(&@1, "Thread control register number %d"
1904 " out of range\n", $1);
1907 error(&@2, "Thread control sub register number %d"
1908 " out of range\n", $2);
1916 PERFORMANCEREG subregnum
1919 if (p->devinfo->gen >= 10)
1921 else if (p->devinfo->gen <= 8)
1927 error(&@2, "Performance sub register number %d"
1928 " out of range\n", $2);
1930 $$.file = BRW_ARCHITECTURE_REGISTER_FILE;
1931 $$.nr = BRW_ARF_TIMESTAMP;
1936 CHANNELENABLEREG subregnum
1939 error(&@1, "Channel enable register number %d"
1940 " out of range\n", $1);
1942 $$ = brw_mask_reg($2);
1946 /* Immediate values */
1952 | LSQUARE exp2 COMMA exp2 COMMA exp2 COMMA exp2 RSQUARE
1954 $$ = ($2 << 0) | ($4 << 8) | ($6 << 16) | ($8 << 24);
1963 if ($2 != 0 && ($2 > 4 || !isPowerofTwo($2)))
1964 error(&@2, "Invalid Horizontal stride %d\n", $2);
1978 $$ = stride($$, BRW_VERTICAL_STRIDE_1, BRW_WIDTH_2, BRW_HORIZONTAL_STRIDE_1);
1982 if ($2 != 0 && ($2 > 32 || !isPowerofTwo($2)))
1983 error(&@2, "Invalid VertStride %d\n", $2);
1985 $$ = stride($$, $2, BRW_WIDTH_1, 0);
1987 | LANGLE exp COMMA exp COMMA exp RANGLE
1990 if ($2 != 0 && ($2 > 32 || !isPowerofTwo($2)))
1991 error(&@2, "Invalid VertStride %d\n", $2);
1993 if ($4 > 16 || !isPowerofTwo($4))
1994 error(&@4, "Invalid width %d\n", $4);
1996 if ($6 != 0 && ($6 > 4 || !isPowerofTwo($6)))
1997 error(&@6, "Invalid Horizontal stride in"
1998 " region_wh %d\n", $6);
2000 $$ = stride($$, $2, $4, $6);
2002 | LANGLE exp SEMICOLON exp COMMA exp RANGLE
2004 if ($2 != 0 && ($2 > 32 || !isPowerofTwo($2)))
2005 error(&@2, "Invalid VertStride %d\n", $2);
2007 if ($4 > 16 || !isPowerofTwo($4))
2008 error(&@4, "Invalid width %d\n", $4);
2010 if ($6 != 0 && ($6 > 4 || !isPowerofTwo($6)))
2011 error(&@6, "Invalid Horizontal stride in"
2012 " region_wh %d\n", $6);
2014 $$ = stride($$, $2, $4, $6);
2016 | LANGLE VxH COMMA exp COMMA exp RANGLE
2018 if ($4 > 16 || !isPowerofTwo($4))
2019 error(&@4, "Invalid width %d\n", $4);
2021 if ($6 != 0 && ($6 > 4 || !isPowerofTwo($6)))
2022 error(&@6, "Invalid Horizontal stride in"
2023 " region_wh %d\n", $6);
2025 $$ = brw_VxH_indirect(0, 0);
2030 LANGLE exp COMMA exp RANGLE
2032 if ($2 > 16 || !isPowerofTwo($2))
2033 error(&@2, "Invalid width %d\n", $2);
2035 if ($4 != 0 && ($4 > 4 || !isPowerofTwo($4)))
2036 error(&@4, "Invalid Horizontal stride in"
2037 " region_wh %d\n", $4);
2039 $$ = stride($$, BRW_VERTICAL_STRIDE_ONE_DIMENSIONAL, $2, $4);
2044 %empty { $$ = retype($$, BRW_REGISTER_TYPE_F); }
2045 | TYPE_F { $$ = retype($$, BRW_REGISTER_TYPE_F); }
2046 | TYPE_UD { $$ = retype($$, BRW_REGISTER_TYPE_UD); }
2047 | TYPE_D { $$ = retype($$, BRW_REGISTER_TYPE_D); }
2048 | TYPE_UW { $$ = retype($$, BRW_REGISTER_TYPE_UW); }
2049 | TYPE_W { $$ = retype($$, BRW_REGISTER_TYPE_W); }
2050 | TYPE_UB { $$ = retype($$, BRW_REGISTER_TYPE_UB); }
2051 | TYPE_B { $$ = retype($$, BRW_REGISTER_TYPE_B); }
2052 | TYPE_DF { $$ = retype($$, BRW_REGISTER_TYPE_DF); }
2053 | TYPE_UQ { $$ = retype($$, BRW_REGISTER_TYPE_UQ); }
2054 | TYPE_Q { $$ = retype($$, BRW_REGISTER_TYPE_Q); }
2055 | TYPE_HF { $$ = retype($$, BRW_REGISTER_TYPE_HF); }
2056 | TYPE_NF { $$ = retype($$, BRW_REGISTER_TYPE_NF); }
2060 srctype { $$ = $1; }
2061 | TYPE_V { $$ = retype($$, BRW_REGISTER_TYPE_V); }
2062 | TYPE_VF { $$ = retype($$, BRW_REGISTER_TYPE_VF); }
2063 | TYPE_UV { $$ = retype($$, BRW_REGISTER_TYPE_UV); }
2067 srctype { $$ = $1; }
2073 $$= brw_set_writemask($$, WRITEMASK_XYZW);
2075 | DOT writemask_x writemask_y writemask_z writemask_w
2077 $$ = brw_set_writemask($$, $2 | $3 | $4 | $5);
2083 | X { $$ = 1 << BRW_CHANNEL_X; }
2088 | Y { $$ = 1 << BRW_CHANNEL_Y; }
2093 | Z { $$ = 1 << BRW_CHANNEL_Z; }
2098 | W { $$ = 1 << BRW_CHANNEL_W; }
2104 $$.swizzle = BRW_SWIZZLE_NOOP;
2108 $$.swizzle = BRW_SWIZZLE4($2, $2, $2, $2);
2110 | DOT chansel chansel chansel chansel
2112 $$.swizzle = BRW_SWIZZLE4($2, $3, $4, $5);
2123 /* Instruction prediction and modifiers */
2127 brw_push_insn_state(p);
2128 brw_set_default_predicate_control(p, BRW_PREDICATE_NONE);
2129 brw_set_default_flag_reg(p, 0, 0);
2130 brw_set_default_predicate_inverse(p, false);
2132 | LPAREN predstate flagreg predctrl RPAREN
2134 brw_push_insn_state(p);
2135 brw_set_default_predicate_inverse(p, $2);
2136 brw_set_default_flag_reg(p, $3.nr, $3.subnr);
2137 brw_set_default_predicate_control(p, $4);
2148 %empty { $$ = BRW_PREDICATE_NORMAL; }
2149 | DOT X { $$ = BRW_PREDICATE_ALIGN16_REPLICATE_X; }
2150 | DOT Y { $$ = BRW_PREDICATE_ALIGN16_REPLICATE_Y; }
2151 | DOT Z { $$ = BRW_PREDICATE_ALIGN16_REPLICATE_Z; }
2152 | DOT W { $$ = BRW_PREDICATE_ALIGN16_REPLICATE_W; }
2167 /* Source Modification */
2178 /* Flag (Conditional) Modifier */
2182 $$.cond_modifier = $1;
2184 $$.flag_subreg_nr = 0;
2186 | condModifiers DOT flagreg
2188 $$.cond_modifier = $1;
2189 $$.flag_reg_nr = $3.nr;
2190 $$.flag_subreg_nr = $3.subnr;
2195 %empty { $$ = BRW_CONDITIONAL_NONE; }
2210 %empty { $$ = BRW_INSTRUCTION_NORMAL; }
2211 | SATURATE { $$ = BRW_INSTRUCTION_SATURATE; }
2214 /* Execution size */
2216 %empty %prec EMPTYEXECSIZE
2220 | LPAREN exp2 RPAREN
2222 if ($2 > 32 || !isPowerofTwo($2))
2223 error(&@2, "Invalid execution size %d\n", $2);
2229 /* Instruction options */
2233 memset(&$$, 0, sizeof($$));
2235 | LCURLY instoption_list RCURLY
2237 memset(&$$, 0, sizeof($$));
2243 instoption_list COMMA instoption
2245 memset(&$$, 0, sizeof($$));
2247 add_instruction_option(&$$, $3);
2249 | instoption_list instoption
2251 memset(&$$, 0, sizeof($$));
2253 add_instruction_option(&$$, $2);
2257 memset(&$$, 0, sizeof($$));
2262 ALIGN1 { $$ = ALIGN1;}
2263 | ALIGN16 { $$ = ALIGN16; }
2264 | ACCWREN { $$ = ACCWREN; }
2265 | SECHALF { $$ = SECHALF; }
2266 | COMPR { $$ = COMPR; }
2267 | COMPR4 { $$ = COMPR4; }
2268 | BREAKPOINT { $$ = BREAKPOINT; }
2269 | NODDCLR { $$ = NODDCLR; }
2270 | NODDCHK { $$ = NODDCHK; }
2271 | MASK_DISABLE { $$ = MASK_DISABLE; }
2273 | SWITCH { $$ = SWITCH; }
2274 | ATOMIC { $$ = ATOMIC; }
2275 | CMPTCTRL { $$ = CMPTCTRL; }
2276 | WECTRL { $$ = WECTRL; }
2277 | QTR_2Q { $$ = QTR_2Q; }
2278 | QTR_3Q { $$ = QTR_3Q; }
2279 | QTR_4Q { $$ = QTR_4Q; }
2280 | QTR_2H { $$ = QTR_2H; }
2281 | QTR_2N { $$ = QTR_2N; }
2282 | QTR_3N { $$ = QTR_3N; }
2283 | QTR_4N { $$ = QTR_4N; }
2284 | QTR_5N { $$ = QTR_5N; }
2285 | QTR_6N { $$ = QTR_6N; }
2286 | QTR_7N { $$ = QTR_7N; }
2287 | QTR_8N { $$ = QTR_8N; }
2292 extern int yylineno;
2297 fprintf(stderr, "%s: %d: %s at \"%s\"\n",
2298 input_filename, yylineno, msg, lex_text());