3 * Copyright © 2018 Intel Corporation
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
21 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
31 #define YYLTYPE YYLTYPE
32 typedef struct YYLTYPE
48 message(enum message_level level, YYLTYPE *location,
51 static const char *level_str[] = { "warning", "error" };
55 fprintf(stderr, "%s:%d:%d: %s: ", input_filename,
57 location->first_column, level_str[level]);
59 fprintf(stderr, "%s:%s: ", input_filename, level_str[level]);
62 vfprintf(stderr, fmt, args);
66 #define warn(flag, l, fmt, ...) \
68 if (warning_flags & WARN_ ## flag) \
69 message(WARN, l, fmt, ## __VA_ARGS__); \
72 #define error(l, fmt, ...) \
74 message(ERROR, l, fmt, ## __VA_ARGS__); \
78 isPowerofTwo(unsigned int x)
80 return x && (!(x & (x - 1)));
84 set_direct_src_operand(struct brw_reg *reg, int type)
86 return brw_reg(reg->file,
100 i965_asm_unary_instruction(int opcode, struct brw_codegen *p,
101 struct brw_reg dest, struct brw_reg src0)
104 case BRW_OPCODE_BFREV:
105 brw_BFREV(p, dest, src0);
107 case BRW_OPCODE_CBIT:
108 brw_CBIT(p, dest, src0);
110 case BRW_OPCODE_F32TO16:
111 brw_F32TO16(p, dest, src0);
113 case BRW_OPCODE_F16TO32:
114 brw_F16TO32(p, dest, src0);
117 brw_MOV(p, dest, src0);
120 brw_FBL(p, dest, src0);
123 brw_FRC(p, dest, src0);
126 brw_FBH(p, dest, src0);
129 brw_NOT(p, dest, src0);
131 case BRW_OPCODE_RNDE:
132 brw_RNDE(p, dest, src0);
134 case BRW_OPCODE_RNDZ:
135 brw_RNDZ(p, dest, src0);
137 case BRW_OPCODE_RNDD:
138 brw_RNDD(p, dest, src0);
141 brw_LZD(p, dest, src0);
144 brw_DIM(p, dest, src0);
146 case BRW_OPCODE_RNDU:
147 fprintf(stderr, "Opcode BRW_OPCODE_RNDU unhandled\n");
150 fprintf(stderr, "Unsupported unary opcode\n");
155 i965_asm_binary_instruction(int opcode,
156 struct brw_codegen *p,
162 case BRW_OPCODE_ADDC:
163 brw_ADDC(p, dest, src0, src1);
165 case BRW_OPCODE_BFI1:
166 brw_BFI1(p, dest, src0, src1);
169 brw_DP2(p, dest, src0, src1);
172 brw_DP3(p, dest, src0, src1);
175 brw_DP4(p, dest, src0, src1);
178 brw_DPH(p, dest, src0, src1);
180 case BRW_OPCODE_LINE:
181 brw_LINE(p, dest, src0, src1);
184 brw_MAC(p, dest, src0, src1);
186 case BRW_OPCODE_MACH:
187 brw_MACH(p, dest, src0, src1);
190 brw_PLN(p, dest, src0, src1);
193 brw_ROL(p, dest, src0, src1);
196 brw_ROR(p, dest, src0, src1);
198 case BRW_OPCODE_SAD2:
199 fprintf(stderr, "Opcode BRW_OPCODE_SAD2 unhandled\n");
201 case BRW_OPCODE_SADA2:
202 fprintf(stderr, "Opcode BRW_OPCODE_SADA2 unhandled\n");
204 case BRW_OPCODE_SUBB:
205 brw_SUBB(p, dest, src0, src1);
208 brw_ADD(p, dest, src0, src1);
211 /* Third parameter is conditional modifier
212 * which gets updated later
214 brw_CMP(p, dest, 0, src0, src1);
217 brw_AND(p, dest, src0, src1);
220 brw_ASR(p, dest, src0, src1);
223 brw_AVG(p, dest, src0, src1);
226 brw_OR(p, dest, src0, src1);
229 brw_SEL(p, dest, src0, src1);
232 brw_SHL(p, dest, src0, src1);
235 brw_SHR(p, dest, src0, src1);
238 brw_XOR(p, dest, src0, src1);
241 brw_MUL(p, dest, src0, src1);
244 fprintf(stderr, "Unsupported binary opcode\n");
249 i965_asm_ternary_instruction(int opcode,
250 struct brw_codegen *p,
258 brw_MAD(p, dest, src0, src1, src2);
260 case BRW_OPCODE_CSEL:
261 brw_CSEL(p, dest, src0, src1, src2);
264 brw_LRP(p, dest, src0, src1, src2);
267 brw_BFE(p, dest, src0, src1, src2);
269 case BRW_OPCODE_BFI2:
270 brw_BFI2(p, dest, src0, src1, src2);
273 fprintf(stderr, "Unsupported ternary opcode\n");
278 i965_asm_set_instruction_options(struct brw_codegen *p,
279 struct options options)
281 brw_inst_set_access_mode(p->devinfo, brw_last_inst,
282 options.access_mode);
283 brw_inst_set_mask_control(p->devinfo, brw_last_inst,
284 options.mask_control);
285 brw_inst_set_thread_control(p->devinfo, brw_last_inst,
286 options.thread_control);
287 brw_inst_set_no_dd_check(p->devinfo, brw_last_inst,
288 options.no_dd_check);
289 brw_inst_set_no_dd_clear(p->devinfo, brw_last_inst,
290 options.no_dd_clear);
291 brw_inst_set_debug_control(p->devinfo, brw_last_inst,
292 options.debug_control);
293 if (p->devinfo->gen >= 6)
294 brw_inst_set_acc_wr_control(p->devinfo, brw_last_inst,
295 options.acc_wr_control);
296 brw_inst_set_cmpt_control(p->devinfo, brw_last_inst,
301 i965_asm_set_dst_nr(struct brw_codegen *p,
303 struct options options)
305 if (p->devinfo->gen <= 6) {
306 if (reg->file == BRW_MESSAGE_REGISTER_FILE &&
307 options.qtr_ctrl == BRW_COMPRESSION_COMPRESSED &&
309 reg->nr |= BRW_MRF_COMPR4;
314 add_label(struct brw_codegen *p, const char* label_name, enum instr_label_type type)
320 struct instr_label *label = rzalloc(p->mem_ctx, struct instr_label);
322 label->name = ralloc_strdup(p->mem_ctx, label_name);
323 label->offset = p->next_insn_offset;
326 list_addtail(&label->link, &instr_labels);
339 unsigned long long int llint;
341 enum brw_reg_type reg_type;
342 struct brw_codegen *program;
343 struct predicate predicate;
344 struct condition condition;
345 struct options options;
346 brw_inst *instruction;
356 %token LSQUARE RSQUARE
361 %token <integer> TYPE_B TYPE_UB
362 %token <integer> TYPE_W TYPE_UW
363 %token <integer> TYPE_D TYPE_UD
364 %token <integer> TYPE_Q TYPE_UQ
365 %token <integer> TYPE_V TYPE_UV
366 %token <integer> TYPE_F TYPE_HF
367 %token <integer> TYPE_DF TYPE_NF
368 %token <integer> TYPE_VF
371 %token <string> JUMP_LABEL
372 %token <string> JUMP_LABEL_TARGET
375 %token <integer> ADD ADD3 ADDC AND ASR AVG
376 %token <integer> BFE BFI1 BFI2 BFB BFREV BRC BRD BREAK
377 %token <integer> CALL CALLA CASE CBIT CMP CMPN CONT CSEL
378 %token <integer> DIM DO DPAS DPASW DP2 DP3 DP4 DP4A DPH
379 %token <integer> ELSE ENDIF F16TO32 F32TO16 FBH FBL FORK FRC
380 %token <integer> GOTO
381 %token <integer> HALT
382 %token <integer> IF IFF ILLEGAL
383 %token <integer> JMPI JOIN
384 %token <integer> LINE LRP LZD
385 %token <integer> MAC MACH MAD MADM MOV MOVI MUL MREST MSAVE
386 %token <integer> NENOP NOP NOT
388 %token <integer> PLN POP PUSH
389 %token <integer> RET RNDD RNDE RNDU RNDZ ROL ROR
390 %token <integer> SAD2 SADA2 SEL SEND SENDC SENDS SENDSC SHL SHR SMOV SUBB SYNC
391 %token <integer> WAIT WHILE
394 /* extended math functions */
395 %token <integer> COS EXP FDIV INV INVM INTDIV INTDIVMOD INTMOD LOG POW RSQ
396 %token <integer> RSQRTM SIN SINCOS SQRT
398 /* shared functions for send */
399 %token CONST CRE DATA DP_DATA_1 GATEWAY MATH PIXEL_INTERP READ RENDER SAMPLER
400 %token THREAD_SPAWNER URB VME WRITE DP_SAMPLER
402 /* Conditional modifiers */
403 %token <integer> EQUAL GREATER GREATER_EQUAL LESS LESS_EQUAL NOT_EQUAL
404 %token <integer> NOT_ZERO OVERFLOW UNORDERED ZERO
406 /* register Access Modes */
407 %token ALIGN1 ALIGN16
409 /* accumulator write control */
412 /* compaction control */
415 /* compression control */
416 %token COMPR COMPR4 SECHALF
418 /* mask control (WeCtrl) */
424 /* dependency control */
425 %token NODDCLR NODDCHK
433 /* predicate control */
434 %token <integer> ANYV ALLV ANY2H ALL2H ANY4H ALL4H ANY8H ALL8H ANY16H ALL16H
435 %token <integer> ANY32H ALL32H
437 /* round instructions */
438 %token <integer> ROUND_INCREMENT
447 %token QTR_2Q QTR_3Q QTR_4Q QTR_2H QTR_2N QTR_3N QTR_4N QTR_5N
448 %token QTR_6N QTR_7N QTR_8N
451 %token <integer> X Y Z W
454 %token GENREGFILE MSGREGFILE
456 /* vertical stride in register region */
460 %token <integer> GENREG MSGREG ADDRREG ACCREG FLAGREG NOTIFYREG STATEREG
461 %token <integer> CONTROLREG IPREG PERFORMANCEREG THREADREG CHANNELENABLEREG
462 %token <integer> MASKREG
464 %token <integer> INTEGER
468 %precedence SUBREGNUM
471 %precedence EMPTYEXECSIZE
474 %type <integer> execsize simple_int exp
477 /* predicate control */
478 %type <integer> predctrl predstate
479 %type <predicate> predicate
481 /* conditional modifier */
482 %type <condition> cond_mod
483 %type <integer> condModifiers
485 /* instruction options */
486 %type <options> instoptions instoption_list
487 %type <integer> instoption
490 %type <integer> writemask_x writemask_y writemask_z writemask_w
491 %type <integer> writemask
494 %type <reg> dst dstoperand dstoperandex dstoperandex_typed dstreg
495 %type <integer> dstregion
497 %type <integer> saturate relativelocation rellocation
498 %type <reg> relativelocation2
501 %type <reg> directsrcoperand directsrcaccoperand indirectsrcoperand srcacc
502 %type <reg> srcarcoperandex srcaccimm srcarcoperandex_typed srcimm
503 %type <reg> indirectgenreg indirectregion
504 %type <reg> immreg src reg32 payload directgenreg_list addrparam region
505 %type <reg> region_wh directgenreg directmsgreg indirectmsgreg
506 %type <integer> swizzle
509 %type <reg> accreg addrreg channelenablereg controlreg flagreg ipreg
510 %type <reg> notifyreg nullreg performancereg threadcontrolreg statereg maskreg
511 %type <integer> subregnum
514 %type <reg_type> reg_type imm_type
516 /* immediate values */
519 /* instruction opcodes */
520 %type <integer> unaryopcodes binaryopcodes binaryaccopcodes ternaryopcodes
521 %type <integer> sendop
522 %type <instruction> sendopcode
524 %type <integer> negate abs chansel math_function sharedfunction
526 %type <string> jumplabeltarget
527 %type <string> jumplabel
532 add_instruction_option(struct options *options, int option)
536 options->access_mode = BRW_ALIGN_1;
539 options->access_mode = BRW_ALIGN_16;
542 options->qtr_ctrl |= BRW_COMPRESSION_2NDHALF;
545 options->qtr_ctrl |= BRW_COMPRESSION_COMPRESSED;
546 options->is_compr = true;
549 options->qtr_ctrl |= BRW_COMPRESSION_COMPRESSED;
552 options->thread_control |= BRW_THREAD_SWITCH;
555 options->thread_control |= BRW_THREAD_ATOMIC;
558 options->no_dd_check = true;
561 options->no_dd_clear = BRW_DEPENDENCY_NOTCLEARED;
564 options->mask_control |= BRW_MASK_DISABLE;
567 options->debug_control = BRW_DEBUG_BREAKPOINT;
570 options->mask_control |= BRW_WE_ALL;
573 options->compaction = true;
576 options->acc_wr_control = true;
579 options->end_of_thread = true;
581 /* TODO : Figure out how to set instruction group and get rid of
585 options->qtr_ctrl = BRW_COMPRESSION_2NDHALF;
588 options->qtr_ctrl = BRW_COMPRESSION_COMPRESSED;
591 options->qtr_ctrl = 3;
594 options->qtr_ctrl = BRW_COMPRESSION_COMPRESSED;
597 options->qtr_ctrl = BRW_COMPRESSION_NONE;
598 options->nib_ctrl = true;
601 options->qtr_ctrl = BRW_COMPRESSION_2NDHALF;
604 options->qtr_ctrl = BRW_COMPRESSION_2NDHALF;
605 options->nib_ctrl = true;
608 options->qtr_ctrl = BRW_COMPRESSION_COMPRESSED;
611 options->qtr_ctrl = BRW_COMPRESSION_COMPRESSED;
612 options->nib_ctrl = true;
615 options->qtr_ctrl = 3;
618 options->qtr_ctrl = 3;
619 options->nib_ctrl = true;
631 instrseq instruction SEMICOLON
632 | instrseq relocatableinstruction SEMICOLON
633 | instruction SEMICOLON
634 | relocatableinstruction SEMICOLON
635 | instrseq jumplabeltarget
639 /* Instruction Group */
643 | binaryaccinstruction
652 relocatableinstruction:
660 ILLEGAL execsize instoptions
662 brw_next_insn(p, $1);
663 brw_inst_set_exec_size(p->devinfo, brw_last_inst, $2);
664 i965_asm_set_instruction_options(p, $3);
668 /* Unary instruction */
670 predicate unaryopcodes saturate cond_mod execsize dst srcaccimm instoptions
672 i965_asm_set_dst_nr(p, &$6, $8);
673 brw_set_default_access_mode(p, $8.access_mode);
674 i965_asm_unary_instruction($2, p, $6, $7);
675 brw_pop_insn_state(p);
676 i965_asm_set_instruction_options(p, $8);
677 brw_inst_set_cond_modifier(p->devinfo, brw_last_inst,
680 if (p->devinfo->gen >= 7) {
681 if ($2 != BRW_OPCODE_DIM) {
682 brw_inst_set_flag_reg_nr(p->devinfo,
685 brw_inst_set_flag_subreg_nr(p->devinfo,
691 if ($7.file != BRW_IMMEDIATE_VALUE) {
692 brw_inst_set_src0_vstride(p->devinfo, brw_last_inst,
695 brw_inst_set_saturate(p->devinfo, brw_last_inst, $3);
696 brw_inst_set_exec_size(p->devinfo, brw_last_inst, $5);
697 // TODO: set instruction group instead of qtr and nib ctrl
698 brw_inst_set_qtr_control(p->devinfo, brw_last_inst,
701 if (p->devinfo->gen >= 7)
702 brw_inst_set_nib_control(p->devinfo, brw_last_inst,
725 /* Binary instruction */
727 predicate binaryopcodes saturate cond_mod execsize dst srcimm srcimm instoptions
729 i965_asm_set_dst_nr(p, &$6, $9);
730 brw_set_default_access_mode(p, $9.access_mode);
731 i965_asm_binary_instruction($2, p, $6, $7, $8);
732 i965_asm_set_instruction_options(p, $9);
733 brw_inst_set_cond_modifier(p->devinfo, brw_last_inst,
736 if (p->devinfo->gen >= 7) {
737 brw_inst_set_flag_reg_nr(p->devinfo, brw_last_inst,
739 brw_inst_set_flag_subreg_nr(p->devinfo, brw_last_inst,
743 brw_inst_set_saturate(p->devinfo, brw_last_inst, $3);
744 brw_inst_set_exec_size(p->devinfo, brw_last_inst, $5);
745 // TODO: set instruction group instead of qtr and nib ctrl
746 brw_inst_set_qtr_control(p->devinfo, brw_last_inst,
749 if (p->devinfo->gen >= 7)
750 brw_inst_set_nib_control(p->devinfo, brw_last_inst,
753 brw_pop_insn_state(p);
776 /* Binary acc instruction */
777 binaryaccinstruction:
778 predicate binaryaccopcodes saturate cond_mod execsize dst srcacc srcimm instoptions
780 i965_asm_set_dst_nr(p, &$6, $9);
781 brw_set_default_access_mode(p, $9.access_mode);
782 i965_asm_binary_instruction($2, p, $6, $7, $8);
783 brw_pop_insn_state(p);
784 i965_asm_set_instruction_options(p, $9);
785 brw_inst_set_cond_modifier(p->devinfo, brw_last_inst,
788 if (p->devinfo->gen >= 7) {
789 if (!brw_inst_flag_reg_nr(p->devinfo, brw_last_inst)) {
790 brw_inst_set_flag_reg_nr(p->devinfo,
793 brw_inst_set_flag_subreg_nr(p->devinfo,
799 brw_inst_set_saturate(p->devinfo, brw_last_inst, $3);
800 brw_inst_set_exec_size(p->devinfo, brw_last_inst, $5);
801 // TODO: set instruction group instead of qtr and nib ctrl
802 brw_inst_set_qtr_control(p->devinfo, brw_last_inst,
805 if (p->devinfo->gen >= 7)
806 brw_inst_set_nib_control(p->devinfo, brw_last_inst,
825 /* Math instruction */
827 predicate MATH saturate math_function execsize dst src srcimm instoptions
829 brw_set_default_access_mode(p, $9.access_mode);
830 gen6_math(p, $6, $4, $7, $8);
831 i965_asm_set_instruction_options(p, $9);
832 brw_inst_set_exec_size(p->devinfo, brw_last_inst, $5);
833 brw_inst_set_saturate(p->devinfo, brw_last_inst, $3);
834 // TODO: set instruction group instead
835 brw_inst_set_qtr_control(p->devinfo, brw_last_inst,
838 if (p->devinfo->gen >= 7)
839 brw_inst_set_nib_control(p->devinfo, brw_last_inst,
842 brw_pop_insn_state(p);
864 /* NOP instruction */
872 /* Ternary operand instruction */
874 predicate ternaryopcodes saturate cond_mod execsize dst src src src instoptions
876 brw_set_default_access_mode(p, $10.access_mode);
877 i965_asm_ternary_instruction($2, p, $6, $7, $8, $9);
878 brw_pop_insn_state(p);
879 i965_asm_set_instruction_options(p, $10);
880 brw_inst_set_cond_modifier(p->devinfo, brw_last_inst,
883 if (p->devinfo->gen >= 7) {
884 brw_inst_set_3src_a16_flag_reg_nr(p->devinfo, brw_last_inst,
886 brw_inst_set_3src_a16_flag_subreg_nr(p->devinfo, brw_last_inst,
890 brw_inst_set_saturate(p->devinfo, brw_last_inst, $3);
891 brw_inst_set_exec_size(p->devinfo, brw_last_inst, $5);
892 // TODO: set instruction group instead of qtr and nib ctrl
893 brw_inst_set_qtr_control(p->devinfo, brw_last_inst,
896 if (p->devinfo->gen >= 7)
897 brw_inst_set_nib_control(p->devinfo, brw_last_inst,
910 /* Sync instruction */
912 WAIT execsize dst instoptions
914 brw_next_insn(p, $1);
915 i965_asm_set_instruction_options(p, $4);
916 brw_inst_set_exec_size(p->devinfo, brw_last_inst, $2);
917 brw_set_default_access_mode(p, $4.access_mode);
918 struct brw_reg dest = $3;
919 dest.swizzle = brw_swizzle_for_mask(dest.writemask);
920 if (dest.file != ARF || dest.nr != BRW_ARF_NOTIFICATION_COUNT)
921 error(&@1, "WAIT must use the notification register\n");
922 brw_set_dest(p, brw_last_inst, dest);
923 brw_set_src0(p, brw_last_inst, dest);
924 brw_set_src1(p, brw_last_inst, brw_null_reg());
925 brw_inst_set_mask_control(p->devinfo, brw_last_inst, BRW_MASK_DISABLE);
929 /* Send instruction */
931 predicate sendopcode execsize dst payload exp2 sharedfunction instoptions
933 i965_asm_set_instruction_options(p, $8);
934 brw_inst_set_exec_size(p->devinfo, brw_last_inst, $3);
935 brw_set_dest(p, brw_last_inst, $4);
936 brw_set_src0(p, brw_last_inst, $5);
937 brw_inst_set_bits(brw_last_inst, 127, 96, $6);
938 brw_inst_set_src1_file_type(p->devinfo, brw_last_inst,
940 BRW_REGISTER_TYPE_UD);
941 brw_inst_set_sfid(p->devinfo, brw_last_inst, $7);
942 brw_inst_set_eot(p->devinfo, brw_last_inst, $8.end_of_thread);
943 // TODO: set instruction group instead of qtr and nib ctrl
944 brw_inst_set_qtr_control(p->devinfo, brw_last_inst,
947 if (p->devinfo->gen >= 7)
948 brw_inst_set_nib_control(p->devinfo, brw_last_inst,
951 brw_pop_insn_state(p);
953 | predicate sendopcode execsize exp dst payload exp2 sharedfunction instoptions
955 i965_asm_set_instruction_options(p, $9);
956 brw_inst_set_exec_size(p->devinfo, brw_last_inst, $3);
957 brw_inst_set_base_mrf(p->devinfo, brw_last_inst, $4);
958 brw_set_dest(p, brw_last_inst, $5);
959 brw_set_src0(p, brw_last_inst, $6);
960 brw_inst_set_bits(brw_last_inst, 127, 96, $7);
961 brw_inst_set_src1_file_type(p->devinfo, brw_last_inst,
963 BRW_REGISTER_TYPE_UD);
964 brw_inst_set_sfid(p->devinfo, brw_last_inst, $8);
965 brw_inst_set_eot(p->devinfo, brw_last_inst, $9.end_of_thread);
966 // TODO: set instruction group instead of qtr and nib ctrl
967 brw_inst_set_qtr_control(p->devinfo, brw_last_inst,
970 if (p->devinfo->gen >= 7)
971 brw_inst_set_nib_control(p->devinfo, brw_last_inst,
974 brw_pop_insn_state(p);
976 | predicate sendopcode execsize dst payload payload exp2 sharedfunction instoptions
978 i965_asm_set_instruction_options(p, $9);
979 brw_inst_set_exec_size(p->devinfo, brw_last_inst, $3);
980 brw_set_dest(p, brw_last_inst, $4);
981 brw_set_src0(p, brw_last_inst, $5);
982 brw_inst_set_bits(brw_last_inst, 127, 96, $7);
983 brw_inst_set_sfid(p->devinfo, brw_last_inst, $8);
984 brw_inst_set_eot(p->devinfo, brw_last_inst, $9.end_of_thread);
985 // TODO: set instruction group instead of qtr and nib ctrl
986 brw_inst_set_qtr_control(p->devinfo, brw_last_inst,
989 if (p->devinfo->gen >= 7)
990 brw_inst_set_nib_control(p->devinfo, brw_last_inst,
993 brw_pop_insn_state(p);
995 | predicate SENDS execsize dst payload payload exp2 exp2 sharedfunction instoptions
997 brw_next_insn(p, $2);
998 i965_asm_set_instruction_options(p, $10);
999 brw_inst_set_exec_size(p->devinfo, brw_last_inst, $3);
1000 brw_set_dest(p, brw_last_inst, $4);
1001 brw_set_src0(p, brw_last_inst, $5);
1002 brw_set_src1(p, brw_last_inst, $6);
1004 if (brw_inst_send_sel_reg32_ex_desc(p->devinfo, brw_last_inst)) {
1005 brw_inst_set_send_ex_desc_ia_subreg_nr(p->devinfo, brw_last_inst, $5.subnr);
1007 brw_inst_set_sends_ex_desc(p->devinfo, brw_last_inst, $8);
1010 brw_inst_set_bits(brw_last_inst, 127, 96, $7);
1011 brw_inst_set_sfid(p->devinfo, brw_last_inst, $9);
1012 brw_inst_set_eot(p->devinfo, brw_last_inst, $10.end_of_thread);
1013 // TODO: set instruction group instead of qtr and nib ctrl
1014 brw_inst_set_qtr_control(p->devinfo, brw_last_inst,
1017 if (p->devinfo->gen >= 7)
1018 brw_inst_set_nib_control(p->devinfo, brw_last_inst,
1021 brw_pop_insn_state(p);
1023 | predicate SENDS execsize dst payload payload src exp2 sharedfunction instoptions
1025 brw_next_insn(p, $2);
1026 i965_asm_set_instruction_options(p, $10);
1027 brw_inst_set_exec_size(p->devinfo, brw_last_inst, $3);
1028 brw_set_dest(p, brw_last_inst, $4);
1029 brw_set_src0(p, brw_last_inst, $5);
1030 brw_set_src1(p, brw_last_inst, $6);
1032 brw_inst_set_send_sel_reg32_desc(p->devinfo, brw_last_inst, 1);
1033 brw_inst_set_sends_ex_desc(p->devinfo, brw_last_inst, $8);
1035 brw_inst_set_sfid(p->devinfo, brw_last_inst, $9);
1036 brw_inst_set_eot(p->devinfo, brw_last_inst, $10.end_of_thread);
1037 // TODO: set instruction group instead of qtr and nib ctrl
1038 brw_inst_set_qtr_control(p->devinfo, brw_last_inst,
1041 if (p->devinfo->gen >= 7)
1042 brw_inst_set_nib_control(p->devinfo, brw_last_inst,
1045 brw_pop_insn_state(p);
1055 sendop { $$ = brw_next_insn(p, $1); }
1059 NULL_TOKEN { $$ = BRW_SFID_NULL; }
1060 | MATH { $$ = BRW_SFID_MATH; }
1061 | GATEWAY { $$ = BRW_SFID_MESSAGE_GATEWAY; }
1062 | READ { $$ = BRW_SFID_DATAPORT_READ; }
1063 | WRITE { $$ = BRW_SFID_DATAPORT_WRITE; }
1064 | URB { $$ = BRW_SFID_URB; }
1065 | THREAD_SPAWNER { $$ = BRW_SFID_THREAD_SPAWNER; }
1066 | VME { $$ = BRW_SFID_VME; }
1067 | RENDER { $$ = GEN6_SFID_DATAPORT_RENDER_CACHE; }
1068 | CONST { $$ = GEN6_SFID_DATAPORT_CONSTANT_CACHE; }
1069 | DATA { $$ = GEN7_SFID_DATAPORT_DATA_CACHE; }
1070 | PIXEL_INTERP { $$ = GEN7_SFID_PIXEL_INTERPOLATOR; }
1071 | DP_DATA_1 { $$ = HSW_SFID_DATAPORT_DATA_CACHE_1; }
1072 | CRE { $$ = HSW_SFID_CRE; }
1073 | SAMPLER { $$ = BRW_SFID_SAMPLER; }
1074 | DP_SAMPLER { $$ = GEN6_SFID_DATAPORT_SAMPLER_CACHE; }
1079 | MINUS LONG { $$ = -$2; }
1082 /* Jump instruction */
1084 predicate JMPI execsize relativelocation2 instoptions
1086 brw_next_insn(p, $2);
1087 i965_asm_set_instruction_options(p, $5);
1088 brw_inst_set_exec_size(p->devinfo, brw_last_inst, $3);
1089 brw_set_dest(p, brw_last_inst, brw_ip_reg());
1090 brw_set_src0(p, brw_last_inst, brw_ip_reg());
1091 brw_set_src1(p, brw_last_inst, $4);
1092 brw_inst_set_pred_control(p->devinfo, brw_last_inst,
1093 brw_inst_pred_control(p->devinfo,
1095 brw_pop_insn_state(p);
1099 /* branch instruction */
1101 predicate ENDIF execsize JUMP_LABEL instoptions
1103 add_label(p, $4, INSTR_LABEL_JIP);
1105 brw_next_insn(p, $2);
1106 i965_asm_set_instruction_options(p, $5);
1107 brw_inst_set_exec_size(p->devinfo, brw_last_inst, $3);
1109 if (p->devinfo->gen == 6) {
1110 brw_set_dest(p, brw_last_inst, brw_imm_w(0x0));
1111 brw_set_src0(p, brw_last_inst, retype(brw_null_reg(),
1112 BRW_REGISTER_TYPE_D));
1113 brw_set_src1(p, brw_last_inst, retype(brw_null_reg(),
1114 BRW_REGISTER_TYPE_D));
1115 } else if (p->devinfo->gen == 7) {
1116 brw_set_dest(p, brw_last_inst, retype(brw_null_reg(),
1117 BRW_REGISTER_TYPE_D));
1118 brw_set_src0(p, brw_last_inst, retype(brw_null_reg(),
1119 BRW_REGISTER_TYPE_D));
1120 brw_set_src1(p, brw_last_inst, brw_imm_w(0x0));
1122 brw_set_src0(p, brw_last_inst, brw_imm_d(0x0));
1125 brw_pop_insn_state(p);
1127 | predicate ENDIF execsize relativelocation instoptions
1129 brw_next_insn(p, $2);
1130 i965_asm_set_instruction_options(p, $5);
1131 brw_inst_set_exec_size(p->devinfo, brw_last_inst, $3);
1133 brw_set_dest(p, brw_last_inst, retype(brw_null_reg(),
1134 BRW_REGISTER_TYPE_D));
1135 brw_set_src0(p, brw_last_inst, retype(brw_null_reg(),
1136 BRW_REGISTER_TYPE_D));
1137 brw_set_src1(p, brw_last_inst, brw_imm_d(0x0));
1138 brw_inst_set_gen4_pop_count(p->devinfo, brw_last_inst, $4);
1140 brw_inst_set_thread_control(p->devinfo, brw_last_inst,
1143 brw_pop_insn_state(p);
1145 | ELSE execsize JUMP_LABEL jumplabel instoptions
1147 add_label(p, $3, INSTR_LABEL_JIP);
1148 add_label(p, $4, INSTR_LABEL_UIP);
1150 brw_next_insn(p, $1);
1151 i965_asm_set_instruction_options(p, $5);
1152 brw_inst_set_exec_size(p->devinfo, brw_last_inst, $2);
1154 if (p->devinfo->gen == 6) {
1155 brw_set_dest(p, brw_last_inst, brw_imm_w(0x0));
1156 brw_set_src0(p, brw_last_inst, retype(brw_null_reg(),
1157 BRW_REGISTER_TYPE_D));
1158 brw_set_src1(p, brw_last_inst, retype(brw_null_reg(),
1159 BRW_REGISTER_TYPE_D));
1160 } else if (p->devinfo->gen == 7) {
1161 brw_set_dest(p, brw_last_inst, retype(brw_null_reg(),
1162 BRW_REGISTER_TYPE_D));
1163 brw_set_src0(p, brw_last_inst, retype(brw_null_reg(),
1164 BRW_REGISTER_TYPE_D));
1165 brw_set_src1(p, brw_last_inst, brw_imm_w(0));
1167 brw_set_dest(p, brw_last_inst, retype(brw_null_reg(),
1168 BRW_REGISTER_TYPE_D));
1169 if (p->devinfo->gen < 12)
1170 brw_set_src0(p, brw_last_inst, brw_imm_d(0));
1173 | ELSE execsize relativelocation rellocation instoptions
1175 brw_next_insn(p, $1);
1176 i965_asm_set_instruction_options(p, $5);
1177 brw_inst_set_exec_size(p->devinfo, brw_last_inst, $2);
1179 brw_set_dest(p, brw_last_inst, brw_ip_reg());
1180 brw_set_src0(p, brw_last_inst, brw_ip_reg());
1181 brw_set_src1(p, brw_last_inst, brw_imm_d(0x0));
1182 brw_inst_set_gen4_jump_count(p->devinfo, brw_last_inst, $3);
1183 brw_inst_set_gen4_pop_count(p->devinfo, brw_last_inst, $4);
1185 if (!p->single_program_flow)
1186 brw_inst_set_thread_control(p->devinfo, brw_last_inst,
1189 | predicate IF execsize JUMP_LABEL jumplabel instoptions
1191 add_label(p, $4, INSTR_LABEL_JIP);
1192 add_label(p, $5, INSTR_LABEL_UIP);
1194 brw_next_insn(p, $2);
1195 i965_asm_set_instruction_options(p, $6);
1196 brw_inst_set_exec_size(p->devinfo, brw_last_inst, $3);
1198 if (p->devinfo->gen == 6) {
1199 brw_set_dest(p, brw_last_inst, brw_imm_w(0x0));
1200 brw_set_src0(p, brw_last_inst,
1201 vec1(retype(brw_null_reg(),
1202 BRW_REGISTER_TYPE_D)));
1203 brw_set_src1(p, brw_last_inst,
1204 vec1(retype(brw_null_reg(),
1205 BRW_REGISTER_TYPE_D)));
1206 } else if (p->devinfo->gen == 7) {
1207 brw_set_dest(p, brw_last_inst,
1208 vec1(retype(brw_null_reg(),
1209 BRW_REGISTER_TYPE_D)));
1210 brw_set_src0(p, brw_last_inst,
1211 vec1(retype(brw_null_reg(),
1212 BRW_REGISTER_TYPE_D)));
1213 brw_set_src1(p, brw_last_inst, brw_imm_w(0x0));
1215 brw_set_dest(p, brw_last_inst,
1216 vec1(retype(brw_null_reg(),
1217 BRW_REGISTER_TYPE_D)));
1218 if (p->devinfo->gen < 12)
1219 brw_set_src0(p, brw_last_inst, brw_imm_d(0x0));
1222 brw_pop_insn_state(p);
1224 | predicate IF execsize relativelocation rellocation instoptions
1226 brw_next_insn(p, $2);
1227 i965_asm_set_instruction_options(p, $6);
1228 brw_inst_set_exec_size(p->devinfo, brw_last_inst, $3);
1230 brw_set_dest(p, brw_last_inst, brw_ip_reg());
1231 brw_set_src0(p, brw_last_inst, brw_ip_reg());
1232 brw_set_src1(p, brw_last_inst, brw_imm_d(0x0));
1233 brw_inst_set_gen4_jump_count(p->devinfo, brw_last_inst, $4);
1234 brw_inst_set_gen4_pop_count(p->devinfo, brw_last_inst, $5);
1236 if (!p->single_program_flow)
1237 brw_inst_set_thread_control(p->devinfo, brw_last_inst,
1240 brw_pop_insn_state(p);
1242 | predicate IFF execsize JUMP_LABEL instoptions
1244 add_label(p, $4, INSTR_LABEL_JIP);
1246 brw_next_insn(p, $2);
1247 i965_asm_set_instruction_options(p, $5);
1248 brw_inst_set_exec_size(p->devinfo, brw_last_inst, $3);
1250 if (p->devinfo->gen == 6) {
1251 brw_set_src0(p, brw_last_inst,
1252 vec1(retype(brw_null_reg(),
1253 BRW_REGISTER_TYPE_D)));
1254 brw_set_src1(p, brw_last_inst,
1255 vec1(retype(brw_null_reg(),
1256 BRW_REGISTER_TYPE_D)));
1257 } else if (p->devinfo->gen == 7) {
1258 brw_set_dest(p, brw_last_inst,
1259 vec1(retype(brw_null_reg(),
1260 BRW_REGISTER_TYPE_D)));
1261 brw_set_src0(p, brw_last_inst,
1262 vec1(retype(brw_null_reg(),
1263 BRW_REGISTER_TYPE_D)));
1264 brw_set_src1(p, brw_last_inst, brw_imm_w(0x0));
1266 brw_set_dest(p, brw_last_inst,
1267 vec1(retype(brw_null_reg(),
1268 BRW_REGISTER_TYPE_D)));
1269 if (p->devinfo->gen < 12)
1270 brw_set_src0(p, brw_last_inst, brw_imm_d(0x0));
1273 brw_pop_insn_state(p);
1275 | predicate IFF execsize relativelocation instoptions
1277 brw_next_insn(p, $2);
1278 i965_asm_set_instruction_options(p, $5);
1279 brw_inst_set_exec_size(p->devinfo, brw_last_inst, $3);
1281 brw_set_dest(p, brw_last_inst, brw_ip_reg());
1282 brw_set_src0(p, brw_last_inst, brw_ip_reg());
1283 brw_inst_set_gen4_jump_count(p->devinfo, brw_last_inst, $4);
1284 brw_set_src1(p, brw_last_inst, brw_imm_d($4));
1286 if (!p->single_program_flow)
1287 brw_inst_set_thread_control(p->devinfo, brw_last_inst,
1290 brw_pop_insn_state(p);
1294 /* break instruction */
1296 predicate BREAK execsize JUMP_LABEL JUMP_LABEL instoptions
1298 add_label(p, $4, INSTR_LABEL_JIP);
1299 add_label(p, $5, INSTR_LABEL_UIP);
1301 brw_next_insn(p, $2);
1302 i965_asm_set_instruction_options(p, $6);
1303 brw_inst_set_exec_size(p->devinfo, brw_last_inst, $3);
1305 if (p->devinfo->gen >= 8) {
1306 brw_set_dest(p, brw_last_inst, retype(brw_null_reg(),
1307 BRW_REGISTER_TYPE_D));
1308 brw_set_src0(p, brw_last_inst, brw_imm_d(0x0));
1310 brw_set_dest(p, brw_last_inst, retype(brw_null_reg(),
1311 BRW_REGISTER_TYPE_D));
1312 brw_set_src0(p, brw_last_inst, retype(brw_null_reg(),
1313 BRW_REGISTER_TYPE_D));
1314 brw_set_src1(p, brw_last_inst, brw_imm_d(0x0));
1317 brw_pop_insn_state(p);
1319 | predicate BREAK execsize relativelocation relativelocation instoptions
1321 brw_next_insn(p, $2);
1322 i965_asm_set_instruction_options(p, $6);
1323 brw_inst_set_exec_size(p->devinfo, brw_last_inst, $3);
1325 brw_set_dest(p, brw_last_inst, brw_ip_reg());
1326 brw_set_src0(p, brw_last_inst, brw_ip_reg());
1327 brw_set_src1(p, brw_last_inst, brw_imm_d(0x0));
1328 brw_inst_set_gen4_jump_count(p->devinfo, brw_last_inst, $4);
1329 brw_inst_set_gen4_pop_count(p->devinfo, brw_last_inst, $5);
1331 brw_pop_insn_state(p);
1333 | predicate HALT execsize JUMP_LABEL JUMP_LABEL instoptions
1335 add_label(p, $4, INSTR_LABEL_JIP);
1336 add_label(p, $5, INSTR_LABEL_UIP);
1338 brw_next_insn(p, $2);
1339 i965_asm_set_instruction_options(p, $6);
1340 brw_inst_set_exec_size(p->devinfo, brw_last_inst, $3);
1342 brw_set_dest(p, brw_last_inst, retype(brw_null_reg(),
1343 BRW_REGISTER_TYPE_D));
1345 if (p->devinfo->gen >= 8) {
1346 brw_set_src0(p, brw_last_inst, brw_imm_d(0x0));
1348 brw_set_src0(p, brw_last_inst, retype(brw_null_reg(),
1349 BRW_REGISTER_TYPE_D));
1350 brw_set_src1(p, brw_last_inst, brw_imm_d(0x0));
1353 brw_pop_insn_state(p);
1355 | predicate CONT execsize JUMP_LABEL JUMP_LABEL instoptions
1357 add_label(p, $4, INSTR_LABEL_JIP);
1358 add_label(p, $5, INSTR_LABEL_UIP);
1360 brw_next_insn(p, $2);
1361 i965_asm_set_instruction_options(p, $6);
1362 brw_inst_set_exec_size(p->devinfo, brw_last_inst, $3);
1363 brw_set_dest(p, brw_last_inst, brw_ip_reg());
1365 if (p->devinfo->gen >= 8) {
1366 brw_set_src0(p, brw_last_inst, brw_imm_d(0x0));
1368 brw_set_src0(p, brw_last_inst, brw_ip_reg());
1369 brw_set_src1(p, brw_last_inst, brw_imm_d(0x0));
1372 brw_pop_insn_state(p);
1374 | predicate CONT execsize relativelocation relativelocation instoptions
1376 brw_next_insn(p, $2);
1377 i965_asm_set_instruction_options(p, $6);
1378 brw_inst_set_exec_size(p->devinfo, brw_last_inst, $3);
1379 brw_set_dest(p, brw_last_inst, brw_ip_reg());
1381 brw_set_src0(p, brw_last_inst, brw_ip_reg());
1382 brw_set_src1(p, brw_last_inst, brw_imm_d(0x0));
1384 brw_inst_set_gen4_jump_count(p->devinfo, brw_last_inst, $4);
1385 brw_inst_set_gen4_pop_count(p->devinfo, brw_last_inst, $5);
1387 brw_pop_insn_state(p);
1391 /* loop instruction */
1393 predicate WHILE execsize JUMP_LABEL instoptions
1395 add_label(p, $4, INSTR_LABEL_JIP);
1397 brw_next_insn(p, $2);
1398 i965_asm_set_instruction_options(p, $5);
1399 brw_inst_set_exec_size(p->devinfo, brw_last_inst, $3);
1401 if (p->devinfo->gen >= 8) {
1402 brw_set_dest(p, brw_last_inst,
1403 retype(brw_null_reg(),
1404 BRW_REGISTER_TYPE_D));
1405 brw_set_src0(p, brw_last_inst, brw_imm_d(0x0));
1406 } else if (p->devinfo->gen == 7) {
1407 brw_set_dest(p, brw_last_inst,
1408 retype(brw_null_reg(),
1409 BRW_REGISTER_TYPE_D));
1410 brw_set_src0(p, brw_last_inst,
1411 retype(brw_null_reg(),
1412 BRW_REGISTER_TYPE_D));
1413 brw_set_src1(p, brw_last_inst,
1416 brw_set_dest(p, brw_last_inst, brw_imm_w(0x0));
1417 brw_set_src0(p, brw_last_inst,
1418 retype(brw_null_reg(),
1419 BRW_REGISTER_TYPE_D));
1420 brw_set_src1(p, brw_last_inst,
1421 retype(brw_null_reg(),
1422 BRW_REGISTER_TYPE_D));
1425 brw_pop_insn_state(p);
1427 | predicate WHILE execsize relativelocation instoptions
1429 brw_next_insn(p, $2);
1430 i965_asm_set_instruction_options(p, $5);
1431 brw_inst_set_exec_size(p->devinfo, brw_last_inst, $3);
1433 brw_set_dest(p, brw_last_inst, brw_ip_reg());
1434 brw_set_src0(p, brw_last_inst, brw_ip_reg());
1435 brw_set_src1(p, brw_last_inst, brw_imm_d(0x0));
1436 brw_inst_set_gen4_jump_count(p->devinfo, brw_last_inst, $4);
1437 brw_inst_set_gen4_pop_count(p->devinfo, brw_last_inst, 0);
1439 brw_pop_insn_state(p);
1441 | DO execsize instoptions
1443 brw_next_insn(p, $1);
1444 if (p->devinfo->gen < 6) {
1445 brw_inst_set_exec_size(p->devinfo, brw_last_inst, $2);
1446 i965_asm_set_instruction_options(p, $3);
1447 brw_set_dest(p, brw_last_inst, brw_null_reg());
1448 brw_set_src0(p, brw_last_inst, brw_null_reg());
1449 brw_set_src1(p, brw_last_inst, brw_null_reg());
1451 brw_inst_set_qtr_control(p->devinfo, brw_last_inst, BRW_COMPRESSION_NONE);
1456 /* Relative location */
1463 INTEGER { $$ = $1; }
1464 | MINUS INTEGER { $$ = -$2; }
1466 | MINUS LONG { $$ = -$2; }
1471 | %empty { $$ = 0; }
1482 JUMP_LABEL { $$ = $1; }
1483 | %empty { $$ = NULL; }
1489 struct target_label *label = rzalloc(p->mem_ctx, struct target_label);
1491 label->name = ralloc_strdup(p->mem_ctx, $1);
1492 label->offset = p->next_insn_offset;
1494 list_addtail(&label->link, &target_labels);
1498 /* Destination register */
1505 dstreg dstregion writemask reg_type
1508 $$.vstride = BRW_VERTICAL_STRIDE_1;
1509 $$.width = BRW_WIDTH_1;
1513 $$.swizzle = BRW_SWIZZLE_NOOP;
1514 $$.subnr = $$.subnr * brw_reg_type_to_size($4);
1519 dstoperandex_typed dstregion writemask reg_type
1525 $$.subnr = $$.subnr * brw_reg_type_to_size($4);
1527 /* BSpec says "When the conditional modifier is present, updates
1528 * to the selected flag register also occur. In this case, the
1529 * register region fields of the ‘null’ operand are valid."
1531 | nullreg dstregion writemask reg_type
1534 $$.vstride = BRW_VERTICAL_STRIDE_1;
1535 $$.width = BRW_WIDTH_1;
1544 $$.type = BRW_REGISTER_TYPE_UW;
1565 $$.address_mode = BRW_ADDRESS_DIRECT;
1570 $$.address_mode = BRW_ADDRESS_REGISTER_INDIRECT_REGISTER;
1575 $$.address_mode = BRW_ADDRESS_DIRECT;
1580 $$.address_mode = BRW_ADDRESS_REGISTER_INDIRECT_REGISTER;
1584 /* Source register */
1594 case BRW_REGISTER_TYPE_UD:
1595 $$ = brw_imm_ud($1);
1597 case BRW_REGISTER_TYPE_D:
1600 case BRW_REGISTER_TYPE_UW:
1601 $$ = brw_imm_uw($1 | ($1 << 16));
1603 case BRW_REGISTER_TYPE_W:
1606 case BRW_REGISTER_TYPE_F:
1607 $$ = brw_imm_reg(BRW_REGISTER_TYPE_F);
1608 /* Set u64 instead of ud since DIM uses a 64-bit F-typed imm */
1611 case BRW_REGISTER_TYPE_V:
1614 case BRW_REGISTER_TYPE_UV:
1615 $$ = brw_imm_uv($1);
1617 case BRW_REGISTER_TYPE_VF:
1618 $$ = brw_imm_vf($1);
1620 case BRW_REGISTER_TYPE_Q:
1623 case BRW_REGISTER_TYPE_UQ:
1624 $$ = brw_imm_uq($1);
1626 case BRW_REGISTER_TYPE_DF:
1627 $$ = brw_imm_reg(BRW_REGISTER_TYPE_DF);
1631 error(&@2, "Unknown immediate type %s\n",
1632 brw_reg_type_to_letters($2));
1638 directgenreg region reg_type
1640 $$ = set_direct_src_operand(&$1, $3);
1641 $$ = stride($$, $2.vstride, $2.width, $2.hstride);
1651 | indirectsrcoperand
1656 | indirectsrcoperand
1661 | indirectsrcoperand
1665 directsrcaccoperand:
1667 | accreg region reg_type
1669 $$ = set_direct_src_operand(&$1, $3);
1670 $$.vstride = $2.vstride;
1671 $$.width = $2.width;
1672 $$.hstride = $2.hstride;
1677 srcarcoperandex_typed region reg_type
1679 $$ = brw_reg($1.file,
1691 | nullreg region reg_type
1693 $$ = set_direct_src_operand(&$1, $3);
1694 $$.vstride = $2.vstride;
1695 $$.width = $2.width;
1696 $$.hstride = $2.hstride;
1700 $$ = set_direct_src_operand(&$1, BRW_REGISTER_TYPE_UW);
1704 srcarcoperandex_typed:
1714 negate abs indirectgenreg indirectregion swizzle reg_type
1716 $$ = brw_reg($3.file,
1728 $$.address_mode = BRW_ADDRESS_REGISTER_INDIRECT_REGISTER;
1729 // brw_reg set indirect_offset to 0 so set it to valid value
1730 $$.indirect_offset = $3.indirect_offset;
1743 negate abs directgenreg_list region swizzle reg_type
1745 $$ = brw_reg($3.file,
1760 /* Address register */
1764 memset(&$$, '\0', sizeof($$));
1765 $$.subnr = $1.subnr;
1766 $$.indirect_offset = $2;
1771 /* Register files and register numbers */
1773 INTEGER { $$ = $1; }
1778 DOT exp { $$ = $2; }
1779 | %empty %prec SUBREGNUM { $$ = 0; }
1785 memset(&$$, '\0', sizeof($$));
1786 $$.file = BRW_GENERAL_REGISTER_FILE;
1793 GENREGFILE LSQUARE addrparam RSQUARE
1795 memset(&$$, '\0', sizeof($$));
1796 $$.file = BRW_GENERAL_REGISTER_FILE;
1797 $$.subnr = $3.subnr;
1798 $$.indirect_offset = $3.indirect_offset;
1805 $$.file = BRW_MESSAGE_REGISTER_FILE;
1812 MSGREGFILE LSQUARE addrparam RSQUARE
1814 memset(&$$, '\0', sizeof($$));
1815 $$.file = BRW_MESSAGE_REGISTER_FILE;
1816 $$.subnr = $3.subnr;
1817 $$.indirect_offset = $3.indirect_offset;
1824 int subnr = (p->devinfo->gen >= 8) ? 16 : 8;
1827 error(&@2, "Address sub register number %d"
1828 "out of range\n", $2);
1830 $$.file = BRW_ARCHITECTURE_REGISTER_FILE;
1831 $$.nr = BRW_ARF_ADDRESS;
1840 if (p->devinfo->gen < 8)
1846 error(&@1, "Accumulator register number %d"
1847 " out of range\n", $1);
1849 memset(&$$, '\0', sizeof($$));
1850 $$.file = BRW_ARCHITECTURE_REGISTER_FILE;
1851 $$.nr = BRW_ARF_ACCUMULATOR;
1859 // SNB = 1 flag reg and IVB+ = 2 flag reg
1860 int nr_reg = (p->devinfo->gen >= 7) ? 2 : 1;
1864 error(&@1, "Flag register number %d"
1865 " out of range \n", $1);
1867 error(&@2, "Flag subregister number %d"
1868 " out of range\n", $2);
1870 $$.file = BRW_ARCHITECTURE_REGISTER_FILE;
1871 $$.nr = BRW_ARF_FLAG | $1;
1880 error(&@1, "Mask register number %d"
1881 " out of range\n", $1);
1883 $$.file = BRW_ARCHITECTURE_REGISTER_FILE;
1884 $$.nr = BRW_ARF_MASK;
1892 int subnr = (p->devinfo->gen >= 11) ? 2 : 3;
1894 error(&@2, "Notification sub register number %d"
1895 " out of range\n", $2);
1897 $$.file = BRW_ARCHITECTURE_REGISTER_FILE;
1898 $$.nr = BRW_ARF_NOTIFICATION_COUNT;
1907 error(&@1, "State register number %d"
1908 " out of range\n", $1);
1911 error(&@2, "State sub register number %d"
1912 " out of range\n", $2);
1914 $$.file = BRW_ARCHITECTURE_REGISTER_FILE;
1915 $$.nr = BRW_ARF_STATE;
1921 CONTROLREG subregnum
1924 error(&@2, "control sub register number %d"
1925 " out of range\n", $2);
1927 $$.file = BRW_ARCHITECTURE_REGISTER_FILE;
1928 $$.nr = BRW_ARF_CONTROL;
1934 IPREG { $$ = brw_ip_reg(); }
1938 NULL_TOKEN { $$ = brw_null_reg(); }
1945 error(&@2, "Thread control sub register number %d"
1946 " out of range\n", $2);
1948 $$.file = BRW_ARCHITECTURE_REGISTER_FILE;
1949 $$.nr = BRW_ARF_TDR;
1955 PERFORMANCEREG subregnum
1958 if (p->devinfo->gen >= 10)
1960 else if (p->devinfo->gen <= 8)
1966 error(&@2, "Performance sub register number %d"
1967 " out of range\n", $2);
1969 $$.file = BRW_ARCHITECTURE_REGISTER_FILE;
1970 $$.nr = BRW_ARF_TIMESTAMP;
1976 CHANNELENABLEREG subregnum
1979 error(&@1, "Channel enable register number %d"
1980 " out of range\n", $1);
1982 $$.file = BRW_ARCHITECTURE_REGISTER_FILE;
1983 $$.nr = BRW_ARF_MASK;
1988 /* Immediate values */
1994 | LSQUARE exp2 COMMA exp2 COMMA exp2 COMMA exp2 RSQUARE
1996 $$ = ($2 << 0) | ($4 << 8) | ($6 << 16) | ($8 << 24);
2004 $$ = BRW_HORIZONTAL_STRIDE_1;
2008 if ($2 != 0 && ($2 > 4 || !isPowerofTwo($2)))
2009 error(&@2, "Invalid Horizontal stride %d\n", $2);
2023 $$ = stride($$, 0, 1, 0);
2027 if ($2 != 0 && ($2 > 32 || !isPowerofTwo($2)))
2028 error(&@2, "Invalid VertStride %d\n", $2);
2030 $$ = stride($$, $2, 1, 0);
2032 | LANGLE exp COMMA exp COMMA exp RANGLE
2035 if ($2 != 0 && ($2 > 32 || !isPowerofTwo($2)))
2036 error(&@2, "Invalid VertStride %d\n", $2);
2038 if ($4 > 16 || !isPowerofTwo($4))
2039 error(&@4, "Invalid width %d\n", $4);
2041 if ($6 != 0 && ($6 > 4 || !isPowerofTwo($6)))
2042 error(&@6, "Invalid Horizontal stride in"
2043 " region_wh %d\n", $6);
2045 $$ = stride($$, $2, $4, $6);
2047 | LANGLE exp SEMICOLON exp COMMA exp RANGLE
2049 if ($2 != 0 && ($2 > 32 || !isPowerofTwo($2)))
2050 error(&@2, "Invalid VertStride %d\n", $2);
2052 if ($4 > 16 || !isPowerofTwo($4))
2053 error(&@4, "Invalid width %d\n", $4);
2055 if ($6 != 0 && ($6 > 4 || !isPowerofTwo($6)))
2056 error(&@6, "Invalid Horizontal stride in"
2057 " region_wh %d\n", $6);
2059 $$ = stride($$, $2, $4, $6);
2061 | LANGLE VxH COMMA exp COMMA exp RANGLE
2063 if ($4 > 16 || !isPowerofTwo($4))
2064 error(&@4, "Invalid width %d\n", $4);
2066 if ($6 != 0 && ($6 > 4 || !isPowerofTwo($6)))
2067 error(&@6, "Invalid Horizontal stride in"
2068 " region_wh %d\n", $6);
2070 $$ = brw_VxH_indirect(0, 0);
2075 LANGLE exp COMMA exp RANGLE
2077 if ($2 > 16 || !isPowerofTwo($2))
2078 error(&@2, "Invalid width %d\n", $2);
2080 if ($4 != 0 && ($4 > 4 || !isPowerofTwo($4)))
2081 error(&@4, "Invalid Horizontal stride in"
2082 " region_wh %d\n", $4);
2084 $$ = stride($$, 0, $2, $4);
2085 $$.vstride = BRW_VERTICAL_STRIDE_ONE_DIMENSIONAL;
2090 TYPE_F { $$ = BRW_REGISTER_TYPE_F; }
2091 | TYPE_UD { $$ = BRW_REGISTER_TYPE_UD; }
2092 | TYPE_D { $$ = BRW_REGISTER_TYPE_D; }
2093 | TYPE_UW { $$ = BRW_REGISTER_TYPE_UW; }
2094 | TYPE_W { $$ = BRW_REGISTER_TYPE_W; }
2095 | TYPE_UB { $$ = BRW_REGISTER_TYPE_UB; }
2096 | TYPE_B { $$ = BRW_REGISTER_TYPE_B; }
2097 | TYPE_DF { $$ = BRW_REGISTER_TYPE_DF; }
2098 | TYPE_UQ { $$ = BRW_REGISTER_TYPE_UQ; }
2099 | TYPE_Q { $$ = BRW_REGISTER_TYPE_Q; }
2100 | TYPE_HF { $$ = BRW_REGISTER_TYPE_HF; }
2101 | TYPE_NF { $$ = BRW_REGISTER_TYPE_NF; }
2105 reg_type { $$ = $1; }
2106 | TYPE_V { $$ = BRW_REGISTER_TYPE_V; }
2107 | TYPE_VF { $$ = BRW_REGISTER_TYPE_VF; }
2108 | TYPE_UV { $$ = BRW_REGISTER_TYPE_UV; }
2114 $$ = WRITEMASK_XYZW;
2116 | DOT writemask_x writemask_y writemask_z writemask_w
2118 $$ = $2 | $3 | $4 | $5;
2124 | X { $$ = 1 << BRW_CHANNEL_X; }
2129 | Y { $$ = 1 << BRW_CHANNEL_Y; }
2134 | Z { $$ = 1 << BRW_CHANNEL_Z; }
2139 | W { $$ = 1 << BRW_CHANNEL_W; }
2145 $$ = BRW_SWIZZLE_NOOP;
2149 $$ = BRW_SWIZZLE4($2, $2, $2, $2);
2151 | DOT chansel chansel chansel chansel
2153 $$ = BRW_SWIZZLE4($2, $3, $4, $5);
2164 /* Instruction prediction and modifiers */
2168 brw_push_insn_state(p);
2169 brw_set_default_predicate_control(p, BRW_PREDICATE_NONE);
2170 brw_set_default_flag_reg(p, 0, 0);
2171 brw_set_default_predicate_inverse(p, false);
2173 | LPAREN predstate flagreg predctrl RPAREN
2175 brw_push_insn_state(p);
2176 brw_set_default_predicate_inverse(p, $2);
2177 brw_set_default_flag_reg(p, $3.nr, $3.subnr);
2178 brw_set_default_predicate_control(p, $4);
2189 %empty { $$ = BRW_PREDICATE_NORMAL; }
2190 | DOT X { $$ = BRW_PREDICATE_ALIGN16_REPLICATE_X; }
2191 | DOT Y { $$ = BRW_PREDICATE_ALIGN16_REPLICATE_Y; }
2192 | DOT Z { $$ = BRW_PREDICATE_ALIGN16_REPLICATE_Z; }
2193 | DOT W { $$ = BRW_PREDICATE_ALIGN16_REPLICATE_W; }
2208 /* Source Modification */
2219 /* Flag (Conditional) Modifier */
2223 $$.cond_modifier = $1;
2225 $$.flag_subreg_nr = 0;
2227 | condModifiers DOT flagreg
2229 $$.cond_modifier = $1;
2230 $$.flag_reg_nr = $3.nr;
2231 $$.flag_subreg_nr = $3.subnr;
2236 %empty { $$ = BRW_CONDITIONAL_NONE; }
2251 %empty { $$ = BRW_INSTRUCTION_NORMAL; }
2252 | SATURATE { $$ = BRW_INSTRUCTION_SATURATE; }
2255 /* Execution size */
2257 %empty %prec EMPTYEXECSIZE
2261 | LPAREN exp2 RPAREN
2263 if ($2 > 32 || !isPowerofTwo($2))
2264 error(&@2, "Invalid execution size %d\n", $2);
2270 /* Instruction options */
2274 memset(&$$, 0, sizeof($$));
2276 | LCURLY instoption_list RCURLY
2278 memset(&$$, 0, sizeof($$));
2284 instoption_list COMMA instoption
2286 memset(&$$, 0, sizeof($$));
2288 add_instruction_option(&$$, $3);
2290 | instoption_list instoption
2292 memset(&$$, 0, sizeof($$));
2294 add_instruction_option(&$$, $2);
2298 memset(&$$, 0, sizeof($$));
2303 ALIGN1 { $$ = ALIGN1;}
2304 | ALIGN16 { $$ = ALIGN16; }
2305 | ACCWREN { $$ = ACCWREN; }
2306 | SECHALF { $$ = SECHALF; }
2307 | COMPR { $$ = COMPR; }
2308 | COMPR4 { $$ = COMPR4; }
2309 | BREAKPOINT { $$ = BREAKPOINT; }
2310 | NODDCLR { $$ = NODDCLR; }
2311 | NODDCHK { $$ = NODDCHK; }
2312 | MASK_DISABLE { $$ = MASK_DISABLE; }
2314 | SWITCH { $$ = SWITCH; }
2315 | ATOMIC { $$ = ATOMIC; }
2316 | CMPTCTRL { $$ = CMPTCTRL; }
2317 | WECTRL { $$ = WECTRL; }
2318 | QTR_2Q { $$ = QTR_2Q; }
2319 | QTR_3Q { $$ = QTR_3Q; }
2320 | QTR_4Q { $$ = QTR_4Q; }
2321 | QTR_2H { $$ = QTR_2H; }
2322 | QTR_2N { $$ = QTR_2N; }
2323 | QTR_3N { $$ = QTR_3N; }
2324 | QTR_4N { $$ = QTR_4N; }
2325 | QTR_5N { $$ = QTR_5N; }
2326 | QTR_6N { $$ = QTR_6N; }
2327 | QTR_7N { $$ = QTR_7N; }
2328 | QTR_8N { $$ = QTR_8N; }
2333 extern int yylineno;
2338 fprintf(stderr, "%s: %d: %s at \"%s\"\n",
2339 input_filename, yylineno, msg, lex_text());