src/intel/tools/i965_gram.y

   1 %{
   2 /*
   3  * Copyright © 2018 Intel Corporation
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a
   6  * copy of this software and associated documentation files (the "Software"),
   7  * to deal in the Software without restriction, including without limitation
   8  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   9  * and/or sell copies of the Software, and to permit persons to whom the
  10  * Software is furnished to do so, subject to the following conditions:
  11  *
  12  * The above copyright notice and this permission notice (including the next
  13  * paragraph) shall be included in all copies or substantial portions of the
  14  * Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  19  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  21  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  22  * IN THE SOFTWARE.
  23  */
  24
  25 #include <stdio.h>
  26 #include <stdlib.h>
  27 #include <string.h>
  28 #include <strings.h>
  29 #include "i965_asm.h"
  30
  31 #define YYLTYPE YYLTYPE
  32 typedef struct YYLTYPE
  33 {
  34         int first_line;
  35         int first_column;
  36         int last_line;
  37         int last_column;
  38 } YYLTYPE;
  39
  40 enum message_level {
  41         WARN,
  42         ERROR,
  43 };
  44
  45 int yydebug = 1;
  46
  47 static void
  48 message(enum message_level level, YYLTYPE *location,
  49         const char *fmt, ...)
  50 {
  51         static const char *level_str[] = { "warning", "error" };
  52         va_list args;
  53
  54         if (location)
  55                 fprintf(stderr, "%s:%d:%d: %s: ", input_filename,
  56                         location->first_line,
  57                         location->first_column, level_str[level]);
  58         else
  59                 fprintf(stderr, "%s:%s: ", input_filename, level_str[level]);
  60
  61         va_start(args, fmt);
  62         vfprintf(stderr, fmt, args);
  63         va_end(args);
  64 }
  65
  66 #define warn(flag, l, fmt, ...)                                  \
  67         do {                                                     \
  68                 if (warning_flags & WARN_ ## flag)               \
  69                         message(WARN, l, fmt, ## __VA_ARGS__);   \
  70         } while (0)
  71
  72 #define error(l, fmt, ...)                                       \
  73         do {                                                     \
  74                 message(ERROR, l, fmt, ## __VA_ARGS__);          \
  75         } while (0)
  76
  77 static bool
  78 isPowerofTwo(unsigned int x)
  79 {
  80         return x && (!(x & (x - 1)));
  81 }
  82
  83 static struct brw_reg
  84 set_direct_src_operand(struct brw_reg *reg, int type)
  85 {
  86         return brw_reg(reg->file,
  87                        reg->nr,
  88                        reg->subnr,
  89                        0,               // negate
  90                        0,               // abs
  91                        type,
  92                        0,               // vstride
  93                        0,               // width
  94                        0,               // hstride
  95                        BRW_SWIZZLE_NOOP,
  96                        WRITEMASK_XYZW);
  97 }
  98
  99 static void
 100 i965_asm_unary_instruction(int opcode, struct brw_codegen *p,
 101                            struct brw_reg dest, struct brw_reg src0)
 102 {
 103         switch (opcode) {
 104         case BRW_OPCODE_BFREV:
 105                 brw_BFREV(p, dest, src0);
 106                 break;
 107         case BRW_OPCODE_CBIT:
 108                 brw_CBIT(p, dest, src0);
 109                 break;
 110         case BRW_OPCODE_F32TO16:
 111                 brw_F32TO16(p, dest, src0);
 112                 break;
 113         case BRW_OPCODE_F16TO32:
 114                 brw_F16TO32(p, dest, src0);
 115                 break;
 116         case BRW_OPCODE_MOV:
 117                 brw_MOV(p, dest, src0);
 118                 break;
 119         case BRW_OPCODE_FBL:
 120                 brw_FBL(p, dest, src0);
 121                 break;
 122         case BRW_OPCODE_FRC:
 123                 brw_FRC(p, dest, src0);
 124                 break;
 125         case BRW_OPCODE_FBH:
 126                 brw_FBH(p, dest, src0);
 127                 break;
 128         case BRW_OPCODE_NOT:
 129                 brw_NOT(p, dest, src0);
 130                 break;
 131         case BRW_OPCODE_RNDE:
 132                 brw_RNDE(p, dest, src0);
 133                 break;
 134         case BRW_OPCODE_RNDZ:
 135                 brw_RNDZ(p, dest, src0);
 136                 break;
 137         case BRW_OPCODE_RNDD:
 138                 brw_RNDD(p, dest, src0);
 139                 break;
 140         case BRW_OPCODE_LZD:
 141                 brw_LZD(p, dest, src0);
 142                 break;
 143         case BRW_OPCODE_DIM:
 144                 brw_DIM(p, dest, src0);
 145                 break;
 146         case BRW_OPCODE_RNDU:
 147                 fprintf(stderr, "Opcode BRW_OPCODE_RNDU unhandled\n");
 148                 break;
 149         default:
 150                 fprintf(stderr, "Unsupported unary opcode\n");
 151         }
 152 }
 153
 154 static void
 155 i965_asm_binary_instruction(int opcode,
 156                             struct brw_codegen *p,
 157                             struct brw_reg dest,
 158                             struct brw_reg src0,
 159                             struct brw_reg src1)
 160 {
 161         switch (opcode) {
 162         case BRW_OPCODE_ADDC:
 163                 brw_ADDC(p, dest, src0, src1);
 164                 break;
 165         case BRW_OPCODE_BFI1:
 166                 brw_BFI1(p, dest, src0, src1);
 167                 break;
 168         case BRW_OPCODE_DP2:
 169                 brw_DP2(p, dest, src0, src1);
 170                 break;
 171         case BRW_OPCODE_DP3:
 172                 brw_DP3(p, dest, src0, src1);
 173                 break;
 174         case BRW_OPCODE_DP4:
 175                 brw_DP4(p, dest, src0, src1);
 176                 break;
 177         case BRW_OPCODE_DPH:
 178                 brw_DPH(p, dest, src0, src1);
 179                 break;
 180         case BRW_OPCODE_LINE:
 181                 brw_LINE(p, dest, src0, src1);
 182                 break;
 183         case BRW_OPCODE_MAC:
 184                 brw_MAC(p, dest, src0, src1);
 185                 break;
 186         case BRW_OPCODE_MACH:
 187                 brw_MACH(p, dest, src0, src1);
 188                 break;
 189         case BRW_OPCODE_PLN:
 190                 brw_PLN(p, dest, src0, src1);
 191                 break;
 192         case BRW_OPCODE_ROL:
 193                 brw_ROL(p, dest, src0, src1);
 194                 break;
 195         case BRW_OPCODE_ROR:
 196                 brw_ROR(p, dest, src0, src1);
 197                 break;
 198         case BRW_OPCODE_SAD2:
 199                 fprintf(stderr, "Opcode BRW_OPCODE_SAD2 unhandled\n");
 200                 break;
 201         case BRW_OPCODE_SADA2:
 202                 fprintf(stderr, "Opcode BRW_OPCODE_SADA2 unhandled\n");
 203                 break;
 204         case BRW_OPCODE_SUBB:
 205                 brw_SUBB(p, dest, src0, src1);
 206                 break;
 207         case BRW_OPCODE_ADD:
 208                 brw_ADD(p, dest, src0, src1);
 209                 break;
 210         case BRW_OPCODE_CMP:
 211                 /* Third parameter is conditional modifier
 212                  * which gets updated later
 213                  */
 214                 brw_CMP(p, dest, 0, src0, src1);
 215                 break;
 216         case BRW_OPCODE_AND:
 217                 brw_AND(p, dest, src0, src1);
 218                 break;
 219         case BRW_OPCODE_ASR:
 220                 brw_ASR(p, dest, src0, src1);
 221                 break;
 222         case BRW_OPCODE_AVG:
 223                 brw_AVG(p, dest, src0, src1);
 224                 break;
 225         case BRW_OPCODE_OR:
 226                 brw_OR(p, dest, src0, src1);
 227                 break;
 228         case BRW_OPCODE_SEL:
 229                 brw_SEL(p, dest, src0, src1);
 230                 break;
 231         case BRW_OPCODE_SHL:
 232                 brw_SHL(p, dest, src0, src1);
 233                 break;
 234         case BRW_OPCODE_SHR:
 235                 brw_SHR(p, dest, src0, src1);
 236                 break;
 237         case BRW_OPCODE_XOR:
 238                 brw_XOR(p, dest, src0, src1);
 239                 break;
 240         case BRW_OPCODE_MUL:
 241                 brw_MUL(p, dest, src0, src1);
 242                 break;
 243         default:
 244                 fprintf(stderr, "Unsupported binary opcode\n");
 245         }
 246 }
 247
 248 static void
 249 i965_asm_ternary_instruction(int opcode,
 250                              struct brw_codegen *p,
 251                              struct brw_reg dest,
 252                              struct brw_reg src0,
 253                              struct brw_reg src1,
 254                              struct brw_reg src2)
 255 {
 256         switch (opcode) {
 257         case BRW_OPCODE_MAD:
 258                 brw_MAD(p, dest, src0, src1, src2);
 259                 break;
 260         case BRW_OPCODE_CSEL:
 261                 brw_CSEL(p, dest, src0, src1, src2);
 262                 break;
 263         case BRW_OPCODE_LRP:
 264                 brw_LRP(p, dest, src0, src1, src2);
 265                 break;
 266         case BRW_OPCODE_BFE:
 267                 brw_BFE(p, dest, src0, src1, src2);
 268                 break;
 269         case BRW_OPCODE_BFI2:
 270                 brw_BFI2(p, dest, src0, src1, src2);
 271                 break;
 272         default:
 273                 fprintf(stderr, "Unsupported ternary opcode\n");
 274         }
 275 }
 276
 277 static void
 278 i965_asm_set_instruction_options(struct brw_codegen *p,
 279                                  struct options options)
 280 {
 281         brw_inst_set_access_mode(p->devinfo, brw_last_inst,
 282                                  options.access_mode);
 283         brw_inst_set_mask_control(p->devinfo, brw_last_inst,
 284                                   options.mask_control);
 285         brw_inst_set_thread_control(p->devinfo, brw_last_inst,
 286                                     options.thread_control);
 287         brw_inst_set_no_dd_check(p->devinfo, brw_last_inst,
 288                                  options.no_dd_check);
 289         brw_inst_set_no_dd_clear(p->devinfo, brw_last_inst,
 290                                  options.no_dd_clear);
 291         brw_inst_set_debug_control(p->devinfo, brw_last_inst,
 292                                    options.debug_control);
 293         if (p->devinfo->gen >= 6)
 294                 brw_inst_set_acc_wr_control(p->devinfo, brw_last_inst,
 295                                             options.acc_wr_control);
 296         brw_inst_set_cmpt_control(p->devinfo, brw_last_inst,
 297                                   options.compaction);
 298 }
 299
 300 static void
 301 i965_asm_set_dst_nr(struct brw_codegen *p,
 302                     struct brw_reg *reg,
 303                     struct options options)
 304 {
 305         if (p->devinfo->gen <= 6) {
 306                 if (reg->file == BRW_MESSAGE_REGISTER_FILE &&
 307                     options.qtr_ctrl == BRW_COMPRESSION_COMPRESSED &&
 308                     !options.is_compr)
 309                         reg->nr |= BRW_MRF_COMPR4;
 310         }
 311 }
 312
 313 %}
 314
 315 %locations
 316
 317 %start ROOT
 318
 319 %union {
 320         double number;
 321         int integer;
 322         unsigned long long int llint;
 323         struct brw_reg reg;
 324         struct brw_codegen *program;
 325         struct predicate predicate;
 326         struct condition condition;
 327         struct options options;
 328         brw_inst *instruction;
 329 }
 330
 331 %token ABS
 332 %token COLON
 333 %token COMMA
 334 %token DOT
 335 %token LANGLE RANGLE
 336 %token LCURLY RCURLY
 337 %token LPAREN RPAREN
 338 %token LSQUARE RSQUARE
 339 %token PLUS MINUS
 340 %token SEMICOLON
 341
 342 /* datatypes */
 343 %token <integer> TYPE_B TYPE_UB
 344 %token <integer> TYPE_W TYPE_UW
 345 %token <integer> TYPE_D TYPE_UD
 346 %token <integer> TYPE_Q TYPE_UQ
 347 %token <integer> TYPE_V TYPE_UV
 348 %token <integer> TYPE_F TYPE_HF
 349 %token <integer> TYPE_DF TYPE_NF
 350 %token <integer> TYPE_VF
 351
 352 /* opcodes */
 353 %token <integer> ADD ADD3 ADDC AND ASR AVG
 354 %token <integer> BFE BFI1 BFI2 BFB BFREV BRC BRD BREAK
 355 %token <integer> CALL CALLA CASE CBIT CMP CMPN CONT CSEL
 356 %token <integer> DIM DO DPAS DPASW DP2 DP3 DP4 DP4A DPH
 357 %token <integer> ELSE ENDIF F16TO32 F32TO16 FBH FBL FORK FRC
 358 %token <integer> GOTO
 359 %token <integer> HALT
 360 %token <integer> IF IFF ILLEGAL
 361 %token <integer> JMPI JOIN
 362 %token <integer> LINE LRP LZD
 363 %token <integer> MAC MACH MAD MADM MOV MOVI MUL MREST MSAVE
 364 %token <integer> NENOP NOP NOT
 365 %token <integer> OR
 366 %token <integer> PLN POP PUSH
 367 %token <integer> RET RNDD RNDE RNDU RNDZ ROL ROR
 368 %token <integer> SAD2 SADA2 SEL SEND SENDC SENDS SENDSC SHL SHR SMOV SUBB SYNC
 369 %token <integer> WAIT WHILE
 370 %token <integer> XOR
 371
 372 /* extended math functions */
 373 %token <integer> COS EXP FDIV INV INVM INTDIV INTDIVMOD INTMOD LOG POW RSQ
 374 %token <integer> RSQRTM SIN SINCOS SQRT
 375
 376 /* shared functions for send */
 377 %token CONST CRE DATA DP_DATA_1 GATEWAY MATH PIXEL_INTERP READ RENDER SAMPLER
 378 %token THREAD_SPAWNER URB VME WRITE DP_SAMPLER
 379
 380 /* Conditional modifiers */
 381 %token <integer> EQUAL GREATER GREATER_EQUAL LESS LESS_EQUAL NOT_EQUAL
 382 %token <integer> NOT_ZERO OVERFLOW UNORDERED ZERO
 383
 384 /* register Access Modes */
 385 %token ALIGN1 ALIGN16
 386
 387 /* accumulator write control */
 388 %token ACCWREN
 389
 390 /* compaction control */
 391 %token CMPTCTRL
 392
 393 /* compression control */
 394 %token COMPR COMPR4 SECHALF
 395
 396 /* mask control (WeCtrl) */
 397 %token WECTRL
 398
 399 /* debug control */
 400 %token BREAKPOINT
 401
 402 /* dependency control */
 403 %token NODDCLR NODDCHK
 404
 405 /* end of thread */
 406 %token EOT
 407
 408 /* mask control */
 409 %token MASK_DISABLE;
 410
 411 /* predicate control */
 412 %token <integer> ANYV ALLV ANY2H ALL2H ANY4H ALL4H ANY8H ALL8H ANY16H ALL16H
 413 %token <integer> ANY32H ALL32H
 414
 415 /* round instructions */
 416 %token <integer> ROUND_INCREMENT
 417
 418 /* staturation */
 419 %token SATURATE
 420
 421 /* thread control */
 422 %token ATOMIC SWITCH
 423
 424 /* quater control */
 425 %token QTR_2Q QTR_3Q QTR_4Q QTR_2H QTR_2N QTR_3N QTR_4N QTR_5N
 426 %token QTR_6N QTR_7N QTR_8N
 427
 428 /* channels */
 429 %token <integer> X Y Z W
 430
 431 /* reg files */
 432 %token GENREGFILE MSGREGFILE
 433
 434 /* vertical stride in register region */
 435 %token VxH
 436
 437 /* register type */
 438 %token <integer> GENREG MSGREG ADDRREG ACCREG FLAGREG NOTIFYREG STATEREG
 439 %token <integer> CONTROLREG IPREG PERFORMANCEREG THREADREG CHANNELENABLEREG
 440 %token <integer> MASKREG
 441
 442 %token <integer> INTEGER
 443 %token <llint> LONG
 444 %token NULL_TOKEN
 445
 446 %precedence SUBREGNUM
 447 %left PLUS MINUS
 448 %precedence DOT
 449 %precedence EMPTYEXECSIZE
 450 %precedence LPAREN
 451
 452 %type <integer> execsize simple_int exp
 453 %type <llint> exp2
 454
 455 /* predicate control */
 456 %type <integer> predctrl predstate
 457 %type <predicate> predicate
 458
 459 /* conditional modifier */
 460 %type <condition> cond_mod
 461 %type <integer> condModifiers
 462
 463 /* instruction options  */
 464 %type <options> instoptions instoption_list
 465 %type <integer> instoption
 466
 467 /* writemask */
 468 %type <integer> writemask_x writemask_y writemask_z writemask_w
 469 %type <reg> writemask
 470
 471 /* dst operand */
 472 %type <reg> dst dstoperand dstoperandex dstoperandex_typed dstreg dsttype
 473 %type <reg> dstoperandex_ud_typed
 474 %type <integer> dstregion
 475
 476 %type <integer> saturate relativelocation rellocation
 477 %type <reg> relativelocation2
 478
 479 /* src operand */
 480 %type <reg> directsrcoperand directsrcaccoperand indirectsrcoperand srcacc
 481 %type <reg> srcarcoperandex srcaccimm srcarcoperandex_typed srctype srcimm
 482 %type <reg> srcarcoperandex_ud_typed srcimmtype indirectgenreg indirectregion
 483 %type <reg> immreg src reg32 payload directgenreg_list addrparam region
 484 %type <reg> region_wh swizzle directgenreg directmsgreg indirectmsgreg
 485
 486 /* registers */
 487 %type <reg> accreg addrreg channelenablereg controlreg flagreg ipreg
 488 %type <reg> notifyreg nullreg performancereg threadcontrolreg statereg maskreg
 489 %type <integer> subregnum
 490
 491 /* immediate values */
 492 %type <llint> immval
 493
 494 /* instruction opcodes */
 495 %type <integer> unaryopcodes binaryopcodes binaryaccopcodes ternaryopcodes
 496 %type <integer> sendop
 497 %type <instruction> sendopcode
 498
 499 %type <integer> negate abs chansel math_function sharedfunction
 500
 501 %code {
 502
 503 static void
 504 add_instruction_option(struct options *options, int option)
 505 {
 506         switch (option) {
 507         case ALIGN1:
 508                 options->access_mode = BRW_ALIGN_1;
 509                 break;
 510         case ALIGN16:
 511                 options->access_mode = BRW_ALIGN_16;
 512                 break;
 513         case SECHALF:
 514                 options->qtr_ctrl |= BRW_COMPRESSION_2NDHALF;
 515                 break;
 516         case COMPR:
 517                 options->qtr_ctrl |= BRW_COMPRESSION_COMPRESSED;
 518                 options->is_compr = true;
 519                 break;
 520         case COMPR4:
 521                 options->qtr_ctrl |= BRW_COMPRESSION_COMPRESSED;
 522                 break;
 523         case SWITCH:
 524                 options->thread_control |= BRW_THREAD_SWITCH;
 525                 break;
 526         case ATOMIC:
 527                 options->thread_control |= BRW_THREAD_ATOMIC;
 528                 break;
 529         case NODDCHK:
 530                 options->no_dd_check = true;
 531                 break;
 532         case NODDCLR:
 533                 options->no_dd_clear = BRW_DEPENDENCY_NOTCLEARED;
 534                 break;
 535         case MASK_DISABLE:
 536                 options->mask_control |= BRW_MASK_DISABLE;
 537                 break;
 538         case BREAKPOINT:
 539                 options->debug_control = BRW_DEBUG_BREAKPOINT;
 540                 break;
 541         case WECTRL:
 542                 options->mask_control |= BRW_WE_ALL;
 543                 break;
 544         case CMPTCTRL:
 545                 options->compaction = true;
 546                 break;
 547         case ACCWREN:
 548                 options->acc_wr_control = true;
 549                 break;
 550         case EOT:
 551                 options->end_of_thread = true;
 552                 break;
 553         /* TODO : Figure out how to set instruction group and get rid of
 554          * code below
 555          */
 556         case QTR_2Q:
 557                 options->qtr_ctrl = BRW_COMPRESSION_2NDHALF;
 558                 break;
 559         case QTR_3Q:
 560                 options->qtr_ctrl = BRW_COMPRESSION_COMPRESSED;
 561                 break;
 562         case QTR_4Q:
 563                 options->qtr_ctrl = 3;
 564                 break;
 565         case QTR_2H:
 566                 options->qtr_ctrl = BRW_COMPRESSION_COMPRESSED;
 567                 break;
 568         case QTR_2N:
 569                 options->qtr_ctrl = BRW_COMPRESSION_NONE;
 570                 options->nib_ctrl = true;
 571                 break;
 572         case QTR_3N:
 573                 options->qtr_ctrl = BRW_COMPRESSION_2NDHALF;
 574                 break;
 575         case QTR_4N:
 576                 options->qtr_ctrl = BRW_COMPRESSION_2NDHALF;
 577                 options->nib_ctrl = true;
 578                 break;
 579         case QTR_5N:
 580                 options->qtr_ctrl = BRW_COMPRESSION_COMPRESSED;
 581                 break;
 582         case QTR_6N:
 583                 options->qtr_ctrl = BRW_COMPRESSION_COMPRESSED;
 584                 options->nib_ctrl = true;
 585                 break;
 586         case QTR_7N:
 587                 options->qtr_ctrl = 3;
 588                 break;
 589         case QTR_8N:
 590                 options->qtr_ctrl = 3;
 591                 options->nib_ctrl = true;
 592                 break;
 593         }
 594 }
 595 }
 596 %%
 597
 598 ROOT:
 599         instrseq
 600         ;
 601
 602 instrseq:
 603         instrseq instruction SEMICOLON
 604         | instrseq relocatableinstruction SEMICOLON
 605         | instruction SEMICOLON
 606         | relocatableinstruction SEMICOLON
 607         ;
 608
 609 /* Instruction Group */
 610 instruction:
 611         unaryinstruction
 612         | binaryinstruction
 613         | binaryaccinstruction
 614         | mathinstruction
 615         | nopinstruction
 616         | syncinstruction
 617         | ternaryinstruction
 618         | sendinstruction
 619         | illegalinstruction
 620         ;
 621
 622 relocatableinstruction:
 623         jumpinstruction
 624         | branchinstruction
 625         | breakinstruction
 626         | loopinstruction
 627         ;
 628
 629 illegalinstruction:
 630         ILLEGAL execsize instoptions
 631         {
 632                 brw_next_insn(p, $1);
 633                 brw_inst_set_exec_size(p->devinfo, brw_last_inst, $2);
 634                 i965_asm_set_instruction_options(p, $3);
 635         }
 636         ;
 637
 638 /* Unary instruction */
 639 unaryinstruction:
 640         predicate unaryopcodes saturate cond_mod execsize dst srcaccimm instoptions
 641         {
 642                 i965_asm_set_dst_nr(p, &$6, $8);
 643                 brw_set_default_access_mode(p, $8.access_mode);
 644                 i965_asm_unary_instruction($2, p, $6, $7);
 645                 brw_pop_insn_state(p);
 646                 i965_asm_set_instruction_options(p, $8);
 647                 brw_inst_set_cond_modifier(p->devinfo, brw_last_inst,
 648                                            $4.cond_modifier);
 649
 650                 if (p->devinfo->gen >= 7) {
 651                         if ($2 != BRW_OPCODE_DIM) {
 652                                 brw_inst_set_flag_reg_nr(p->devinfo,
 653                                                          brw_last_inst,
 654                                                          $4.flag_reg_nr);
 655                                 brw_inst_set_flag_subreg_nr(p->devinfo,
 656                                                             brw_last_inst,
 657                                                             $4.flag_subreg_nr);
 658                         }
 659                 }
 660
 661                 if ($7.file != BRW_IMMEDIATE_VALUE) {
 662                         brw_inst_set_src0_vstride(p->devinfo, brw_last_inst,
 663                                                   $7.vstride);
 664                 }
 665                 brw_inst_set_saturate(p->devinfo, brw_last_inst, $3);
 666                 brw_inst_set_exec_size(p->devinfo, brw_last_inst, $5);
 667                 // TODO: set instruction group instead of qtr and nib ctrl
 668                 brw_inst_set_qtr_control(p->devinfo, brw_last_inst,
 669                                          $8.qtr_ctrl);
 670
 671                 if (p->devinfo->gen >= 7)
 672                         brw_inst_set_nib_control(p->devinfo, brw_last_inst,
 673                                                  $8.nib_ctrl);
 674         }
 675         ;
 676
 677 unaryopcodes:
 678         BFREV
 679         | CBIT
 680         | DIM
 681         | F16TO32
 682         | F32TO16
 683         | FBH
 684         | FBL
 685         | FRC
 686         | LZD
 687         | MOV
 688         | NOT
 689         | RNDD
 690         | RNDE
 691         | RNDU
 692         | RNDZ
 693         ;
 694
 695 /* Binary instruction */
 696 binaryinstruction:
 697         predicate binaryopcodes saturate cond_mod execsize dst srcimm srcimm instoptions
 698         {
 699                 i965_asm_set_dst_nr(p, &$6, $9);
 700                 brw_set_default_access_mode(p, $9.access_mode);
 701                 i965_asm_binary_instruction($2, p, $6, $7, $8);
 702                 i965_asm_set_instruction_options(p, $9);
 703                 brw_inst_set_cond_modifier(p->devinfo, brw_last_inst,
 704                                            $4.cond_modifier);
 705
 706                 if (p->devinfo->gen >= 7) {
 707                         brw_inst_set_flag_reg_nr(p->devinfo, brw_last_inst,
 708                                                  $4.flag_reg_nr);
 709                         brw_inst_set_flag_subreg_nr(p->devinfo, brw_last_inst,
 710                                                     $4.flag_subreg_nr);
 711                 }
 712
 713                 brw_inst_set_saturate(p->devinfo, brw_last_inst, $3);
 714                 brw_inst_set_exec_size(p->devinfo, brw_last_inst, $5);
 715                 // TODO: set instruction group instead of qtr and nib ctrl
 716                 brw_inst_set_qtr_control(p->devinfo, brw_last_inst,
 717                                          $9.qtr_ctrl);
 718
 719                 if (p->devinfo->gen >= 7)
 720                         brw_inst_set_nib_control(p->devinfo, brw_last_inst,
 721                                                  $9.nib_ctrl);
 722
 723                 brw_pop_insn_state(p);
 724         }
 725         ;
 726
 727 binaryopcodes:
 728         ADDC
 729         | BFI1
 730         | DP2
 731         | DP3
 732         | DP4
 733         | DPH
 734         | LINE
 735         | MAC
 736         | MACH
 737         | MUL
 738         | PLN
 739         | ROL
 740         | ROR
 741         | SAD2
 742         | SADA2
 743         | SUBB
 744         ;
 745
 746 /* Binary acc instruction */
 747 binaryaccinstruction:
 748         predicate binaryaccopcodes saturate cond_mod execsize dst srcacc srcimm instoptions
 749         {
 750                 i965_asm_set_dst_nr(p, &$6, $9);
 751                 brw_set_default_access_mode(p, $9.access_mode);
 752                 i965_asm_binary_instruction($2, p, $6, $7, $8);
 753                 brw_pop_insn_state(p);
 754                 i965_asm_set_instruction_options(p, $9);
 755                 brw_inst_set_cond_modifier(p->devinfo, brw_last_inst,
 756                                            $4.cond_modifier);
 757
 758                 if (p->devinfo->gen >= 7) {
 759                         if (!brw_inst_flag_reg_nr(p->devinfo, brw_last_inst)) {
 760                                 brw_inst_set_flag_reg_nr(p->devinfo,
 761                                                          brw_last_inst,
 762                                                          $4.flag_reg_nr);
 763                                 brw_inst_set_flag_subreg_nr(p->devinfo,
 764                                                             brw_last_inst,
 765                                                             $4.flag_subreg_nr);
 766                         }
 767                 }
 768
 769                 brw_inst_set_saturate(p->devinfo, brw_last_inst, $3);
 770                 brw_inst_set_exec_size(p->devinfo, brw_last_inst, $5);
 771                 // TODO: set instruction group instead of qtr and nib ctrl
 772                 brw_inst_set_qtr_control(p->devinfo, brw_last_inst,
 773                                          $9.qtr_ctrl);
 774
 775                 if (p->devinfo->gen >= 7)
 776                         brw_inst_set_nib_control(p->devinfo, brw_last_inst,
 777                                                  $9.nib_ctrl);
 778
 779         }
 780         ;
 781
 782 binaryaccopcodes:
 783         ADD
 784         | AND
 785         | ASR
 786         | AVG
 787         | CMP
 788         | CMPN
 789         | OR
 790         | SEL
 791         | SHL
 792         | SHR
 793         | XOR
 794         ;
 795
 796 /* Math instruction */
 797 mathinstruction:
 798         predicate MATH saturate math_function execsize dst src srcimm instoptions
 799         {
 800                 brw_set_default_access_mode(p, $9.access_mode);
 801                 gen6_math(p, $6, $4, $7, $8);
 802                 i965_asm_set_instruction_options(p, $9);
 803                 brw_inst_set_exec_size(p->devinfo, brw_last_inst, $5);
 804                 brw_inst_set_saturate(p->devinfo, brw_last_inst, $3);
 805                 // TODO: set instruction group instead
 806                 brw_inst_set_qtr_control(p->devinfo, brw_last_inst,
 807                                          $9.qtr_ctrl);
 808
 809                 if (p->devinfo->gen >= 7)
 810                         brw_inst_set_nib_control(p->devinfo, brw_last_inst,
 811                                                  $9.nib_ctrl);
 812
 813                 brw_pop_insn_state(p);
 814         }
 815         ;
 816
 817 math_function:
 818         COS
 819         | EXP
 820         | FDIV
 821         | INV
 822         | INVM
 823         | INTDIV
 824         | INTDIVMOD
 825         | INTMOD
 826         | LOG
 827         | POW
 828         | RSQ
 829         | RSQRTM
 830         | SIN
 831         | SQRT
 832         | SINCOS
 833         ;
 834
 835 /* NOP instruction */
 836 nopinstruction:
 837         NOP
 838         {
 839                 brw_NOP(p);
 840         }
 841         ;
 842
 843 /* Ternary operand instruction */
 844 ternaryinstruction:
 845         predicate ternaryopcodes saturate cond_mod execsize dst src src src instoptions
 846         {
 847                 brw_set_default_access_mode(p, $10.access_mode);
 848                 i965_asm_ternary_instruction($2, p, $6, $7, $8, $9);
 849                 brw_pop_insn_state(p);
 850                 i965_asm_set_instruction_options(p, $10);
 851                 brw_inst_set_cond_modifier(p->devinfo, brw_last_inst,
 852                                            $4.cond_modifier);
 853
 854                 if (p->devinfo->gen >= 7) {
 855                         brw_inst_set_3src_a16_flag_reg_nr(p->devinfo, brw_last_inst,
 856                                                  $4.flag_reg_nr);
 857                         brw_inst_set_3src_a16_flag_subreg_nr(p->devinfo, brw_last_inst,
 858                                                     $4.flag_subreg_nr);
 859                 }
 860
 861                 brw_inst_set_saturate(p->devinfo, brw_last_inst, $3);
 862                 brw_inst_set_exec_size(p->devinfo, brw_last_inst, $5);
 863                 // TODO: set instruction group instead of qtr and nib ctrl
 864                 brw_inst_set_qtr_control(p->devinfo, brw_last_inst,
 865                                          $10.qtr_ctrl);
 866
 867                 if (p->devinfo->gen >= 7)
 868                         brw_inst_set_nib_control(p->devinfo, brw_last_inst,
 869                                                  $10.nib_ctrl);
 870         }
 871         ;
 872
 873 ternaryopcodes:
 874         CSEL
 875         | BFE
 876         | BFI2
 877         | LRP
 878         | MAD
 879         ;
 880
 881 /* Sync instruction */
 882 syncinstruction:
 883         WAIT execsize src instoptions
 884         {
 885                 brw_next_insn(p, $1);
 886                 i965_asm_set_instruction_options(p, $4);
 887                 brw_inst_set_exec_size(p->devinfo, brw_last_inst, $2);
 888                 brw_set_default_access_mode(p, $4.access_mode);
 889                 struct brw_reg src = brw_notification_reg();
 890                 brw_set_dest(p, brw_last_inst, src);
 891                 brw_set_src0(p, brw_last_inst, src);
 892                 brw_set_src1(p, brw_last_inst, brw_null_reg());
 893                 brw_inst_set_mask_control(p->devinfo, brw_last_inst, BRW_MASK_DISABLE);
 894         }
 895         ;
 896
 897 /* Send instruction */
 898 sendinstruction:
 899         predicate sendopcode execsize dst payload exp2 sharedfunction instoptions
 900         {
 901                 i965_asm_set_instruction_options(p, $8);
 902                 brw_inst_set_exec_size(p->devinfo, brw_last_inst, $3);
 903                 brw_set_dest(p, brw_last_inst, $4);
 904                 brw_set_src0(p, brw_last_inst, $5);
 905                 brw_inst_set_bits(brw_last_inst, 127, 96, $6);
 906                 brw_inst_set_src1_file_type(p->devinfo, brw_last_inst,
 907                                             BRW_IMMEDIATE_VALUE,
 908                                             BRW_REGISTER_TYPE_UD);
 909                 brw_inst_set_sfid(p->devinfo, brw_last_inst, $7);
 910                 brw_inst_set_eot(p->devinfo, brw_last_inst, $8.end_of_thread);
 911                 // TODO: set instruction group instead of qtr and nib ctrl
 912                 brw_inst_set_qtr_control(p->devinfo, brw_last_inst,
 913                                          $8.qtr_ctrl);
 914
 915                 if (p->devinfo->gen >= 7)
 916                         brw_inst_set_nib_control(p->devinfo, brw_last_inst,
 917                                                  $8.nib_ctrl);
 918
 919                 brw_pop_insn_state(p);
 920         }
 921         | predicate sendopcode execsize exp dst payload exp2 sharedfunction instoptions
 922         {
 923                 i965_asm_set_instruction_options(p, $9);
 924                 brw_inst_set_exec_size(p->devinfo, brw_last_inst, $3);
 925                 brw_inst_set_base_mrf(p->devinfo, brw_last_inst, $4);
 926                 brw_set_dest(p, brw_last_inst, $5);
 927                 brw_set_src0(p, brw_last_inst, $6);
 928                 brw_inst_set_bits(brw_last_inst, 127, 96, $7);
 929                 brw_inst_set_src1_file_type(p->devinfo, brw_last_inst,
 930                                             BRW_IMMEDIATE_VALUE,
 931                                             BRW_REGISTER_TYPE_UD);
 932                 brw_inst_set_sfid(p->devinfo, brw_last_inst, $8);
 933                 brw_inst_set_eot(p->devinfo, brw_last_inst, $9.end_of_thread);
 934                 // TODO: set instruction group instead of qtr and nib ctrl
 935                 brw_inst_set_qtr_control(p->devinfo, brw_last_inst,
 936                                          $9.qtr_ctrl);
 937
 938                 if (p->devinfo->gen >= 7)
 939                         brw_inst_set_nib_control(p->devinfo, brw_last_inst,
 940                                                  $9.nib_ctrl);
 941
 942                 brw_pop_insn_state(p);
 943         }
 944         | predicate sendopcode execsize dst payload payload exp2 sharedfunction instoptions
 945         {
 946                 i965_asm_set_instruction_options(p, $9);
 947                 brw_inst_set_exec_size(p->devinfo, brw_last_inst, $3);
 948                 brw_set_dest(p, brw_last_inst, $4);
 949                 brw_set_src0(p, brw_last_inst, $5);
 950                 brw_inst_set_bits(brw_last_inst, 127, 96, $7);
 951                 brw_inst_set_sfid(p->devinfo, brw_last_inst, $8);
 952                 brw_inst_set_eot(p->devinfo, brw_last_inst, $9.end_of_thread);
 953                 // TODO: set instruction group instead of qtr and nib ctrl
 954                 brw_inst_set_qtr_control(p->devinfo, brw_last_inst,
 955                                          $9.qtr_ctrl);
 956
 957                 if (p->devinfo->gen >= 7)
 958                         brw_inst_set_nib_control(p->devinfo, brw_last_inst,
 959                                                  $9.nib_ctrl);
 960
 961                 brw_pop_insn_state(p);
 962         }
 963         | predicate SENDS execsize dst payload payload exp2 exp2 sharedfunction instoptions
 964         {
 965                 brw_next_insn(p, $2);
 966                 i965_asm_set_instruction_options(p, $10);
 967                 brw_inst_set_exec_size(p->devinfo, brw_last_inst, $3);
 968                 brw_set_dest(p, brw_last_inst, $4);
 969                 brw_set_src0(p, brw_last_inst, $5);
 970                 brw_set_src1(p, brw_last_inst, $6);
 971
 972                 if (brw_inst_send_sel_reg32_ex_desc(p->devinfo, brw_last_inst)) {
 973                         brw_inst_set_send_ex_desc_ia_subreg_nr(p->devinfo, brw_last_inst, $5.subnr);
 974                 } else {
 975                         brw_inst_set_sends_ex_desc(p->devinfo, brw_last_inst, $8);
 976                 }
 977
 978                 brw_inst_set_bits(brw_last_inst, 127, 96, $7);
 979                 brw_inst_set_sfid(p->devinfo, brw_last_inst, $9);
 980                 brw_inst_set_eot(p->devinfo, brw_last_inst, $10.end_of_thread);
 981                 // TODO: set instruction group instead of qtr and nib ctrl
 982                 brw_inst_set_qtr_control(p->devinfo, brw_last_inst,
 983                                          $10.qtr_ctrl);
 984
 985                 if (p->devinfo->gen >= 7)
 986                         brw_inst_set_nib_control(p->devinfo, brw_last_inst,
 987                                                  $10.nib_ctrl);
 988
 989                 brw_pop_insn_state(p);
 990         }
 991         | predicate SENDS execsize dst payload payload src exp2 sharedfunction instoptions
 992         {
 993                 brw_next_insn(p, $2);
 994                 i965_asm_set_instruction_options(p, $10);
 995                 brw_inst_set_exec_size(p->devinfo, brw_last_inst, $3);
 996                 brw_set_dest(p, brw_last_inst, $4);
 997                 brw_set_src0(p, brw_last_inst, $5);
 998                 brw_set_src1(p, brw_last_inst, $6);
 999
1000                 brw_inst_set_send_sel_reg32_desc(p->devinfo, brw_last_inst, 1);
1001                 brw_inst_set_sends_ex_desc(p->devinfo, brw_last_inst, $8);
1002
1003                 brw_inst_set_sfid(p->devinfo, brw_last_inst, $9);
1004                 brw_inst_set_eot(p->devinfo, brw_last_inst, $10.end_of_thread);
1005                 // TODO: set instruction group instead of qtr and nib ctrl
1006                 brw_inst_set_qtr_control(p->devinfo, brw_last_inst,
1007                                          $10.qtr_ctrl);
1008
1009                 if (p->devinfo->gen >= 7)
1010                         brw_inst_set_nib_control(p->devinfo, brw_last_inst,
1011                                                  $10.nib_ctrl);
1012
1013                 brw_pop_insn_state(p);
1014         }
1015         ;
1016
1017 sendop:
1018         SEND
1019         | SENDC
1020         ;
1021
1022 sendopcode:
1023         sendop   { $$ = brw_next_insn(p, $1); }
1024         ;
1025
1026 sharedfunction:
1027         NULL_TOKEN              { $$ = BRW_SFID_NULL; }
1028         | MATH                  { $$ = BRW_SFID_MATH; }
1029         | GATEWAY               { $$ = BRW_SFID_MESSAGE_GATEWAY; }
1030         | READ                  { $$ = BRW_SFID_DATAPORT_READ; }
1031         | WRITE                 { $$ = BRW_SFID_DATAPORT_WRITE; }
1032         | URB                   { $$ = BRW_SFID_URB; }
1033         | THREAD_SPAWNER        { $$ = BRW_SFID_THREAD_SPAWNER; }
1034         | VME                   { $$ = BRW_SFID_VME; }
1035         | RENDER                { $$ = GEN6_SFID_DATAPORT_RENDER_CACHE; }
1036         | CONST                 { $$ = GEN6_SFID_DATAPORT_CONSTANT_CACHE; }
1037         | DATA                  { $$ = GEN7_SFID_DATAPORT_DATA_CACHE; }
1038         | PIXEL_INTERP          { $$ = GEN7_SFID_PIXEL_INTERPOLATOR; }
1039         | DP_DATA_1             { $$ = HSW_SFID_DATAPORT_DATA_CACHE_1; }
1040         | CRE                   { $$ = HSW_SFID_CRE; }
1041         | SAMPLER               { $$ = BRW_SFID_SAMPLER; }
1042         | DP_SAMPLER            { $$ = GEN6_SFID_DATAPORT_SAMPLER_CACHE; }
1043         ;
1044
1045 exp2:
1046         LONG            { $$ = $1; }
1047         | MINUS LONG    { $$ = -$2; }
1048         ;
1049
1050 /* Jump instruction */
1051 jumpinstruction:
1052         predicate JMPI execsize relativelocation2 instoptions
1053         {
1054                 brw_next_insn(p, $2);
1055                 i965_asm_set_instruction_options(p, $5);
1056                 brw_inst_set_exec_size(p->devinfo, brw_last_inst, $3);
1057                 brw_set_dest(p, brw_last_inst, brw_ip_reg());
1058                 brw_set_src0(p, brw_last_inst, brw_ip_reg());
1059                 brw_set_src1(p, brw_last_inst, $4);
1060                 brw_inst_set_pred_control(p->devinfo, brw_last_inst,
1061                                           brw_inst_pred_control(p->devinfo,
1062                                                                 brw_last_inst));
1063                 brw_pop_insn_state(p);
1064         }
1065         ;
1066
1067 /* branch instruction */
1068 branchinstruction:
1069         predicate ENDIF execsize relativelocation instoptions
1070         {
1071                 brw_next_insn(p, $2);
1072                 i965_asm_set_instruction_options(p, $5);
1073                 brw_inst_set_exec_size(p->devinfo, brw_last_inst, $3);
1074
1075                 if (p->devinfo->gen < 6) {
1076                         brw_set_dest(p, brw_last_inst, retype(brw_null_reg(),
1077                                      BRW_REGISTER_TYPE_D));
1078                         brw_set_src0(p, brw_last_inst, retype(brw_null_reg(),
1079                                      BRW_REGISTER_TYPE_D));
1080                         brw_set_src1(p, brw_last_inst, brw_imm_d(0x0));
1081                         brw_inst_set_gen4_pop_count(p->devinfo, brw_last_inst,
1082                                                     $4);
1083                 } else if (p->devinfo->gen == 6) {
1084                         brw_set_dest(p, brw_last_inst, brw_imm_w(0x0));
1085                         brw_inst_set_gen6_jump_count(p->devinfo, brw_last_inst,
1086                                                      $4);
1087                         brw_set_src0(p, brw_last_inst, retype(brw_null_reg(),
1088                                      BRW_REGISTER_TYPE_D));
1089                         brw_set_src1(p, brw_last_inst, retype(brw_null_reg(),
1090                                      BRW_REGISTER_TYPE_D));
1091                 } else if (p->devinfo->gen == 7) {
1092                         brw_set_dest(p, brw_last_inst, retype(brw_null_reg(),
1093                                      BRW_REGISTER_TYPE_D));
1094                         brw_set_src0(p, brw_last_inst, retype(brw_null_reg(),
1095                                      BRW_REGISTER_TYPE_D));
1096                         brw_set_src1(p, brw_last_inst, brw_imm_w(0x0));
1097                         brw_inst_set_jip(p->devinfo, brw_last_inst, $4);
1098                 } else {
1099                         brw_set_src0(p, brw_last_inst, brw_imm_d($4));
1100                 }
1101
1102                 if (p->devinfo->gen < 6)
1103                         brw_inst_set_thread_control(p->devinfo, brw_last_inst,
1104                                                     BRW_THREAD_SWITCH);
1105                 brw_pop_insn_state(p);
1106         }
1107         | ELSE execsize relativelocation rellocation instoptions
1108         {
1109                 brw_next_insn(p, $1);
1110                 i965_asm_set_instruction_options(p, $5);
1111                 brw_inst_set_exec_size(p->devinfo, brw_last_inst, $2);
1112
1113                 if (p->devinfo->gen < 6) {
1114                         brw_set_dest(p, brw_last_inst, brw_ip_reg());
1115                         brw_set_src0(p, brw_last_inst, brw_ip_reg());
1116                         brw_set_src1(p, brw_last_inst, brw_imm_d(0x0));
1117                         brw_inst_set_gen4_jump_count(p->devinfo, brw_last_inst,
1118                                                      $3);
1119                         brw_inst_set_gen4_pop_count(p->devinfo, brw_last_inst,
1120                                                     $4);
1121                 } else if (p->devinfo->gen == 6) {
1122                         brw_set_dest(p, brw_last_inst, brw_imm_w(0x0));
1123                         brw_inst_set_gen6_jump_count(p->devinfo, brw_last_inst,
1124                                                      $3);
1125                         brw_set_src0(p, brw_last_inst, retype(brw_null_reg(),
1126                                      BRW_REGISTER_TYPE_D));
1127                         brw_set_src1(p, brw_last_inst, retype(brw_null_reg(),
1128                                      BRW_REGISTER_TYPE_D));
1129                 } else if (p->devinfo->gen == 7) {
1130                         brw_set_dest(p, brw_last_inst, retype(brw_null_reg(),
1131                                      BRW_REGISTER_TYPE_D));
1132                         brw_set_src0(p, brw_last_inst, retype(brw_null_reg(),
1133                                      BRW_REGISTER_TYPE_D));
1134                         brw_set_src1(p, brw_last_inst, brw_imm_w($3));
1135                         brw_inst_set_jip(p->devinfo, brw_last_inst, $3);
1136                         brw_inst_set_uip(p->devinfo, brw_last_inst, $4);
1137                 } else {
1138                         brw_set_dest(p, brw_last_inst, retype(brw_null_reg(),
1139                                      BRW_REGISTER_TYPE_D));
1140                         brw_set_src0(p, brw_last_inst, brw_imm_d($3));
1141                         brw_inst_set_jip(p->devinfo, brw_last_inst, $3);
1142                         brw_inst_set_uip(p->devinfo, brw_last_inst, $4);
1143                 }
1144
1145                 if (!p->single_program_flow && p->devinfo->gen < 6)
1146                         brw_inst_set_thread_control(p->devinfo, brw_last_inst,
1147                                                     BRW_THREAD_SWITCH);
1148         }
1149         | predicate IF execsize relativelocation rellocation instoptions
1150         {
1151                 brw_next_insn(p, $2);
1152                 i965_asm_set_instruction_options(p, $6);
1153                 brw_inst_set_exec_size(p->devinfo, brw_last_inst, $3);
1154
1155                 if (p->devinfo->gen < 6) {
1156                         brw_set_dest(p, brw_last_inst, brw_ip_reg());
1157                         brw_set_src0(p, brw_last_inst, brw_ip_reg());
1158                         brw_set_src1(p, brw_last_inst, brw_imm_d(0x0));
1159                         brw_inst_set_gen4_jump_count(p->devinfo, brw_last_inst,
1160                                                      $4);
1161                         brw_inst_set_gen4_pop_count(p->devinfo, brw_last_inst,
1162                                                     $5);
1163                 } else if (p->devinfo->gen == 6) {
1164                         brw_set_dest(p, brw_last_inst, brw_imm_w(0x0));
1165                         brw_inst_set_gen6_jump_count(p->devinfo, brw_last_inst,
1166                                                      $4);
1167                         brw_set_src0(p, brw_last_inst,
1168                                      vec1(retype(brw_null_reg(),
1169                                      BRW_REGISTER_TYPE_D)));
1170                         brw_set_src1(p, brw_last_inst,
1171                                      vec1(retype(brw_null_reg(),
1172                                      BRW_REGISTER_TYPE_D)));
1173                 } else if (p->devinfo->gen == 7) {
1174                         brw_set_dest(p, brw_last_inst,
1175                                      vec1(retype(brw_null_reg(),
1176                                      BRW_REGISTER_TYPE_D)));
1177                         brw_set_src0(p, brw_last_inst,
1178                                      vec1(retype(brw_null_reg(),
1179                                      BRW_REGISTER_TYPE_D)));
1180                         brw_set_src1(p, brw_last_inst, brw_imm_w($4));
1181                         brw_inst_set_jip(p->devinfo, brw_last_inst, $4);
1182                         brw_inst_set_uip(p->devinfo, brw_last_inst, $5);
1183                 } else {
1184                         brw_set_dest(p, brw_last_inst,
1185                                      vec1(retype(brw_null_reg(),
1186                                      BRW_REGISTER_TYPE_D)));
1187                         brw_set_src0(p, brw_last_inst, brw_imm_d($4));
1188                         brw_inst_set_jip(p->devinfo, brw_last_inst, $4);
1189                         brw_inst_set_uip(p->devinfo, brw_last_inst, $5);
1190                 }
1191
1192                 if (!p->single_program_flow && p->devinfo->gen < 6)
1193                         brw_inst_set_thread_control(p->devinfo, brw_last_inst,
1194                                                     BRW_THREAD_SWITCH);
1195
1196                 brw_pop_insn_state(p);
1197         }
1198         | predicate IFF execsize relativelocation instoptions
1199         {
1200                 brw_next_insn(p, $2);
1201                 i965_asm_set_instruction_options(p, $5);
1202                 brw_inst_set_exec_size(p->devinfo, brw_last_inst, $3);
1203
1204                 if (p->devinfo->gen < 6) {
1205                         brw_set_dest(p, brw_last_inst, brw_ip_reg());
1206                         brw_set_src0(p, brw_last_inst, brw_ip_reg());
1207                         brw_inst_set_gen4_jump_count(p->devinfo, brw_last_inst,
1208                                                      $4);
1209                         brw_set_src1(p, brw_last_inst, brw_imm_d($4));
1210                 } else if (p->devinfo->gen == 6) {
1211                         brw_set_dest(p, brw_last_inst, brw_imm_w($4));
1212                         brw_inst_set_gen6_jump_count(p->devinfo, brw_last_inst,
1213                                                      $4);
1214                         brw_set_src0(p, brw_last_inst,
1215                                      vec1(retype(brw_null_reg(),
1216                                      BRW_REGISTER_TYPE_D)));
1217                         brw_set_src1(p, brw_last_inst,
1218                                      vec1(retype(brw_null_reg(),
1219                                      BRW_REGISTER_TYPE_D)));
1220                 } else if (p->devinfo->gen == 7) {
1221                         brw_set_dest(p, brw_last_inst,
1222                                      vec1(retype(brw_null_reg(),
1223                                      BRW_REGISTER_TYPE_D)));
1224                         brw_set_src0(p, brw_last_inst,
1225                                      vec1(retype(brw_null_reg(),
1226                                      BRW_REGISTER_TYPE_D)));
1227                         brw_set_src1(p, brw_last_inst, brw_imm_w($4));
1228                         brw_inst_set_jip(p->devinfo, brw_last_inst, $4);
1229                 } else {
1230                         brw_set_dest(p, brw_last_inst,
1231                                      vec1(retype(brw_null_reg(),
1232                                      BRW_REGISTER_TYPE_D)));
1233                         brw_set_src0(p, brw_last_inst, brw_imm_d($4));
1234                         brw_inst_set_jip(p->devinfo, brw_last_inst, $4);
1235                 }
1236
1237                 if (!p->single_program_flow && p->devinfo->gen < 6)
1238                         brw_inst_set_thread_control(p->devinfo, brw_last_inst,
1239                                                     BRW_THREAD_SWITCH);
1240
1241                 brw_pop_insn_state(p);
1242         }
1243         ;
1244
1245 /* break instruction */
1246 breakinstruction:
1247         predicate BREAK execsize relativelocation relativelocation instoptions
1248         {
1249                 brw_next_insn(p, $2);
1250                 i965_asm_set_instruction_options(p, $6);
1251                 brw_inst_set_exec_size(p->devinfo, brw_last_inst, $3);
1252
1253                 if (p->devinfo->gen >= 8) {
1254                         brw_set_dest(p, brw_last_inst, retype(brw_null_reg(),
1255                                      BRW_REGISTER_TYPE_D));
1256                         brw_set_src0(p, brw_last_inst, brw_imm_d($4));
1257                         brw_inst_set_uip(p->devinfo, brw_last_inst, $5);
1258                 } else if (p->devinfo->gen >= 6) {
1259                         brw_set_dest(p, brw_last_inst, retype(brw_null_reg(),
1260                                      BRW_REGISTER_TYPE_D));
1261                         brw_set_src0(p, brw_last_inst, retype(brw_null_reg(),
1262                                      BRW_REGISTER_TYPE_D));
1263                         brw_set_src1(p, brw_last_inst, brw_imm_d(0x0));
1264                         brw_inst_set_jip(p->devinfo, brw_last_inst, $4);
1265                         brw_inst_set_uip(p->devinfo, brw_last_inst, $5);
1266                 } else {
1267                         brw_set_dest(p, brw_last_inst, brw_ip_reg());
1268                         brw_set_src0(p, brw_last_inst, brw_ip_reg());
1269                         brw_set_src1(p, brw_last_inst, brw_imm_d(0x0));
1270                         brw_inst_set_gen4_jump_count(p->devinfo, brw_last_inst,
1271                                                      $4);
1272                         brw_inst_set_gen4_pop_count(p->devinfo, brw_last_inst,
1273                                                     $5);
1274                 }
1275
1276                 brw_pop_insn_state(p);
1277         }
1278         | predicate HALT execsize relativelocation relativelocation instoptions
1279         {
1280                 brw_next_insn(p, $2);
1281                 i965_asm_set_instruction_options(p, $6);
1282                 brw_inst_set_exec_size(p->devinfo, brw_last_inst, $3);
1283                 brw_set_dest(p, brw_last_inst, retype(brw_null_reg(),
1284                              BRW_REGISTER_TYPE_D));
1285
1286                 if (p->devinfo->gen >= 8) {
1287                         brw_set_src0(p, brw_last_inst, brw_imm_d($4));
1288                         brw_inst_set_uip(p->devinfo, brw_last_inst, $5);
1289                 } else {
1290                         brw_set_src0(p, brw_last_inst, retype(brw_null_reg(),
1291                                      BRW_REGISTER_TYPE_D));
1292                         brw_set_src1(p, brw_last_inst, brw_imm_d($5));
1293                 }
1294
1295                 brw_inst_set_jip(p->devinfo, brw_last_inst, $4);
1296                 brw_inst_set_uip(p->devinfo, brw_last_inst, $5);
1297                 brw_pop_insn_state(p);
1298         }
1299         | predicate CONT execsize relativelocation relativelocation instoptions
1300         {
1301                 brw_next_insn(p, $2);
1302                 i965_asm_set_instruction_options(p, $6);
1303                 brw_inst_set_exec_size(p->devinfo, brw_last_inst, $3);
1304                 brw_set_dest(p, brw_last_inst, brw_ip_reg());
1305
1306                 if (p->devinfo->gen >= 8) {
1307                         brw_set_src0(p, brw_last_inst, brw_imm_d(0x0));
1308                         brw_inst_set_jip(p->devinfo, brw_last_inst, $4);
1309                         brw_inst_set_uip(p->devinfo, brw_last_inst, $5);
1310                 } else {
1311                         brw_set_src0(p, brw_last_inst, brw_ip_reg());
1312                         brw_set_src1(p, brw_last_inst, brw_imm_d(0x0));
1313                         if (p->devinfo->gen >= 6) {
1314                                 brw_inst_set_jip(p->devinfo, brw_last_inst, $4);
1315                                 brw_inst_set_uip(p->devinfo, brw_last_inst, $5);
1316                         } else {
1317                                 brw_inst_set_gen4_jump_count(p->devinfo, brw_last_inst,
1318                                                              $4);
1319                                 brw_inst_set_gen4_pop_count(p->devinfo, brw_last_inst,
1320                                                             $5);
1321                         }
1322                 }
1323
1324                 brw_pop_insn_state(p);
1325         }
1326         ;
1327
1328 /* loop instruction */
1329 loopinstruction:
1330         predicate WHILE execsize relativelocation instoptions
1331         {
1332                 brw_next_insn(p, $2);
1333                 i965_asm_set_instruction_options(p, $5);
1334                 brw_inst_set_exec_size(p->devinfo, brw_last_inst, $3);
1335
1336                 if (p->devinfo->gen >= 6) {
1337                         if (p->devinfo->gen >= 8) {
1338                                 brw_set_dest(p, brw_last_inst,
1339                                              retype(brw_null_reg(),
1340                                              BRW_REGISTER_TYPE_D));
1341                                 brw_set_src0(p, brw_last_inst, brw_imm_d($4));
1342                         } else if (p->devinfo->gen == 7) {
1343                                 brw_set_dest(p, brw_last_inst,
1344                                              retype(brw_null_reg(),
1345                                              BRW_REGISTER_TYPE_D));
1346                                 brw_set_src0(p, brw_last_inst,
1347                                              retype(brw_null_reg(),
1348                                              BRW_REGISTER_TYPE_D));
1349                                 brw_set_src1(p, brw_last_inst,
1350                                              brw_imm_w(0x0));
1351                                 brw_inst_set_jip(p->devinfo, brw_last_inst,
1352                                                  $4);
1353                         } else {
1354                                 brw_set_dest(p, brw_last_inst, brw_imm_w(0x0));
1355                                 brw_inst_set_gen6_jump_count(p->devinfo,
1356                                                              brw_last_inst,
1357                                                              $4);
1358                                 brw_set_src0(p, brw_last_inst,
1359                                              retype(brw_null_reg(),
1360                                              BRW_REGISTER_TYPE_D));
1361                                 brw_set_src1(p, brw_last_inst,
1362                                              retype(brw_null_reg(),
1363                                              BRW_REGISTER_TYPE_D));
1364                         }
1365                 } else {
1366                         brw_set_dest(p, brw_last_inst, brw_ip_reg());
1367                         brw_set_src0(p, brw_last_inst, brw_ip_reg());
1368                         brw_set_src1(p, brw_last_inst, brw_imm_d(0x0));
1369                         brw_inst_set_gen4_jump_count(p->devinfo, brw_last_inst,
1370                                                      $4);
1371                         brw_inst_set_gen4_pop_count(p->devinfo, brw_last_inst,
1372                                                     0);
1373                 }
1374                 brw_pop_insn_state(p);
1375         }
1376         | DO execsize instoptions
1377         {
1378                 brw_next_insn(p, $1);
1379                 if (p->devinfo->gen < 6) {
1380                         brw_inst_set_exec_size(p->devinfo, brw_last_inst, $2);
1381                         i965_asm_set_instruction_options(p, $3);
1382                         brw_set_dest(p, brw_last_inst, brw_null_reg());
1383                         brw_set_src0(p, brw_last_inst, brw_null_reg());
1384                         brw_set_src1(p, brw_last_inst, brw_null_reg());
1385
1386                         brw_inst_set_qtr_control(p->devinfo, brw_last_inst, BRW_COMPRESSION_NONE);
1387                 }
1388         }
1389         ;
1390
1391 /* Relative location */
1392 relativelocation2:
1393         immreg
1394         | reg32
1395         ;
1396
1397 simple_int:
1398         INTEGER                 { $$ = $1; }
1399         | MINUS INTEGER         { $$ = -$2; }
1400         | LONG                  { $$ = $1; }
1401         | MINUS LONG            { $$ = -$2; }
1402         ;
1403
1404 rellocation:
1405         relativelocation
1406         | %empty { $$ = 0; }
1407         ;
1408
1409 relativelocation:
1410         simple_int
1411         {
1412                 $$ = $1;
1413         }
1414         ;
1415
1416 /* Destination register */
1417 dst:
1418         dstoperand
1419         | dstoperandex
1420         ;
1421
1422 dstoperand:
1423         dstreg dstregion writemask dsttype
1424         {
1425                 $$ = $1;
1426
1427                 if ($2 == -1) {
1428                         $$.hstride = BRW_HORIZONTAL_STRIDE_1;
1429                         $$.vstride = BRW_VERTICAL_STRIDE_1;
1430                         $$.width = BRW_WIDTH_1;
1431                 } else {
1432                         $$.hstride = $2;
1433                 }
1434                 $$.type = $4.type;
1435                 $$.writemask = $3.writemask;
1436                 $$.swizzle = BRW_SWIZZLE_NOOP;
1437                 $$.subnr = $$.subnr * brw_reg_type_to_size($4.type);
1438         }
1439         ;
1440
1441 dstoperandex:
1442         dstoperandex_typed dstregion writemask dsttype
1443         {
1444                 $$ = $1;
1445                 $$.hstride = $2;
1446                 $$.type = $4.type;
1447                 $$.writemask = $3.writemask;
1448                 $$.subnr = $$.subnr * brw_reg_type_to_size($4.type);
1449         }
1450         | dstoperandex_ud_typed
1451         {
1452                 $$ = $1;
1453                 $$.hstride = 1;
1454                 $$.type = BRW_REGISTER_TYPE_UD;
1455         }
1456         /* BSpec says "When the conditional modifier is present, updates
1457          * to the selected flag register also occur. In this case, the
1458          * register region fields of the ‘null’ operand are valid."
1459          */
1460         | nullreg dstregion writemask dsttype
1461         {
1462                 $$ = $1;
1463                 if ($2 == -1) {
1464                         $$.hstride = BRW_HORIZONTAL_STRIDE_1;
1465                         $$.vstride = BRW_VERTICAL_STRIDE_1;
1466                         $$.width = BRW_WIDTH_1;
1467                 } else {
1468                         $$.hstride = $2;
1469                 }
1470                 $$.writemask = $3.writemask;
1471                 $$.type = $4.type;
1472         }
1473         | threadcontrolreg
1474         {
1475                 $$ = $1;
1476                 $$.hstride = 1;
1477                 $$.type = BRW_REGISTER_TYPE_UW;
1478         }
1479         ;
1480
1481 dstoperandex_ud_typed:
1482         controlreg
1483         | ipreg
1484         | channelenablereg
1485         | performancereg
1486         ;
1487
1488 dstoperandex_typed:
1489         accreg
1490         | flagreg
1491         | addrreg
1492         | maskreg
1493         | statereg
1494         ;
1495
1496 dstreg:
1497         directgenreg
1498         {
1499                 $$ = $1;
1500                 $$.address_mode = BRW_ADDRESS_DIRECT;
1501         }
1502         | indirectgenreg
1503         {
1504                 $$ = $1;
1505                 $$.address_mode = BRW_ADDRESS_REGISTER_INDIRECT_REGISTER;
1506         }
1507         | directmsgreg
1508         {
1509                 $$ = $1;
1510                 $$.address_mode = BRW_ADDRESS_DIRECT;
1511         }
1512         | indirectmsgreg
1513         {
1514                 $$ = $1;
1515                 $$.address_mode = BRW_ADDRESS_REGISTER_INDIRECT_REGISTER;
1516         }
1517         ;
1518
1519 /* Source register */
1520 srcaccimm:
1521         srcacc
1522         | immreg
1523         ;
1524
1525 immreg:
1526         immval srcimmtype
1527         {
1528                 uint32_t u32;
1529                 uint64_t u64;
1530                 switch ($2.type) {
1531                 case BRW_REGISTER_TYPE_UD:
1532                         u32 = $1;
1533                         $$ = brw_imm_ud(u32);
1534                         break;
1535                 case BRW_REGISTER_TYPE_D:
1536                         $$ = brw_imm_d($1);
1537                         break;
1538                 case BRW_REGISTER_TYPE_UW:
1539                         u32 = $1 | ($1 << 16);
1540                         $$ = brw_imm_uw(u32);
1541                         break;
1542                 case BRW_REGISTER_TYPE_W:
1543                         u32 = $1;
1544                         $$ = brw_imm_w(u32);
1545                         break;
1546                 case BRW_REGISTER_TYPE_F:
1547                         $$ = brw_imm_reg(BRW_REGISTER_TYPE_F);
1548                         $$.u64 = $1;
1549                         $$.ud = $1;
1550                         break;
1551                 case BRW_REGISTER_TYPE_V:
1552                         $$ = brw_imm_v($1);
1553                         break;
1554                 case BRW_REGISTER_TYPE_UV:
1555                         $$ = brw_imm_uv($1);
1556                         break;
1557                 case BRW_REGISTER_TYPE_VF:
1558                         $$ = brw_imm_reg(BRW_REGISTER_TYPE_VF);
1559                         $$.d = $1;
1560                         break;
1561                 case BRW_REGISTER_TYPE_Q:
1562                         u64 = $1;
1563                         $$ = brw_imm_q(u64);
1564                         break;
1565                 case BRW_REGISTER_TYPE_UQ:
1566                         u64 = $1;
1567                         $$ = brw_imm_uq(u64);
1568                         break;
1569                 case BRW_REGISTER_TYPE_DF:
1570                         $$ = brw_imm_reg(BRW_REGISTER_TYPE_DF);
1571                         $$.d64 = $1;
1572                         break;
1573                 default:
1574                         error(&@2, "Unkown immdediate type %s\n",
1575                               brw_reg_type_to_letters($2.type));
1576                 }
1577         }
1578         ;
1579
1580 reg32:
1581         directgenreg region srctype
1582         {
1583                 $$ = set_direct_src_operand(&$1, $3.type);
1584                 $$ = stride($$, $2.vstride, $2.width, $2.hstride);
1585         }
1586         ;
1587
1588 payload:
1589         directsrcoperand
1590         ;
1591
1592 src:
1593         directsrcoperand
1594         | indirectsrcoperand
1595         ;
1596
1597 srcacc:
1598         directsrcaccoperand
1599         | indirectsrcoperand
1600         ;
1601
1602 srcimm:
1603         directsrcoperand
1604         | indirectsrcoperand
1605         | immreg
1606         ;
1607
1608 directsrcaccoperand:
1609         directsrcoperand
1610         | accreg region srctype
1611         {
1612                 $$ = set_direct_src_operand(&$1, $3.type);
1613                 $$.vstride = $2.vstride;
1614                 $$.width = $2.width;
1615                 $$.hstride = $2.hstride;
1616         }
1617         ;
1618
1619 srcarcoperandex:
1620         srcarcoperandex_typed region srctype
1621         {
1622                 $$ = brw_reg($1.file,
1623                              $1.nr,
1624                              $1.subnr,
1625                              0,
1626                              0,
1627                              $3.type,
1628                              $2.vstride,
1629                              $2.width,
1630                              $2.hstride,
1631                              BRW_SWIZZLE_NOOP,
1632                              WRITEMASK_XYZW);
1633         }
1634         | srcarcoperandex_ud_typed
1635         {
1636                 $$ = set_direct_src_operand(&$1, BRW_REGISTER_TYPE_UD);
1637         }
1638         | nullreg region srctype
1639         {
1640                 $$ = set_direct_src_operand(&$1, $3.type);
1641                 $$.vstride = $2.vstride;
1642                 $$.width = $2.width;
1643                 $$.hstride = $2.hstride;
1644         }
1645         | threadcontrolreg
1646         {
1647                 $$ = set_direct_src_operand(&$1, BRW_REGISTER_TYPE_UW);
1648         }
1649         ;
1650
1651 srcarcoperandex_ud_typed:
1652         controlreg
1653         | statereg
1654         | ipreg
1655         | channelenablereg
1656         ;
1657
1658 srcarcoperandex_typed:
1659         flagreg
1660         | maskreg
1661         ;
1662
1663 indirectsrcoperand:
1664         negate abs indirectgenreg indirectregion swizzle srctype
1665         {
1666                 $$ = brw_reg($3.file,
1667                              0,
1668                              $3.subnr,
1669                              $1,  // negate
1670                              $2,  // abs
1671                              $6.type,
1672                              $4.vstride,
1673                              $4.width,
1674                              $4.hstride,
1675                              $5.swizzle,
1676                              WRITEMASK_X);
1677
1678                 $$.address_mode = BRW_ADDRESS_REGISTER_INDIRECT_REGISTER;
1679                 // brw_reg set indirect_offset to 0 so set it to valid value
1680                 $$.indirect_offset = $3.indirect_offset;
1681         }
1682         ;
1683
1684 directgenreg_list:
1685         directgenreg
1686         | directmsgreg
1687         | notifyreg
1688         | addrreg
1689         | performancereg
1690         ;
1691
1692 directsrcoperand:
1693         negate abs directgenreg_list region swizzle srctype
1694         {
1695                 $$ = brw_reg($3.file,
1696                              $3.nr,
1697                              $3.subnr,
1698                              $1,
1699                              $2,
1700                              $6.type,
1701                              $4.vstride,
1702                              $4.width,
1703                              $4.hstride,
1704                              $5.swizzle,
1705                              WRITEMASK_X);
1706         }
1707         | srcarcoperandex
1708         ;
1709
1710 /* Address register */
1711 addrparam:
1712         addrreg exp
1713         {
1714                 memset(&$$, '\0', sizeof($$));
1715                 $$.subnr = $1.subnr;
1716                 $$.indirect_offset = $2;
1717         }
1718         | addrreg
1719         ;
1720
1721 /* Register files and register numbers */
1722 exp:
1723         INTEGER         { $$ = $1; }
1724         | LONG          { $$ = $1; }
1725         ;
1726
1727 subregnum:
1728         DOT exp                         { $$ = $2; }
1729         | %empty %prec SUBREGNUM        { $$ = 0; }
1730         ;
1731
1732 directgenreg:
1733         GENREG subregnum
1734         {
1735                 memset(&$$, '\0', sizeof($$));
1736                 $$.file = BRW_GENERAL_REGISTER_FILE;
1737                 $$.nr = $1;
1738                 $$.subnr = $2;
1739         }
1740         ;
1741
1742 indirectgenreg:
1743         GENREGFILE LSQUARE addrparam RSQUARE
1744         {
1745                 memset(&$$, '\0', sizeof($$));
1746                 $$.file = BRW_GENERAL_REGISTER_FILE;
1747                 $$.subnr = $3.subnr;
1748                 $$.indirect_offset = $3.indirect_offset;
1749         }
1750         ;
1751
1752 directmsgreg:
1753         MSGREG subregnum
1754         {
1755                 $$ = brw_message_reg($1);
1756                 $$.subnr = $2;
1757         }
1758         ;
1759
1760 indirectmsgreg:
1761         MSGREGFILE LSQUARE addrparam RSQUARE
1762         {
1763                 memset(&$$, '\0', sizeof($$));
1764                 $$.file = BRW_MESSAGE_REGISTER_FILE;
1765                 $$.subnr = $3.subnr;
1766                 $$.indirect_offset = $3.indirect_offset;
1767         }
1768         ;
1769
1770 addrreg:
1771         ADDRREG subregnum
1772         {
1773                 if ($1 != 0)
1774                         error(&@1, "Address register number %d"
1775                                    "out of range\n", $1);
1776
1777                 int subnr = (p->devinfo->gen >= 8) ? 16 : 8;
1778
1779                 if ($2 > subnr)
1780                         error(&@2, "Address sub resgister number %d"
1781                                    "out of range\n", $2);
1782
1783                 $$ = brw_address_reg($2);
1784         }
1785         ;
1786
1787 accreg:
1788         ACCREG subregnum
1789         {
1790                 int nr_reg;
1791                 if (p->devinfo->gen < 8)
1792                         nr_reg = 2;
1793                 else
1794                         nr_reg = 10;
1795
1796                 if ($1 > nr_reg)
1797                         error(&@1, "Accumulator register number %d"
1798                                    " out of range\n", $1);
1799
1800                 memset(&$$, '\0', sizeof($$));
1801                 $$.file = BRW_ARCHITECTURE_REGISTER_FILE;
1802                 $$.nr = BRW_ARF_ACCUMULATOR;
1803                 $$.subnr = $2;
1804         }
1805         ;
1806
1807 flagreg:
1808         FLAGREG subregnum
1809         {
1810                 // SNB = 1 flag reg and IVB+ = 2 flag reg
1811                 int nr_reg = (p->devinfo->gen >= 7) ? 2 : 1;
1812                 int subnr = nr_reg;
1813
1814                 if ($1 > nr_reg)
1815                         error(&@1, "Flag register number %d"
1816                                    " out of range \n", $1);
1817                 if ($2 > subnr)
1818                         error(&@2, "Flag subregister number %d"
1819                                    " out of range\n", $2);
1820
1821                 $$.file = BRW_ARCHITECTURE_REGISTER_FILE;
1822                 $$.nr = BRW_ARF_FLAG | $1;
1823                 $$.subnr = $2;
1824         }
1825         ;
1826
1827 maskreg:
1828         MASKREG subregnum
1829         {
1830                 if ($1 > 0)
1831                         error(&@1, "Mask register number %d"
1832                                    " out of range\n", $1);
1833
1834                 $$ = brw_mask_reg($2);
1835         }
1836         ;
1837
1838 notifyreg:
1839         NOTIFYREG subregnum
1840         {
1841                 if ($1 > 0)
1842                         error(&@1, "Notification register number %d"
1843                                    " out of range\n", $1);
1844
1845                 int subnr = (p->devinfo->gen >= 11) ? 2 : 3;
1846                 if ($2 > subnr)
1847                         error(&@2, "Notification sub register number %d"
1848                                    " out of range\n", $2);
1849
1850                 $$ = brw_notification_reg();
1851                 $$.subnr = $2;
1852         }
1853         ;
1854
1855 statereg:
1856         STATEREG subregnum
1857         {
1858                 if ($1 > 2)
1859                         error(&@1, "State register number %d"
1860                                    " out of range\n", $1);
1861
1862                 if ($2 > 4)
1863                         error(&@2, "State sub register number %d"
1864                                    " out of range\n", $2);
1865
1866                 $$ = brw_sr0_reg($2);
1867                 $$.nr = $1;
1868         }
1869         ;
1870
1871 controlreg:
1872         CONTROLREG subregnum
1873         {
1874                 if ($1 > 0)
1875                         error(&@1, "Control register number %d"
1876                                    " out of range\n", $1);
1877
1878                 if ($2 > 4)
1879                         error(&@2, "control sub register number %d"
1880                                    " out of range\n", $2);
1881
1882                 $$ = brw_cr0_reg($2);
1883                 $$.nr = $1;
1884         }
1885         ;
1886
1887 ipreg:
1888         IPREG srctype   { $$ = brw_ip_reg(); }
1889         ;
1890
1891 nullreg:
1892         NULL_TOKEN      { $$ = brw_null_reg(); }
1893         ;
1894
1895 threadcontrolreg:
1896         THREADREG subregnum
1897         {
1898                 if ($1 > 0)
1899                         error(&@1, "Thread control register number %d"
1900                                    " out of range\n", $1);
1901
1902                 if ($2 > 7)
1903                         error(&@2, "Thread control sub register number %d"
1904                                    " out of range\n", $2);
1905
1906                 $$ = brw_tdr_reg();
1907                 $$.subnr = $2;
1908         }
1909         ;
1910
1911 performancereg:
1912         PERFORMANCEREG subregnum
1913         {
1914                 int subnr;
1915                 if (p->devinfo->gen >= 10)
1916                         subnr = 5;
1917                 else if (p->devinfo->gen <= 8)
1918                         subnr = 3;
1919                 else
1920                         subnr = 4;
1921
1922                 if ($2 > subnr)
1923                         error(&@2, "Performance sub register number %d"
1924                                    " out of range\n", $2);
1925
1926                 $$.file = BRW_ARCHITECTURE_REGISTER_FILE;
1927                 $$.nr = BRW_ARF_TIMESTAMP;
1928         }
1929         ;
1930
1931 channelenablereg:
1932         CHANNELENABLEREG subregnum
1933         {
1934                 if ($1 > 0)
1935                         error(&@1, "Channel enable register number %d"
1936                                    " out of range\n", $1);
1937
1938                 $$ = brw_mask_reg($2);
1939         }
1940         ;
1941
1942 /* Immediate values */
1943 immval:
1944         exp2
1945         {
1946                 $$ = $1;
1947         }
1948         | LSQUARE exp2 COMMA exp2 COMMA exp2 COMMA exp2 RSQUARE
1949         {
1950                 $$ = ($2 << 0) | ($4 << 8) | ($6 << 16) | ($8 << 24);
1951         }
1952         ;
1953
1954 /* Regions */
1955 dstregion:
1956         %empty  { $$ = -1; }
1957         | LANGLE exp RANGLE
1958         {
1959                 if ($2 != 0 && ($2 > 4 || !isPowerofTwo($2)))
1960                         error(&@2, "Invalid Horizontal stride %d\n", $2);
1961
1962                 $$ = ffs($2);
1963         }
1964         ;
1965
1966 indirectregion:
1967         region
1968         | region_wh
1969         ;
1970
1971 region:
1972         %empty
1973         {
1974                 $$ = stride($$, BRW_VERTICAL_STRIDE_1, BRW_WIDTH_2, BRW_HORIZONTAL_STRIDE_1);
1975         }
1976         | LANGLE exp RANGLE
1977         {
1978                 if ($2 != 0 && ($2 > 32 || !isPowerofTwo($2)))
1979                         error(&@2, "Invalid VertStride %d\n", $2);
1980
1981                 $$ = stride($$, $2, BRW_WIDTH_1, 0);
1982         }
1983         | LANGLE exp COMMA exp COMMA exp RANGLE
1984         {
1985
1986                 if ($2 != 0 && ($2 > 32 || !isPowerofTwo($2)))
1987                         error(&@2, "Invalid VertStride %d\n", $2);
1988
1989                 if ($4 > 16 || !isPowerofTwo($4))
1990                         error(&@4, "Invalid width %d\n", $4);
1991
1992                 if ($6 != 0 && ($6 > 4 || !isPowerofTwo($6)))
1993                         error(&@6, "Invalid Horizontal stride in"
1994                                    "  region_wh %d\n", $6);
1995
1996                 $$ = stride($$, $2, $4, $6);
1997         }
1998         | LANGLE exp SEMICOLON exp COMMA exp RANGLE
1999         {
2000                 if ($2 != 0 && ($2 > 32 || !isPowerofTwo($2)))
2001                         error(&@2, "Invalid VertStride %d\n", $2);
2002
2003                 if ($4 > 16 || !isPowerofTwo($4))
2004                         error(&@4, "Invalid width %d\n", $4);
2005
2006                 if ($6 != 0 && ($6 > 4 || !isPowerofTwo($6)))
2007                         error(&@6, "Invalid Horizontal stride in"
2008                                    " region_wh %d\n", $6);
2009
2010                 $$ = stride($$, $2, $4, $6);
2011         }
2012         | LANGLE VxH COMMA exp COMMA exp RANGLE
2013         {
2014                 if ($4 > 16 || !isPowerofTwo($4))
2015                         error(&@4, "Invalid width %d\n", $4);
2016
2017                 if ($6 != 0 && ($6 > 4 || !isPowerofTwo($6)))
2018                         error(&@6, "Invalid Horizontal stride in"
2019                                    " region_wh %d\n", $6);
2020
2021                 $$ = brw_VxH_indirect(0, 0);
2022         }
2023         ;
2024
2025 region_wh:
2026         LANGLE exp COMMA exp RANGLE
2027         {
2028                 if ($2 > 16 || !isPowerofTwo($2))
2029                         error(&@2, "Invalid width %d\n", $2);
2030
2031                 if ($4 != 0 && ($4 > 4 || !isPowerofTwo($4)))
2032                         error(&@4, "Invalid Horizontal stride in"
2033                                    " region_wh %d\n", $4);
2034
2035                 $$ = stride($$, BRW_VERTICAL_STRIDE_ONE_DIMENSIONAL, $2, $4);
2036         }
2037         ;
2038
2039 srctype:
2040         %empty          { $$ = retype($$, BRW_REGISTER_TYPE_F); }
2041         | TYPE_F        { $$ = retype($$, BRW_REGISTER_TYPE_F); }
2042         | TYPE_UD       { $$ = retype($$, BRW_REGISTER_TYPE_UD); }
2043         | TYPE_D        { $$ = retype($$, BRW_REGISTER_TYPE_D); }
2044         | TYPE_UW       { $$ = retype($$, BRW_REGISTER_TYPE_UW); }
2045         | TYPE_W        { $$ = retype($$, BRW_REGISTER_TYPE_W); }
2046         | TYPE_UB       { $$ = retype($$, BRW_REGISTER_TYPE_UB); }
2047         | TYPE_B        { $$ = retype($$, BRW_REGISTER_TYPE_B); }
2048         | TYPE_DF       { $$ = retype($$, BRW_REGISTER_TYPE_DF); }
2049         | TYPE_UQ       { $$ = retype($$, BRW_REGISTER_TYPE_UQ); }
2050         | TYPE_Q        { $$ = retype($$, BRW_REGISTER_TYPE_Q); }
2051         | TYPE_HF       { $$ = retype($$, BRW_REGISTER_TYPE_HF); }
2052         | TYPE_NF       { $$ = retype($$, BRW_REGISTER_TYPE_NF); }
2053         ;
2054
2055 srcimmtype:
2056         srctype         { $$ = $1; }
2057         | TYPE_V        { $$ = retype($$, BRW_REGISTER_TYPE_V); }
2058         | TYPE_VF       { $$ = retype($$, BRW_REGISTER_TYPE_VF); }
2059         | TYPE_UV       { $$ = retype($$, BRW_REGISTER_TYPE_UV); }
2060         ;
2061
2062 dsttype:
2063         srctype         { $$ = $1; }
2064         ;
2065
2066 writemask:
2067         %empty
2068         {
2069                 $$= brw_set_writemask($$, WRITEMASK_XYZW);
2070         }
2071         | DOT writemask_x writemask_y writemask_z writemask_w
2072         {
2073                 $$ = brw_set_writemask($$, $2 | $3 | $4 | $5);
2074         }
2075         ;
2076
2077 writemask_x:
2078         %empty  { $$ = 0; }
2079         | X     { $$ = 1 << BRW_CHANNEL_X; }
2080         ;
2081
2082 writemask_y:
2083         %empty  { $$ = 0; }
2084         | Y     { $$ = 1 << BRW_CHANNEL_Y; }
2085         ;
2086
2087 writemask_z:
2088         %empty  { $$ = 0; }
2089         | Z     { $$ = 1 << BRW_CHANNEL_Z; }
2090         ;
2091
2092 writemask_w:
2093         %empty  { $$ = 0; }
2094         | W     { $$ = 1 << BRW_CHANNEL_W; }
2095         ;
2096
2097 swizzle:
2098         %empty
2099         {
2100                 $$.swizzle = BRW_SWIZZLE_NOOP;
2101         }
2102         | DOT chansel
2103         {
2104                 $$.swizzle = BRW_SWIZZLE4($2, $2, $2, $2);
2105         }
2106         | DOT chansel chansel chansel chansel
2107         {
2108                 $$.swizzle = BRW_SWIZZLE4($2, $3, $4, $5);
2109         }
2110         ;
2111
2112 chansel:
2113         X
2114         | Y
2115         | Z
2116         | W
2117         ;
2118
2119 /* Instruction prediction and modifiers */
2120 predicate:
2121         %empty
2122         {
2123                 brw_push_insn_state(p);
2124                 brw_set_default_predicate_control(p, BRW_PREDICATE_NONE);
2125                 brw_set_default_flag_reg(p, 0, 0);
2126                 brw_set_default_predicate_inverse(p, false);
2127         }
2128         | LPAREN predstate flagreg predctrl RPAREN
2129         {
2130                 brw_push_insn_state(p);
2131                 brw_set_default_predicate_inverse(p, $2);
2132                 brw_set_default_flag_reg(p, $3.nr, $3.subnr);
2133                 brw_set_default_predicate_control(p, $4);
2134         }
2135         ;
2136
2137 predstate:
2138         %empty          { $$ = 0; }
2139         | PLUS          { $$ = 0; }
2140         | MINUS         { $$ = 1; }
2141         ;
2142
2143 predctrl:
2144         %empty          { $$ = BRW_PREDICATE_NORMAL; }
2145         | DOT X         { $$ = BRW_PREDICATE_ALIGN16_REPLICATE_X; }
2146         | DOT Y         { $$ = BRW_PREDICATE_ALIGN16_REPLICATE_Y; }
2147         | DOT Z         { $$ = BRW_PREDICATE_ALIGN16_REPLICATE_Z; }
2148         | DOT W         { $$ = BRW_PREDICATE_ALIGN16_REPLICATE_W; }
2149         | ANYV
2150         | ALLV
2151         | ANY2H
2152         | ALL2H
2153         | ANY4H
2154         | ALL4H
2155         | ANY8H
2156         | ALL8H
2157         | ANY16H
2158         | ALL16H
2159         | ANY32H
2160         | ALL32H
2161         ;
2162
2163 /* Source Modification */
2164 negate:
2165         %empty          { $$ = 0; }
2166         | MINUS         { $$ = 1; }
2167         ;
2168
2169 abs:
2170         %empty  { $$ = 0; }
2171         | ABS   { $$ = 1; }
2172         ;
2173
2174 /* Flag (Conditional) Modifier */
2175 cond_mod:
2176         condModifiers
2177         {
2178                 $$.cond_modifier = $1;
2179                 $$.flag_reg_nr = 0;
2180                 $$.flag_subreg_nr = 0;
2181         }
2182         | condModifiers DOT flagreg
2183         {
2184                 $$.cond_modifier = $1;
2185                 $$.flag_reg_nr = $3.nr;
2186                 $$.flag_subreg_nr = $3.subnr;
2187         }
2188         ;
2189
2190 condModifiers:
2191         %empty  { $$ = BRW_CONDITIONAL_NONE; }
2192         | ZERO
2193         | EQUAL
2194         | NOT_ZERO
2195         | NOT_EQUAL
2196         | GREATER
2197         | GREATER_EQUAL
2198         | LESS
2199         | LESS_EQUAL
2200         | OVERFLOW
2201         | ROUND_INCREMENT
2202         | UNORDERED
2203         ;
2204
2205 saturate:
2206         %empty          { $$ = BRW_INSTRUCTION_NORMAL; }
2207         | SATURATE      { $$ = BRW_INSTRUCTION_SATURATE; }
2208         ;
2209
2210 /* Execution size */
2211 execsize:
2212         %empty %prec EMPTYEXECSIZE
2213         {
2214                 $$ = 0;
2215         }
2216         | LPAREN exp2 RPAREN
2217         {
2218                 if ($2 > 32 || !isPowerofTwo($2))
2219                         error(&@2, "Invalid execution size %d\n", $2);
2220
2221                 $$ = cvt($2) - 1;
2222         }
2223         ;
2224
2225 /* Instruction options */
2226 instoptions:
2227         %empty
2228         {
2229                 memset(&$$, 0, sizeof($$));
2230         }
2231         | LCURLY instoption_list RCURLY
2232         {
2233                 memset(&$$, 0, sizeof($$));
2234                 $$ = $2;
2235         }
2236         ;
2237
2238 instoption_list:
2239         instoption_list COMMA instoption
2240         {
2241                 memset(&$$, 0, sizeof($$));
2242                 $$ = $1;
2243                 add_instruction_option(&$$, $3);
2244         }
2245         | instoption_list instoption
2246         {
2247                 memset(&$$, 0, sizeof($$));
2248                 $$ = $1;
2249                 add_instruction_option(&$$, $2);
2250         }
2251         | %empty
2252         {
2253                 memset(&$$, 0, sizeof($$));
2254         }
2255         ;
2256
2257 instoption:
2258         ALIGN1          { $$ = ALIGN1;}
2259         | ALIGN16       { $$ = ALIGN16; }
2260         | ACCWREN       { $$ = ACCWREN; }
2261         | SECHALF       { $$ = SECHALF; }
2262         | COMPR         { $$ = COMPR; }
2263         | COMPR4        { $$ = COMPR4; }
2264         | BREAKPOINT    { $$ = BREAKPOINT; }
2265         | NODDCLR       { $$ = NODDCLR; }
2266         | NODDCHK       { $$ = NODDCHK; }
2267         | MASK_DISABLE  { $$ = MASK_DISABLE; }
2268         | EOT           { $$ = EOT; }
2269         | SWITCH        { $$ = SWITCH; }
2270         | ATOMIC        { $$ = ATOMIC; }
2271         | CMPTCTRL      { $$ = CMPTCTRL; }
2272         | WECTRL        { $$ = WECTRL; }
2273         | QTR_2Q        { $$ = QTR_2Q; }
2274         | QTR_3Q        { $$ = QTR_3Q; }
2275         | QTR_4Q        { $$ = QTR_4Q; }
2276         | QTR_2H        { $$ = QTR_2H; }
2277         | QTR_2N        { $$ = QTR_2N; }
2278         | QTR_3N        { $$ = QTR_3N; }
2279         | QTR_4N        { $$ = QTR_4N; }
2280         | QTR_5N        { $$ = QTR_5N; }
2281         | QTR_6N        { $$ = QTR_6N; }
2282         | QTR_7N        { $$ = QTR_7N; }
2283         | QTR_8N        { $$ = QTR_8N; }
2284         ;
2285
2286 %%
2287
2288 extern int yylineno;
2289
2290 void
2291 yyerror(char *msg)
2292 {
2293         fprintf(stderr, "%s: %d: %s at \"%s\"\n",
2294                 input_filename, yylineno, msg, lex_text());
2295         ++errors;
2296 }