2 * Copyright © 2015 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
30 #include "util/mesa-sha1.h"
31 #include "util/os_time.h"
32 #include "common/gen_l3_config.h"
33 #include "common/gen_disasm.h"
34 #include "anv_private.h"
35 #include "compiler/brw_nir.h"
37 #include "nir/nir_xfb_info.h"
38 #include "spirv/nir_spirv.h"
41 /* Needed for SWIZZLE macros */
42 #include "program/prog_instruction.h"
46 VkResult
anv_CreateShaderModule(
48 const VkShaderModuleCreateInfo
* pCreateInfo
,
49 const VkAllocationCallbacks
* pAllocator
,
50 VkShaderModule
* pShaderModule
)
52 ANV_FROM_HANDLE(anv_device
, device
, _device
);
53 struct anv_shader_module
*module
;
55 assert(pCreateInfo
->sType
== VK_STRUCTURE_TYPE_SHADER_MODULE_CREATE_INFO
);
56 assert(pCreateInfo
->flags
== 0);
58 module
= vk_alloc2(&device
->alloc
, pAllocator
,
59 sizeof(*module
) + pCreateInfo
->codeSize
, 8,
60 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT
);
62 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY
);
64 module
->size
= pCreateInfo
->codeSize
;
65 memcpy(module
->data
, pCreateInfo
->pCode
, module
->size
);
67 _mesa_sha1_compute(module
->data
, module
->size
, module
->sha1
);
69 *pShaderModule
= anv_shader_module_to_handle(module
);
74 void anv_DestroyShaderModule(
76 VkShaderModule _module
,
77 const VkAllocationCallbacks
* pAllocator
)
79 ANV_FROM_HANDLE(anv_device
, device
, _device
);
80 ANV_FROM_HANDLE(anv_shader_module
, module
, _module
);
85 vk_free2(&device
->alloc
, pAllocator
, module
);
88 #define SPIR_V_MAGIC_NUMBER 0x07230203
90 struct anv_spirv_debug_data
{
91 struct anv_device
*device
;
92 const struct anv_shader_module
*module
;
95 static void anv_spirv_nir_debug(void *private_data
,
96 enum nir_spirv_debug_level level
,
100 struct anv_spirv_debug_data
*debug_data
= private_data
;
101 struct anv_instance
*instance
= debug_data
->device
->physical
->instance
;
103 static const VkDebugReportFlagsEXT vk_flags
[] = {
104 [NIR_SPIRV_DEBUG_LEVEL_INFO
] = VK_DEBUG_REPORT_INFORMATION_BIT_EXT
,
105 [NIR_SPIRV_DEBUG_LEVEL_WARNING
] = VK_DEBUG_REPORT_WARNING_BIT_EXT
,
106 [NIR_SPIRV_DEBUG_LEVEL_ERROR
] = VK_DEBUG_REPORT_ERROR_BIT_EXT
,
110 snprintf(buffer
, sizeof(buffer
), "SPIR-V offset %lu: %s", (unsigned long) spirv_offset
, message
);
112 vk_debug_report(&instance
->debug_report_callbacks
,
114 VK_DEBUG_REPORT_OBJECT_TYPE_SHADER_MODULE_EXT
,
115 (uint64_t) (uintptr_t) debug_data
->module
,
116 0, 0, "anv", buffer
);
119 /* Eventually, this will become part of anv_CreateShader. Unfortunately,
120 * we can't do that yet because we don't have the ability to copy nir.
123 anv_shader_compile_to_nir(struct anv_device
*device
,
125 const struct anv_shader_module
*module
,
126 const char *entrypoint_name
,
127 gl_shader_stage stage
,
128 const VkSpecializationInfo
*spec_info
)
130 const struct anv_physical_device
*pdevice
= device
->physical
;
131 const struct brw_compiler
*compiler
= pdevice
->compiler
;
132 const nir_shader_compiler_options
*nir_options
=
133 compiler
->glsl_compiler_options
[stage
].NirOptions
;
135 uint32_t *spirv
= (uint32_t *) module
->data
;
136 assert(spirv
[0] == SPIR_V_MAGIC_NUMBER
);
137 assert(module
->size
% 4 == 0);
139 uint32_t num_spec_entries
= 0;
140 struct nir_spirv_specialization
*spec_entries
= NULL
;
141 if (spec_info
&& spec_info
->mapEntryCount
> 0) {
142 num_spec_entries
= spec_info
->mapEntryCount
;
143 spec_entries
= malloc(num_spec_entries
* sizeof(*spec_entries
));
144 for (uint32_t i
= 0; i
< num_spec_entries
; i
++) {
145 VkSpecializationMapEntry entry
= spec_info
->pMapEntries
[i
];
146 const void *data
= spec_info
->pData
+ entry
.offset
;
147 assert(data
+ entry
.size
<= spec_info
->pData
+ spec_info
->dataSize
);
149 spec_entries
[i
].id
= spec_info
->pMapEntries
[i
].constantID
;
150 if (spec_info
->dataSize
== 8)
151 spec_entries
[i
].data64
= *(const uint64_t *)data
;
153 spec_entries
[i
].data32
= *(const uint32_t *)data
;
157 struct anv_spirv_debug_data spirv_debug_data
= {
161 struct spirv_to_nir_options spirv_options
= {
162 .frag_coord_is_sysval
= true,
164 .demote_to_helper_invocation
= true,
165 .derivative_group
= true,
166 .descriptor_array_dynamic_indexing
= true,
167 .descriptor_array_non_uniform_indexing
= true,
168 .descriptor_indexing
= true,
169 .device_group
= true,
170 .draw_parameters
= true,
171 .float16
= pdevice
->info
.gen
>= 8,
172 .float64
= pdevice
->info
.gen
>= 8,
173 .fragment_shader_sample_interlock
= pdevice
->info
.gen
>= 9,
174 .fragment_shader_pixel_interlock
= pdevice
->info
.gen
>= 9,
175 .geometry_streams
= true,
176 .image_write_without_format
= true,
177 .int8
= pdevice
->info
.gen
>= 8,
178 .int16
= pdevice
->info
.gen
>= 8,
179 .int64
= pdevice
->info
.gen
>= 8,
180 .int64_atomics
= pdevice
->info
.gen
>= 9 && pdevice
->use_softpin
,
181 .integer_functions2
= pdevice
->info
.gen
>= 8,
184 .physical_storage_buffer_address
= pdevice
->has_a64_buffer_access
,
185 .post_depth_coverage
= pdevice
->info
.gen
>= 9,
186 .runtime_descriptor_array
= true,
187 .float_controls
= pdevice
->info
.gen
>= 8,
188 .shader_clock
= true,
189 .shader_viewport_index_layer
= true,
190 .stencil_export
= pdevice
->info
.gen
>= 9,
191 .storage_8bit
= pdevice
->info
.gen
>= 8,
192 .storage_16bit
= pdevice
->info
.gen
>= 8,
193 .subgroup_arithmetic
= true,
194 .subgroup_basic
= true,
195 .subgroup_ballot
= true,
196 .subgroup_quad
= true,
197 .subgroup_shuffle
= true,
198 .subgroup_vote
= true,
199 .tessellation
= true,
200 .transform_feedback
= pdevice
->info
.gen
>= 8,
201 .variable_pointers
= true,
202 .vk_memory_model
= true,
203 .vk_memory_model_device_scope
= true,
205 .ubo_addr_format
= nir_address_format_32bit_index_offset
,
207 anv_nir_ssbo_addr_format(pdevice
, device
->robust_buffer_access
),
208 .phys_ssbo_addr_format
= nir_address_format_64bit_global
,
209 .push_const_addr_format
= nir_address_format_logical
,
211 /* TODO: Consider changing this to an address format that has the NULL
212 * pointer equals to 0. That might be a better format to play nice
213 * with certain code / code generators.
215 .shared_addr_format
= nir_address_format_32bit_offset
,
217 .func
= anv_spirv_nir_debug
,
218 .private_data
= &spirv_debug_data
,
224 spirv_to_nir(spirv
, module
->size
/ 4,
225 spec_entries
, num_spec_entries
,
226 stage
, entrypoint_name
, &spirv_options
, nir_options
);
227 assert(nir
->info
.stage
== stage
);
228 nir_validate_shader(nir
, "after spirv_to_nir");
229 ralloc_steal(mem_ctx
, nir
);
233 if (unlikely(INTEL_DEBUG
& intel_debug_flag_for_shader_stage(stage
))) {
234 fprintf(stderr
, "NIR (from SPIR-V) for %s shader:\n",
235 gl_shader_stage_name(stage
));
236 nir_print_shader(nir
, stderr
);
239 /* We have to lower away local constant initializers right before we
240 * inline functions. That way they get properly initialized at the top
241 * of the function and not at the top of its caller.
243 NIR_PASS_V(nir
, nir_lower_variable_initializers
, nir_var_function_temp
);
244 NIR_PASS_V(nir
, nir_lower_returns
);
245 NIR_PASS_V(nir
, nir_inline_functions
);
246 NIR_PASS_V(nir
, nir_opt_deref
);
248 /* Pick off the single entrypoint that we want */
249 foreach_list_typed_safe(nir_function
, func
, node
, &nir
->functions
) {
250 if (!func
->is_entrypoint
)
251 exec_node_remove(&func
->node
);
253 assert(exec_list_length(&nir
->functions
) == 1);
255 /* Now that we've deleted all but the main function, we can go ahead and
256 * lower the rest of the constant initializers. We do this here so that
257 * nir_remove_dead_variables and split_per_member_structs below see the
258 * corresponding stores.
260 NIR_PASS_V(nir
, nir_lower_variable_initializers
, ~0);
262 /* Split member structs. We do this before lower_io_to_temporaries so that
263 * it doesn't lower system values to temporaries by accident.
265 NIR_PASS_V(nir
, nir_split_var_copies
);
266 NIR_PASS_V(nir
, nir_split_per_member_structs
);
268 NIR_PASS_V(nir
, nir_remove_dead_variables
,
269 nir_var_shader_in
| nir_var_shader_out
| nir_var_system_value
);
271 NIR_PASS_V(nir
, nir_propagate_invariant
);
272 NIR_PASS_V(nir
, nir_lower_io_to_temporaries
,
273 nir_shader_get_entrypoint(nir
), true, false);
275 NIR_PASS_V(nir
, nir_lower_frexp
);
277 /* Vulkan uses the separate-shader linking model */
278 nir
->info
.separate_shader
= true;
280 brw_preprocess_nir(compiler
, nir
, NULL
);
285 void anv_DestroyPipeline(
287 VkPipeline _pipeline
,
288 const VkAllocationCallbacks
* pAllocator
)
290 ANV_FROM_HANDLE(anv_device
, device
, _device
);
291 ANV_FROM_HANDLE(anv_pipeline
, pipeline
, _pipeline
);
296 anv_reloc_list_finish(&pipeline
->batch_relocs
,
297 pAllocator
? pAllocator
: &device
->alloc
);
299 ralloc_free(pipeline
->mem_ctx
);
301 if (pipeline
->blend_state
.map
)
302 anv_state_pool_free(&device
->dynamic_state_pool
, pipeline
->blend_state
);
304 switch (pipeline
->type
) {
305 case ANV_PIPELINE_GRAPHICS
:
306 for (unsigned s
= 0; s
< MESA_SHADER_STAGES
; s
++) {
307 if (pipeline
->shaders
[s
])
308 anv_shader_bin_unref(device
, pipeline
->shaders
[s
]);
312 case ANV_PIPELINE_COMPUTE
:
314 anv_shader_bin_unref(device
, pipeline
->cs
);
318 unreachable("invalid pipeline type");
321 vk_free2(&device
->alloc
, pAllocator
, pipeline
);
324 static const uint32_t vk_to_gen_primitive_type
[] = {
325 [VK_PRIMITIVE_TOPOLOGY_POINT_LIST
] = _3DPRIM_POINTLIST
,
326 [VK_PRIMITIVE_TOPOLOGY_LINE_LIST
] = _3DPRIM_LINELIST
,
327 [VK_PRIMITIVE_TOPOLOGY_LINE_STRIP
] = _3DPRIM_LINESTRIP
,
328 [VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST
] = _3DPRIM_TRILIST
,
329 [VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP
] = _3DPRIM_TRISTRIP
,
330 [VK_PRIMITIVE_TOPOLOGY_TRIANGLE_FAN
] = _3DPRIM_TRIFAN
,
331 [VK_PRIMITIVE_TOPOLOGY_LINE_LIST_WITH_ADJACENCY
] = _3DPRIM_LINELIST_ADJ
,
332 [VK_PRIMITIVE_TOPOLOGY_LINE_STRIP_WITH_ADJACENCY
] = _3DPRIM_LINESTRIP_ADJ
,
333 [VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST_WITH_ADJACENCY
] = _3DPRIM_TRILIST_ADJ
,
334 [VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP_WITH_ADJACENCY
] = _3DPRIM_TRISTRIP_ADJ
,
338 populate_sampler_prog_key(const struct gen_device_info
*devinfo
,
339 struct brw_sampler_prog_key_data
*key
)
341 /* Almost all multisampled textures are compressed. The only time when we
342 * don't compress a multisampled texture is for 16x MSAA with a surface
343 * width greater than 8k which is a bit of an edge case. Since the sampler
344 * just ignores the MCS parameter to ld2ms when MCS is disabled, it's safe
345 * to tell the compiler to always assume compression.
347 key
->compressed_multisample_layout_mask
= ~0;
349 /* SkyLake added support for 16x MSAA. With this came a new message for
350 * reading from a 16x MSAA surface with compression. The new message was
351 * needed because now the MCS data is 64 bits instead of 32 or lower as is
352 * the case for 8x, 4x, and 2x. The key->msaa_16 bit-field controls which
353 * message we use. Fortunately, the 16x message works for 8x, 4x, and 2x
354 * so we can just use it unconditionally. This may not be quite as
355 * efficient but it saves us from recompiling.
357 if (devinfo
->gen
>= 9)
360 /* XXX: Handle texture swizzle on HSW- */
361 for (int i
= 0; i
< MAX_SAMPLERS
; i
++) {
362 /* Assume color sampler, no swizzling. (Works for BDW+) */
363 key
->swizzles
[i
] = SWIZZLE_XYZW
;
368 populate_base_prog_key(const struct gen_device_info
*devinfo
,
369 VkPipelineShaderStageCreateFlags flags
,
370 struct brw_base_prog_key
*key
)
372 if (flags
& VK_PIPELINE_SHADER_STAGE_CREATE_ALLOW_VARYING_SUBGROUP_SIZE_BIT_EXT
)
373 key
->subgroup_size_type
= BRW_SUBGROUP_SIZE_VARYING
;
375 key
->subgroup_size_type
= BRW_SUBGROUP_SIZE_API_CONSTANT
;
377 populate_sampler_prog_key(devinfo
, &key
->tex
);
381 populate_vs_prog_key(const struct gen_device_info
*devinfo
,
382 VkPipelineShaderStageCreateFlags flags
,
383 struct brw_vs_prog_key
*key
)
385 memset(key
, 0, sizeof(*key
));
387 populate_base_prog_key(devinfo
, flags
, &key
->base
);
389 /* XXX: Handle vertex input work-arounds */
391 /* XXX: Handle sampler_prog_key */
395 populate_tcs_prog_key(const struct gen_device_info
*devinfo
,
396 VkPipelineShaderStageCreateFlags flags
,
397 unsigned input_vertices
,
398 struct brw_tcs_prog_key
*key
)
400 memset(key
, 0, sizeof(*key
));
402 populate_base_prog_key(devinfo
, flags
, &key
->base
);
404 key
->input_vertices
= input_vertices
;
408 populate_tes_prog_key(const struct gen_device_info
*devinfo
,
409 VkPipelineShaderStageCreateFlags flags
,
410 struct brw_tes_prog_key
*key
)
412 memset(key
, 0, sizeof(*key
));
414 populate_base_prog_key(devinfo
, flags
, &key
->base
);
418 populate_gs_prog_key(const struct gen_device_info
*devinfo
,
419 VkPipelineShaderStageCreateFlags flags
,
420 struct brw_gs_prog_key
*key
)
422 memset(key
, 0, sizeof(*key
));
424 populate_base_prog_key(devinfo
, flags
, &key
->base
);
428 populate_wm_prog_key(const struct gen_device_info
*devinfo
,
429 VkPipelineShaderStageCreateFlags flags
,
430 const struct anv_subpass
*subpass
,
431 const VkPipelineMultisampleStateCreateInfo
*ms_info
,
432 struct brw_wm_prog_key
*key
)
434 memset(key
, 0, sizeof(*key
));
436 populate_base_prog_key(devinfo
, flags
, &key
->base
);
438 /* We set this to 0 here and set to the actual value before we call
441 key
->input_slots_valid
= 0;
443 /* Vulkan doesn't specify a default */
444 key
->high_quality_derivatives
= false;
446 /* XXX Vulkan doesn't appear to specify */
447 key
->clamp_fragment_color
= false;
449 assert(subpass
->color_count
<= MAX_RTS
);
450 for (uint32_t i
= 0; i
< subpass
->color_count
; i
++) {
451 if (subpass
->color_attachments
[i
].attachment
!= VK_ATTACHMENT_UNUSED
)
452 key
->color_outputs_valid
|= (1 << i
);
455 key
->nr_color_regions
= subpass
->color_count
;
457 /* To reduce possible shader recompilations we would need to know if
458 * there is a SampleMask output variable to compute if we should emit
459 * code to workaround the issue that hardware disables alpha to coverage
460 * when there is SampleMask output.
462 key
->alpha_to_coverage
= ms_info
&& ms_info
->alphaToCoverageEnable
;
464 /* Vulkan doesn't support fixed-function alpha test */
465 key
->alpha_test_replicate_alpha
= false;
468 /* We should probably pull this out of the shader, but it's fairly
469 * harmless to compute it and then let dead-code take care of it.
471 if (ms_info
->rasterizationSamples
> 1) {
472 key
->persample_interp
= ms_info
->sampleShadingEnable
&&
473 (ms_info
->minSampleShading
* ms_info
->rasterizationSamples
) > 1;
474 key
->multisample_fbo
= true;
477 key
->frag_coord_adds_sample_pos
= key
->persample_interp
;
482 populate_cs_prog_key(const struct gen_device_info
*devinfo
,
483 VkPipelineShaderStageCreateFlags flags
,
484 const VkPipelineShaderStageRequiredSubgroupSizeCreateInfoEXT
*rss_info
,
485 struct brw_cs_prog_key
*key
)
487 memset(key
, 0, sizeof(*key
));
489 populate_base_prog_key(devinfo
, flags
, &key
->base
);
492 assert(key
->base
.subgroup_size_type
!= BRW_SUBGROUP_SIZE_VARYING
);
494 /* These enum values are expressly chosen to be equal to the subgroup
495 * size that they require.
497 assert(rss_info
->requiredSubgroupSize
== 8 ||
498 rss_info
->requiredSubgroupSize
== 16 ||
499 rss_info
->requiredSubgroupSize
== 32);
500 key
->base
.subgroup_size_type
= rss_info
->requiredSubgroupSize
;
501 } else if (flags
& VK_PIPELINE_SHADER_STAGE_CREATE_REQUIRE_FULL_SUBGROUPS_BIT_EXT
) {
502 /* If the client expressly requests full subgroups and they don't
503 * specify a subgroup size, we need to pick one. If they're requested
504 * varying subgroup sizes, we set it to UNIFORM and let the back-end
505 * compiler pick. Otherwise, we specify the API value of 32.
506 * Performance will likely be terrible in this case but there's nothing
507 * we can do about that. The client should have chosen a size.
509 if (flags
& VK_PIPELINE_SHADER_STAGE_CREATE_ALLOW_VARYING_SUBGROUP_SIZE_BIT_EXT
)
510 key
->base
.subgroup_size_type
= BRW_SUBGROUP_SIZE_UNIFORM
;
512 key
->base
.subgroup_size_type
= BRW_SUBGROUP_SIZE_REQUIRE_32
;
516 struct anv_pipeline_stage
{
517 gl_shader_stage stage
;
519 const struct anv_shader_module
*module
;
520 const char *entrypoint
;
521 const VkSpecializationInfo
*spec_info
;
523 unsigned char shader_sha1
[20];
525 union brw_any_prog_key key
;
528 gl_shader_stage stage
;
529 unsigned char sha1
[20];
534 struct anv_pipeline_binding surface_to_descriptor
[256];
535 struct anv_pipeline_binding sampler_to_descriptor
[256];
536 struct anv_pipeline_bind_map bind_map
;
538 union brw_any_prog_data prog_data
;
541 struct brw_compile_stats stats
[3];
544 VkPipelineCreationFeedbackEXT feedback
;
546 const unsigned *code
;
550 anv_pipeline_hash_shader(const struct anv_shader_module
*module
,
551 const char *entrypoint
,
552 gl_shader_stage stage
,
553 const VkSpecializationInfo
*spec_info
,
554 unsigned char *sha1_out
)
556 struct mesa_sha1 ctx
;
557 _mesa_sha1_init(&ctx
);
559 _mesa_sha1_update(&ctx
, module
->sha1
, sizeof(module
->sha1
));
560 _mesa_sha1_update(&ctx
, entrypoint
, strlen(entrypoint
));
561 _mesa_sha1_update(&ctx
, &stage
, sizeof(stage
));
563 _mesa_sha1_update(&ctx
, spec_info
->pMapEntries
,
564 spec_info
->mapEntryCount
*
565 sizeof(*spec_info
->pMapEntries
));
566 _mesa_sha1_update(&ctx
, spec_info
->pData
,
567 spec_info
->dataSize
);
570 _mesa_sha1_final(&ctx
, sha1_out
);
574 anv_pipeline_hash_graphics(struct anv_pipeline
*pipeline
,
575 struct anv_pipeline_layout
*layout
,
576 struct anv_pipeline_stage
*stages
,
577 unsigned char *sha1_out
)
579 struct mesa_sha1 ctx
;
580 _mesa_sha1_init(&ctx
);
582 _mesa_sha1_update(&ctx
, &pipeline
->subpass
->view_mask
,
583 sizeof(pipeline
->subpass
->view_mask
));
586 _mesa_sha1_update(&ctx
, layout
->sha1
, sizeof(layout
->sha1
));
588 const bool rba
= pipeline
->device
->robust_buffer_access
;
589 _mesa_sha1_update(&ctx
, &rba
, sizeof(rba
));
591 for (unsigned s
= 0; s
< MESA_SHADER_STAGES
; s
++) {
592 if (stages
[s
].entrypoint
) {
593 _mesa_sha1_update(&ctx
, stages
[s
].shader_sha1
,
594 sizeof(stages
[s
].shader_sha1
));
595 _mesa_sha1_update(&ctx
, &stages
[s
].key
, brw_prog_key_size(s
));
599 _mesa_sha1_final(&ctx
, sha1_out
);
603 anv_pipeline_hash_compute(struct anv_pipeline
*pipeline
,
604 struct anv_pipeline_layout
*layout
,
605 struct anv_pipeline_stage
*stage
,
606 unsigned char *sha1_out
)
608 struct mesa_sha1 ctx
;
609 _mesa_sha1_init(&ctx
);
612 _mesa_sha1_update(&ctx
, layout
->sha1
, sizeof(layout
->sha1
));
614 const bool rba
= pipeline
->device
->robust_buffer_access
;
615 _mesa_sha1_update(&ctx
, &rba
, sizeof(rba
));
617 _mesa_sha1_update(&ctx
, stage
->shader_sha1
,
618 sizeof(stage
->shader_sha1
));
619 _mesa_sha1_update(&ctx
, &stage
->key
.cs
, sizeof(stage
->key
.cs
));
621 _mesa_sha1_final(&ctx
, sha1_out
);
625 anv_pipeline_stage_get_nir(struct anv_pipeline
*pipeline
,
626 struct anv_pipeline_cache
*cache
,
628 struct anv_pipeline_stage
*stage
)
630 const struct brw_compiler
*compiler
=
631 pipeline
->device
->physical
->compiler
;
632 const nir_shader_compiler_options
*nir_options
=
633 compiler
->glsl_compiler_options
[stage
->stage
].NirOptions
;
636 nir
= anv_device_search_for_nir(pipeline
->device
, cache
,
641 assert(nir
->info
.stage
== stage
->stage
);
645 nir
= anv_shader_compile_to_nir(pipeline
->device
,
652 anv_device_upload_nir(pipeline
->device
, cache
, nir
, stage
->shader_sha1
);
660 anv_pipeline_lower_nir(struct anv_pipeline
*pipeline
,
662 struct anv_pipeline_stage
*stage
,
663 struct anv_pipeline_layout
*layout
)
665 const struct anv_physical_device
*pdevice
= pipeline
->device
->physical
;
666 const struct brw_compiler
*compiler
= pdevice
->compiler
;
668 struct brw_stage_prog_data
*prog_data
= &stage
->prog_data
.base
;
669 nir_shader
*nir
= stage
->nir
;
671 if (nir
->info
.stage
== MESA_SHADER_FRAGMENT
) {
672 NIR_PASS_V(nir
, nir_lower_wpos_center
, pipeline
->sample_shading_enable
);
673 NIR_PASS_V(nir
, nir_lower_input_attachments
, true);
676 NIR_PASS_V(nir
, anv_nir_lower_ycbcr_textures
, layout
);
678 if (pipeline
->type
== ANV_PIPELINE_GRAPHICS
)
679 NIR_PASS_V(nir
, anv_nir_lower_multiview
, pipeline
->subpass
->view_mask
);
681 nir_shader_gather_info(nir
, nir_shader_get_entrypoint(nir
));
683 NIR_PASS_V(nir
, brw_nir_lower_image_load_store
, compiler
->devinfo
);
685 NIR_PASS_V(nir
, nir_lower_explicit_io
, nir_var_mem_global
,
686 nir_address_format_64bit_global
);
688 /* Apply the actual pipeline layout to UBOs, SSBOs, and textures */
689 anv_nir_apply_pipeline_layout(pdevice
,
690 pipeline
->device
->robust_buffer_access
,
691 layout
, nir
, &stage
->bind_map
);
693 NIR_PASS_V(nir
, nir_lower_explicit_io
, nir_var_mem_ubo
,
694 nir_address_format_32bit_index_offset
);
695 NIR_PASS_V(nir
, nir_lower_explicit_io
, nir_var_mem_ssbo
,
696 anv_nir_ssbo_addr_format(pdevice
,
697 pipeline
->device
->robust_buffer_access
));
699 NIR_PASS_V(nir
, nir_opt_constant_folding
);
701 /* We don't support non-uniform UBOs and non-uniform SSBO access is
702 * handled naturally by falling back to A64 messages.
704 NIR_PASS_V(nir
, nir_lower_non_uniform_access
,
705 nir_lower_non_uniform_texture_access
|
706 nir_lower_non_uniform_image_access
);
708 anv_nir_compute_push_layout(pdevice
, pipeline
->device
->robust_buffer_access
,
709 nir
, prog_data
, &stage
->bind_map
, mem_ctx
);
715 anv_pipeline_link_vs(const struct brw_compiler
*compiler
,
716 struct anv_pipeline_stage
*vs_stage
,
717 struct anv_pipeline_stage
*next_stage
)
720 brw_nir_link_shaders(compiler
, vs_stage
->nir
, next_stage
->nir
);
724 anv_pipeline_compile_vs(const struct brw_compiler
*compiler
,
726 struct anv_device
*device
,
727 struct anv_pipeline_stage
*vs_stage
)
729 brw_compute_vue_map(compiler
->devinfo
,
730 &vs_stage
->prog_data
.vs
.base
.vue_map
,
731 vs_stage
->nir
->info
.outputs_written
,
732 vs_stage
->nir
->info
.separate_shader
);
734 vs_stage
->num_stats
= 1;
735 vs_stage
->code
= brw_compile_vs(compiler
, device
, mem_ctx
,
737 &vs_stage
->prog_data
.vs
,
739 vs_stage
->stats
, NULL
);
743 merge_tess_info(struct shader_info
*tes_info
,
744 const struct shader_info
*tcs_info
)
746 /* The Vulkan 1.0.38 spec, section 21.1 Tessellator says:
748 * "PointMode. Controls generation of points rather than triangles
749 * or lines. This functionality defaults to disabled, and is
750 * enabled if either shader stage includes the execution mode.
752 * and about Triangles, Quads, IsoLines, VertexOrderCw, VertexOrderCcw,
753 * PointMode, SpacingEqual, SpacingFractionalEven, SpacingFractionalOdd,
754 * and OutputVertices, it says:
756 * "One mode must be set in at least one of the tessellation
759 * So, the fields can be set in either the TCS or TES, but they must
760 * agree if set in both. Our backend looks at TES, so bitwise-or in
761 * the values from the TCS.
763 assert(tcs_info
->tess
.tcs_vertices_out
== 0 ||
764 tes_info
->tess
.tcs_vertices_out
== 0 ||
765 tcs_info
->tess
.tcs_vertices_out
== tes_info
->tess
.tcs_vertices_out
);
766 tes_info
->tess
.tcs_vertices_out
|= tcs_info
->tess
.tcs_vertices_out
;
768 assert(tcs_info
->tess
.spacing
== TESS_SPACING_UNSPECIFIED
||
769 tes_info
->tess
.spacing
== TESS_SPACING_UNSPECIFIED
||
770 tcs_info
->tess
.spacing
== tes_info
->tess
.spacing
);
771 tes_info
->tess
.spacing
|= tcs_info
->tess
.spacing
;
773 assert(tcs_info
->tess
.primitive_mode
== 0 ||
774 tes_info
->tess
.primitive_mode
== 0 ||
775 tcs_info
->tess
.primitive_mode
== tes_info
->tess
.primitive_mode
);
776 tes_info
->tess
.primitive_mode
|= tcs_info
->tess
.primitive_mode
;
777 tes_info
->tess
.ccw
|= tcs_info
->tess
.ccw
;
778 tes_info
->tess
.point_mode
|= tcs_info
->tess
.point_mode
;
782 anv_pipeline_link_tcs(const struct brw_compiler
*compiler
,
783 struct anv_pipeline_stage
*tcs_stage
,
784 struct anv_pipeline_stage
*tes_stage
)
786 assert(tes_stage
&& tes_stage
->stage
== MESA_SHADER_TESS_EVAL
);
788 brw_nir_link_shaders(compiler
, tcs_stage
->nir
, tes_stage
->nir
);
790 nir_lower_patch_vertices(tes_stage
->nir
,
791 tcs_stage
->nir
->info
.tess
.tcs_vertices_out
,
794 /* Copy TCS info into the TES info */
795 merge_tess_info(&tes_stage
->nir
->info
, &tcs_stage
->nir
->info
);
797 /* Whacking the key after cache lookup is a bit sketchy, but all of
798 * this comes from the SPIR-V, which is part of the hash used for the
799 * pipeline cache. So it should be safe.
801 tcs_stage
->key
.tcs
.tes_primitive_mode
=
802 tes_stage
->nir
->info
.tess
.primitive_mode
;
803 tcs_stage
->key
.tcs
.quads_workaround
=
804 compiler
->devinfo
->gen
< 9 &&
805 tes_stage
->nir
->info
.tess
.primitive_mode
== 7 /* GL_QUADS */ &&
806 tes_stage
->nir
->info
.tess
.spacing
== TESS_SPACING_EQUAL
;
810 anv_pipeline_compile_tcs(const struct brw_compiler
*compiler
,
812 struct anv_device
*device
,
813 struct anv_pipeline_stage
*tcs_stage
,
814 struct anv_pipeline_stage
*prev_stage
)
816 tcs_stage
->key
.tcs
.outputs_written
=
817 tcs_stage
->nir
->info
.outputs_written
;
818 tcs_stage
->key
.tcs
.patch_outputs_written
=
819 tcs_stage
->nir
->info
.patch_outputs_written
;
821 tcs_stage
->num_stats
= 1;
822 tcs_stage
->code
= brw_compile_tcs(compiler
, device
, mem_ctx
,
824 &tcs_stage
->prog_data
.tcs
,
826 tcs_stage
->stats
, NULL
);
830 anv_pipeline_link_tes(const struct brw_compiler
*compiler
,
831 struct anv_pipeline_stage
*tes_stage
,
832 struct anv_pipeline_stage
*next_stage
)
835 brw_nir_link_shaders(compiler
, tes_stage
->nir
, next_stage
->nir
);
839 anv_pipeline_compile_tes(const struct brw_compiler
*compiler
,
841 struct anv_device
*device
,
842 struct anv_pipeline_stage
*tes_stage
,
843 struct anv_pipeline_stage
*tcs_stage
)
845 tes_stage
->key
.tes
.inputs_read
=
846 tcs_stage
->nir
->info
.outputs_written
;
847 tes_stage
->key
.tes
.patch_inputs_read
=
848 tcs_stage
->nir
->info
.patch_outputs_written
;
850 tes_stage
->num_stats
= 1;
851 tes_stage
->code
= brw_compile_tes(compiler
, device
, mem_ctx
,
853 &tcs_stage
->prog_data
.tcs
.base
.vue_map
,
854 &tes_stage
->prog_data
.tes
,
856 tes_stage
->stats
, NULL
);
860 anv_pipeline_link_gs(const struct brw_compiler
*compiler
,
861 struct anv_pipeline_stage
*gs_stage
,
862 struct anv_pipeline_stage
*next_stage
)
865 brw_nir_link_shaders(compiler
, gs_stage
->nir
, next_stage
->nir
);
869 anv_pipeline_compile_gs(const struct brw_compiler
*compiler
,
871 struct anv_device
*device
,
872 struct anv_pipeline_stage
*gs_stage
,
873 struct anv_pipeline_stage
*prev_stage
)
875 brw_compute_vue_map(compiler
->devinfo
,
876 &gs_stage
->prog_data
.gs
.base
.vue_map
,
877 gs_stage
->nir
->info
.outputs_written
,
878 gs_stage
->nir
->info
.separate_shader
);
880 gs_stage
->num_stats
= 1;
881 gs_stage
->code
= brw_compile_gs(compiler
, device
, mem_ctx
,
883 &gs_stage
->prog_data
.gs
,
884 gs_stage
->nir
, NULL
, -1,
885 gs_stage
->stats
, NULL
);
889 anv_pipeline_link_fs(const struct brw_compiler
*compiler
,
890 struct anv_pipeline_stage
*stage
)
892 unsigned num_rt_bindings
;
893 struct anv_pipeline_binding rt_bindings
[MAX_RTS
];
894 if (stage
->key
.wm
.nr_color_regions
> 0) {
895 assert(stage
->key
.wm
.nr_color_regions
<= MAX_RTS
);
896 for (unsigned rt
= 0; rt
< stage
->key
.wm
.nr_color_regions
; rt
++) {
897 if (stage
->key
.wm
.color_outputs_valid
& BITFIELD_BIT(rt
)) {
898 rt_bindings
[rt
] = (struct anv_pipeline_binding
) {
899 .set
= ANV_DESCRIPTOR_SET_COLOR_ATTACHMENTS
,
903 /* Setup a null render target */
904 rt_bindings
[rt
] = (struct anv_pipeline_binding
) {
905 .set
= ANV_DESCRIPTOR_SET_COLOR_ATTACHMENTS
,
910 num_rt_bindings
= stage
->key
.wm
.nr_color_regions
;
912 /* Setup a null render target */
913 rt_bindings
[0] = (struct anv_pipeline_binding
) {
914 .set
= ANV_DESCRIPTOR_SET_COLOR_ATTACHMENTS
,
920 assert(num_rt_bindings
<= MAX_RTS
);
921 assert(stage
->bind_map
.surface_count
== 0);
922 typed_memcpy(stage
->bind_map
.surface_to_descriptor
,
923 rt_bindings
, num_rt_bindings
);
924 stage
->bind_map
.surface_count
+= num_rt_bindings
;
926 /* Now that we've set up the color attachments, we can go through and
927 * eliminate any shader outputs that map to VK_ATTACHMENT_UNUSED in the
928 * hopes that dead code can clean them up in this and any earlier shader
931 nir_function_impl
*impl
= nir_shader_get_entrypoint(stage
->nir
);
932 bool deleted_output
= false;
933 nir_foreach_variable_safe(var
, &stage
->nir
->outputs
) {
934 /* TODO: We don't delete depth/stencil writes. We probably could if the
935 * subpass doesn't have a depth/stencil attachment.
937 if (var
->data
.location
< FRAG_RESULT_DATA0
)
940 const unsigned rt
= var
->data
.location
- FRAG_RESULT_DATA0
;
942 /* If this is the RT at location 0 and we have alpha to coverage
943 * enabled we still need that write because it will affect the coverage
944 * mask even if it's never written to a color target.
946 if (rt
== 0 && stage
->key
.wm
.alpha_to_coverage
)
949 const unsigned array_len
=
950 glsl_type_is_array(var
->type
) ? glsl_get_length(var
->type
) : 1;
951 assert(rt
+ array_len
<= MAX_RTS
);
953 if (rt
>= MAX_RTS
|| !(stage
->key
.wm
.color_outputs_valid
&
954 BITFIELD_RANGE(rt
, array_len
))) {
955 deleted_output
= true;
956 var
->data
.mode
= nir_var_function_temp
;
957 exec_node_remove(&var
->node
);
958 exec_list_push_tail(&impl
->locals
, &var
->node
);
963 nir_fixup_deref_modes(stage
->nir
);
965 /* We stored the number of subpass color attachments in nr_color_regions
966 * when calculating the key for caching. Now that we've computed the bind
967 * map, we can reduce this to the actual max before we go into the back-end
970 stage
->key
.wm
.nr_color_regions
=
971 util_last_bit(stage
->key
.wm
.color_outputs_valid
);
975 anv_pipeline_compile_fs(const struct brw_compiler
*compiler
,
977 struct anv_device
*device
,
978 struct anv_pipeline_stage
*fs_stage
,
979 struct anv_pipeline_stage
*prev_stage
)
981 /* TODO: we could set this to 0 based on the information in nir_shader, but
982 * we need this before we call spirv_to_nir.
985 fs_stage
->key
.wm
.input_slots_valid
=
986 prev_stage
->prog_data
.vue
.vue_map
.slots_valid
;
988 fs_stage
->code
= brw_compile_fs(compiler
, device
, mem_ctx
,
990 &fs_stage
->prog_data
.wm
,
991 fs_stage
->nir
, -1, -1, -1,
993 fs_stage
->stats
, NULL
);
995 fs_stage
->num_stats
= (uint32_t)fs_stage
->prog_data
.wm
.dispatch_8
+
996 (uint32_t)fs_stage
->prog_data
.wm
.dispatch_16
+
997 (uint32_t)fs_stage
->prog_data
.wm
.dispatch_32
;
999 if (fs_stage
->key
.wm
.color_outputs_valid
== 0 &&
1000 !fs_stage
->prog_data
.wm
.has_side_effects
&&
1001 !fs_stage
->prog_data
.wm
.uses_omask
&&
1002 !fs_stage
->key
.wm
.alpha_to_coverage
&&
1003 !fs_stage
->prog_data
.wm
.uses_kill
&&
1004 fs_stage
->prog_data
.wm
.computed_depth_mode
== BRW_PSCDEPTH_OFF
&&
1005 !fs_stage
->prog_data
.wm
.computed_stencil
) {
1006 /* This fragment shader has no outputs and no side effects. Go ahead
1007 * and return the code pointer so we don't accidentally think the
1008 * compile failed but zero out prog_data which will set program_size to
1009 * zero and disable the stage.
1011 memset(&fs_stage
->prog_data
, 0, sizeof(fs_stage
->prog_data
));
1016 anv_pipeline_add_executable(struct anv_pipeline
*pipeline
,
1017 struct anv_pipeline_stage
*stage
,
1018 struct brw_compile_stats
*stats
,
1019 uint32_t code_offset
)
1024 VK_PIPELINE_CREATE_CAPTURE_INTERNAL_REPRESENTATIONS_BIT_KHR
)) {
1025 char *stream_data
= NULL
;
1026 size_t stream_size
= 0;
1027 FILE *stream
= open_memstream(&stream_data
, &stream_size
);
1029 nir_print_shader(stage
->nir
, stream
);
1033 /* Copy it to a ralloc'd thing */
1034 nir
= ralloc_size(pipeline
->mem_ctx
, stream_size
+ 1);
1035 memcpy(nir
, stream_data
, stream_size
);
1036 nir
[stream_size
] = 0;
1041 char *disasm
= NULL
;
1044 VK_PIPELINE_CREATE_CAPTURE_INTERNAL_REPRESENTATIONS_BIT_KHR
)) {
1045 char *stream_data
= NULL
;
1046 size_t stream_size
= 0;
1047 FILE *stream
= open_memstream(&stream_data
, &stream_size
);
1049 /* Creating this is far cheaper than it looks. It's perfectly fine to
1050 * do it for every binary.
1052 struct gen_disasm
*d
= gen_disasm_create(&pipeline
->device
->info
);
1053 gen_disasm_disassemble(d
, stage
->code
, code_offset
, stream
);
1054 gen_disasm_destroy(d
);
1058 /* Copy it to a ralloc'd thing */
1059 disasm
= ralloc_size(pipeline
->mem_ctx
, stream_size
+ 1);
1060 memcpy(disasm
, stream_data
, stream_size
);
1061 disasm
[stream_size
] = 0;
1066 const struct anv_pipeline_executable exe
= {
1067 .stage
= stage
->stage
,
1072 util_dynarray_append(&pipeline
->executables
,
1073 struct anv_pipeline_executable
, exe
);
1077 anv_pipeline_add_executables(struct anv_pipeline
*pipeline
,
1078 struct anv_pipeline_stage
*stage
,
1079 struct anv_shader_bin
*bin
)
1081 if (stage
->stage
== MESA_SHADER_FRAGMENT
) {
1082 /* We pull the prog data and stats out of the anv_shader_bin because
1083 * the anv_pipeline_stage may not be fully populated if we successfully
1084 * looked up the shader in a cache.
1086 const struct brw_wm_prog_data
*wm_prog_data
=
1087 (const struct brw_wm_prog_data
*)bin
->prog_data
;
1088 struct brw_compile_stats
*stats
= bin
->stats
;
1090 if (wm_prog_data
->dispatch_8
) {
1091 anv_pipeline_add_executable(pipeline
, stage
, stats
++, 0);
1094 if (wm_prog_data
->dispatch_16
) {
1095 anv_pipeline_add_executable(pipeline
, stage
, stats
++,
1096 wm_prog_data
->prog_offset_16
);
1099 if (wm_prog_data
->dispatch_32
) {
1100 anv_pipeline_add_executable(pipeline
, stage
, stats
++,
1101 wm_prog_data
->prog_offset_32
);
1104 anv_pipeline_add_executable(pipeline
, stage
, bin
->stats
, 0);
1109 anv_pipeline_compile_graphics(struct anv_pipeline
*pipeline
,
1110 struct anv_pipeline_cache
*cache
,
1111 const VkGraphicsPipelineCreateInfo
*info
)
1113 VkPipelineCreationFeedbackEXT pipeline_feedback
= {
1114 .flags
= VK_PIPELINE_CREATION_FEEDBACK_VALID_BIT_EXT
,
1116 int64_t pipeline_start
= os_time_get_nano();
1118 const struct brw_compiler
*compiler
= pipeline
->device
->physical
->compiler
;
1119 struct anv_pipeline_stage stages
[MESA_SHADER_STAGES
] = {};
1121 pipeline
->active_stages
= 0;
1124 for (uint32_t i
= 0; i
< info
->stageCount
; i
++) {
1125 const VkPipelineShaderStageCreateInfo
*sinfo
= &info
->pStages
[i
];
1126 gl_shader_stage stage
= vk_to_mesa_shader_stage(sinfo
->stage
);
1128 pipeline
->active_stages
|= sinfo
->stage
;
1130 int64_t stage_start
= os_time_get_nano();
1132 stages
[stage
].stage
= stage
;
1133 stages
[stage
].module
= anv_shader_module_from_handle(sinfo
->module
);
1134 stages
[stage
].entrypoint
= sinfo
->pName
;
1135 stages
[stage
].spec_info
= sinfo
->pSpecializationInfo
;
1136 anv_pipeline_hash_shader(stages
[stage
].module
,
1137 stages
[stage
].entrypoint
,
1139 stages
[stage
].spec_info
,
1140 stages
[stage
].shader_sha1
);
1142 const struct gen_device_info
*devinfo
= &pipeline
->device
->info
;
1144 case MESA_SHADER_VERTEX
:
1145 populate_vs_prog_key(devinfo
, sinfo
->flags
, &stages
[stage
].key
.vs
);
1147 case MESA_SHADER_TESS_CTRL
:
1148 populate_tcs_prog_key(devinfo
, sinfo
->flags
,
1149 info
->pTessellationState
->patchControlPoints
,
1150 &stages
[stage
].key
.tcs
);
1152 case MESA_SHADER_TESS_EVAL
:
1153 populate_tes_prog_key(devinfo
, sinfo
->flags
, &stages
[stage
].key
.tes
);
1155 case MESA_SHADER_GEOMETRY
:
1156 populate_gs_prog_key(devinfo
, sinfo
->flags
, &stages
[stage
].key
.gs
);
1158 case MESA_SHADER_FRAGMENT
: {
1159 const bool raster_enabled
=
1160 !info
->pRasterizationState
->rasterizerDiscardEnable
;
1161 populate_wm_prog_key(devinfo
, sinfo
->flags
,
1163 raster_enabled
? info
->pMultisampleState
: NULL
,
1164 &stages
[stage
].key
.wm
);
1168 unreachable("Invalid graphics shader stage");
1171 stages
[stage
].feedback
.duration
+= os_time_get_nano() - stage_start
;
1172 stages
[stage
].feedback
.flags
|= VK_PIPELINE_CREATION_FEEDBACK_VALID_BIT_EXT
;
1175 if (pipeline
->active_stages
& VK_SHADER_STAGE_TESSELLATION_EVALUATION_BIT
)
1176 pipeline
->active_stages
|= VK_SHADER_STAGE_TESSELLATION_CONTROL_BIT
;
1178 assert(pipeline
->active_stages
& VK_SHADER_STAGE_VERTEX_BIT
);
1180 ANV_FROM_HANDLE(anv_pipeline_layout
, layout
, info
->layout
);
1182 unsigned char sha1
[20];
1183 anv_pipeline_hash_graphics(pipeline
, layout
, stages
, sha1
);
1185 for (unsigned s
= 0; s
< MESA_SHADER_STAGES
; s
++) {
1186 if (!stages
[s
].entrypoint
)
1189 stages
[s
].cache_key
.stage
= s
;
1190 memcpy(stages
[s
].cache_key
.sha1
, sha1
, sizeof(sha1
));
1193 const bool skip_cache_lookup
=
1194 (pipeline
->flags
& VK_PIPELINE_CREATE_CAPTURE_INTERNAL_REPRESENTATIONS_BIT_KHR
);
1196 if (!skip_cache_lookup
) {
1198 unsigned cache_hits
= 0;
1199 for (unsigned s
= 0; s
< MESA_SHADER_STAGES
; s
++) {
1200 if (!stages
[s
].entrypoint
)
1203 int64_t stage_start
= os_time_get_nano();
1206 struct anv_shader_bin
*bin
=
1207 anv_device_search_for_kernel(pipeline
->device
, cache
,
1208 &stages
[s
].cache_key
,
1209 sizeof(stages
[s
].cache_key
), &cache_hit
);
1212 pipeline
->shaders
[s
] = bin
;
1217 stages
[s
].feedback
.flags
|=
1218 VK_PIPELINE_CREATION_FEEDBACK_APPLICATION_PIPELINE_CACHE_HIT_BIT_EXT
;
1220 stages
[s
].feedback
.duration
+= os_time_get_nano() - stage_start
;
1223 if (found
== __builtin_popcount(pipeline
->active_stages
)) {
1224 if (cache_hits
== found
) {
1225 pipeline_feedback
.flags
|=
1226 VK_PIPELINE_CREATION_FEEDBACK_APPLICATION_PIPELINE_CACHE_HIT_BIT_EXT
;
1228 /* We found all our shaders in the cache. We're done. */
1229 for (unsigned s
= 0; s
< MESA_SHADER_STAGES
; s
++) {
1230 if (!stages
[s
].entrypoint
)
1233 anv_pipeline_add_executables(pipeline
, &stages
[s
],
1234 pipeline
->shaders
[s
]);
1237 } else if (found
> 0) {
1238 /* We found some but not all of our shaders. This shouldn't happen
1239 * most of the time but it can if we have a partially populated
1242 assert(found
< __builtin_popcount(pipeline
->active_stages
));
1244 vk_debug_report(&pipeline
->device
->physical
->instance
->debug_report_callbacks
,
1245 VK_DEBUG_REPORT_WARNING_BIT_EXT
|
1246 VK_DEBUG_REPORT_PERFORMANCE_WARNING_BIT_EXT
,
1247 VK_DEBUG_REPORT_OBJECT_TYPE_PIPELINE_CACHE_EXT
,
1248 (uint64_t)(uintptr_t)cache
,
1250 "Found a partial pipeline in the cache. This is "
1251 "most likely caused by an incomplete pipeline cache "
1252 "import or export");
1254 /* We're going to have to recompile anyway, so just throw away our
1255 * references to the shaders in the cache. We'll get them out of the
1256 * cache again as part of the compilation process.
1258 for (unsigned s
= 0; s
< MESA_SHADER_STAGES
; s
++) {
1259 stages
[s
].feedback
.flags
= 0;
1260 if (pipeline
->shaders
[s
]) {
1261 anv_shader_bin_unref(pipeline
->device
, pipeline
->shaders
[s
]);
1262 pipeline
->shaders
[s
] = NULL
;
1268 void *pipeline_ctx
= ralloc_context(NULL
);
1270 for (unsigned s
= 0; s
< MESA_SHADER_STAGES
; s
++) {
1271 if (!stages
[s
].entrypoint
)
1274 int64_t stage_start
= os_time_get_nano();
1276 assert(stages
[s
].stage
== s
);
1277 assert(pipeline
->shaders
[s
] == NULL
);
1279 stages
[s
].bind_map
= (struct anv_pipeline_bind_map
) {
1280 .surface_to_descriptor
= stages
[s
].surface_to_descriptor
,
1281 .sampler_to_descriptor
= stages
[s
].sampler_to_descriptor
1284 stages
[s
].nir
= anv_pipeline_stage_get_nir(pipeline
, cache
,
1287 if (stages
[s
].nir
== NULL
) {
1288 result
= vk_error(VK_ERROR_OUT_OF_HOST_MEMORY
);
1292 stages
[s
].feedback
.duration
+= os_time_get_nano() - stage_start
;
1295 /* Walk backwards to link */
1296 struct anv_pipeline_stage
*next_stage
= NULL
;
1297 for (int s
= MESA_SHADER_STAGES
- 1; s
>= 0; s
--) {
1298 if (!stages
[s
].entrypoint
)
1302 case MESA_SHADER_VERTEX
:
1303 anv_pipeline_link_vs(compiler
, &stages
[s
], next_stage
);
1305 case MESA_SHADER_TESS_CTRL
:
1306 anv_pipeline_link_tcs(compiler
, &stages
[s
], next_stage
);
1308 case MESA_SHADER_TESS_EVAL
:
1309 anv_pipeline_link_tes(compiler
, &stages
[s
], next_stage
);
1311 case MESA_SHADER_GEOMETRY
:
1312 anv_pipeline_link_gs(compiler
, &stages
[s
], next_stage
);
1314 case MESA_SHADER_FRAGMENT
:
1315 anv_pipeline_link_fs(compiler
, &stages
[s
]);
1318 unreachable("Invalid graphics shader stage");
1321 next_stage
= &stages
[s
];
1324 struct anv_pipeline_stage
*prev_stage
= NULL
;
1325 for (unsigned s
= 0; s
< MESA_SHADER_STAGES
; s
++) {
1326 if (!stages
[s
].entrypoint
)
1329 int64_t stage_start
= os_time_get_nano();
1331 void *stage_ctx
= ralloc_context(NULL
);
1333 nir_xfb_info
*xfb_info
= NULL
;
1334 if (s
== MESA_SHADER_VERTEX
||
1335 s
== MESA_SHADER_TESS_EVAL
||
1336 s
== MESA_SHADER_GEOMETRY
)
1337 xfb_info
= nir_gather_xfb_info(stages
[s
].nir
, stage_ctx
);
1339 anv_pipeline_lower_nir(pipeline
, stage_ctx
, &stages
[s
], layout
);
1342 case MESA_SHADER_VERTEX
:
1343 anv_pipeline_compile_vs(compiler
, stage_ctx
, pipeline
->device
,
1346 case MESA_SHADER_TESS_CTRL
:
1347 anv_pipeline_compile_tcs(compiler
, stage_ctx
, pipeline
->device
,
1348 &stages
[s
], prev_stage
);
1350 case MESA_SHADER_TESS_EVAL
:
1351 anv_pipeline_compile_tes(compiler
, stage_ctx
, pipeline
->device
,
1352 &stages
[s
], prev_stage
);
1354 case MESA_SHADER_GEOMETRY
:
1355 anv_pipeline_compile_gs(compiler
, stage_ctx
, pipeline
->device
,
1356 &stages
[s
], prev_stage
);
1358 case MESA_SHADER_FRAGMENT
:
1359 anv_pipeline_compile_fs(compiler
, stage_ctx
, pipeline
->device
,
1360 &stages
[s
], prev_stage
);
1363 unreachable("Invalid graphics shader stage");
1365 if (stages
[s
].code
== NULL
) {
1366 ralloc_free(stage_ctx
);
1367 result
= vk_error(VK_ERROR_OUT_OF_HOST_MEMORY
);
1371 anv_nir_validate_push_layout(&stages
[s
].prog_data
.base
,
1372 &stages
[s
].bind_map
);
1374 struct anv_shader_bin
*bin
=
1375 anv_device_upload_kernel(pipeline
->device
, cache
, s
,
1376 &stages
[s
].cache_key
,
1377 sizeof(stages
[s
].cache_key
),
1379 stages
[s
].prog_data
.base
.program_size
,
1380 stages
[s
].nir
->constant_data
,
1381 stages
[s
].nir
->constant_data_size
,
1382 &stages
[s
].prog_data
.base
,
1383 brw_prog_data_size(s
),
1384 stages
[s
].stats
, stages
[s
].num_stats
,
1385 xfb_info
, &stages
[s
].bind_map
);
1387 ralloc_free(stage_ctx
);
1388 result
= vk_error(VK_ERROR_OUT_OF_HOST_MEMORY
);
1392 anv_pipeline_add_executables(pipeline
, &stages
[s
], bin
);
1394 pipeline
->shaders
[s
] = bin
;
1395 ralloc_free(stage_ctx
);
1397 stages
[s
].feedback
.duration
+= os_time_get_nano() - stage_start
;
1399 prev_stage
= &stages
[s
];
1402 ralloc_free(pipeline_ctx
);
1406 if (pipeline
->shaders
[MESA_SHADER_FRAGMENT
] &&
1407 pipeline
->shaders
[MESA_SHADER_FRAGMENT
]->prog_data
->program_size
== 0) {
1408 /* This can happen if we decided to implicitly disable the fragment
1409 * shader. See anv_pipeline_compile_fs().
1411 anv_shader_bin_unref(pipeline
->device
,
1412 pipeline
->shaders
[MESA_SHADER_FRAGMENT
]);
1413 pipeline
->shaders
[MESA_SHADER_FRAGMENT
] = NULL
;
1414 pipeline
->active_stages
&= ~VK_SHADER_STAGE_FRAGMENT_BIT
;
1417 pipeline_feedback
.duration
= os_time_get_nano() - pipeline_start
;
1419 const VkPipelineCreationFeedbackCreateInfoEXT
*create_feedback
=
1420 vk_find_struct_const(info
->pNext
, PIPELINE_CREATION_FEEDBACK_CREATE_INFO_EXT
);
1421 if (create_feedback
) {
1422 *create_feedback
->pPipelineCreationFeedback
= pipeline_feedback
;
1424 assert(info
->stageCount
== create_feedback
->pipelineStageCreationFeedbackCount
);
1425 for (uint32_t i
= 0; i
< info
->stageCount
; i
++) {
1426 gl_shader_stage s
= vk_to_mesa_shader_stage(info
->pStages
[i
].stage
);
1427 create_feedback
->pPipelineStageCreationFeedbacks
[i
] = stages
[s
].feedback
;
1434 ralloc_free(pipeline_ctx
);
1436 for (unsigned s
= 0; s
< MESA_SHADER_STAGES
; s
++) {
1437 if (pipeline
->shaders
[s
])
1438 anv_shader_bin_unref(pipeline
->device
, pipeline
->shaders
[s
]);
1445 shared_type_info(const struct glsl_type
*type
, unsigned *size
, unsigned *align
)
1447 assert(glsl_type_is_vector_or_scalar(type
));
1449 uint32_t comp_size
= glsl_type_is_boolean(type
)
1450 ? 4 : glsl_get_bit_size(type
) / 8;
1451 unsigned length
= glsl_get_vector_elements(type
);
1452 *size
= comp_size
* length
,
1453 *align
= comp_size
* (length
== 3 ? 4 : length
);
1457 anv_pipeline_compile_cs(struct anv_pipeline
*pipeline
,
1458 struct anv_pipeline_cache
*cache
,
1459 const VkComputePipelineCreateInfo
*info
,
1460 const struct anv_shader_module
*module
,
1461 const char *entrypoint
,
1462 const VkSpecializationInfo
*spec_info
)
1464 VkPipelineCreationFeedbackEXT pipeline_feedback
= {
1465 .flags
= VK_PIPELINE_CREATION_FEEDBACK_VALID_BIT_EXT
,
1467 int64_t pipeline_start
= os_time_get_nano();
1469 const struct brw_compiler
*compiler
= pipeline
->device
->physical
->compiler
;
1471 struct anv_pipeline_stage stage
= {
1472 .stage
= MESA_SHADER_COMPUTE
,
1474 .entrypoint
= entrypoint
,
1475 .spec_info
= spec_info
,
1477 .stage
= MESA_SHADER_COMPUTE
,
1480 .flags
= VK_PIPELINE_CREATION_FEEDBACK_VALID_BIT_EXT
,
1483 anv_pipeline_hash_shader(stage
.module
,
1485 MESA_SHADER_COMPUTE
,
1489 struct anv_shader_bin
*bin
= NULL
;
1491 const VkPipelineShaderStageRequiredSubgroupSizeCreateInfoEXT
*rss_info
=
1492 vk_find_struct_const(info
->stage
.pNext
,
1493 PIPELINE_SHADER_STAGE_REQUIRED_SUBGROUP_SIZE_CREATE_INFO_EXT
);
1495 populate_cs_prog_key(&pipeline
->device
->info
, info
->stage
.flags
,
1496 rss_info
, &stage
.key
.cs
);
1498 ANV_FROM_HANDLE(anv_pipeline_layout
, layout
, info
->layout
);
1500 const bool skip_cache_lookup
=
1501 (pipeline
->flags
& VK_PIPELINE_CREATE_CAPTURE_INTERNAL_REPRESENTATIONS_BIT_KHR
);
1503 anv_pipeline_hash_compute(pipeline
, layout
, &stage
, stage
.cache_key
.sha1
);
1505 bool cache_hit
= false;
1506 if (!skip_cache_lookup
) {
1507 bin
= anv_device_search_for_kernel(pipeline
->device
, cache
,
1509 sizeof(stage
.cache_key
),
1513 void *mem_ctx
= ralloc_context(NULL
);
1515 int64_t stage_start
= os_time_get_nano();
1517 stage
.bind_map
= (struct anv_pipeline_bind_map
) {
1518 .surface_to_descriptor
= stage
.surface_to_descriptor
,
1519 .sampler_to_descriptor
= stage
.sampler_to_descriptor
1522 /* Set up a binding for the gl_NumWorkGroups */
1523 stage
.bind_map
.surface_count
= 1;
1524 stage
.bind_map
.surface_to_descriptor
[0] = (struct anv_pipeline_binding
) {
1525 .set
= ANV_DESCRIPTOR_SET_NUM_WORK_GROUPS
,
1528 stage
.nir
= anv_pipeline_stage_get_nir(pipeline
, cache
, mem_ctx
, &stage
);
1529 if (stage
.nir
== NULL
) {
1530 ralloc_free(mem_ctx
);
1531 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY
);
1534 NIR_PASS_V(stage
.nir
, anv_nir_add_base_work_group_id
);
1536 anv_pipeline_lower_nir(pipeline
, mem_ctx
, &stage
, layout
);
1538 NIR_PASS_V(stage
.nir
, nir_lower_vars_to_explicit_types
,
1539 nir_var_mem_shared
, shared_type_info
);
1540 NIR_PASS_V(stage
.nir
, nir_lower_explicit_io
,
1541 nir_var_mem_shared
, nir_address_format_32bit_offset
);
1543 stage
.num_stats
= 1;
1544 stage
.code
= brw_compile_cs(compiler
, pipeline
->device
, mem_ctx
,
1545 &stage
.key
.cs
, &stage
.prog_data
.cs
,
1546 stage
.nir
, -1, stage
.stats
, NULL
);
1547 if (stage
.code
== NULL
) {
1548 ralloc_free(mem_ctx
);
1549 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY
);
1552 anv_nir_validate_push_layout(&stage
.prog_data
.base
, &stage
.bind_map
);
1554 if (!stage
.prog_data
.cs
.uses_num_work_groups
) {
1555 assert(stage
.bind_map
.surface_to_descriptor
[0].set
==
1556 ANV_DESCRIPTOR_SET_NUM_WORK_GROUPS
);
1557 stage
.bind_map
.surface_to_descriptor
[0].set
= ANV_DESCRIPTOR_SET_NULL
;
1560 const unsigned code_size
= stage
.prog_data
.base
.program_size
;
1561 bin
= anv_device_upload_kernel(pipeline
->device
, cache
,
1562 MESA_SHADER_COMPUTE
,
1563 &stage
.cache_key
, sizeof(stage
.cache_key
),
1564 stage
.code
, code_size
,
1565 stage
.nir
->constant_data
,
1566 stage
.nir
->constant_data_size
,
1567 &stage
.prog_data
.base
,
1568 sizeof(stage
.prog_data
.cs
),
1569 stage
.stats
, stage
.num_stats
,
1570 NULL
, &stage
.bind_map
);
1572 ralloc_free(mem_ctx
);
1573 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY
);
1576 stage
.feedback
.duration
= os_time_get_nano() - stage_start
;
1579 anv_pipeline_add_executables(pipeline
, &stage
, bin
);
1581 ralloc_free(mem_ctx
);
1584 stage
.feedback
.flags
|=
1585 VK_PIPELINE_CREATION_FEEDBACK_APPLICATION_PIPELINE_CACHE_HIT_BIT_EXT
;
1586 pipeline_feedback
.flags
|=
1587 VK_PIPELINE_CREATION_FEEDBACK_APPLICATION_PIPELINE_CACHE_HIT_BIT_EXT
;
1589 pipeline_feedback
.duration
= os_time_get_nano() - pipeline_start
;
1591 const VkPipelineCreationFeedbackCreateInfoEXT
*create_feedback
=
1592 vk_find_struct_const(info
->pNext
, PIPELINE_CREATION_FEEDBACK_CREATE_INFO_EXT
);
1593 if (create_feedback
) {
1594 *create_feedback
->pPipelineCreationFeedback
= pipeline_feedback
;
1596 assert(create_feedback
->pipelineStageCreationFeedbackCount
== 1);
1597 create_feedback
->pPipelineStageCreationFeedbacks
[0] = stage
.feedback
;
1600 pipeline
->active_stages
= VK_SHADER_STAGE_COMPUTE_BIT
;
1607 * Copy pipeline state not marked as dynamic.
1608 * Dynamic state is pipeline state which hasn't been provided at pipeline
1609 * creation time, but is dynamically provided afterwards using various
1610 * vkCmdSet* functions.
1612 * The set of state considered "non_dynamic" is determined by the pieces of
1613 * state that have their corresponding VkDynamicState enums omitted from
1614 * VkPipelineDynamicStateCreateInfo::pDynamicStates.
1616 * @param[out] pipeline Destination non_dynamic state.
1617 * @param[in] pCreateInfo Source of non_dynamic state to be copied.
1620 copy_non_dynamic_state(struct anv_pipeline
*pipeline
,
1621 const VkGraphicsPipelineCreateInfo
*pCreateInfo
)
1623 anv_cmd_dirty_mask_t states
= ANV_CMD_DIRTY_DYNAMIC_ALL
;
1624 struct anv_subpass
*subpass
= pipeline
->subpass
;
1626 pipeline
->dynamic_state
= default_dynamic_state
;
1628 if (pCreateInfo
->pDynamicState
) {
1629 /* Remove all of the states that are marked as dynamic */
1630 uint32_t count
= pCreateInfo
->pDynamicState
->dynamicStateCount
;
1631 for (uint32_t s
= 0; s
< count
; s
++) {
1632 states
&= ~anv_cmd_dirty_bit_for_vk_dynamic_state(
1633 pCreateInfo
->pDynamicState
->pDynamicStates
[s
]);
1637 struct anv_dynamic_state
*dynamic
= &pipeline
->dynamic_state
;
1639 /* Section 9.2 of the Vulkan 1.0.15 spec says:
1641 * pViewportState is [...] NULL if the pipeline
1642 * has rasterization disabled.
1644 if (!pCreateInfo
->pRasterizationState
->rasterizerDiscardEnable
) {
1645 assert(pCreateInfo
->pViewportState
);
1647 dynamic
->viewport
.count
= pCreateInfo
->pViewportState
->viewportCount
;
1648 if (states
& ANV_CMD_DIRTY_DYNAMIC_VIEWPORT
) {
1649 typed_memcpy(dynamic
->viewport
.viewports
,
1650 pCreateInfo
->pViewportState
->pViewports
,
1651 pCreateInfo
->pViewportState
->viewportCount
);
1654 dynamic
->scissor
.count
= pCreateInfo
->pViewportState
->scissorCount
;
1655 if (states
& ANV_CMD_DIRTY_DYNAMIC_SCISSOR
) {
1656 typed_memcpy(dynamic
->scissor
.scissors
,
1657 pCreateInfo
->pViewportState
->pScissors
,
1658 pCreateInfo
->pViewportState
->scissorCount
);
1662 if (states
& ANV_CMD_DIRTY_DYNAMIC_LINE_WIDTH
) {
1663 assert(pCreateInfo
->pRasterizationState
);
1664 dynamic
->line_width
= pCreateInfo
->pRasterizationState
->lineWidth
;
1667 if (states
& ANV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS
) {
1668 assert(pCreateInfo
->pRasterizationState
);
1669 dynamic
->depth_bias
.bias
=
1670 pCreateInfo
->pRasterizationState
->depthBiasConstantFactor
;
1671 dynamic
->depth_bias
.clamp
=
1672 pCreateInfo
->pRasterizationState
->depthBiasClamp
;
1673 dynamic
->depth_bias
.slope
=
1674 pCreateInfo
->pRasterizationState
->depthBiasSlopeFactor
;
1677 /* Section 9.2 of the Vulkan 1.0.15 spec says:
1679 * pColorBlendState is [...] NULL if the pipeline has rasterization
1680 * disabled or if the subpass of the render pass the pipeline is
1681 * created against does not use any color attachments.
1683 bool uses_color_att
= false;
1684 for (unsigned i
= 0; i
< subpass
->color_count
; ++i
) {
1685 if (subpass
->color_attachments
[i
].attachment
!= VK_ATTACHMENT_UNUSED
) {
1686 uses_color_att
= true;
1691 if (uses_color_att
&&
1692 !pCreateInfo
->pRasterizationState
->rasterizerDiscardEnable
) {
1693 assert(pCreateInfo
->pColorBlendState
);
1695 if (states
& ANV_CMD_DIRTY_DYNAMIC_BLEND_CONSTANTS
)
1696 typed_memcpy(dynamic
->blend_constants
,
1697 pCreateInfo
->pColorBlendState
->blendConstants
, 4);
1700 /* If there is no depthstencil attachment, then don't read
1701 * pDepthStencilState. The Vulkan spec states that pDepthStencilState may
1702 * be NULL in this case. Even if pDepthStencilState is non-NULL, there is
1703 * no need to override the depthstencil defaults in
1704 * anv_pipeline::dynamic_state when there is no depthstencil attachment.
1706 * Section 9.2 of the Vulkan 1.0.15 spec says:
1708 * pDepthStencilState is [...] NULL if the pipeline has rasterization
1709 * disabled or if the subpass of the render pass the pipeline is created
1710 * against does not use a depth/stencil attachment.
1712 if (!pCreateInfo
->pRasterizationState
->rasterizerDiscardEnable
&&
1713 subpass
->depth_stencil_attachment
) {
1714 assert(pCreateInfo
->pDepthStencilState
);
1716 if (states
& ANV_CMD_DIRTY_DYNAMIC_DEPTH_BOUNDS
) {
1717 dynamic
->depth_bounds
.min
=
1718 pCreateInfo
->pDepthStencilState
->minDepthBounds
;
1719 dynamic
->depth_bounds
.max
=
1720 pCreateInfo
->pDepthStencilState
->maxDepthBounds
;
1723 if (states
& ANV_CMD_DIRTY_DYNAMIC_STENCIL_COMPARE_MASK
) {
1724 dynamic
->stencil_compare_mask
.front
=
1725 pCreateInfo
->pDepthStencilState
->front
.compareMask
;
1726 dynamic
->stencil_compare_mask
.back
=
1727 pCreateInfo
->pDepthStencilState
->back
.compareMask
;
1730 if (states
& ANV_CMD_DIRTY_DYNAMIC_STENCIL_WRITE_MASK
) {
1731 dynamic
->stencil_write_mask
.front
=
1732 pCreateInfo
->pDepthStencilState
->front
.writeMask
;
1733 dynamic
->stencil_write_mask
.back
=
1734 pCreateInfo
->pDepthStencilState
->back
.writeMask
;
1737 if (states
& ANV_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE
) {
1738 dynamic
->stencil_reference
.front
=
1739 pCreateInfo
->pDepthStencilState
->front
.reference
;
1740 dynamic
->stencil_reference
.back
=
1741 pCreateInfo
->pDepthStencilState
->back
.reference
;
1745 const VkPipelineRasterizationLineStateCreateInfoEXT
*line_state
=
1746 vk_find_struct_const(pCreateInfo
->pRasterizationState
->pNext
,
1747 PIPELINE_RASTERIZATION_LINE_STATE_CREATE_INFO_EXT
);
1749 if (states
& ANV_CMD_DIRTY_DYNAMIC_LINE_STIPPLE
) {
1750 dynamic
->line_stipple
.factor
= line_state
->lineStippleFactor
;
1751 dynamic
->line_stipple
.pattern
= line_state
->lineStipplePattern
;
1755 pipeline
->dynamic_state_mask
= states
;
1759 anv_pipeline_validate_create_info(const VkGraphicsPipelineCreateInfo
*info
)
1762 struct anv_render_pass
*renderpass
= NULL
;
1763 struct anv_subpass
*subpass
= NULL
;
1765 /* Assert that all required members of VkGraphicsPipelineCreateInfo are
1766 * present. See the Vulkan 1.0.28 spec, Section 9.2 Graphics Pipelines.
1768 assert(info
->sType
== VK_STRUCTURE_TYPE_GRAPHICS_PIPELINE_CREATE_INFO
);
1770 renderpass
= anv_render_pass_from_handle(info
->renderPass
);
1773 assert(info
->subpass
< renderpass
->subpass_count
);
1774 subpass
= &renderpass
->subpasses
[info
->subpass
];
1776 assert(info
->stageCount
>= 1);
1777 assert(info
->pVertexInputState
);
1778 assert(info
->pInputAssemblyState
);
1779 assert(info
->pRasterizationState
);
1780 if (!info
->pRasterizationState
->rasterizerDiscardEnable
) {
1781 assert(info
->pViewportState
);
1782 assert(info
->pMultisampleState
);
1784 if (subpass
&& subpass
->depth_stencil_attachment
)
1785 assert(info
->pDepthStencilState
);
1787 if (subpass
&& subpass
->color_count
> 0) {
1788 bool all_color_unused
= true;
1789 for (int i
= 0; i
< subpass
->color_count
; i
++) {
1790 if (subpass
->color_attachments
[i
].attachment
!= VK_ATTACHMENT_UNUSED
)
1791 all_color_unused
= false;
1793 /* pColorBlendState is ignored if the pipeline has rasterization
1794 * disabled or if the subpass of the render pass the pipeline is
1795 * created against does not use any color attachments.
1797 assert(info
->pColorBlendState
|| all_color_unused
);
1801 for (uint32_t i
= 0; i
< info
->stageCount
; ++i
) {
1802 switch (info
->pStages
[i
].stage
) {
1803 case VK_SHADER_STAGE_TESSELLATION_CONTROL_BIT
:
1804 case VK_SHADER_STAGE_TESSELLATION_EVALUATION_BIT
:
1805 assert(info
->pTessellationState
);
1815 * Calculate the desired L3 partitioning based on the current state of the
1816 * pipeline. For now this simply returns the conservative defaults calculated
1817 * by get_default_l3_weights(), but we could probably do better by gathering
1818 * more statistics from the pipeline state (e.g. guess of expected URB usage
1819 * and bound surfaces), or by using feed-back from performance counters.
1822 anv_pipeline_setup_l3_config(struct anv_pipeline
*pipeline
, bool needs_slm
)
1824 const struct gen_device_info
*devinfo
= &pipeline
->device
->info
;
1826 const struct gen_l3_weights w
=
1827 gen_get_default_l3_weights(devinfo
, true, needs_slm
);
1829 pipeline
->l3_config
= gen_get_l3_config(devinfo
, w
);
1833 anv_pipeline_init(struct anv_pipeline
*pipeline
,
1834 struct anv_device
*device
,
1835 struct anv_pipeline_cache
*cache
,
1836 const VkGraphicsPipelineCreateInfo
*pCreateInfo
,
1837 const VkAllocationCallbacks
*alloc
)
1841 anv_pipeline_validate_create_info(pCreateInfo
);
1844 alloc
= &device
->alloc
;
1846 pipeline
->device
= device
;
1847 pipeline
->type
= ANV_PIPELINE_GRAPHICS
;
1849 ANV_FROM_HANDLE(anv_render_pass
, render_pass
, pCreateInfo
->renderPass
);
1850 assert(pCreateInfo
->subpass
< render_pass
->subpass_count
);
1851 pipeline
->subpass
= &render_pass
->subpasses
[pCreateInfo
->subpass
];
1853 result
= anv_reloc_list_init(&pipeline
->batch_relocs
, alloc
);
1854 if (result
!= VK_SUCCESS
)
1857 pipeline
->batch
.alloc
= alloc
;
1858 pipeline
->batch
.next
= pipeline
->batch
.start
= pipeline
->batch_data
;
1859 pipeline
->batch
.end
= pipeline
->batch
.start
+ sizeof(pipeline
->batch_data
);
1860 pipeline
->batch
.relocs
= &pipeline
->batch_relocs
;
1861 pipeline
->batch
.status
= VK_SUCCESS
;
1863 pipeline
->mem_ctx
= ralloc_context(NULL
);
1864 pipeline
->flags
= pCreateInfo
->flags
;
1866 assert(pCreateInfo
->pRasterizationState
);
1868 copy_non_dynamic_state(pipeline
, pCreateInfo
);
1869 pipeline
->depth_clamp_enable
= pCreateInfo
->pRasterizationState
->depthClampEnable
;
1871 /* Previously we enabled depth clipping when !depthClampEnable.
1872 * DepthClipStateCreateInfo now makes depth clipping explicit so if the
1873 * clipping info is available, use its enable value to determine clipping,
1874 * otherwise fallback to the previous !depthClampEnable logic.
1876 const VkPipelineRasterizationDepthClipStateCreateInfoEXT
*clip_info
=
1877 vk_find_struct_const(pCreateInfo
->pRasterizationState
->pNext
,
1878 PIPELINE_RASTERIZATION_DEPTH_CLIP_STATE_CREATE_INFO_EXT
);
1879 pipeline
->depth_clip_enable
= clip_info
? clip_info
->depthClipEnable
: !pipeline
->depth_clamp_enable
;
1881 pipeline
->sample_shading_enable
=
1882 !pCreateInfo
->pRasterizationState
->rasterizerDiscardEnable
&&
1883 pCreateInfo
->pMultisampleState
&&
1884 pCreateInfo
->pMultisampleState
->sampleShadingEnable
;
1886 /* When we free the pipeline, we detect stages based on the NULL status
1887 * of various prog_data pointers. Make them NULL by default.
1889 memset(pipeline
->shaders
, 0, sizeof(pipeline
->shaders
));
1891 util_dynarray_init(&pipeline
->executables
, pipeline
->mem_ctx
);
1893 result
= anv_pipeline_compile_graphics(pipeline
, cache
, pCreateInfo
);
1894 if (result
!= VK_SUCCESS
) {
1895 ralloc_free(pipeline
->mem_ctx
);
1896 anv_reloc_list_finish(&pipeline
->batch_relocs
, alloc
);
1900 assert(pipeline
->shaders
[MESA_SHADER_VERTEX
]);
1902 anv_pipeline_setup_l3_config(pipeline
, false);
1904 const VkPipelineVertexInputStateCreateInfo
*vi_info
=
1905 pCreateInfo
->pVertexInputState
;
1907 const uint64_t inputs_read
= get_vs_prog_data(pipeline
)->inputs_read
;
1909 pipeline
->vb_used
= 0;
1910 for (uint32_t i
= 0; i
< vi_info
->vertexAttributeDescriptionCount
; i
++) {
1911 const VkVertexInputAttributeDescription
*desc
=
1912 &vi_info
->pVertexAttributeDescriptions
[i
];
1914 if (inputs_read
& (1ull << (VERT_ATTRIB_GENERIC0
+ desc
->location
)))
1915 pipeline
->vb_used
|= 1 << desc
->binding
;
1918 for (uint32_t i
= 0; i
< vi_info
->vertexBindingDescriptionCount
; i
++) {
1919 const VkVertexInputBindingDescription
*desc
=
1920 &vi_info
->pVertexBindingDescriptions
[i
];
1922 pipeline
->vb
[desc
->binding
].stride
= desc
->stride
;
1924 /* Step rate is programmed per vertex element (attribute), not
1925 * binding. Set up a map of which bindings step per instance, for
1926 * reference by vertex element setup. */
1927 switch (desc
->inputRate
) {
1929 case VK_VERTEX_INPUT_RATE_VERTEX
:
1930 pipeline
->vb
[desc
->binding
].instanced
= false;
1932 case VK_VERTEX_INPUT_RATE_INSTANCE
:
1933 pipeline
->vb
[desc
->binding
].instanced
= true;
1937 pipeline
->vb
[desc
->binding
].instance_divisor
= 1;
1940 const VkPipelineVertexInputDivisorStateCreateInfoEXT
*vi_div_state
=
1941 vk_find_struct_const(vi_info
->pNext
,
1942 PIPELINE_VERTEX_INPUT_DIVISOR_STATE_CREATE_INFO_EXT
);
1944 for (uint32_t i
= 0; i
< vi_div_state
->vertexBindingDivisorCount
; i
++) {
1945 const VkVertexInputBindingDivisorDescriptionEXT
*desc
=
1946 &vi_div_state
->pVertexBindingDivisors
[i
];
1948 pipeline
->vb
[desc
->binding
].instance_divisor
= desc
->divisor
;
1952 /* Our implementation of VK_KHR_multiview uses instancing to draw the
1953 * different views. If the client asks for instancing, we need to multiply
1954 * the instance divisor by the number of views ensure that we repeat the
1955 * client's per-instance data once for each view.
1957 if (pipeline
->subpass
->view_mask
) {
1958 const uint32_t view_count
= anv_subpass_view_count(pipeline
->subpass
);
1959 for (uint32_t vb
= 0; vb
< MAX_VBS
; vb
++) {
1960 if (pipeline
->vb
[vb
].instanced
)
1961 pipeline
->vb
[vb
].instance_divisor
*= view_count
;
1965 const VkPipelineInputAssemblyStateCreateInfo
*ia_info
=
1966 pCreateInfo
->pInputAssemblyState
;
1967 const VkPipelineTessellationStateCreateInfo
*tess_info
=
1968 pCreateInfo
->pTessellationState
;
1969 pipeline
->primitive_restart
= ia_info
->primitiveRestartEnable
;
1971 if (anv_pipeline_has_stage(pipeline
, MESA_SHADER_TESS_EVAL
))
1972 pipeline
->topology
= _3DPRIM_PATCHLIST(tess_info
->patchControlPoints
);
1974 pipeline
->topology
= vk_to_gen_primitive_type
[ia_info
->topology
];
1979 #define WRITE_STR(field, ...) ({ \
1980 memset(field, 0, sizeof(field)); \
1981 UNUSED int i = snprintf(field, sizeof(field), __VA_ARGS__); \
1982 assert(i > 0 && i < sizeof(field)); \
1985 VkResult
anv_GetPipelineExecutablePropertiesKHR(
1987 const VkPipelineInfoKHR
* pPipelineInfo
,
1988 uint32_t* pExecutableCount
,
1989 VkPipelineExecutablePropertiesKHR
* pProperties
)
1991 ANV_FROM_HANDLE(anv_pipeline
, pipeline
, pPipelineInfo
->pipeline
);
1992 VK_OUTARRAY_MAKE(out
, pProperties
, pExecutableCount
);
1994 util_dynarray_foreach (&pipeline
->executables
, struct anv_pipeline_executable
, exe
) {
1995 vk_outarray_append(&out
, props
) {
1996 gl_shader_stage stage
= exe
->stage
;
1997 props
->stages
= mesa_to_vk_shader_stage(stage
);
1999 unsigned simd_width
= exe
->stats
.dispatch_width
;
2000 if (stage
== MESA_SHADER_FRAGMENT
) {
2001 WRITE_STR(props
->name
, "%s%d %s",
2002 simd_width
? "SIMD" : "vec",
2003 simd_width
? simd_width
: 4,
2004 _mesa_shader_stage_to_string(stage
));
2006 WRITE_STR(props
->name
, "%s", _mesa_shader_stage_to_string(stage
));
2008 WRITE_STR(props
->description
, "%s%d %s shader",
2009 simd_width
? "SIMD" : "vec",
2010 simd_width
? simd_width
: 4,
2011 _mesa_shader_stage_to_string(stage
));
2013 /* The compiler gives us a dispatch width of 0 for vec4 but Vulkan
2014 * wants a subgroup size of 1.
2016 props
->subgroupSize
= MAX2(simd_width
, 1);
2020 return vk_outarray_status(&out
);
2023 static const struct anv_pipeline_executable
*
2024 anv_pipeline_get_executable(struct anv_pipeline
*pipeline
, uint32_t index
)
2026 assert(index
< util_dynarray_num_elements(&pipeline
->executables
,
2027 struct anv_pipeline_executable
));
2028 return util_dynarray_element(
2029 &pipeline
->executables
, struct anv_pipeline_executable
, index
);
2032 VkResult
anv_GetPipelineExecutableStatisticsKHR(
2034 const VkPipelineExecutableInfoKHR
* pExecutableInfo
,
2035 uint32_t* pStatisticCount
,
2036 VkPipelineExecutableStatisticKHR
* pStatistics
)
2038 ANV_FROM_HANDLE(anv_pipeline
, pipeline
, pExecutableInfo
->pipeline
);
2039 VK_OUTARRAY_MAKE(out
, pStatistics
, pStatisticCount
);
2041 const struct anv_pipeline_executable
*exe
=
2042 anv_pipeline_get_executable(pipeline
, pExecutableInfo
->executableIndex
);
2044 const struct brw_stage_prog_data
*prog_data
;
2045 switch (pipeline
->type
) {
2046 case ANV_PIPELINE_GRAPHICS
:
2047 prog_data
= pipeline
->shaders
[exe
->stage
]->prog_data
;
2049 case ANV_PIPELINE_COMPUTE
:
2050 prog_data
= pipeline
->cs
->prog_data
;
2053 unreachable("invalid pipeline type");
2056 vk_outarray_append(&out
, stat
) {
2057 WRITE_STR(stat
->name
, "Instruction Count");
2058 WRITE_STR(stat
->description
,
2059 "Number of GEN instructions in the final generated "
2060 "shader executable.");
2061 stat
->format
= VK_PIPELINE_EXECUTABLE_STATISTIC_FORMAT_UINT64_KHR
;
2062 stat
->value
.u64
= exe
->stats
.instructions
;
2065 vk_outarray_append(&out
, stat
) {
2066 WRITE_STR(stat
->name
, "Loop Count");
2067 WRITE_STR(stat
->description
,
2068 "Number of loops (not unrolled) in the final generated "
2069 "shader executable.");
2070 stat
->format
= VK_PIPELINE_EXECUTABLE_STATISTIC_FORMAT_UINT64_KHR
;
2071 stat
->value
.u64
= exe
->stats
.loops
;
2074 vk_outarray_append(&out
, stat
) {
2075 WRITE_STR(stat
->name
, "Cycle Count");
2076 WRITE_STR(stat
->description
,
2077 "Estimate of the number of EU cycles required to execute "
2078 "the final generated executable. This is an estimate only "
2079 "and may vary greatly from actual run-time performance.");
2080 stat
->format
= VK_PIPELINE_EXECUTABLE_STATISTIC_FORMAT_UINT64_KHR
;
2081 stat
->value
.u64
= exe
->stats
.cycles
;
2084 vk_outarray_append(&out
, stat
) {
2085 WRITE_STR(stat
->name
, "Spill Count");
2086 WRITE_STR(stat
->description
,
2087 "Number of scratch spill operations. This gives a rough "
2088 "estimate of the cost incurred due to spilling temporary "
2089 "values to memory. If this is non-zero, you may want to "
2090 "adjust your shader to reduce register pressure.");
2091 stat
->format
= VK_PIPELINE_EXECUTABLE_STATISTIC_FORMAT_UINT64_KHR
;
2092 stat
->value
.u64
= exe
->stats
.spills
;
2095 vk_outarray_append(&out
, stat
) {
2096 WRITE_STR(stat
->name
, "Fill Count");
2097 WRITE_STR(stat
->description
,
2098 "Number of scratch fill operations. This gives a rough "
2099 "estimate of the cost incurred due to spilling temporary "
2100 "values to memory. If this is non-zero, you may want to "
2101 "adjust your shader to reduce register pressure.");
2102 stat
->format
= VK_PIPELINE_EXECUTABLE_STATISTIC_FORMAT_UINT64_KHR
;
2103 stat
->value
.u64
= exe
->stats
.fills
;
2106 vk_outarray_append(&out
, stat
) {
2107 WRITE_STR(stat
->name
, "Scratch Memory Size");
2108 WRITE_STR(stat
->description
,
2109 "Number of bytes of scratch memory required by the "
2110 "generated shader executable. If this is non-zero, you "
2111 "may want to adjust your shader to reduce register "
2113 stat
->format
= VK_PIPELINE_EXECUTABLE_STATISTIC_FORMAT_UINT64_KHR
;
2114 stat
->value
.u64
= prog_data
->total_scratch
;
2117 if (exe
->stage
== MESA_SHADER_COMPUTE
) {
2118 vk_outarray_append(&out
, stat
) {
2119 WRITE_STR(stat
->name
, "Workgroup Memory Size");
2120 WRITE_STR(stat
->description
,
2121 "Number of bytes of workgroup shared memory used by this "
2122 "compute shader including any padding.");
2123 stat
->format
= VK_PIPELINE_EXECUTABLE_STATISTIC_FORMAT_UINT64_KHR
;
2124 stat
->value
.u64
= prog_data
->total_scratch
;
2128 return vk_outarray_status(&out
);
2132 write_ir_text(VkPipelineExecutableInternalRepresentationKHR
* ir
,
2135 ir
->isText
= VK_TRUE
;
2137 size_t data_len
= strlen(data
) + 1;
2139 if (ir
->pData
== NULL
) {
2140 ir
->dataSize
= data_len
;
2144 strncpy(ir
->pData
, data
, ir
->dataSize
);
2145 if (ir
->dataSize
< data_len
)
2148 ir
->dataSize
= data_len
;
2152 VkResult
anv_GetPipelineExecutableInternalRepresentationsKHR(
2154 const VkPipelineExecutableInfoKHR
* pExecutableInfo
,
2155 uint32_t* pInternalRepresentationCount
,
2156 VkPipelineExecutableInternalRepresentationKHR
* pInternalRepresentations
)
2158 ANV_FROM_HANDLE(anv_pipeline
, pipeline
, pExecutableInfo
->pipeline
);
2159 VK_OUTARRAY_MAKE(out
, pInternalRepresentations
,
2160 pInternalRepresentationCount
);
2161 bool incomplete_text
= false;
2163 const struct anv_pipeline_executable
*exe
=
2164 anv_pipeline_get_executable(pipeline
, pExecutableInfo
->executableIndex
);
2167 vk_outarray_append(&out
, ir
) {
2168 WRITE_STR(ir
->name
, "Final NIR");
2169 WRITE_STR(ir
->description
,
2170 "Final NIR before going into the back-end compiler");
2172 if (!write_ir_text(ir
, exe
->nir
))
2173 incomplete_text
= true;
2178 vk_outarray_append(&out
, ir
) {
2179 WRITE_STR(ir
->name
, "GEN Assembly");
2180 WRITE_STR(ir
->description
,
2181 "Final GEN assembly for the generated shader binary");
2183 if (!write_ir_text(ir
, exe
->disasm
))
2184 incomplete_text
= true;
2188 return incomplete_text
? VK_INCOMPLETE
: vk_outarray_status(&out
);