src/intel/vulkan/gen7_cmd_buffer.c

   1 /*
   2  * Copyright © 2015 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  */
  23
  24 #include <assert.h>
  25 #include <stdbool.h>
  26 #include <string.h>
  27 #include <unistd.h>
  28 #include <fcntl.h>
  29
  30 #include "anv_private.h"
  31 #include "vk_format_info.h"
  32
  33 #include "genxml/gen_macros.h"
  34 #include "genxml/genX_pack.h"
  35
  36 #if GEN_GEN == 7 && !GEN_IS_HASWELL
  37 static int64_t
  38 clamp_int64(int64_t x, int64_t min, int64_t max)
  39 {
  40    if (x < min)
  41       return min;
  42    else if (x < max)
  43       return x;
  44    else
  45       return max;
  46 }
  47
  48 void
  49 gen7_cmd_buffer_emit_scissor(struct anv_cmd_buffer *cmd_buffer)
  50 {
  51    uint32_t count = cmd_buffer->state.dynamic.scissor.count;
  52    const VkRect2D *scissors =  cmd_buffer->state.dynamic.scissor.scissors;
  53    struct anv_state scissor_state =
  54       anv_cmd_buffer_alloc_dynamic_state(cmd_buffer, count * 8, 32);
  55
  56    for (uint32_t i = 0; i < count; i++) {
  57       const VkRect2D *s = &scissors[i];
  58
  59       /* Since xmax and ymax are inclusive, we have to have xmax < xmin or
  60        * ymax < ymin for empty clips.  In case clip x, y, width height are all
  61        * 0, the clamps below produce 0 for xmin, ymin, xmax, ymax, which isn't
  62        * what we want. Just special case empty clips and produce a canonical
  63        * empty clip. */
  64       static const struct GEN7_SCISSOR_RECT empty_scissor = {
  65          .ScissorRectangleYMin = 1,
  66          .ScissorRectangleXMin = 1,
  67          .ScissorRectangleYMax = 0,
  68          .ScissorRectangleXMax = 0
  69       };
  70
  71       const int max = 0xffff;
  72       struct GEN7_SCISSOR_RECT scissor = {
  73          /* Do this math using int64_t so overflow gets clamped correctly. */
  74          .ScissorRectangleYMin = clamp_int64(s->offset.y, 0, max),
  75          .ScissorRectangleXMin = clamp_int64(s->offset.x, 0, max),
  76          .ScissorRectangleYMax = clamp_int64((uint64_t) s->offset.y + s->extent.height - 1, 0, max),
  77          .ScissorRectangleXMax = clamp_int64((uint64_t) s->offset.x + s->extent.width - 1, 0, max)
  78       };
  79
  80       if (s->extent.width <= 0 || s->extent.height <= 0) {
  81          GEN7_SCISSOR_RECT_pack(NULL, scissor_state.map + i * 8,
  82                                 &empty_scissor);
  83       } else {
  84          GEN7_SCISSOR_RECT_pack(NULL, scissor_state.map + i * 8, &scissor);
  85       }
  86    }
  87
  88    anv_batch_emit(&cmd_buffer->batch,
  89                   GEN7_3DSTATE_SCISSOR_STATE_POINTERS, ssp) {
  90       ssp.ScissorRectPointer = scissor_state.offset;
  91    }
  92
  93    anv_state_flush(cmd_buffer->device, scissor_state);
  94 }
  95 #endif
  96
  97 static const uint32_t vk_to_gen_index_type[] = {
  98    [VK_INDEX_TYPE_UINT16]                       = INDEX_WORD,
  99    [VK_INDEX_TYPE_UINT32]                       = INDEX_DWORD,
 100 };
 101
 102 static const uint32_t restart_index_for_type[] = {
 103    [VK_INDEX_TYPE_UINT16]                    = UINT16_MAX,
 104    [VK_INDEX_TYPE_UINT32]                    = UINT32_MAX,
 105 };
 106
 107 void genX(CmdBindIndexBuffer)(
 108     VkCommandBuffer                             commandBuffer,
 109     VkBuffer                                    _buffer,
 110     VkDeviceSize                                offset,
 111     VkIndexType                                 indexType)
 112 {
 113    ANV_FROM_HANDLE(anv_cmd_buffer, cmd_buffer, commandBuffer);
 114    ANV_FROM_HANDLE(anv_buffer, buffer, _buffer);
 115
 116    cmd_buffer->state.dirty |= ANV_CMD_DIRTY_INDEX_BUFFER;
 117    if (GEN_IS_HASWELL)
 118       cmd_buffer->state.restart_index = restart_index_for_type[indexType];
 119    cmd_buffer->state.gen7.index_buffer = buffer;
 120    cmd_buffer->state.gen7.index_type = vk_to_gen_index_type[indexType];
 121    cmd_buffer->state.gen7.index_offset = offset;
 122 }
 123
 124 static uint32_t
 125 get_depth_format(struct anv_cmd_buffer *cmd_buffer)
 126 {
 127    const struct anv_render_pass *pass = cmd_buffer->state.pass;
 128    const struct anv_subpass *subpass = cmd_buffer->state.subpass;
 129
 130    if (subpass->depth_stencil_attachment.attachment >= pass->attachment_count)
 131       return D16_UNORM;
 132
 133    struct anv_render_pass_attachment *att =
 134       &pass->attachments[subpass->depth_stencil_attachment.attachment];
 135
 136    switch (att->format) {
 137    case VK_FORMAT_D16_UNORM:
 138    case VK_FORMAT_D16_UNORM_S8_UINT:
 139       return D16_UNORM;
 140
 141    case VK_FORMAT_X8_D24_UNORM_PACK32:
 142    case VK_FORMAT_D24_UNORM_S8_UINT:
 143       return D24_UNORM_X8_UINT;
 144
 145    case VK_FORMAT_D32_SFLOAT:
 146    case VK_FORMAT_D32_SFLOAT_S8_UINT:
 147       return D32_FLOAT;
 148
 149    default:
 150       return D16_UNORM;
 151    }
 152 }
 153
 154 void
 155 genX(cmd_buffer_flush_dynamic_state)(struct anv_cmd_buffer *cmd_buffer)
 156 {
 157    struct anv_pipeline *pipeline = cmd_buffer->state.gfx.base.pipeline;
 158
 159    if (cmd_buffer->state.dirty & (ANV_CMD_DIRTY_PIPELINE |
 160                                   ANV_CMD_DIRTY_RENDER_TARGETS |
 161                                   ANV_CMD_DIRTY_DYNAMIC_LINE_WIDTH |
 162                                   ANV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS)) {
 163       uint32_t sf_dw[GENX(3DSTATE_SF_length)];
 164       struct GENX(3DSTATE_SF) sf = {
 165          GENX(3DSTATE_SF_header),
 166          .DepthBufferSurfaceFormat = get_depth_format(cmd_buffer),
 167          .LineWidth = cmd_buffer->state.dynamic.line_width,
 168          .GlobalDepthOffsetConstant = cmd_buffer->state.dynamic.depth_bias.bias,
 169          .GlobalDepthOffsetScale = cmd_buffer->state.dynamic.depth_bias.slope,
 170          .GlobalDepthOffsetClamp = cmd_buffer->state.dynamic.depth_bias.clamp
 171       };
 172       GENX(3DSTATE_SF_pack)(NULL, sf_dw, &sf);
 173
 174       anv_batch_emit_merge(&cmd_buffer->batch, sf_dw, pipeline->gen7.sf);
 175    }
 176
 177    if (cmd_buffer->state.dirty & (ANV_CMD_DIRTY_DYNAMIC_BLEND_CONSTANTS |
 178                                   ANV_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE)) {
 179       struct anv_dynamic_state *d = &cmd_buffer->state.dynamic;
 180       struct anv_state cc_state =
 181          anv_cmd_buffer_alloc_dynamic_state(cmd_buffer,
 182                                             GENX(COLOR_CALC_STATE_length) * 4,
 183                                             64);
 184       struct GENX(COLOR_CALC_STATE) cc = {
 185          .BlendConstantColorRed = cmd_buffer->state.dynamic.blend_constants[0],
 186          .BlendConstantColorGreen = cmd_buffer->state.dynamic.blend_constants[1],
 187          .BlendConstantColorBlue = cmd_buffer->state.dynamic.blend_constants[2],
 188          .BlendConstantColorAlpha = cmd_buffer->state.dynamic.blend_constants[3],
 189          .StencilReferenceValue = d->stencil_reference.front & 0xff,
 190          .BackfaceStencilReferenceValue = d->stencil_reference.back & 0xff,
 191       };
 192       GENX(COLOR_CALC_STATE_pack)(NULL, cc_state.map, &cc);
 193       anv_state_flush(cmd_buffer->device, cc_state);
 194
 195       anv_batch_emit(&cmd_buffer->batch, GENX(3DSTATE_CC_STATE_POINTERS), ccp) {
 196          ccp.ColorCalcStatePointer = cc_state.offset;
 197       }
 198    }
 199
 200    if (cmd_buffer->state.dirty & (ANV_CMD_DIRTY_PIPELINE |
 201                                   ANV_CMD_DIRTY_RENDER_TARGETS |
 202                                   ANV_CMD_DIRTY_DYNAMIC_STENCIL_COMPARE_MASK |
 203                                   ANV_CMD_DIRTY_DYNAMIC_STENCIL_WRITE_MASK)) {
 204       uint32_t depth_stencil_dw[GENX(DEPTH_STENCIL_STATE_length)];
 205       struct anv_dynamic_state *d = &cmd_buffer->state.dynamic;
 206
 207       struct GENX(DEPTH_STENCIL_STATE) depth_stencil = {
 208          .StencilTestMask = d->stencil_compare_mask.front & 0xff,
 209          .StencilWriteMask = d->stencil_write_mask.front & 0xff,
 210
 211          .BackfaceStencilTestMask = d->stencil_compare_mask.back & 0xff,
 212          .BackfaceStencilWriteMask = d->stencil_write_mask.back & 0xff,
 213
 214          .StencilBufferWriteEnable =
 215             (d->stencil_write_mask.front || d->stencil_write_mask.back) &&
 216             pipeline->writes_stencil,
 217       };
 218       GENX(DEPTH_STENCIL_STATE_pack)(NULL, depth_stencil_dw, &depth_stencil);
 219
 220       struct anv_state ds_state =
 221          anv_cmd_buffer_merge_dynamic(cmd_buffer, depth_stencil_dw,
 222                                       pipeline->gen7.depth_stencil_state,
 223                                       GENX(DEPTH_STENCIL_STATE_length), 64);
 224
 225       anv_batch_emit(&cmd_buffer->batch,
 226                      GENX(3DSTATE_DEPTH_STENCIL_STATE_POINTERS), dsp) {
 227          dsp.PointertoDEPTH_STENCIL_STATE = ds_state.offset;
 228       }
 229    }
 230
 231    if (cmd_buffer->state.gen7.index_buffer &&
 232        cmd_buffer->state.dirty & (ANV_CMD_DIRTY_PIPELINE |
 233                                   ANV_CMD_DIRTY_INDEX_BUFFER)) {
 234       struct anv_buffer *buffer = cmd_buffer->state.gen7.index_buffer;
 235       uint32_t offset = cmd_buffer->state.gen7.index_offset;
 236
 237 #if GEN_IS_HASWELL
 238       anv_batch_emit(&cmd_buffer->batch, GEN75_3DSTATE_VF, vf) {
 239          vf.IndexedDrawCutIndexEnable  = pipeline->primitive_restart;
 240          vf.CutIndex                   = cmd_buffer->state.restart_index;
 241       }
 242 #endif
 243
 244       anv_batch_emit(&cmd_buffer->batch, GENX(3DSTATE_INDEX_BUFFER), ib) {
 245 #if !GEN_IS_HASWELL
 246          ib.CutIndexEnable             = pipeline->primitive_restart;
 247 #endif
 248          ib.IndexFormat                = cmd_buffer->state.gen7.index_type;
 249          ib.MemoryObjectControlState   = GENX(MOCS);
 250
 251          ib.BufferStartingAddress =
 252             (struct anv_address) { buffer->bo, buffer->offset + offset };
 253          ib.BufferEndingAddress =
 254             (struct anv_address) { buffer->bo, buffer->offset + buffer->size };
 255       }
 256    }
 257
 258    cmd_buffer->state.dirty = 0;
 259 }
 260
 261 void
 262 genX(cmd_buffer_enable_pma_fix)(struct anv_cmd_buffer *cmd_buffer,
 263                                 bool enable)
 264 {
 265    /* The NP PMA fix doesn't exist on gen7 */
 266 }
 267
 268 void genX(CmdSetEvent)(
 269     VkCommandBuffer                             commandBuffer,
 270     VkEvent                                     event,
 271     VkPipelineStageFlags                        stageMask)
 272 {
 273    anv_finishme("Implement events on gen7");
 274 }
 275
 276 void genX(CmdResetEvent)(
 277     VkCommandBuffer                             commandBuffer,
 278     VkEvent                                     event,
 279     VkPipelineStageFlags                        stageMask)
 280 {
 281    anv_finishme("Implement events on gen7");
 282 }
 283
 284 void genX(CmdWaitEvents)(
 285     VkCommandBuffer                             commandBuffer,
 286     uint32_t                                    eventCount,
 287     const VkEvent*                              pEvents,
 288     VkPipelineStageFlags                        srcStageMask,
 289     VkPipelineStageFlags                        destStageMask,
 290     uint32_t                                    memoryBarrierCount,
 291     const VkMemoryBarrier*                      pMemoryBarriers,
 292     uint32_t                                    bufferMemoryBarrierCount,
 293     const VkBufferMemoryBarrier*                pBufferMemoryBarriers,
 294     uint32_t                                    imageMemoryBarrierCount,
 295     const VkImageMemoryBarrier*                 pImageMemoryBarriers)
 296 {
 297    anv_finishme("Implement events on gen7");
 298
 299    genX(CmdPipelineBarrier)(commandBuffer, srcStageMask, destStageMask,
 300                             false, /* byRegion */
 301                             memoryBarrierCount, pMemoryBarriers,
 302                             bufferMemoryBarrierCount, pBufferMemoryBarriers,
 303                             imageMemoryBarrierCount, pImageMemoryBarriers);
 304 }