2 * Copyright © 2015 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
27 #include "anv_private.h"
28 #include "vk_format_info.h"
31 #include "common/gen_l3_config.h"
32 #include "genxml/gen_macros.h"
33 #include "genxml/genX_pack.h"
36 emit_lrm(struct anv_batch
*batch
, uint32_t reg
, struct anv_address addr
)
38 anv_batch_emit(batch
, GENX(MI_LOAD_REGISTER_MEM
), lrm
) {
39 lrm
.RegisterAddress
= reg
;
40 lrm
.MemoryAddress
= addr
;
45 emit_lri(struct anv_batch
*batch
, uint32_t reg
, uint32_t imm
)
47 anv_batch_emit(batch
, GENX(MI_LOAD_REGISTER_IMM
), lri
) {
48 lri
.RegisterOffset
= reg
;
53 #if GEN_IS_HASWELL || GEN_GEN >= 8
55 emit_lrr(struct anv_batch
*batch
, uint32_t dst
, uint32_t src
)
57 anv_batch_emit(batch
, GENX(MI_LOAD_REGISTER_REG
), lrr
) {
58 lrr
.SourceRegisterAddress
= src
;
59 lrr
.DestinationRegisterAddress
= dst
;
65 genX(cmd_buffer_emit_state_base_address
)(struct anv_cmd_buffer
*cmd_buffer
)
67 struct anv_device
*device
= cmd_buffer
->device
;
69 /* If we are emitting a new state base address we probably need to re-emit
72 cmd_buffer
->state
.descriptors_dirty
|= ~0;
74 /* Emit a render target cache flush.
76 * This isn't documented anywhere in the PRM. However, it seems to be
77 * necessary prior to changing the surface state base adress. Without
78 * this, we get GPU hangs when using multi-level command buffers which
79 * clear depth, reset state base address, and then go render stuff.
81 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pc
) {
82 pc
.DCFlushEnable
= true;
83 pc
.RenderTargetCacheFlushEnable
= true;
84 pc
.CommandStreamerStallEnable
= true;
87 anv_batch_emit(&cmd_buffer
->batch
, GENX(STATE_BASE_ADDRESS
), sba
) {
88 sba
.GeneralStateBaseAddress
= (struct anv_address
) { NULL
, 0 };
89 sba
.GeneralStateMemoryObjectControlState
= GENX(MOCS
);
90 sba
.GeneralStateBaseAddressModifyEnable
= true;
92 sba
.SurfaceStateBaseAddress
=
93 anv_cmd_buffer_surface_base_address(cmd_buffer
);
94 sba
.SurfaceStateMemoryObjectControlState
= GENX(MOCS
);
95 sba
.SurfaceStateBaseAddressModifyEnable
= true;
97 sba
.DynamicStateBaseAddress
=
98 (struct anv_address
) { &device
->dynamic_state_pool
.block_pool
.bo
, 0 };
99 sba
.DynamicStateMemoryObjectControlState
= GENX(MOCS
);
100 sba
.DynamicStateBaseAddressModifyEnable
= true;
102 sba
.IndirectObjectBaseAddress
= (struct anv_address
) { NULL
, 0 };
103 sba
.IndirectObjectMemoryObjectControlState
= GENX(MOCS
);
104 sba
.IndirectObjectBaseAddressModifyEnable
= true;
106 sba
.InstructionBaseAddress
=
107 (struct anv_address
) { &device
->instruction_state_pool
.block_pool
.bo
, 0 };
108 sba
.InstructionMemoryObjectControlState
= GENX(MOCS
);
109 sba
.InstructionBaseAddressModifyEnable
= true;
112 /* Broadwell requires that we specify a buffer size for a bunch of
113 * these fields. However, since we will be growing the BO's live, we
114 * just set them all to the maximum.
116 sba
.GeneralStateBufferSize
= 0xfffff;
117 sba
.GeneralStateBufferSizeModifyEnable
= true;
118 sba
.DynamicStateBufferSize
= 0xfffff;
119 sba
.DynamicStateBufferSizeModifyEnable
= true;
120 sba
.IndirectObjectBufferSize
= 0xfffff;
121 sba
.IndirectObjectBufferSizeModifyEnable
= true;
122 sba
.InstructionBufferSize
= 0xfffff;
123 sba
.InstructionBuffersizeModifyEnable
= true;
126 sba
.BindlessSurfaceStateBaseAddress
= (struct anv_address
) { NULL
, 0 };
127 sba
.BindlessSurfaceStateMemoryObjectControlState
= GENX(MOCS
);
128 sba
.BindlessSurfaceStateBaseAddressModifyEnable
= true;
129 sba
.BindlessSurfaceStateSize
= 0;
132 sba
.BindlessSamplerStateBaseAddress
= (struct anv_address
) { NULL
, 0 };
133 sba
.BindlessSamplerStateMemoryObjectControlState
= GENX(MOCS
);
134 sba
.BindlessSamplerStateBaseAddressModifyEnable
= true;
135 sba
.BindlessSamplerStateBufferSize
= 0;
139 /* After re-setting the surface state base address, we have to do some
140 * cache flusing so that the sampler engine will pick up the new
141 * SURFACE_STATE objects and binding tables. From the Broadwell PRM,
142 * Shared Function > 3D Sampler > State > State Caching (page 96):
144 * Coherency with system memory in the state cache, like the texture
145 * cache is handled partially by software. It is expected that the
146 * command stream or shader will issue Cache Flush operation or
147 * Cache_Flush sampler message to ensure that the L1 cache remains
148 * coherent with system memory.
152 * Whenever the value of the Dynamic_State_Base_Addr,
153 * Surface_State_Base_Addr are altered, the L1 state cache must be
154 * invalidated to ensure the new surface or sampler state is fetched
155 * from system memory.
157 * The PIPE_CONTROL command has a "State Cache Invalidation Enable" bit
158 * which, according the PIPE_CONTROL instruction documentation in the
161 * Setting this bit is independent of any other bit in this packet.
162 * This bit controls the invalidation of the L1 and L2 state caches
163 * at the top of the pipe i.e. at the parsing time.
165 * Unfortunately, experimentation seems to indicate that state cache
166 * invalidation through a PIPE_CONTROL does nothing whatsoever in
167 * regards to surface state and binding tables. In stead, it seems that
168 * invalidating the texture cache is what is actually needed.
170 * XXX: As far as we have been able to determine through
171 * experimentation, shows that flush the texture cache appears to be
172 * sufficient. The theory here is that all of the sampling/rendering
173 * units cache the binding table in the texture cache. However, we have
174 * yet to be able to actually confirm this.
176 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pc
) {
177 pc
.TextureCacheInvalidationEnable
= true;
178 pc
.ConstantCacheInvalidationEnable
= true;
179 pc
.StateCacheInvalidationEnable
= true;
184 add_surface_reloc(struct anv_cmd_buffer
*cmd_buffer
,
185 struct anv_state state
, struct anv_address addr
)
187 const struct isl_device
*isl_dev
= &cmd_buffer
->device
->isl_dev
;
190 anv_reloc_list_add(&cmd_buffer
->surface_relocs
, &cmd_buffer
->pool
->alloc
,
191 state
.offset
+ isl_dev
->ss
.addr_offset
,
192 addr
.bo
, addr
.offset
);
193 if (result
!= VK_SUCCESS
)
194 anv_batch_set_error(&cmd_buffer
->batch
, result
);
198 add_surface_state_relocs(struct anv_cmd_buffer
*cmd_buffer
,
199 struct anv_surface_state state
)
201 const struct isl_device
*isl_dev
= &cmd_buffer
->device
->isl_dev
;
203 assert(!anv_address_is_null(state
.address
));
204 add_surface_reloc(cmd_buffer
, state
.state
, state
.address
);
206 if (!anv_address_is_null(state
.aux_address
)) {
208 anv_reloc_list_add(&cmd_buffer
->surface_relocs
,
209 &cmd_buffer
->pool
->alloc
,
210 state
.state
.offset
+ isl_dev
->ss
.aux_addr_offset
,
211 state
.aux_address
.bo
, state
.aux_address
.offset
);
212 if (result
!= VK_SUCCESS
)
213 anv_batch_set_error(&cmd_buffer
->batch
, result
);
216 if (!anv_address_is_null(state
.clear_address
)) {
218 anv_reloc_list_add(&cmd_buffer
->surface_relocs
,
219 &cmd_buffer
->pool
->alloc
,
221 isl_dev
->ss
.clear_color_state_offset
,
222 state
.clear_address
.bo
, state
.clear_address
.offset
);
223 if (result
!= VK_SUCCESS
)
224 anv_batch_set_error(&cmd_buffer
->batch
, result
);
229 color_attachment_compute_aux_usage(struct anv_device
* device
,
230 struct anv_cmd_state
* cmd_state
,
231 uint32_t att
, VkRect2D render_area
,
232 union isl_color_value
*fast_clear_color
)
234 struct anv_attachment_state
*att_state
= &cmd_state
->attachments
[att
];
235 struct anv_image_view
*iview
= cmd_state
->framebuffer
->attachments
[att
];
237 assert(iview
->n_planes
== 1);
239 if (iview
->planes
[0].isl
.base_array_layer
>=
240 anv_image_aux_layers(iview
->image
, VK_IMAGE_ASPECT_COLOR_BIT
,
241 iview
->planes
[0].isl
.base_level
)) {
242 /* There is no aux buffer which corresponds to the level and layer(s)
245 att_state
->aux_usage
= ISL_AUX_USAGE_NONE
;
246 att_state
->input_aux_usage
= ISL_AUX_USAGE_NONE
;
247 att_state
->fast_clear
= false;
251 att_state
->aux_usage
=
252 anv_layout_to_aux_usage(&device
->info
, iview
->image
,
253 VK_IMAGE_ASPECT_COLOR_BIT
,
254 VK_IMAGE_LAYOUT_COLOR_ATTACHMENT_OPTIMAL
);
256 /* If we don't have aux, then we should have returned early in the layer
257 * check above. If we got here, we must have something.
259 assert(att_state
->aux_usage
!= ISL_AUX_USAGE_NONE
);
261 if (att_state
->aux_usage
== ISL_AUX_USAGE_CCS_E
||
262 att_state
->aux_usage
== ISL_AUX_USAGE_MCS
) {
263 att_state
->input_aux_usage
= att_state
->aux_usage
;
265 /* From the Sky Lake PRM, RENDER_SURFACE_STATE::AuxiliarySurfaceMode:
267 * "If Number of Multisamples is MULTISAMPLECOUNT_1, AUX_CCS_D
268 * setting is only allowed if Surface Format supported for Fast
269 * Clear. In addition, if the surface is bound to the sampling
270 * engine, Surface Format must be supported for Render Target
271 * Compression for surfaces bound to the sampling engine."
273 * In other words, we can only sample from a fast-cleared image if it
274 * also supports color compression.
276 if (isl_format_supports_ccs_e(&device
->info
, iview
->planes
[0].isl
.format
)) {
277 att_state
->input_aux_usage
= ISL_AUX_USAGE_CCS_D
;
279 /* While fast-clear resolves and partial resolves are fairly cheap in the
280 * case where you render to most of the pixels, full resolves are not
281 * because they potentially involve reading and writing the entire
282 * framebuffer. If we can't texture with CCS_E, we should leave it off and
283 * limit ourselves to fast clears.
285 if (cmd_state
->pass
->attachments
[att
].first_subpass_layout
==
286 VK_IMAGE_LAYOUT_COLOR_ATTACHMENT_OPTIMAL
) {
287 anv_perf_warn(device
->instance
, iview
->image
,
288 "Not temporarily enabling CCS_E.");
291 att_state
->input_aux_usage
= ISL_AUX_USAGE_NONE
;
295 assert(iview
->image
->planes
[0].aux_surface
.isl
.usage
&
296 (ISL_SURF_USAGE_CCS_BIT
| ISL_SURF_USAGE_MCS_BIT
));
298 union isl_color_value clear_color
= {};
299 anv_clear_color_from_att_state(&clear_color
, att_state
, iview
);
301 att_state
->clear_color_is_zero_one
=
302 isl_color_value_is_zero_one(clear_color
, iview
->planes
[0].isl
.format
);
303 att_state
->clear_color_is_zero
=
304 isl_color_value_is_zero(clear_color
, iview
->planes
[0].isl
.format
);
306 if (att_state
->pending_clear_aspects
== VK_IMAGE_ASPECT_COLOR_BIT
) {
307 /* Start by getting the fast clear type. We use the first subpass
308 * layout here because we don't want to fast-clear if the first subpass
309 * to use the attachment can't handle fast-clears.
311 enum anv_fast_clear_type fast_clear_type
=
312 anv_layout_to_fast_clear_type(&device
->info
, iview
->image
,
313 VK_IMAGE_ASPECT_COLOR_BIT
,
314 cmd_state
->pass
->attachments
[att
].first_subpass_layout
);
315 switch (fast_clear_type
) {
316 case ANV_FAST_CLEAR_NONE
:
317 att_state
->fast_clear
= false;
319 case ANV_FAST_CLEAR_DEFAULT_VALUE
:
320 att_state
->fast_clear
= att_state
->clear_color_is_zero
;
322 case ANV_FAST_CLEAR_ANY
:
323 att_state
->fast_clear
= true;
327 /* Potentially, we could do partial fast-clears but doing so has crazy
328 * alignment restrictions. It's easier to just restrict to full size
329 * fast clears for now.
331 if (render_area
.offset
.x
!= 0 ||
332 render_area
.offset
.y
!= 0 ||
333 render_area
.extent
.width
!= iview
->extent
.width
||
334 render_area
.extent
.height
!= iview
->extent
.height
)
335 att_state
->fast_clear
= false;
337 /* On Broadwell and earlier, we can only handle 0/1 clear colors */
338 if (GEN_GEN
<= 8 && !att_state
->clear_color_is_zero_one
)
339 att_state
->fast_clear
= false;
341 /* We only allow fast clears to the first slice of an image (level 0,
342 * layer 0) and only for the entire slice. This guarantees us that, at
343 * any given time, there is only one clear color on any given image at
344 * any given time. At the time of our testing (Jan 17, 2018), there
345 * were no known applications which would benefit from fast-clearing
346 * more than just the first slice.
348 if (att_state
->fast_clear
&&
349 (iview
->planes
[0].isl
.base_level
> 0 ||
350 iview
->planes
[0].isl
.base_array_layer
> 0)) {
351 anv_perf_warn(device
->instance
, iview
->image
,
352 "Rendering with multi-lod or multi-layer framebuffer "
353 "with LOAD_OP_LOAD and baseMipLevel > 0 or "
354 "baseArrayLayer > 0. Not fast clearing.");
355 att_state
->fast_clear
= false;
356 } else if (att_state
->fast_clear
&& cmd_state
->framebuffer
->layers
> 1) {
357 anv_perf_warn(device
->instance
, iview
->image
,
358 "Rendering to a multi-layer framebuffer with "
359 "LOAD_OP_CLEAR. Only fast-clearing the first slice");
362 if (att_state
->fast_clear
)
363 *fast_clear_color
= clear_color
;
365 att_state
->fast_clear
= false;
370 depth_stencil_attachment_compute_aux_usage(struct anv_device
*device
,
371 struct anv_cmd_state
*cmd_state
,
372 uint32_t att
, VkRect2D render_area
)
374 struct anv_render_pass_attachment
*pass_att
=
375 &cmd_state
->pass
->attachments
[att
];
376 struct anv_attachment_state
*att_state
= &cmd_state
->attachments
[att
];
377 struct anv_image_view
*iview
= cmd_state
->framebuffer
->attachments
[att
];
379 /* These will be initialized after the first subpass transition. */
380 att_state
->aux_usage
= ISL_AUX_USAGE_NONE
;
381 att_state
->input_aux_usage
= ISL_AUX_USAGE_NONE
;
384 /* We don't do any HiZ or depth fast-clears on gen7 yet */
385 att_state
->fast_clear
= false;
389 if (!(att_state
->pending_clear_aspects
& VK_IMAGE_ASPECT_DEPTH_BIT
)) {
390 /* If we're just clearing stencil, we can always HiZ clear */
391 att_state
->fast_clear
= true;
395 /* Default to false for now */
396 att_state
->fast_clear
= false;
398 /* We must have depth in order to have HiZ */
399 if (!(iview
->image
->aspects
& VK_IMAGE_ASPECT_DEPTH_BIT
))
402 const enum isl_aux_usage first_subpass_aux_usage
=
403 anv_layout_to_aux_usage(&device
->info
, iview
->image
,
404 VK_IMAGE_ASPECT_DEPTH_BIT
,
405 pass_att
->first_subpass_layout
);
406 if (first_subpass_aux_usage
!= ISL_AUX_USAGE_HIZ
)
409 if (!blorp_can_hiz_clear_depth(GEN_GEN
,
410 iview
->planes
[0].isl
.format
,
411 iview
->image
->samples
,
412 render_area
.offset
.x
,
413 render_area
.offset
.y
,
414 render_area
.offset
.x
+
415 render_area
.extent
.width
,
416 render_area
.offset
.y
+
417 render_area
.extent
.height
))
420 if (att_state
->clear_value
.depthStencil
.depth
!= ANV_HZ_FC_VAL
)
423 if (GEN_GEN
== 8 && anv_can_sample_with_hiz(&device
->info
, iview
->image
)) {
424 /* Only gen9+ supports returning ANV_HZ_FC_VAL when sampling a
425 * fast-cleared portion of a HiZ buffer. Testing has revealed that Gen8
426 * only supports returning 0.0f. Gens prior to gen8 do not support this
432 /* If we got here, then we can fast clear */
433 att_state
->fast_clear
= true;
437 need_input_attachment_state(const struct anv_render_pass_attachment
*att
)
439 if (!(att
->usage
& VK_IMAGE_USAGE_INPUT_ATTACHMENT_BIT
))
442 /* We only allocate input attachment states for color surfaces. Compression
443 * is not yet enabled for depth textures and stencil doesn't allow
444 * compression so we can just use the texture surface state from the view.
446 return vk_format_is_color(att
->format
);
449 /* Transitions a HiZ-enabled depth buffer from one layout to another. Unless
450 * the initial layout is undefined, the HiZ buffer and depth buffer will
451 * represent the same data at the end of this operation.
454 transition_depth_buffer(struct anv_cmd_buffer
*cmd_buffer
,
455 const struct anv_image
*image
,
456 VkImageLayout initial_layout
,
457 VkImageLayout final_layout
)
459 const bool hiz_enabled
= ISL_AUX_USAGE_HIZ
==
460 anv_layout_to_aux_usage(&cmd_buffer
->device
->info
, image
,
461 VK_IMAGE_ASPECT_DEPTH_BIT
, initial_layout
);
462 const bool enable_hiz
= ISL_AUX_USAGE_HIZ
==
463 anv_layout_to_aux_usage(&cmd_buffer
->device
->info
, image
,
464 VK_IMAGE_ASPECT_DEPTH_BIT
, final_layout
);
466 enum isl_aux_op hiz_op
;
467 if (hiz_enabled
&& !enable_hiz
) {
468 hiz_op
= ISL_AUX_OP_FULL_RESOLVE
;
469 } else if (!hiz_enabled
&& enable_hiz
) {
470 hiz_op
= ISL_AUX_OP_AMBIGUATE
;
472 assert(hiz_enabled
== enable_hiz
);
473 /* If the same buffer will be used, no resolves are necessary. */
474 hiz_op
= ISL_AUX_OP_NONE
;
477 if (hiz_op
!= ISL_AUX_OP_NONE
)
478 anv_image_hiz_op(cmd_buffer
, image
, VK_IMAGE_ASPECT_DEPTH_BIT
,
482 #define MI_PREDICATE_SRC0 0x2400
483 #define MI_PREDICATE_SRC1 0x2408
486 set_image_compressed_bit(struct anv_cmd_buffer
*cmd_buffer
,
487 const struct anv_image
*image
,
488 VkImageAspectFlagBits aspect
,
490 uint32_t base_layer
, uint32_t layer_count
,
493 uint32_t plane
= anv_image_aspect_to_plane(image
->aspects
, aspect
);
495 /* We only have compression tracking for CCS_E */
496 if (image
->planes
[plane
].aux_usage
!= ISL_AUX_USAGE_CCS_E
)
499 for (uint32_t a
= 0; a
< layer_count
; a
++) {
500 uint32_t layer
= base_layer
+ a
;
501 anv_batch_emit(&cmd_buffer
->batch
, GENX(MI_STORE_DATA_IMM
), sdi
) {
502 sdi
.Address
= anv_image_get_compression_state_addr(cmd_buffer
->device
,
505 sdi
.ImmediateData
= compressed
? UINT32_MAX
: 0;
511 set_image_fast_clear_state(struct anv_cmd_buffer
*cmd_buffer
,
512 const struct anv_image
*image
,
513 VkImageAspectFlagBits aspect
,
514 enum anv_fast_clear_type fast_clear
)
516 anv_batch_emit(&cmd_buffer
->batch
, GENX(MI_STORE_DATA_IMM
), sdi
) {
517 sdi
.Address
= anv_image_get_fast_clear_type_addr(cmd_buffer
->device
,
519 sdi
.ImmediateData
= fast_clear
;
522 /* Whenever we have fast-clear, we consider that slice to be compressed.
523 * This makes building predicates much easier.
525 if (fast_clear
!= ANV_FAST_CLEAR_NONE
)
526 set_image_compressed_bit(cmd_buffer
, image
, aspect
, 0, 0, 1, true);
529 #if GEN_IS_HASWELL || GEN_GEN >= 8
530 static inline uint32_t
531 mi_alu(uint32_t opcode
, uint32_t operand1
, uint32_t operand2
)
533 struct GENX(MI_MATH_ALU_INSTRUCTION
) instr
= {
535 .Operand1
= operand1
,
536 .Operand2
= operand2
,
540 GENX(MI_MATH_ALU_INSTRUCTION_pack
)(NULL
, &dw
, &instr
);
546 #define CS_GPR(n) (0x2600 + (n) * 8)
548 /* This is only really practical on haswell and above because it requires
549 * MI math in order to get it correct.
551 #if GEN_GEN >= 8 || GEN_IS_HASWELL
553 anv_cmd_compute_resolve_predicate(struct anv_cmd_buffer
*cmd_buffer
,
554 const struct anv_image
*image
,
555 VkImageAspectFlagBits aspect
,
556 uint32_t level
, uint32_t array_layer
,
557 enum isl_aux_op resolve_op
,
558 enum anv_fast_clear_type fast_clear_supported
)
560 struct anv_address fast_clear_type_addr
=
561 anv_image_get_fast_clear_type_addr(cmd_buffer
->device
, image
, aspect
);
563 /* Name some registers */
564 const int image_fc_reg
= MI_ALU_REG0
;
565 const int fc_imm_reg
= MI_ALU_REG1
;
566 const int pred_reg
= MI_ALU_REG2
;
570 if (resolve_op
== ISL_AUX_OP_FULL_RESOLVE
) {
571 /* In this case, we're doing a full resolve which means we want the
572 * resolve to happen if any compression (including fast-clears) is
575 * In order to simplify the logic a bit, we make the assumption that,
576 * if the first slice has been fast-cleared, it is also marked as
577 * compressed. See also set_image_fast_clear_state.
579 struct anv_address compression_state_addr
=
580 anv_image_get_compression_state_addr(cmd_buffer
->device
, image
,
581 aspect
, level
, array_layer
);
582 anv_batch_emit(&cmd_buffer
->batch
, GENX(MI_LOAD_REGISTER_MEM
), lrm
) {
583 lrm
.RegisterAddress
= MI_PREDICATE_SRC0
;
584 lrm
.MemoryAddress
= compression_state_addr
;
586 anv_batch_emit(&cmd_buffer
->batch
, GENX(MI_STORE_DATA_IMM
), sdi
) {
587 sdi
.Address
= compression_state_addr
;
588 sdi
.ImmediateData
= 0;
591 if (level
== 0 && array_layer
== 0) {
592 /* If the predicate is true, we want to write 0 to the fast clear type
593 * and, if it's false, leave it alone. We can do this by writing
595 * clear_type = clear_type & ~predicate;
597 anv_batch_emit(&cmd_buffer
->batch
, GENX(MI_LOAD_REGISTER_MEM
), lrm
) {
598 lrm
.RegisterAddress
= CS_GPR(image_fc_reg
);
599 lrm
.MemoryAddress
= fast_clear_type_addr
;
601 anv_batch_emit(&cmd_buffer
->batch
, GENX(MI_LOAD_REGISTER_REG
), lrr
) {
602 lrr
.DestinationRegisterAddress
= CS_GPR(pred_reg
);
603 lrr
.SourceRegisterAddress
= MI_PREDICATE_SRC0
;
606 dw
= anv_batch_emitn(&cmd_buffer
->batch
, 5, GENX(MI_MATH
));
607 dw
[1] = mi_alu(MI_ALU_LOAD
, MI_ALU_SRCA
, image_fc_reg
);
608 dw
[2] = mi_alu(MI_ALU_LOADINV
, MI_ALU_SRCB
, pred_reg
);
609 dw
[3] = mi_alu(MI_ALU_AND
, 0, 0);
610 dw
[4] = mi_alu(MI_ALU_STORE
, image_fc_reg
, MI_ALU_ACCU
);
612 anv_batch_emit(&cmd_buffer
->batch
, GENX(MI_STORE_REGISTER_MEM
), srm
) {
613 srm
.MemoryAddress
= fast_clear_type_addr
;
614 srm
.RegisterAddress
= CS_GPR(image_fc_reg
);
617 } else if (level
== 0 && array_layer
== 0) {
618 /* In this case, we are doing a partial resolve to get rid of fast-clear
619 * colors. We don't care about the compression state but we do care
620 * about how much fast clear is allowed by the final layout.
622 assert(resolve_op
== ISL_AUX_OP_PARTIAL_RESOLVE
);
623 assert(fast_clear_supported
< ANV_FAST_CLEAR_ANY
);
625 anv_batch_emit(&cmd_buffer
->batch
, GENX(MI_LOAD_REGISTER_MEM
), lrm
) {
626 lrm
.RegisterAddress
= CS_GPR(image_fc_reg
);
627 lrm
.MemoryAddress
= fast_clear_type_addr
;
629 emit_lri(&cmd_buffer
->batch
, CS_GPR(image_fc_reg
) + 4, 0);
631 emit_lri(&cmd_buffer
->batch
, CS_GPR(fc_imm_reg
), fast_clear_supported
);
632 emit_lri(&cmd_buffer
->batch
, CS_GPR(fc_imm_reg
) + 4, 0);
634 /* We need to compute (fast_clear_supported < image->fast_clear).
635 * We do this by subtracting and storing the carry bit.
637 dw
= anv_batch_emitn(&cmd_buffer
->batch
, 5, GENX(MI_MATH
));
638 dw
[1] = mi_alu(MI_ALU_LOAD
, MI_ALU_SRCA
, fc_imm_reg
);
639 dw
[2] = mi_alu(MI_ALU_LOAD
, MI_ALU_SRCB
, image_fc_reg
);
640 dw
[3] = mi_alu(MI_ALU_SUB
, 0, 0);
641 dw
[4] = mi_alu(MI_ALU_STORE
, pred_reg
, MI_ALU_CF
);
643 /* Store the predicate */
644 emit_lrr(&cmd_buffer
->batch
, MI_PREDICATE_SRC0
, CS_GPR(pred_reg
));
646 /* If the predicate is true, we want to write 0 to the fast clear type
647 * and, if it's false, leave it alone. We can do this by writing
649 * clear_type = clear_type & ~predicate;
651 dw
= anv_batch_emitn(&cmd_buffer
->batch
, 5, GENX(MI_MATH
));
652 dw
[1] = mi_alu(MI_ALU_LOAD
, MI_ALU_SRCA
, image_fc_reg
);
653 dw
[2] = mi_alu(MI_ALU_LOADINV
, MI_ALU_SRCB
, pred_reg
);
654 dw
[3] = mi_alu(MI_ALU_AND
, 0, 0);
655 dw
[4] = mi_alu(MI_ALU_STORE
, image_fc_reg
, MI_ALU_ACCU
);
657 anv_batch_emit(&cmd_buffer
->batch
, GENX(MI_STORE_REGISTER_MEM
), srm
) {
658 srm
.RegisterAddress
= CS_GPR(image_fc_reg
);
659 srm
.MemoryAddress
= fast_clear_type_addr
;
662 /* In this case, we're trying to do a partial resolve on a slice that
663 * doesn't have clear color. There's nothing to do.
665 assert(resolve_op
== ISL_AUX_OP_PARTIAL_RESOLVE
);
669 /* We use the first half of src0 for the actual predicate. Set the second
670 * half of src0 and all of src1 to 0 as the predicate operation will be
671 * doing an implicit src0 != src1.
673 emit_lri(&cmd_buffer
->batch
, MI_PREDICATE_SRC0
+ 4, 0);
674 emit_lri(&cmd_buffer
->batch
, MI_PREDICATE_SRC1
, 0);
675 emit_lri(&cmd_buffer
->batch
, MI_PREDICATE_SRC1
+ 4, 0);
677 anv_batch_emit(&cmd_buffer
->batch
, GENX(MI_PREDICATE
), mip
) {
678 mip
.LoadOperation
= LOAD_LOADINV
;
679 mip
.CombineOperation
= COMBINE_SET
;
680 mip
.CompareOperation
= COMPARE_SRCS_EQUAL
;
683 #endif /* GEN_GEN >= 8 || GEN_IS_HASWELL */
687 anv_cmd_simple_resolve_predicate(struct anv_cmd_buffer
*cmd_buffer
,
688 const struct anv_image
*image
,
689 VkImageAspectFlagBits aspect
,
690 uint32_t level
, uint32_t array_layer
,
691 enum isl_aux_op resolve_op
,
692 enum anv_fast_clear_type fast_clear_supported
)
694 struct anv_address fast_clear_type_addr
=
695 anv_image_get_fast_clear_type_addr(cmd_buffer
->device
, image
, aspect
);
697 /* This only works for partial resolves and only when the clear color is
698 * all or nothing. On the upside, this emits less command streamer code
699 * and works on Ivybridge and Bay Trail.
701 assert(resolve_op
== ISL_AUX_OP_PARTIAL_RESOLVE
);
702 assert(fast_clear_supported
!= ANV_FAST_CLEAR_ANY
);
704 /* We don't support fast clears on anything other than the first slice. */
705 if (level
> 0 || array_layer
> 0)
708 /* On gen8, we don't have a concept of default clear colors because we
709 * can't sample from CCS surfaces. It's enough to just load the fast clear
710 * state into the predicate register.
712 anv_batch_emit(&cmd_buffer
->batch
, GENX(MI_LOAD_REGISTER_MEM
), lrm
) {
713 lrm
.RegisterAddress
= MI_PREDICATE_SRC0
;
714 lrm
.MemoryAddress
= fast_clear_type_addr
;
716 anv_batch_emit(&cmd_buffer
->batch
, GENX(MI_STORE_DATA_IMM
), sdi
) {
717 sdi
.Address
= fast_clear_type_addr
;
718 sdi
.ImmediateData
= 0;
721 /* We use the first half of src0 for the actual predicate. Set the second
722 * half of src0 and all of src1 to 0 as the predicate operation will be
723 * doing an implicit src0 != src1.
725 emit_lri(&cmd_buffer
->batch
, MI_PREDICATE_SRC0
+ 4, 0);
726 emit_lri(&cmd_buffer
->batch
, MI_PREDICATE_SRC1
, 0);
727 emit_lri(&cmd_buffer
->batch
, MI_PREDICATE_SRC1
+ 4, 0);
729 anv_batch_emit(&cmd_buffer
->batch
, GENX(MI_PREDICATE
), mip
) {
730 mip
.LoadOperation
= LOAD_LOADINV
;
731 mip
.CombineOperation
= COMBINE_SET
;
732 mip
.CompareOperation
= COMPARE_SRCS_EQUAL
;
735 #endif /* GEN_GEN <= 8 */
738 anv_cmd_predicated_ccs_resolve(struct anv_cmd_buffer
*cmd_buffer
,
739 const struct anv_image
*image
,
740 VkImageAspectFlagBits aspect
,
741 uint32_t level
, uint32_t array_layer
,
742 enum isl_aux_op resolve_op
,
743 enum anv_fast_clear_type fast_clear_supported
)
745 const uint32_t plane
= anv_image_aspect_to_plane(image
->aspects
, aspect
);
748 anv_cmd_compute_resolve_predicate(cmd_buffer
, image
,
749 aspect
, level
, array_layer
,
750 resolve_op
, fast_clear_supported
);
751 #else /* GEN_GEN <= 8 */
752 anv_cmd_simple_resolve_predicate(cmd_buffer
, image
,
753 aspect
, level
, array_layer
,
754 resolve_op
, fast_clear_supported
);
757 /* CCS_D only supports full resolves and BLORP will assert on us if we try
758 * to do a partial resolve on a CCS_D surface.
760 if (resolve_op
== ISL_AUX_OP_PARTIAL_RESOLVE
&&
761 image
->planes
[plane
].aux_usage
== ISL_AUX_USAGE_NONE
)
762 resolve_op
= ISL_AUX_OP_FULL_RESOLVE
;
764 anv_image_ccs_op(cmd_buffer
, image
, aspect
, level
,
765 array_layer
, 1, resolve_op
, NULL
, true);
769 anv_cmd_predicated_mcs_resolve(struct anv_cmd_buffer
*cmd_buffer
,
770 const struct anv_image
*image
,
771 VkImageAspectFlagBits aspect
,
772 uint32_t array_layer
,
773 enum isl_aux_op resolve_op
,
774 enum anv_fast_clear_type fast_clear_supported
)
776 assert(aspect
== VK_IMAGE_ASPECT_COLOR_BIT
);
777 assert(resolve_op
== ISL_AUX_OP_PARTIAL_RESOLVE
);
779 #if GEN_GEN >= 8 || GEN_IS_HASWELL
780 anv_cmd_compute_resolve_predicate(cmd_buffer
, image
,
781 aspect
, 0, array_layer
,
782 resolve_op
, fast_clear_supported
);
784 anv_image_mcs_op(cmd_buffer
, image
, aspect
,
785 array_layer
, 1, resolve_op
, NULL
, true);
787 unreachable("MCS resolves are unsupported on Ivybridge and Bay Trail");
792 genX(cmd_buffer_mark_image_written
)(struct anv_cmd_buffer
*cmd_buffer
,
793 const struct anv_image
*image
,
794 VkImageAspectFlagBits aspect
,
795 enum isl_aux_usage aux_usage
,
798 uint32_t layer_count
)
800 /* The aspect must be exactly one of the image aspects. */
801 assert(util_bitcount(aspect
) == 1 && (aspect
& image
->aspects
));
803 /* The only compression types with more than just fast-clears are MCS,
804 * CCS_E, and HiZ. With HiZ we just trust the layout and don't actually
805 * track the current fast-clear and compression state. This leaves us
806 * with just MCS and CCS_E.
808 if (aux_usage
!= ISL_AUX_USAGE_CCS_E
&&
809 aux_usage
!= ISL_AUX_USAGE_MCS
)
812 set_image_compressed_bit(cmd_buffer
, image
, aspect
,
813 level
, base_layer
, layer_count
, true);
817 init_fast_clear_color(struct anv_cmd_buffer
*cmd_buffer
,
818 const struct anv_image
*image
,
819 VkImageAspectFlagBits aspect
)
821 assert(cmd_buffer
&& image
);
822 assert(image
->aspects
& VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV
);
824 set_image_fast_clear_state(cmd_buffer
, image
, aspect
,
825 ANV_FAST_CLEAR_NONE
);
827 /* The fast clear value dword(s) will be copied into a surface state object.
828 * Ensure that the restrictions of the fields in the dword(s) are followed.
830 * CCS buffers on SKL+ can have any value set for the clear colors.
832 if (image
->samples
== 1 && GEN_GEN
>= 9)
835 /* Other combinations of auxiliary buffers and platforms require specific
836 * values in the clear value dword(s).
838 struct anv_address addr
=
839 anv_image_get_clear_color_addr(cmd_buffer
->device
, image
, aspect
);
842 for (unsigned i
= 0; i
< 4; i
++) {
843 anv_batch_emit(&cmd_buffer
->batch
, GENX(MI_STORE_DATA_IMM
), sdi
) {
845 sdi
.Address
.offset
+= i
* 4;
846 /* MCS buffers on SKL+ can only have 1/0 clear colors. */
847 assert(image
->samples
> 1);
848 sdi
.ImmediateData
= 0;
852 anv_batch_emit(&cmd_buffer
->batch
, GENX(MI_STORE_DATA_IMM
), sdi
) {
854 if (GEN_GEN
>= 8 || GEN_IS_HASWELL
) {
855 /* Pre-SKL, the dword containing the clear values also contains
856 * other fields, so we need to initialize those fields to match the
857 * values that would be in a color attachment.
859 sdi
.ImmediateData
= ISL_CHANNEL_SELECT_RED
<< 25 |
860 ISL_CHANNEL_SELECT_GREEN
<< 22 |
861 ISL_CHANNEL_SELECT_BLUE
<< 19 |
862 ISL_CHANNEL_SELECT_ALPHA
<< 16;
863 } else if (GEN_GEN
== 7) {
864 /* On IVB, the dword containing the clear values also contains
865 * other fields that must be zero or can be zero.
867 sdi
.ImmediateData
= 0;
873 /* Copy the fast-clear value dword(s) between a surface state object and an
874 * image's fast clear state buffer.
877 genX(copy_fast_clear_dwords
)(struct anv_cmd_buffer
*cmd_buffer
,
878 struct anv_state surface_state
,
879 const struct anv_image
*image
,
880 VkImageAspectFlagBits aspect
,
881 bool copy_from_surface_state
)
883 assert(cmd_buffer
&& image
);
884 assert(image
->aspects
& VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV
);
886 struct anv_address ss_clear_addr
= {
887 .bo
= &cmd_buffer
->device
->surface_state_pool
.block_pool
.bo
,
888 .offset
= surface_state
.offset
+
889 cmd_buffer
->device
->isl_dev
.ss
.clear_value_offset
,
891 const struct anv_address entry_addr
=
892 anv_image_get_clear_color_addr(cmd_buffer
->device
, image
, aspect
);
893 unsigned copy_size
= cmd_buffer
->device
->isl_dev
.ss
.clear_value_size
;
895 if (copy_from_surface_state
) {
896 genX(cmd_buffer_mi_memcpy
)(cmd_buffer
, entry_addr
,
897 ss_clear_addr
, copy_size
);
899 genX(cmd_buffer_mi_memcpy
)(cmd_buffer
, ss_clear_addr
,
900 entry_addr
, copy_size
);
902 /* Updating a surface state object may require that the state cache be
903 * invalidated. From the SKL PRM, Shared Functions -> State -> State
906 * Whenever the RENDER_SURFACE_STATE object in memory pointed to by
907 * the Binding Table Pointer (BTP) and Binding Table Index (BTI) is
908 * modified [...], the L1 state cache must be invalidated to ensure
909 * the new surface or sampler state is fetched from system memory.
911 * In testing, SKL doesn't actually seem to need this, but HSW does.
913 cmd_buffer
->state
.pending_pipe_bits
|=
914 ANV_PIPE_STATE_CACHE_INVALIDATE_BIT
;
919 * @brief Transitions a color buffer from one layout to another.
921 * See section 6.1.1. Image Layout Transitions of the Vulkan 1.0.50 spec for
924 * @param level_count VK_REMAINING_MIP_LEVELS isn't supported.
925 * @param layer_count VK_REMAINING_ARRAY_LAYERS isn't supported. For 3D images,
926 * this represents the maximum layers to transition at each
927 * specified miplevel.
930 transition_color_buffer(struct anv_cmd_buffer
*cmd_buffer
,
931 const struct anv_image
*image
,
932 VkImageAspectFlagBits aspect
,
933 const uint32_t base_level
, uint32_t level_count
,
934 uint32_t base_layer
, uint32_t layer_count
,
935 VkImageLayout initial_layout
,
936 VkImageLayout final_layout
)
938 const struct gen_device_info
*devinfo
= &cmd_buffer
->device
->info
;
939 /* Validate the inputs. */
941 assert(image
&& image
->aspects
& VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV
);
942 /* These values aren't supported for simplicity's sake. */
943 assert(level_count
!= VK_REMAINING_MIP_LEVELS
&&
944 layer_count
!= VK_REMAINING_ARRAY_LAYERS
);
945 /* Ensure the subresource range is valid. */
946 uint64_t last_level_num
= base_level
+ level_count
;
947 const uint32_t max_depth
= anv_minify(image
->extent
.depth
, base_level
);
948 UNUSED
const uint32_t image_layers
= MAX2(image
->array_size
, max_depth
);
949 assert((uint64_t)base_layer
+ layer_count
<= image_layers
);
950 assert(last_level_num
<= image
->levels
);
951 /* The spec disallows these final layouts. */
952 assert(final_layout
!= VK_IMAGE_LAYOUT_UNDEFINED
&&
953 final_layout
!= VK_IMAGE_LAYOUT_PREINITIALIZED
);
955 /* No work is necessary if the layout stays the same or if this subresource
956 * range lacks auxiliary data.
958 if (initial_layout
== final_layout
)
961 uint32_t plane
= anv_image_aspect_to_plane(image
->aspects
, aspect
);
963 if (image
->planes
[plane
].shadow_surface
.isl
.size_B
> 0 &&
964 final_layout
== VK_IMAGE_LAYOUT_SHADER_READ_ONLY_OPTIMAL
) {
965 /* This surface is a linear compressed image with a tiled shadow surface
966 * for texturing. The client is about to use it in READ_ONLY_OPTIMAL so
967 * we need to ensure the shadow copy is up-to-date.
969 assert(image
->aspects
== VK_IMAGE_ASPECT_COLOR_BIT
);
970 assert(image
->planes
[plane
].surface
.isl
.tiling
== ISL_TILING_LINEAR
);
971 assert(image
->planes
[plane
].shadow_surface
.isl
.tiling
!= ISL_TILING_LINEAR
);
972 assert(isl_format_is_compressed(image
->planes
[plane
].surface
.isl
.format
));
974 anv_image_copy_to_shadow(cmd_buffer
, image
,
975 base_level
, level_count
,
976 base_layer
, layer_count
);
979 if (base_layer
>= anv_image_aux_layers(image
, aspect
, base_level
))
982 assert(image
->tiling
== VK_IMAGE_TILING_OPTIMAL
);
984 if (initial_layout
== VK_IMAGE_LAYOUT_UNDEFINED
||
985 initial_layout
== VK_IMAGE_LAYOUT_PREINITIALIZED
) {
986 /* A subresource in the undefined layout may have been aliased and
987 * populated with any arrangement of bits. Therefore, we must initialize
988 * the related aux buffer and clear buffer entry with desirable values.
989 * An initial layout of PREINITIALIZED is the same as UNDEFINED for
990 * images with VK_IMAGE_TILING_OPTIMAL.
992 * Initialize the relevant clear buffer entries.
994 if (base_level
== 0 && base_layer
== 0)
995 init_fast_clear_color(cmd_buffer
, image
, aspect
);
997 /* Initialize the aux buffers to enable correct rendering. In order to
998 * ensure that things such as storage images work correctly, aux buffers
999 * need to be initialized to valid data.
1001 * Having an aux buffer with invalid data is a problem for two reasons:
1003 * 1) Having an invalid value in the buffer can confuse the hardware.
1004 * For instance, with CCS_E on SKL, a two-bit CCS value of 2 is
1005 * invalid and leads to the hardware doing strange things. It
1006 * doesn't hang as far as we can tell but rendering corruption can
1009 * 2) If this transition is into the GENERAL layout and we then use the
1010 * image as a storage image, then we must have the aux buffer in the
1011 * pass-through state so that, if we then go to texture from the
1012 * image, we get the results of our storage image writes and not the
1013 * fast clear color or other random data.
1015 * For CCS both of the problems above are real demonstrable issues. In
1016 * that case, the only thing we can do is to perform an ambiguate to
1017 * transition the aux surface into the pass-through state.
1019 * For MCS, (2) is never an issue because we don't support multisampled
1020 * storage images. In theory, issue (1) is a problem with MCS but we've
1021 * never seen it in the wild. For 4x and 16x, all bit patters could, in
1022 * theory, be interpreted as something but we don't know that all bit
1023 * patterns are actually valid. For 2x and 8x, you could easily end up
1024 * with the MCS referring to an invalid plane because not all bits of
1025 * the MCS value are actually used. Even though we've never seen issues
1026 * in the wild, it's best to play it safe and initialize the MCS. We
1027 * can use a fast-clear for MCS because we only ever touch from render
1028 * and texture (no image load store).
1030 if (image
->samples
== 1) {
1031 for (uint32_t l
= 0; l
< level_count
; l
++) {
1032 const uint32_t level
= base_level
+ l
;
1034 uint32_t aux_layers
= anv_image_aux_layers(image
, aspect
, level
);
1035 if (base_layer
>= aux_layers
)
1036 break; /* We will only get fewer layers as level increases */
1037 uint32_t level_layer_count
=
1038 MIN2(layer_count
, aux_layers
- base_layer
);
1040 anv_image_ccs_op(cmd_buffer
, image
, aspect
, level
,
1041 base_layer
, level_layer_count
,
1042 ISL_AUX_OP_AMBIGUATE
, NULL
, false);
1044 if (image
->planes
[plane
].aux_usage
== ISL_AUX_USAGE_CCS_E
) {
1045 set_image_compressed_bit(cmd_buffer
, image
, aspect
,
1046 level
, base_layer
, level_layer_count
,
1051 if (image
->samples
== 4 || image
->samples
== 16) {
1052 anv_perf_warn(cmd_buffer
->device
->instance
, image
,
1053 "Doing a potentially unnecessary fast-clear to "
1054 "define an MCS buffer.");
1057 assert(base_level
== 0 && level_count
== 1);
1058 anv_image_mcs_op(cmd_buffer
, image
, aspect
,
1059 base_layer
, layer_count
,
1060 ISL_AUX_OP_FAST_CLEAR
, NULL
, false);
1065 const enum isl_aux_usage initial_aux_usage
=
1066 anv_layout_to_aux_usage(devinfo
, image
, aspect
, initial_layout
);
1067 const enum isl_aux_usage final_aux_usage
=
1068 anv_layout_to_aux_usage(devinfo
, image
, aspect
, final_layout
);
1070 /* The current code assumes that there is no mixing of CCS_E and CCS_D.
1071 * We can handle transitions between CCS_D/E to and from NONE. What we
1072 * don't yet handle is switching between CCS_E and CCS_D within a given
1073 * image. Doing so in a performant way requires more detailed aux state
1074 * tracking such as what is done in i965. For now, just assume that we
1075 * only have one type of compression.
1077 assert(initial_aux_usage
== ISL_AUX_USAGE_NONE
||
1078 final_aux_usage
== ISL_AUX_USAGE_NONE
||
1079 initial_aux_usage
== final_aux_usage
);
1081 /* If initial aux usage is NONE, there is nothing to resolve */
1082 if (initial_aux_usage
== ISL_AUX_USAGE_NONE
)
1085 enum isl_aux_op resolve_op
= ISL_AUX_OP_NONE
;
1087 /* If the initial layout supports more fast clear than the final layout
1088 * then we need at least a partial resolve.
1090 const enum anv_fast_clear_type initial_fast_clear
=
1091 anv_layout_to_fast_clear_type(devinfo
, image
, aspect
, initial_layout
);
1092 const enum anv_fast_clear_type final_fast_clear
=
1093 anv_layout_to_fast_clear_type(devinfo
, image
, aspect
, final_layout
);
1094 if (final_fast_clear
< initial_fast_clear
)
1095 resolve_op
= ISL_AUX_OP_PARTIAL_RESOLVE
;
1097 if (initial_aux_usage
== ISL_AUX_USAGE_CCS_E
&&
1098 final_aux_usage
!= ISL_AUX_USAGE_CCS_E
)
1099 resolve_op
= ISL_AUX_OP_FULL_RESOLVE
;
1101 if (resolve_op
== ISL_AUX_OP_NONE
)
1104 /* Perform a resolve to synchronize data between the main and aux buffer.
1105 * Before we begin, we must satisfy the cache flushing requirement specified
1106 * in the Sky Lake PRM Vol. 7, "MCS Buffer for Render Target(s)":
1108 * Any transition from any value in {Clear, Render, Resolve} to a
1109 * different value in {Clear, Render, Resolve} requires end of pipe
1112 * We perform a flush of the write cache before and after the clear and
1113 * resolve operations to meet this requirement.
1115 * Unlike other drawing, fast clear operations are not properly
1116 * synchronized. The first PIPE_CONTROL here likely ensures that the
1117 * contents of the previous render or clear hit the render target before we
1118 * resolve and the second likely ensures that the resolve is complete before
1119 * we do any more rendering or clearing.
1121 cmd_buffer
->state
.pending_pipe_bits
|=
1122 ANV_PIPE_RENDER_TARGET_CACHE_FLUSH_BIT
| ANV_PIPE_CS_STALL_BIT
;
1124 for (uint32_t l
= 0; l
< level_count
; l
++) {
1125 uint32_t level
= base_level
+ l
;
1127 uint32_t aux_layers
= anv_image_aux_layers(image
, aspect
, level
);
1128 if (base_layer
>= aux_layers
)
1129 break; /* We will only get fewer layers as level increases */
1130 uint32_t level_layer_count
=
1131 MIN2(layer_count
, aux_layers
- base_layer
);
1133 for (uint32_t a
= 0; a
< level_layer_count
; a
++) {
1134 uint32_t array_layer
= base_layer
+ a
;
1135 if (image
->samples
== 1) {
1136 anv_cmd_predicated_ccs_resolve(cmd_buffer
, image
, aspect
,
1137 level
, array_layer
, resolve_op
,
1140 anv_cmd_predicated_mcs_resolve(cmd_buffer
, image
, aspect
,
1141 array_layer
, resolve_op
,
1147 cmd_buffer
->state
.pending_pipe_bits
|=
1148 ANV_PIPE_RENDER_TARGET_CACHE_FLUSH_BIT
| ANV_PIPE_CS_STALL_BIT
;
1152 * Setup anv_cmd_state::attachments for vkCmdBeginRenderPass.
1155 genX(cmd_buffer_setup_attachments
)(struct anv_cmd_buffer
*cmd_buffer
,
1156 struct anv_render_pass
*pass
,
1157 const VkRenderPassBeginInfo
*begin
)
1159 const struct isl_device
*isl_dev
= &cmd_buffer
->device
->isl_dev
;
1160 struct anv_cmd_state
*state
= &cmd_buffer
->state
;
1162 vk_free(&cmd_buffer
->pool
->alloc
, state
->attachments
);
1164 if (pass
->attachment_count
> 0) {
1165 state
->attachments
= vk_alloc(&cmd_buffer
->pool
->alloc
,
1166 pass
->attachment_count
*
1167 sizeof(state
->attachments
[0]),
1168 8, VK_SYSTEM_ALLOCATION_SCOPE_OBJECT
);
1169 if (state
->attachments
== NULL
) {
1170 /* Propagate VK_ERROR_OUT_OF_HOST_MEMORY to vkEndCommandBuffer */
1171 return anv_batch_set_error(&cmd_buffer
->batch
,
1172 VK_ERROR_OUT_OF_HOST_MEMORY
);
1175 state
->attachments
= NULL
;
1178 /* Reserve one for the NULL state. */
1179 unsigned num_states
= 1;
1180 for (uint32_t i
= 0; i
< pass
->attachment_count
; ++i
) {
1181 if (vk_format_is_color(pass
->attachments
[i
].format
))
1184 if (need_input_attachment_state(&pass
->attachments
[i
]))
1188 const uint32_t ss_stride
= align_u32(isl_dev
->ss
.size
, isl_dev
->ss
.align
);
1189 state
->render_pass_states
=
1190 anv_state_stream_alloc(&cmd_buffer
->surface_state_stream
,
1191 num_states
* ss_stride
, isl_dev
->ss
.align
);
1193 struct anv_state next_state
= state
->render_pass_states
;
1194 next_state
.alloc_size
= isl_dev
->ss
.size
;
1196 state
->null_surface_state
= next_state
;
1197 next_state
.offset
+= ss_stride
;
1198 next_state
.map
+= ss_stride
;
1200 for (uint32_t i
= 0; i
< pass
->attachment_count
; ++i
) {
1201 if (vk_format_is_color(pass
->attachments
[i
].format
)) {
1202 state
->attachments
[i
].color
.state
= next_state
;
1203 next_state
.offset
+= ss_stride
;
1204 next_state
.map
+= ss_stride
;
1207 if (need_input_attachment_state(&pass
->attachments
[i
])) {
1208 state
->attachments
[i
].input
.state
= next_state
;
1209 next_state
.offset
+= ss_stride
;
1210 next_state
.map
+= ss_stride
;
1213 assert(next_state
.offset
== state
->render_pass_states
.offset
+
1214 state
->render_pass_states
.alloc_size
);
1217 ANV_FROM_HANDLE(anv_framebuffer
, framebuffer
, begin
->framebuffer
);
1218 assert(pass
->attachment_count
== framebuffer
->attachment_count
);
1220 isl_null_fill_state(isl_dev
, state
->null_surface_state
.map
,
1221 isl_extent3d(framebuffer
->width
,
1222 framebuffer
->height
,
1223 framebuffer
->layers
));
1225 for (uint32_t i
= 0; i
< pass
->attachment_count
; ++i
) {
1226 struct anv_render_pass_attachment
*att
= &pass
->attachments
[i
];
1227 VkImageAspectFlags att_aspects
= vk_format_aspects(att
->format
);
1228 VkImageAspectFlags clear_aspects
= 0;
1229 VkImageAspectFlags load_aspects
= 0;
1231 if (att_aspects
& VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV
) {
1232 /* color attachment */
1233 if (att
->load_op
== VK_ATTACHMENT_LOAD_OP_CLEAR
) {
1234 clear_aspects
|= VK_IMAGE_ASPECT_COLOR_BIT
;
1235 } else if (att
->load_op
== VK_ATTACHMENT_LOAD_OP_LOAD
) {
1236 load_aspects
|= VK_IMAGE_ASPECT_COLOR_BIT
;
1239 /* depthstencil attachment */
1240 if (att_aspects
& VK_IMAGE_ASPECT_DEPTH_BIT
) {
1241 if (att
->load_op
== VK_ATTACHMENT_LOAD_OP_CLEAR
) {
1242 clear_aspects
|= VK_IMAGE_ASPECT_DEPTH_BIT
;
1243 } else if (att
->load_op
== VK_ATTACHMENT_LOAD_OP_LOAD
) {
1244 load_aspects
|= VK_IMAGE_ASPECT_DEPTH_BIT
;
1247 if (att_aspects
& VK_IMAGE_ASPECT_STENCIL_BIT
) {
1248 if (att
->stencil_load_op
== VK_ATTACHMENT_LOAD_OP_CLEAR
) {
1249 clear_aspects
|= VK_IMAGE_ASPECT_STENCIL_BIT
;
1250 } else if (att
->stencil_load_op
== VK_ATTACHMENT_LOAD_OP_LOAD
) {
1251 load_aspects
|= VK_IMAGE_ASPECT_STENCIL_BIT
;
1256 state
->attachments
[i
].current_layout
= att
->initial_layout
;
1257 state
->attachments
[i
].pending_clear_aspects
= clear_aspects
;
1258 state
->attachments
[i
].pending_load_aspects
= load_aspects
;
1260 state
->attachments
[i
].clear_value
= begin
->pClearValues
[i
];
1262 struct anv_image_view
*iview
= framebuffer
->attachments
[i
];
1263 anv_assert(iview
->vk_format
== att
->format
);
1265 const uint32_t num_layers
= iview
->planes
[0].isl
.array_len
;
1266 state
->attachments
[i
].pending_clear_views
= (1 << num_layers
) - 1;
1268 union isl_color_value clear_color
= { .u32
= { 0, } };
1269 if (att_aspects
& VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV
) {
1270 anv_assert(iview
->n_planes
== 1);
1271 assert(att_aspects
== VK_IMAGE_ASPECT_COLOR_BIT
);
1272 color_attachment_compute_aux_usage(cmd_buffer
->device
,
1273 state
, i
, begin
->renderArea
,
1276 anv_image_fill_surface_state(cmd_buffer
->device
,
1278 VK_IMAGE_ASPECT_COLOR_BIT
,
1279 &iview
->planes
[0].isl
,
1280 ISL_SURF_USAGE_RENDER_TARGET_BIT
,
1281 state
->attachments
[i
].aux_usage
,
1284 &state
->attachments
[i
].color
,
1287 add_surface_state_relocs(cmd_buffer
, state
->attachments
[i
].color
);
1289 depth_stencil_attachment_compute_aux_usage(cmd_buffer
->device
,
1294 if (need_input_attachment_state(&pass
->attachments
[i
])) {
1295 anv_image_fill_surface_state(cmd_buffer
->device
,
1297 VK_IMAGE_ASPECT_COLOR_BIT
,
1298 &iview
->planes
[0].isl
,
1299 ISL_SURF_USAGE_TEXTURE_BIT
,
1300 state
->attachments
[i
].input_aux_usage
,
1303 &state
->attachments
[i
].input
,
1306 add_surface_state_relocs(cmd_buffer
, state
->attachments
[i
].input
);
1315 genX(BeginCommandBuffer
)(
1316 VkCommandBuffer commandBuffer
,
1317 const VkCommandBufferBeginInfo
* pBeginInfo
)
1319 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
1321 /* If this is the first vkBeginCommandBuffer, we must *initialize* the
1322 * command buffer's state. Otherwise, we must *reset* its state. In both
1323 * cases we reset it.
1325 * From the Vulkan 1.0 spec:
1327 * If a command buffer is in the executable state and the command buffer
1328 * was allocated from a command pool with the
1329 * VK_COMMAND_POOL_CREATE_RESET_COMMAND_BUFFER_BIT flag set, then
1330 * vkBeginCommandBuffer implicitly resets the command buffer, behaving
1331 * as if vkResetCommandBuffer had been called with
1332 * VK_COMMAND_BUFFER_RESET_RELEASE_RESOURCES_BIT not set. It then puts
1333 * the command buffer in the recording state.
1335 anv_cmd_buffer_reset(cmd_buffer
);
1337 cmd_buffer
->usage_flags
= pBeginInfo
->flags
;
1339 assert(cmd_buffer
->level
== VK_COMMAND_BUFFER_LEVEL_SECONDARY
||
1340 !(cmd_buffer
->usage_flags
& VK_COMMAND_BUFFER_USAGE_RENDER_PASS_CONTINUE_BIT
));
1342 genX(cmd_buffer_emit_state_base_address
)(cmd_buffer
);
1344 /* We sometimes store vertex data in the dynamic state buffer for blorp
1345 * operations and our dynamic state stream may re-use data from previous
1346 * command buffers. In order to prevent stale cache data, we flush the VF
1347 * cache. We could do this on every blorp call but that's not really
1348 * needed as all of the data will get written by the CPU prior to the GPU
1349 * executing anything. The chances are fairly high that they will use
1350 * blorp at least once per primary command buffer so it shouldn't be
1353 if (cmd_buffer
->level
== VK_COMMAND_BUFFER_LEVEL_PRIMARY
)
1354 cmd_buffer
->state
.pending_pipe_bits
|= ANV_PIPE_VF_CACHE_INVALIDATE_BIT
;
1356 /* We send an "Indirect State Pointers Disable" packet at
1357 * EndCommandBuffer, so all push contant packets are ignored during a
1358 * context restore. Documentation says after that command, we need to
1359 * emit push constants again before any rendering operation. So we
1360 * flag them dirty here to make sure they get emitted.
1362 cmd_buffer
->state
.push_constants_dirty
|= VK_SHADER_STAGE_ALL_GRAPHICS
;
1364 VkResult result
= VK_SUCCESS
;
1365 if (cmd_buffer
->usage_flags
&
1366 VK_COMMAND_BUFFER_USAGE_RENDER_PASS_CONTINUE_BIT
) {
1367 assert(pBeginInfo
->pInheritanceInfo
);
1368 cmd_buffer
->state
.pass
=
1369 anv_render_pass_from_handle(pBeginInfo
->pInheritanceInfo
->renderPass
);
1370 cmd_buffer
->state
.subpass
=
1371 &cmd_buffer
->state
.pass
->subpasses
[pBeginInfo
->pInheritanceInfo
->subpass
];
1373 /* This is optional in the inheritance info. */
1374 cmd_buffer
->state
.framebuffer
=
1375 anv_framebuffer_from_handle(pBeginInfo
->pInheritanceInfo
->framebuffer
);
1377 result
= genX(cmd_buffer_setup_attachments
)(cmd_buffer
,
1378 cmd_buffer
->state
.pass
, NULL
);
1380 /* Record that HiZ is enabled if we can. */
1381 if (cmd_buffer
->state
.framebuffer
) {
1382 const struct anv_image_view
* const iview
=
1383 anv_cmd_buffer_get_depth_stencil_view(cmd_buffer
);
1386 VkImageLayout layout
=
1387 cmd_buffer
->state
.subpass
->depth_stencil_attachment
->layout
;
1389 enum isl_aux_usage aux_usage
=
1390 anv_layout_to_aux_usage(&cmd_buffer
->device
->info
, iview
->image
,
1391 VK_IMAGE_ASPECT_DEPTH_BIT
, layout
);
1393 cmd_buffer
->state
.hiz_enabled
= aux_usage
== ISL_AUX_USAGE_HIZ
;
1397 cmd_buffer
->state
.gfx
.dirty
|= ANV_CMD_DIRTY_RENDER_TARGETS
;
1403 /* From the PRM, Volume 2a:
1405 * "Indirect State Pointers Disable
1407 * At the completion of the post-sync operation associated with this pipe
1408 * control packet, the indirect state pointers in the hardware are
1409 * considered invalid; the indirect pointers are not saved in the context.
1410 * If any new indirect state commands are executed in the command stream
1411 * while the pipe control is pending, the new indirect state commands are
1414 * [DevIVB+]: Using Invalidate State Pointer (ISP) only inhibits context
1415 * restoring of Push Constant (3DSTATE_CONSTANT_*) commands. Push Constant
1416 * commands are only considered as Indirect State Pointers. Once ISP is
1417 * issued in a context, SW must initialize by programming push constant
1418 * commands for all the shaders (at least to zero length) before attempting
1419 * any rendering operation for the same context."
1421 * 3DSTATE_CONSTANT_* packets are restored during a context restore,
1422 * even though they point to a BO that has been already unreferenced at
1423 * the end of the previous batch buffer. This has been fine so far since
1424 * we are protected by these scratch page (every address not covered by
1425 * a BO should be pointing to the scratch page). But on CNL, it is
1426 * causing a GPU hang during context restore at the 3DSTATE_CONSTANT_*
1429 * The flag "Indirect State Pointers Disable" in PIPE_CONTROL tells the
1430 * hardware to ignore previous 3DSTATE_CONSTANT_* packets during a
1431 * context restore, so the mentioned hang doesn't happen. However,
1432 * software must program push constant commands for all stages prior to
1433 * rendering anything. So we flag them dirty in BeginCommandBuffer.
1435 * Finally, we also make sure to stall at pixel scoreboard to make sure the
1436 * constants have been loaded into the EUs prior to disable the push constants
1437 * so that it doesn't hang a previous 3DPRIMITIVE.
1440 emit_isp_disable(struct anv_cmd_buffer
*cmd_buffer
)
1442 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pc
) {
1443 pc
.StallAtPixelScoreboard
= true;
1444 pc
.CommandStreamerStallEnable
= true;
1446 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pc
) {
1447 pc
.IndirectStatePointersDisable
= true;
1448 pc
.CommandStreamerStallEnable
= true;
1453 genX(EndCommandBuffer
)(
1454 VkCommandBuffer commandBuffer
)
1456 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
1458 if (anv_batch_has_error(&cmd_buffer
->batch
))
1459 return cmd_buffer
->batch
.status
;
1461 /* We want every command buffer to start with the PMA fix in a known state,
1462 * so we disable it at the end of the command buffer.
1464 genX(cmd_buffer_enable_pma_fix
)(cmd_buffer
, false);
1466 genX(cmd_buffer_apply_pipe_flushes
)(cmd_buffer
);
1468 emit_isp_disable(cmd_buffer
);
1470 anv_cmd_buffer_end_batch_buffer(cmd_buffer
);
1476 genX(CmdExecuteCommands
)(
1477 VkCommandBuffer commandBuffer
,
1478 uint32_t commandBufferCount
,
1479 const VkCommandBuffer
* pCmdBuffers
)
1481 ANV_FROM_HANDLE(anv_cmd_buffer
, primary
, commandBuffer
);
1483 assert(primary
->level
== VK_COMMAND_BUFFER_LEVEL_PRIMARY
);
1485 if (anv_batch_has_error(&primary
->batch
))
1488 /* The secondary command buffers will assume that the PMA fix is disabled
1489 * when they begin executing. Make sure this is true.
1491 genX(cmd_buffer_enable_pma_fix
)(primary
, false);
1493 /* The secondary command buffer doesn't know which textures etc. have been
1494 * flushed prior to their execution. Apply those flushes now.
1496 genX(cmd_buffer_apply_pipe_flushes
)(primary
);
1498 for (uint32_t i
= 0; i
< commandBufferCount
; i
++) {
1499 ANV_FROM_HANDLE(anv_cmd_buffer
, secondary
, pCmdBuffers
[i
]);
1501 assert(secondary
->level
== VK_COMMAND_BUFFER_LEVEL_SECONDARY
);
1502 assert(!anv_batch_has_error(&secondary
->batch
));
1504 if (secondary
->usage_flags
&
1505 VK_COMMAND_BUFFER_USAGE_RENDER_PASS_CONTINUE_BIT
) {
1506 /* If we're continuing a render pass from the primary, we need to
1507 * copy the surface states for the current subpass into the storage
1508 * we allocated for them in BeginCommandBuffer.
1510 struct anv_bo
*ss_bo
=
1511 &primary
->device
->surface_state_pool
.block_pool
.bo
;
1512 struct anv_state src_state
= primary
->state
.render_pass_states
;
1513 struct anv_state dst_state
= secondary
->state
.render_pass_states
;
1514 assert(src_state
.alloc_size
== dst_state
.alloc_size
);
1516 genX(cmd_buffer_so_memcpy
)(primary
,
1517 (struct anv_address
) {
1519 .offset
= dst_state
.offset
,
1521 (struct anv_address
) {
1523 .offset
= src_state
.offset
,
1525 src_state
.alloc_size
);
1528 anv_cmd_buffer_add_secondary(primary
, secondary
);
1531 /* The secondary may have selected a different pipeline (3D or compute) and
1532 * may have changed the current L3$ configuration. Reset our tracking
1533 * variables to invalid values to ensure that we re-emit these in the case
1534 * where we do any draws or compute dispatches from the primary after the
1535 * secondary has returned.
1537 primary
->state
.current_pipeline
= UINT32_MAX
;
1538 primary
->state
.current_l3_config
= NULL
;
1540 /* Each of the secondary command buffers will use its own state base
1541 * address. We need to re-emit state base address for the primary after
1542 * all of the secondaries are done.
1544 * TODO: Maybe we want to make this a dirty bit to avoid extra state base
1547 genX(cmd_buffer_emit_state_base_address
)(primary
);
1550 #define IVB_L3SQCREG1_SQGHPCI_DEFAULT 0x00730000
1551 #define VLV_L3SQCREG1_SQGHPCI_DEFAULT 0x00d30000
1552 #define HSW_L3SQCREG1_SQGHPCI_DEFAULT 0x00610000
1555 * Program the hardware to use the specified L3 configuration.
1558 genX(cmd_buffer_config_l3
)(struct anv_cmd_buffer
*cmd_buffer
,
1559 const struct gen_l3_config
*cfg
)
1562 if (cfg
== cmd_buffer
->state
.current_l3_config
)
1565 if (unlikely(INTEL_DEBUG
& DEBUG_L3
)) {
1566 intel_logd("L3 config transition: ");
1567 gen_dump_l3_config(cfg
, stderr
);
1570 const bool has_slm
= cfg
->n
[GEN_L3P_SLM
];
1572 /* According to the hardware docs, the L3 partitioning can only be changed
1573 * while the pipeline is completely drained and the caches are flushed,
1574 * which involves a first PIPE_CONTROL flush which stalls the pipeline...
1576 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pc
) {
1577 pc
.DCFlushEnable
= true;
1578 pc
.PostSyncOperation
= NoWrite
;
1579 pc
.CommandStreamerStallEnable
= true;
1582 /* ...followed by a second pipelined PIPE_CONTROL that initiates
1583 * invalidation of the relevant caches. Note that because RO invalidation
1584 * happens at the top of the pipeline (i.e. right away as the PIPE_CONTROL
1585 * command is processed by the CS) we cannot combine it with the previous
1586 * stalling flush as the hardware documentation suggests, because that
1587 * would cause the CS to stall on previous rendering *after* RO
1588 * invalidation and wouldn't prevent the RO caches from being polluted by
1589 * concurrent rendering before the stall completes. This intentionally
1590 * doesn't implement the SKL+ hardware workaround suggesting to enable CS
1591 * stall on PIPE_CONTROLs with the texture cache invalidation bit set for
1592 * GPGPU workloads because the previous and subsequent PIPE_CONTROLs
1593 * already guarantee that there is no concurrent GPGPU kernel execution
1594 * (see SKL HSD 2132585).
1596 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pc
) {
1597 pc
.TextureCacheInvalidationEnable
= true;
1598 pc
.ConstantCacheInvalidationEnable
= true;
1599 pc
.InstructionCacheInvalidateEnable
= true;
1600 pc
.StateCacheInvalidationEnable
= true;
1601 pc
.PostSyncOperation
= NoWrite
;
1604 /* Now send a third stalling flush to make sure that invalidation is
1605 * complete when the L3 configuration registers are modified.
1607 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pc
) {
1608 pc
.DCFlushEnable
= true;
1609 pc
.PostSyncOperation
= NoWrite
;
1610 pc
.CommandStreamerStallEnable
= true;
1615 assert(!cfg
->n
[GEN_L3P_IS
] && !cfg
->n
[GEN_L3P_C
] && !cfg
->n
[GEN_L3P_T
]);
1618 anv_pack_struct(&l3cr
, GENX(L3CNTLREG
),
1619 .SLMEnable
= has_slm
,
1621 /* WA_1406697149: Bit 9 "Error Detection Behavior Control" must be set
1622 * in L3CNTLREG register. The default setting of the bit is not the
1623 * desirable behavior.
1625 .ErrorDetectionBehaviorControl
= true,
1627 .URBAllocation
= cfg
->n
[GEN_L3P_URB
],
1628 .ROAllocation
= cfg
->n
[GEN_L3P_RO
],
1629 .DCAllocation
= cfg
->n
[GEN_L3P_DC
],
1630 .AllAllocation
= cfg
->n
[GEN_L3P_ALL
]);
1632 /* Set up the L3 partitioning. */
1633 emit_lri(&cmd_buffer
->batch
, GENX(L3CNTLREG_num
), l3cr
);
1637 const bool has_dc
= cfg
->n
[GEN_L3P_DC
] || cfg
->n
[GEN_L3P_ALL
];
1638 const bool has_is
= cfg
->n
[GEN_L3P_IS
] || cfg
->n
[GEN_L3P_RO
] ||
1639 cfg
->n
[GEN_L3P_ALL
];
1640 const bool has_c
= cfg
->n
[GEN_L3P_C
] || cfg
->n
[GEN_L3P_RO
] ||
1641 cfg
->n
[GEN_L3P_ALL
];
1642 const bool has_t
= cfg
->n
[GEN_L3P_T
] || cfg
->n
[GEN_L3P_RO
] ||
1643 cfg
->n
[GEN_L3P_ALL
];
1645 assert(!cfg
->n
[GEN_L3P_ALL
]);
1647 /* When enabled SLM only uses a portion of the L3 on half of the banks,
1648 * the matching space on the remaining banks has to be allocated to a
1649 * client (URB for all validated configurations) set to the
1650 * lower-bandwidth 2-bank address hashing mode.
1652 const struct gen_device_info
*devinfo
= &cmd_buffer
->device
->info
;
1653 const bool urb_low_bw
= has_slm
&& !devinfo
->is_baytrail
;
1654 assert(!urb_low_bw
|| cfg
->n
[GEN_L3P_URB
] == cfg
->n
[GEN_L3P_SLM
]);
1656 /* Minimum number of ways that can be allocated to the URB. */
1657 MAYBE_UNUSED
const unsigned n0_urb
= devinfo
->is_baytrail
? 32 : 0;
1658 assert(cfg
->n
[GEN_L3P_URB
] >= n0_urb
);
1660 uint32_t l3sqcr1
, l3cr2
, l3cr3
;
1661 anv_pack_struct(&l3sqcr1
, GENX(L3SQCREG1
),
1662 .ConvertDC_UC
= !has_dc
,
1663 .ConvertIS_UC
= !has_is
,
1664 .ConvertC_UC
= !has_c
,
1665 .ConvertT_UC
= !has_t
);
1667 GEN_IS_HASWELL
? HSW_L3SQCREG1_SQGHPCI_DEFAULT
:
1668 devinfo
->is_baytrail
? VLV_L3SQCREG1_SQGHPCI_DEFAULT
:
1669 IVB_L3SQCREG1_SQGHPCI_DEFAULT
;
1671 anv_pack_struct(&l3cr2
, GENX(L3CNTLREG2
),
1672 .SLMEnable
= has_slm
,
1673 .URBLowBandwidth
= urb_low_bw
,
1674 .URBAllocation
= cfg
->n
[GEN_L3P_URB
] - n0_urb
,
1676 .ALLAllocation
= cfg
->n
[GEN_L3P_ALL
],
1678 .ROAllocation
= cfg
->n
[GEN_L3P_RO
],
1679 .DCAllocation
= cfg
->n
[GEN_L3P_DC
]);
1681 anv_pack_struct(&l3cr3
, GENX(L3CNTLREG3
),
1682 .ISAllocation
= cfg
->n
[GEN_L3P_IS
],
1683 .ISLowBandwidth
= 0,
1684 .CAllocation
= cfg
->n
[GEN_L3P_C
],
1686 .TAllocation
= cfg
->n
[GEN_L3P_T
],
1687 .TLowBandwidth
= 0);
1689 /* Set up the L3 partitioning. */
1690 emit_lri(&cmd_buffer
->batch
, GENX(L3SQCREG1_num
), l3sqcr1
);
1691 emit_lri(&cmd_buffer
->batch
, GENX(L3CNTLREG2_num
), l3cr2
);
1692 emit_lri(&cmd_buffer
->batch
, GENX(L3CNTLREG3_num
), l3cr3
);
1695 if (cmd_buffer
->device
->instance
->physicalDevice
.cmd_parser_version
>= 4) {
1696 /* Enable L3 atomics on HSW if we have a DC partition, otherwise keep
1697 * them disabled to avoid crashing the system hard.
1699 uint32_t scratch1
, chicken3
;
1700 anv_pack_struct(&scratch1
, GENX(SCRATCH1
),
1701 .L3AtomicDisable
= !has_dc
);
1702 anv_pack_struct(&chicken3
, GENX(CHICKEN3
),
1703 .L3AtomicDisableMask
= true,
1704 .L3AtomicDisable
= !has_dc
);
1705 emit_lri(&cmd_buffer
->batch
, GENX(SCRATCH1_num
), scratch1
);
1706 emit_lri(&cmd_buffer
->batch
, GENX(CHICKEN3_num
), chicken3
);
1712 cmd_buffer
->state
.current_l3_config
= cfg
;
1716 genX(cmd_buffer_apply_pipe_flushes
)(struct anv_cmd_buffer
*cmd_buffer
)
1718 enum anv_pipe_bits bits
= cmd_buffer
->state
.pending_pipe_bits
;
1720 /* Flushes are pipelined while invalidations are handled immediately.
1721 * Therefore, if we're flushing anything then we need to schedule a stall
1722 * before any invalidations can happen.
1724 if (bits
& ANV_PIPE_FLUSH_BITS
)
1725 bits
|= ANV_PIPE_NEEDS_CS_STALL_BIT
;
1727 /* If we're going to do an invalidate and we have a pending CS stall that
1728 * has yet to be resolved, we do the CS stall now.
1730 if ((bits
& ANV_PIPE_INVALIDATE_BITS
) &&
1731 (bits
& ANV_PIPE_NEEDS_CS_STALL_BIT
)) {
1732 bits
|= ANV_PIPE_CS_STALL_BIT
;
1733 bits
&= ~ANV_PIPE_NEEDS_CS_STALL_BIT
;
1736 if (bits
& (ANV_PIPE_FLUSH_BITS
| ANV_PIPE_CS_STALL_BIT
)) {
1737 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pipe
) {
1738 pipe
.DepthCacheFlushEnable
= bits
& ANV_PIPE_DEPTH_CACHE_FLUSH_BIT
;
1739 pipe
.DCFlushEnable
= bits
& ANV_PIPE_DATA_CACHE_FLUSH_BIT
;
1740 pipe
.RenderTargetCacheFlushEnable
=
1741 bits
& ANV_PIPE_RENDER_TARGET_CACHE_FLUSH_BIT
;
1743 pipe
.DepthStallEnable
= bits
& ANV_PIPE_DEPTH_STALL_BIT
;
1744 pipe
.CommandStreamerStallEnable
= bits
& ANV_PIPE_CS_STALL_BIT
;
1745 pipe
.StallAtPixelScoreboard
= bits
& ANV_PIPE_STALL_AT_SCOREBOARD_BIT
;
1748 * According to the Broadwell documentation, any PIPE_CONTROL with the
1749 * "Command Streamer Stall" bit set must also have another bit set,
1750 * with five different options:
1752 * - Render Target Cache Flush
1753 * - Depth Cache Flush
1754 * - Stall at Pixel Scoreboard
1755 * - Post-Sync Operation
1759 * I chose "Stall at Pixel Scoreboard" since that's what we use in
1760 * mesa and it seems to work fine. The choice is fairly arbitrary.
1762 if ((bits
& ANV_PIPE_CS_STALL_BIT
) &&
1763 !(bits
& (ANV_PIPE_FLUSH_BITS
| ANV_PIPE_DEPTH_STALL_BIT
|
1764 ANV_PIPE_STALL_AT_SCOREBOARD_BIT
)))
1765 pipe
.StallAtPixelScoreboard
= true;
1768 bits
&= ~(ANV_PIPE_FLUSH_BITS
| ANV_PIPE_CS_STALL_BIT
);
1771 if (bits
& ANV_PIPE_INVALIDATE_BITS
) {
1772 /* From the SKL PRM, Vol. 2a, "PIPE_CONTROL",
1774 * "If the VF Cache Invalidation Enable is set to a 1 in a
1775 * PIPE_CONTROL, a separate Null PIPE_CONTROL, all bitfields sets to
1776 * 0, with the VF Cache Invalidation Enable set to 0 needs to be sent
1777 * prior to the PIPE_CONTROL with VF Cache Invalidation Enable set to
1780 * This appears to hang Broadwell, so we restrict it to just gen9.
1782 if (GEN_GEN
== 9 && (bits
& ANV_PIPE_VF_CACHE_INVALIDATE_BIT
))
1783 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pipe
);
1785 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pipe
) {
1786 pipe
.StateCacheInvalidationEnable
=
1787 bits
& ANV_PIPE_STATE_CACHE_INVALIDATE_BIT
;
1788 pipe
.ConstantCacheInvalidationEnable
=
1789 bits
& ANV_PIPE_CONSTANT_CACHE_INVALIDATE_BIT
;
1790 pipe
.VFCacheInvalidationEnable
=
1791 bits
& ANV_PIPE_VF_CACHE_INVALIDATE_BIT
;
1792 pipe
.TextureCacheInvalidationEnable
=
1793 bits
& ANV_PIPE_TEXTURE_CACHE_INVALIDATE_BIT
;
1794 pipe
.InstructionCacheInvalidateEnable
=
1795 bits
& ANV_PIPE_INSTRUCTION_CACHE_INVALIDATE_BIT
;
1797 /* From the SKL PRM, Vol. 2a, "PIPE_CONTROL",
1799 * "When VF Cache Invalidate is set “Post Sync Operation” must be
1800 * enabled to “Write Immediate Data” or “Write PS Depth Count” or
1801 * “Write Timestamp”.
1803 if (GEN_GEN
== 9 && pipe
.VFCacheInvalidationEnable
) {
1804 pipe
.PostSyncOperation
= WriteImmediateData
;
1806 (struct anv_address
) { &cmd_buffer
->device
->workaround_bo
, 0 };
1810 bits
&= ~ANV_PIPE_INVALIDATE_BITS
;
1813 cmd_buffer
->state
.pending_pipe_bits
= bits
;
1816 void genX(CmdPipelineBarrier
)(
1817 VkCommandBuffer commandBuffer
,
1818 VkPipelineStageFlags srcStageMask
,
1819 VkPipelineStageFlags destStageMask
,
1821 uint32_t memoryBarrierCount
,
1822 const VkMemoryBarrier
* pMemoryBarriers
,
1823 uint32_t bufferMemoryBarrierCount
,
1824 const VkBufferMemoryBarrier
* pBufferMemoryBarriers
,
1825 uint32_t imageMemoryBarrierCount
,
1826 const VkImageMemoryBarrier
* pImageMemoryBarriers
)
1828 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
1830 /* XXX: Right now, we're really dumb and just flush whatever categories
1831 * the app asks for. One of these days we may make this a bit better
1832 * but right now that's all the hardware allows for in most areas.
1834 VkAccessFlags src_flags
= 0;
1835 VkAccessFlags dst_flags
= 0;
1837 for (uint32_t i
= 0; i
< memoryBarrierCount
; i
++) {
1838 src_flags
|= pMemoryBarriers
[i
].srcAccessMask
;
1839 dst_flags
|= pMemoryBarriers
[i
].dstAccessMask
;
1842 for (uint32_t i
= 0; i
< bufferMemoryBarrierCount
; i
++) {
1843 src_flags
|= pBufferMemoryBarriers
[i
].srcAccessMask
;
1844 dst_flags
|= pBufferMemoryBarriers
[i
].dstAccessMask
;
1847 for (uint32_t i
= 0; i
< imageMemoryBarrierCount
; i
++) {
1848 src_flags
|= pImageMemoryBarriers
[i
].srcAccessMask
;
1849 dst_flags
|= pImageMemoryBarriers
[i
].dstAccessMask
;
1850 ANV_FROM_HANDLE(anv_image
, image
, pImageMemoryBarriers
[i
].image
);
1851 const VkImageSubresourceRange
*range
=
1852 &pImageMemoryBarriers
[i
].subresourceRange
;
1854 if (range
->aspectMask
& VK_IMAGE_ASPECT_DEPTH_BIT
) {
1855 transition_depth_buffer(cmd_buffer
, image
,
1856 pImageMemoryBarriers
[i
].oldLayout
,
1857 pImageMemoryBarriers
[i
].newLayout
);
1858 } else if (range
->aspectMask
& VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV
) {
1859 VkImageAspectFlags color_aspects
=
1860 anv_image_expand_aspects(image
, range
->aspectMask
);
1861 uint32_t aspect_bit
;
1863 uint32_t base_layer
, layer_count
;
1864 if (image
->type
== VK_IMAGE_TYPE_3D
) {
1866 layer_count
= anv_minify(image
->extent
.depth
, range
->baseMipLevel
);
1868 base_layer
= range
->baseArrayLayer
;
1869 layer_count
= anv_get_layerCount(image
, range
);
1872 anv_foreach_image_aspect_bit(aspect_bit
, image
, color_aspects
) {
1873 transition_color_buffer(cmd_buffer
, image
, 1UL << aspect_bit
,
1874 range
->baseMipLevel
,
1875 anv_get_levelCount(image
, range
),
1876 base_layer
, layer_count
,
1877 pImageMemoryBarriers
[i
].oldLayout
,
1878 pImageMemoryBarriers
[i
].newLayout
);
1883 cmd_buffer
->state
.pending_pipe_bits
|=
1884 anv_pipe_flush_bits_for_access_flags(src_flags
) |
1885 anv_pipe_invalidate_bits_for_access_flags(dst_flags
);
1889 cmd_buffer_alloc_push_constants(struct anv_cmd_buffer
*cmd_buffer
)
1891 VkShaderStageFlags stages
=
1892 cmd_buffer
->state
.gfx
.base
.pipeline
->active_stages
;
1894 /* In order to avoid thrash, we assume that vertex and fragment stages
1895 * always exist. In the rare case where one is missing *and* the other
1896 * uses push concstants, this may be suboptimal. However, avoiding stalls
1897 * seems more important.
1899 stages
|= VK_SHADER_STAGE_FRAGMENT_BIT
| VK_SHADER_STAGE_VERTEX_BIT
;
1901 if (stages
== cmd_buffer
->state
.push_constant_stages
)
1905 const unsigned push_constant_kb
= 32;
1906 #elif GEN_IS_HASWELL
1907 const unsigned push_constant_kb
= cmd_buffer
->device
->info
.gt
== 3 ? 32 : 16;
1909 const unsigned push_constant_kb
= 16;
1912 const unsigned num_stages
=
1913 util_bitcount(stages
& VK_SHADER_STAGE_ALL_GRAPHICS
);
1914 unsigned size_per_stage
= push_constant_kb
/ num_stages
;
1916 /* Broadwell+ and Haswell gt3 require that the push constant sizes be in
1917 * units of 2KB. Incidentally, these are the same platforms that have
1918 * 32KB worth of push constant space.
1920 if (push_constant_kb
== 32)
1921 size_per_stage
&= ~1u;
1923 uint32_t kb_used
= 0;
1924 for (int i
= MESA_SHADER_VERTEX
; i
< MESA_SHADER_FRAGMENT
; i
++) {
1925 unsigned push_size
= (stages
& (1 << i
)) ? size_per_stage
: 0;
1926 anv_batch_emit(&cmd_buffer
->batch
,
1927 GENX(3DSTATE_PUSH_CONSTANT_ALLOC_VS
), alloc
) {
1928 alloc
._3DCommandSubOpcode
= 18 + i
;
1929 alloc
.ConstantBufferOffset
= (push_size
> 0) ? kb_used
: 0;
1930 alloc
.ConstantBufferSize
= push_size
;
1932 kb_used
+= push_size
;
1935 anv_batch_emit(&cmd_buffer
->batch
,
1936 GENX(3DSTATE_PUSH_CONSTANT_ALLOC_PS
), alloc
) {
1937 alloc
.ConstantBufferOffset
= kb_used
;
1938 alloc
.ConstantBufferSize
= push_constant_kb
- kb_used
;
1941 cmd_buffer
->state
.push_constant_stages
= stages
;
1943 /* From the BDW PRM for 3DSTATE_PUSH_CONSTANT_ALLOC_VS:
1945 * "The 3DSTATE_CONSTANT_VS must be reprogrammed prior to
1946 * the next 3DPRIMITIVE command after programming the
1947 * 3DSTATE_PUSH_CONSTANT_ALLOC_VS"
1949 * Since 3DSTATE_PUSH_CONSTANT_ALLOC_VS is programmed as part of
1950 * pipeline setup, we need to dirty push constants.
1952 cmd_buffer
->state
.push_constants_dirty
|= VK_SHADER_STAGE_ALL_GRAPHICS
;
1955 static const struct anv_descriptor
*
1956 anv_descriptor_for_binding(const struct anv_cmd_pipeline_state
*pipe_state
,
1957 const struct anv_pipeline_binding
*binding
)
1959 assert(binding
->set
< MAX_SETS
);
1960 const struct anv_descriptor_set
*set
=
1961 pipe_state
->descriptors
[binding
->set
];
1962 const uint32_t offset
=
1963 set
->layout
->binding
[binding
->binding
].descriptor_index
;
1964 return &set
->descriptors
[offset
+ binding
->index
];
1968 dynamic_offset_for_binding(const struct anv_cmd_pipeline_state
*pipe_state
,
1969 const struct anv_pipeline_binding
*binding
)
1971 assert(binding
->set
< MAX_SETS
);
1972 const struct anv_descriptor_set
*set
=
1973 pipe_state
->descriptors
[binding
->set
];
1975 uint32_t dynamic_offset_idx
=
1976 pipe_state
->layout
->set
[binding
->set
].dynamic_offset_start
+
1977 set
->layout
->binding
[binding
->binding
].dynamic_offset_index
+
1980 return pipe_state
->dynamic_offsets
[dynamic_offset_idx
];
1984 emit_binding_table(struct anv_cmd_buffer
*cmd_buffer
,
1985 gl_shader_stage stage
,
1986 struct anv_state
*bt_state
)
1988 struct anv_subpass
*subpass
= cmd_buffer
->state
.subpass
;
1989 struct anv_cmd_pipeline_state
*pipe_state
;
1990 struct anv_pipeline
*pipeline
;
1991 uint32_t bias
, state_offset
;
1994 case MESA_SHADER_COMPUTE
:
1995 pipe_state
= &cmd_buffer
->state
.compute
.base
;
1999 pipe_state
= &cmd_buffer
->state
.gfx
.base
;
2003 pipeline
= pipe_state
->pipeline
;
2005 if (!anv_pipeline_has_stage(pipeline
, stage
)) {
2006 *bt_state
= (struct anv_state
) { 0, };
2010 struct anv_pipeline_bind_map
*map
= &pipeline
->shaders
[stage
]->bind_map
;
2011 if (bias
+ map
->surface_count
== 0) {
2012 *bt_state
= (struct anv_state
) { 0, };
2016 *bt_state
= anv_cmd_buffer_alloc_binding_table(cmd_buffer
,
2017 bias
+ map
->surface_count
,
2019 uint32_t *bt_map
= bt_state
->map
;
2021 if (bt_state
->map
== NULL
)
2022 return VK_ERROR_OUT_OF_DEVICE_MEMORY
;
2024 if (stage
== MESA_SHADER_COMPUTE
&&
2025 get_cs_prog_data(pipeline
)->uses_num_work_groups
) {
2026 struct anv_state surface_state
;
2028 anv_cmd_buffer_alloc_surface_state(cmd_buffer
);
2030 const enum isl_format format
=
2031 anv_isl_format_for_descriptor_type(VK_DESCRIPTOR_TYPE_STORAGE_BUFFER
);
2032 anv_fill_buffer_surface_state(cmd_buffer
->device
, surface_state
,
2034 cmd_buffer
->state
.compute
.num_workgroups
,
2037 bt_map
[0] = surface_state
.offset
+ state_offset
;
2038 add_surface_reloc(cmd_buffer
, surface_state
,
2039 cmd_buffer
->state
.compute
.num_workgroups
);
2042 if (map
->surface_count
== 0)
2045 if (map
->image_count
> 0) {
2047 anv_cmd_buffer_ensure_push_constant_field(cmd_buffer
, stage
, images
);
2048 if (result
!= VK_SUCCESS
)
2051 cmd_buffer
->state
.push_constants_dirty
|= 1 << stage
;
2055 for (uint32_t s
= 0; s
< map
->surface_count
; s
++) {
2056 struct anv_pipeline_binding
*binding
= &map
->surface_to_descriptor
[s
];
2058 struct anv_state surface_state
;
2060 if (binding
->set
== ANV_DESCRIPTOR_SET_COLOR_ATTACHMENTS
) {
2061 /* Color attachment binding */
2062 assert(stage
== MESA_SHADER_FRAGMENT
);
2063 assert(binding
->binding
== 0);
2064 if (binding
->index
< subpass
->color_count
) {
2065 const unsigned att
=
2066 subpass
->color_attachments
[binding
->index
].attachment
;
2068 /* From the Vulkan 1.0.46 spec:
2070 * "If any color or depth/stencil attachments are
2071 * VK_ATTACHMENT_UNUSED, then no writes occur for those
2074 if (att
== VK_ATTACHMENT_UNUSED
) {
2075 surface_state
= cmd_buffer
->state
.null_surface_state
;
2077 surface_state
= cmd_buffer
->state
.attachments
[att
].color
.state
;
2080 surface_state
= cmd_buffer
->state
.null_surface_state
;
2083 bt_map
[bias
+ s
] = surface_state
.offset
+ state_offset
;
2085 } else if (binding
->set
== ANV_DESCRIPTOR_SET_SHADER_CONSTANTS
) {
2086 struct anv_state surface_state
=
2087 anv_cmd_buffer_alloc_surface_state(cmd_buffer
);
2089 struct anv_address constant_data
= {
2090 .bo
= &pipeline
->device
->dynamic_state_pool
.block_pool
.bo
,
2091 .offset
= pipeline
->shaders
[stage
]->constant_data
.offset
,
2093 unsigned constant_data_size
=
2094 pipeline
->shaders
[stage
]->constant_data_size
;
2096 const enum isl_format format
=
2097 anv_isl_format_for_descriptor_type(VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER
);
2098 anv_fill_buffer_surface_state(cmd_buffer
->device
,
2099 surface_state
, format
,
2100 constant_data
, constant_data_size
, 1);
2102 bt_map
[bias
+ s
] = surface_state
.offset
+ state_offset
;
2103 add_surface_reloc(cmd_buffer
, surface_state
, constant_data
);
2107 const struct anv_descriptor
*desc
=
2108 anv_descriptor_for_binding(pipe_state
, binding
);
2110 switch (desc
->type
) {
2111 case VK_DESCRIPTOR_TYPE_SAMPLER
:
2112 /* Nothing for us to do here */
2115 case VK_DESCRIPTOR_TYPE_COMBINED_IMAGE_SAMPLER
:
2116 case VK_DESCRIPTOR_TYPE_SAMPLED_IMAGE
: {
2117 struct anv_surface_state sstate
=
2118 (desc
->layout
== VK_IMAGE_LAYOUT_GENERAL
) ?
2119 desc
->image_view
->planes
[binding
->plane
].general_sampler_surface_state
:
2120 desc
->image_view
->planes
[binding
->plane
].optimal_sampler_surface_state
;
2121 surface_state
= sstate
.state
;
2122 assert(surface_state
.alloc_size
);
2123 add_surface_state_relocs(cmd_buffer
, sstate
);
2126 case VK_DESCRIPTOR_TYPE_INPUT_ATTACHMENT
:
2127 assert(stage
== MESA_SHADER_FRAGMENT
);
2128 if ((desc
->image_view
->aspect_mask
& VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV
) == 0) {
2129 /* For depth and stencil input attachments, we treat it like any
2130 * old texture that a user may have bound.
2132 struct anv_surface_state sstate
=
2133 (desc
->layout
== VK_IMAGE_LAYOUT_GENERAL
) ?
2134 desc
->image_view
->planes
[binding
->plane
].general_sampler_surface_state
:
2135 desc
->image_view
->planes
[binding
->plane
].optimal_sampler_surface_state
;
2136 surface_state
= sstate
.state
;
2137 assert(surface_state
.alloc_size
);
2138 add_surface_state_relocs(cmd_buffer
, sstate
);
2140 /* For color input attachments, we create the surface state at
2141 * vkBeginRenderPass time so that we can include aux and clear
2142 * color information.
2144 assert(binding
->input_attachment_index
< subpass
->input_count
);
2145 const unsigned subpass_att
= binding
->input_attachment_index
;
2146 const unsigned att
= subpass
->input_attachments
[subpass_att
].attachment
;
2147 surface_state
= cmd_buffer
->state
.attachments
[att
].input
.state
;
2151 case VK_DESCRIPTOR_TYPE_STORAGE_IMAGE
: {
2152 struct anv_surface_state sstate
= (binding
->write_only
)
2153 ? desc
->image_view
->planes
[binding
->plane
].writeonly_storage_surface_state
2154 : desc
->image_view
->planes
[binding
->plane
].storage_surface_state
;
2155 surface_state
= sstate
.state
;
2156 assert(surface_state
.alloc_size
);
2157 add_surface_state_relocs(cmd_buffer
, sstate
);
2159 struct brw_image_param
*image_param
=
2160 &cmd_buffer
->state
.push_constants
[stage
]->images
[image
++];
2162 *image_param
= desc
->image_view
->planes
[binding
->plane
].storage_image_param
;
2166 case VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER
:
2167 case VK_DESCRIPTOR_TYPE_STORAGE_BUFFER
:
2168 case VK_DESCRIPTOR_TYPE_UNIFORM_TEXEL_BUFFER
:
2169 surface_state
= desc
->buffer_view
->surface_state
;
2170 assert(surface_state
.alloc_size
);
2171 add_surface_reloc(cmd_buffer
, surface_state
,
2172 desc
->buffer_view
->address
);
2175 case VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER_DYNAMIC
:
2176 case VK_DESCRIPTOR_TYPE_STORAGE_BUFFER_DYNAMIC
: {
2177 /* Compute the offset within the buffer */
2178 uint32_t dynamic_offset
=
2179 dynamic_offset_for_binding(pipe_state
, binding
);
2180 uint64_t offset
= desc
->offset
+ dynamic_offset
;
2181 /* Clamp to the buffer size */
2182 offset
= MIN2(offset
, desc
->buffer
->size
);
2183 /* Clamp the range to the buffer size */
2184 uint32_t range
= MIN2(desc
->range
, desc
->buffer
->size
- offset
);
2186 struct anv_address address
=
2187 anv_address_add(desc
->buffer
->address
, offset
);
2190 anv_state_stream_alloc(&cmd_buffer
->surface_state_stream
, 64, 64);
2191 enum isl_format format
=
2192 anv_isl_format_for_descriptor_type(desc
->type
);
2194 anv_fill_buffer_surface_state(cmd_buffer
->device
, surface_state
,
2195 format
, address
, range
, 1);
2196 add_surface_reloc(cmd_buffer
, surface_state
, address
);
2200 case VK_DESCRIPTOR_TYPE_STORAGE_TEXEL_BUFFER
:
2201 surface_state
= (binding
->write_only
)
2202 ? desc
->buffer_view
->writeonly_storage_surface_state
2203 : desc
->buffer_view
->storage_surface_state
;
2204 assert(surface_state
.alloc_size
);
2205 add_surface_reloc(cmd_buffer
, surface_state
,
2206 desc
->buffer_view
->address
);
2208 struct brw_image_param
*image_param
=
2209 &cmd_buffer
->state
.push_constants
[stage
]->images
[image
++];
2211 *image_param
= desc
->buffer_view
->storage_image_param
;
2215 assert(!"Invalid descriptor type");
2219 bt_map
[bias
+ s
] = surface_state
.offset
+ state_offset
;
2221 assert(image
== map
->image_count
);
2224 anv_state_flush(cmd_buffer
->device
, *bt_state
);
2227 /* The PIPE_CONTROL command description says:
2229 * "Whenever a Binding Table Index (BTI) used by a Render Taget Message
2230 * points to a different RENDER_SURFACE_STATE, SW must issue a Render
2231 * Target Cache Flush by enabling this bit. When render target flush
2232 * is set due to new association of BTI, PS Scoreboard Stall bit must
2233 * be set in this packet."
2235 * FINISHME: Currently we shuffle around the surface states in the binding
2236 * table based on if they are getting used or not. So, we've to do below
2237 * pipe control flush for every binding table upload. Make changes so
2238 * that we do it only when we modify render target surface states.
2240 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pc
) {
2241 pc
.RenderTargetCacheFlushEnable
= true;
2242 pc
.StallAtPixelScoreboard
= true;
2250 emit_samplers(struct anv_cmd_buffer
*cmd_buffer
,
2251 gl_shader_stage stage
,
2252 struct anv_state
*state
)
2254 struct anv_cmd_pipeline_state
*pipe_state
=
2255 stage
== MESA_SHADER_COMPUTE
? &cmd_buffer
->state
.compute
.base
:
2256 &cmd_buffer
->state
.gfx
.base
;
2257 struct anv_pipeline
*pipeline
= pipe_state
->pipeline
;
2259 if (!anv_pipeline_has_stage(pipeline
, stage
)) {
2260 *state
= (struct anv_state
) { 0, };
2264 struct anv_pipeline_bind_map
*map
= &pipeline
->shaders
[stage
]->bind_map
;
2265 if (map
->sampler_count
== 0) {
2266 *state
= (struct anv_state
) { 0, };
2270 uint32_t size
= map
->sampler_count
* 16;
2271 *state
= anv_cmd_buffer_alloc_dynamic_state(cmd_buffer
, size
, 32);
2273 if (state
->map
== NULL
)
2274 return VK_ERROR_OUT_OF_DEVICE_MEMORY
;
2276 for (uint32_t s
= 0; s
< map
->sampler_count
; s
++) {
2277 struct anv_pipeline_binding
*binding
= &map
->sampler_to_descriptor
[s
];
2278 const struct anv_descriptor
*desc
=
2279 anv_descriptor_for_binding(pipe_state
, binding
);
2281 if (desc
->type
!= VK_DESCRIPTOR_TYPE_SAMPLER
&&
2282 desc
->type
!= VK_DESCRIPTOR_TYPE_COMBINED_IMAGE_SAMPLER
)
2285 struct anv_sampler
*sampler
= desc
->sampler
;
2287 /* This can happen if we have an unfilled slot since TYPE_SAMPLER
2288 * happens to be zero.
2290 if (sampler
== NULL
)
2293 memcpy(state
->map
+ (s
* 16),
2294 sampler
->state
[binding
->plane
], sizeof(sampler
->state
[0]));
2297 anv_state_flush(cmd_buffer
->device
, *state
);
2303 flush_descriptor_sets(struct anv_cmd_buffer
*cmd_buffer
)
2305 struct anv_pipeline
*pipeline
= cmd_buffer
->state
.gfx
.base
.pipeline
;
2307 VkShaderStageFlags dirty
= cmd_buffer
->state
.descriptors_dirty
&
2308 pipeline
->active_stages
;
2310 VkResult result
= VK_SUCCESS
;
2311 anv_foreach_stage(s
, dirty
) {
2312 result
= emit_samplers(cmd_buffer
, s
, &cmd_buffer
->state
.samplers
[s
]);
2313 if (result
!= VK_SUCCESS
)
2315 result
= emit_binding_table(cmd_buffer
, s
,
2316 &cmd_buffer
->state
.binding_tables
[s
]);
2317 if (result
!= VK_SUCCESS
)
2321 if (result
!= VK_SUCCESS
) {
2322 assert(result
== VK_ERROR_OUT_OF_DEVICE_MEMORY
);
2324 result
= anv_cmd_buffer_new_binding_table_block(cmd_buffer
);
2325 if (result
!= VK_SUCCESS
)
2328 /* Re-emit state base addresses so we get the new surface state base
2329 * address before we start emitting binding tables etc.
2331 genX(cmd_buffer_emit_state_base_address
)(cmd_buffer
);
2333 /* Re-emit all active binding tables */
2334 dirty
|= pipeline
->active_stages
;
2335 anv_foreach_stage(s
, dirty
) {
2336 result
= emit_samplers(cmd_buffer
, s
, &cmd_buffer
->state
.samplers
[s
]);
2337 if (result
!= VK_SUCCESS
) {
2338 anv_batch_set_error(&cmd_buffer
->batch
, result
);
2341 result
= emit_binding_table(cmd_buffer
, s
,
2342 &cmd_buffer
->state
.binding_tables
[s
]);
2343 if (result
!= VK_SUCCESS
) {
2344 anv_batch_set_error(&cmd_buffer
->batch
, result
);
2350 cmd_buffer
->state
.descriptors_dirty
&= ~dirty
;
2356 cmd_buffer_emit_descriptor_pointers(struct anv_cmd_buffer
*cmd_buffer
,
2359 static const uint32_t sampler_state_opcodes
[] = {
2360 [MESA_SHADER_VERTEX
] = 43,
2361 [MESA_SHADER_TESS_CTRL
] = 44, /* HS */
2362 [MESA_SHADER_TESS_EVAL
] = 45, /* DS */
2363 [MESA_SHADER_GEOMETRY
] = 46,
2364 [MESA_SHADER_FRAGMENT
] = 47,
2365 [MESA_SHADER_COMPUTE
] = 0,
2368 static const uint32_t binding_table_opcodes
[] = {
2369 [MESA_SHADER_VERTEX
] = 38,
2370 [MESA_SHADER_TESS_CTRL
] = 39,
2371 [MESA_SHADER_TESS_EVAL
] = 40,
2372 [MESA_SHADER_GEOMETRY
] = 41,
2373 [MESA_SHADER_FRAGMENT
] = 42,
2374 [MESA_SHADER_COMPUTE
] = 0,
2377 anv_foreach_stage(s
, stages
) {
2378 assert(s
< ARRAY_SIZE(binding_table_opcodes
));
2379 assert(binding_table_opcodes
[s
] > 0);
2381 if (cmd_buffer
->state
.samplers
[s
].alloc_size
> 0) {
2382 anv_batch_emit(&cmd_buffer
->batch
,
2383 GENX(3DSTATE_SAMPLER_STATE_POINTERS_VS
), ssp
) {
2384 ssp
._3DCommandSubOpcode
= sampler_state_opcodes
[s
];
2385 ssp
.PointertoVSSamplerState
= cmd_buffer
->state
.samplers
[s
].offset
;
2389 /* Always emit binding table pointers if we're asked to, since on SKL
2390 * this is what flushes push constants. */
2391 anv_batch_emit(&cmd_buffer
->batch
,
2392 GENX(3DSTATE_BINDING_TABLE_POINTERS_VS
), btp
) {
2393 btp
._3DCommandSubOpcode
= binding_table_opcodes
[s
];
2394 btp
.PointertoVSBindingTable
= cmd_buffer
->state
.binding_tables
[s
].offset
;
2400 cmd_buffer_flush_push_constants(struct anv_cmd_buffer
*cmd_buffer
,
2401 VkShaderStageFlags dirty_stages
)
2403 const struct anv_cmd_graphics_state
*gfx_state
= &cmd_buffer
->state
.gfx
;
2404 const struct anv_pipeline
*pipeline
= gfx_state
->base
.pipeline
;
2406 static const uint32_t push_constant_opcodes
[] = {
2407 [MESA_SHADER_VERTEX
] = 21,
2408 [MESA_SHADER_TESS_CTRL
] = 25, /* HS */
2409 [MESA_SHADER_TESS_EVAL
] = 26, /* DS */
2410 [MESA_SHADER_GEOMETRY
] = 22,
2411 [MESA_SHADER_FRAGMENT
] = 23,
2412 [MESA_SHADER_COMPUTE
] = 0,
2415 VkShaderStageFlags flushed
= 0;
2417 anv_foreach_stage(stage
, dirty_stages
) {
2418 assert(stage
< ARRAY_SIZE(push_constant_opcodes
));
2419 assert(push_constant_opcodes
[stage
] > 0);
2421 anv_batch_emit(&cmd_buffer
->batch
, GENX(3DSTATE_CONSTANT_VS
), c
) {
2422 c
._3DCommandSubOpcode
= push_constant_opcodes
[stage
];
2424 if (anv_pipeline_has_stage(pipeline
, stage
)) {
2425 #if GEN_GEN >= 8 || GEN_IS_HASWELL
2426 const struct brw_stage_prog_data
*prog_data
=
2427 pipeline
->shaders
[stage
]->prog_data
;
2428 const struct anv_pipeline_bind_map
*bind_map
=
2429 &pipeline
->shaders
[stage
]->bind_map
;
2431 /* The Skylake PRM contains the following restriction:
2433 * "The driver must ensure The following case does not occur
2434 * without a flush to the 3D engine: 3DSTATE_CONSTANT_* with
2435 * buffer 3 read length equal to zero committed followed by a
2436 * 3DSTATE_CONSTANT_* with buffer 0 read length not equal to
2439 * To avoid this, we program the buffers in the highest slots.
2440 * This way, slot 0 is only used if slot 3 is also used.
2444 for (int i
= 3; i
>= 0; i
--) {
2445 const struct brw_ubo_range
*range
= &prog_data
->ubo_ranges
[i
];
2446 if (range
->length
== 0)
2449 const unsigned surface
=
2450 prog_data
->binding_table
.ubo_start
+ range
->block
;
2452 assert(surface
<= bind_map
->surface_count
);
2453 const struct anv_pipeline_binding
*binding
=
2454 &bind_map
->surface_to_descriptor
[surface
];
2456 struct anv_address read_addr
;
2458 if (binding
->set
== ANV_DESCRIPTOR_SET_SHADER_CONSTANTS
) {
2459 struct anv_address constant_data
= {
2460 .bo
= &pipeline
->device
->dynamic_state_pool
.block_pool
.bo
,
2461 .offset
= pipeline
->shaders
[stage
]->constant_data
.offset
,
2463 unsigned constant_data_size
=
2464 pipeline
->shaders
[stage
]->constant_data_size
;
2466 read_len
= MIN2(range
->length
,
2467 DIV_ROUND_UP(constant_data_size
, 32) - range
->start
);
2468 read_addr
= anv_address_add(constant_data
,
2471 const struct anv_descriptor
*desc
=
2472 anv_descriptor_for_binding(&gfx_state
->base
, binding
);
2474 if (desc
->type
== VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER
) {
2475 read_len
= MIN2(range
->length
,
2476 DIV_ROUND_UP(desc
->buffer_view
->range
, 32) - range
->start
);
2477 read_addr
= anv_address_add(desc
->buffer_view
->address
,
2480 assert(desc
->type
== VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER_DYNAMIC
);
2482 uint32_t dynamic_offset
=
2483 dynamic_offset_for_binding(&gfx_state
->base
, binding
);
2484 uint32_t buf_offset
=
2485 MIN2(desc
->offset
+ dynamic_offset
, desc
->buffer
->size
);
2486 uint32_t buf_range
=
2487 MIN2(desc
->range
, desc
->buffer
->size
- buf_offset
);
2489 read_len
= MIN2(range
->length
,
2490 DIV_ROUND_UP(buf_range
, 32) - range
->start
);
2491 read_addr
= anv_address_add(desc
->buffer
->address
,
2492 buf_offset
+ range
->start
* 32);
2497 c
.ConstantBody
.Buffer
[n
] = read_addr
;
2498 c
.ConstantBody
.ReadLength
[n
] = read_len
;
2503 struct anv_state state
=
2504 anv_cmd_buffer_push_constants(cmd_buffer
, stage
);
2506 if (state
.alloc_size
> 0) {
2507 c
.ConstantBody
.Buffer
[n
] = (struct anv_address
) {
2508 .bo
= &cmd_buffer
->device
->dynamic_state_pool
.block_pool
.bo
,
2509 .offset
= state
.offset
,
2511 c
.ConstantBody
.ReadLength
[n
] =
2512 DIV_ROUND_UP(state
.alloc_size
, 32);
2515 /* For Ivy Bridge, the push constants packets have a different
2516 * rule that would require us to iterate in the other direction
2517 * and possibly mess around with dynamic state base address.
2518 * Don't bother; just emit regular push constants at n = 0.
2520 struct anv_state state
=
2521 anv_cmd_buffer_push_constants(cmd_buffer
, stage
);
2523 if (state
.alloc_size
> 0) {
2524 c
.ConstantBody
.Buffer
[0].offset
= state
.offset
,
2525 c
.ConstantBody
.ReadLength
[0] =
2526 DIV_ROUND_UP(state
.alloc_size
, 32);
2532 flushed
|= mesa_to_vk_shader_stage(stage
);
2535 cmd_buffer
->state
.push_constants_dirty
&= ~flushed
;
2539 genX(cmd_buffer_flush_state
)(struct anv_cmd_buffer
*cmd_buffer
)
2541 struct anv_pipeline
*pipeline
= cmd_buffer
->state
.gfx
.base
.pipeline
;
2544 uint32_t vb_emit
= cmd_buffer
->state
.gfx
.vb_dirty
& pipeline
->vb_used
;
2545 if (cmd_buffer
->state
.gfx
.dirty
& ANV_CMD_DIRTY_PIPELINE
)
2546 vb_emit
|= pipeline
->vb_used
;
2548 assert((pipeline
->active_stages
& VK_SHADER_STAGE_COMPUTE_BIT
) == 0);
2550 genX(cmd_buffer_config_l3
)(cmd_buffer
, pipeline
->urb
.l3_config
);
2552 genX(flush_pipeline_select_3d
)(cmd_buffer
);
2555 const uint32_t num_buffers
= __builtin_popcount(vb_emit
);
2556 const uint32_t num_dwords
= 1 + num_buffers
* 4;
2558 p
= anv_batch_emitn(&cmd_buffer
->batch
, num_dwords
,
2559 GENX(3DSTATE_VERTEX_BUFFERS
));
2561 for_each_bit(vb
, vb_emit
) {
2562 struct anv_buffer
*buffer
= cmd_buffer
->state
.vertex_bindings
[vb
].buffer
;
2563 uint32_t offset
= cmd_buffer
->state
.vertex_bindings
[vb
].offset
;
2565 struct GENX(VERTEX_BUFFER_STATE
) state
= {
2566 .VertexBufferIndex
= vb
,
2568 .VertexBufferMOCS
= anv_mocs_for_bo(cmd_buffer
->device
,
2569 buffer
->address
.bo
),
2571 .BufferAccessType
= pipeline
->vb
[vb
].instanced
? INSTANCEDATA
: VERTEXDATA
,
2572 .InstanceDataStepRate
= pipeline
->vb
[vb
].instance_divisor
,
2575 .AddressModifyEnable
= true,
2576 .BufferPitch
= pipeline
->vb
[vb
].stride
,
2577 .BufferStartingAddress
= anv_address_add(buffer
->address
, offset
),
2580 .BufferSize
= buffer
->size
- offset
2582 .EndAddress
= anv_address_add(buffer
->address
, buffer
->size
- 1),
2586 GENX(VERTEX_BUFFER_STATE_pack
)(&cmd_buffer
->batch
, &p
[1 + i
* 4], &state
);
2591 cmd_buffer
->state
.gfx
.vb_dirty
&= ~vb_emit
;
2593 if (cmd_buffer
->state
.gfx
.dirty
& ANV_CMD_DIRTY_PIPELINE
) {
2594 anv_batch_emit_batch(&cmd_buffer
->batch
, &pipeline
->batch
);
2596 /* The exact descriptor layout is pulled from the pipeline, so we need
2597 * to re-emit binding tables on every pipeline change.
2599 cmd_buffer
->state
.descriptors_dirty
|= pipeline
->active_stages
;
2601 /* If the pipeline changed, we may need to re-allocate push constant
2604 cmd_buffer_alloc_push_constants(cmd_buffer
);
2608 if (cmd_buffer
->state
.descriptors_dirty
& VK_SHADER_STAGE_VERTEX_BIT
||
2609 cmd_buffer
->state
.push_constants_dirty
& VK_SHADER_STAGE_VERTEX_BIT
) {
2610 /* From the IVB PRM Vol. 2, Part 1, Section 3.2.1:
2612 * "A PIPE_CONTROL with Post-Sync Operation set to 1h and a depth
2613 * stall needs to be sent just prior to any 3DSTATE_VS,
2614 * 3DSTATE_URB_VS, 3DSTATE_CONSTANT_VS,
2615 * 3DSTATE_BINDING_TABLE_POINTER_VS,
2616 * 3DSTATE_SAMPLER_STATE_POINTER_VS command. Only one
2617 * PIPE_CONTROL needs to be sent before any combination of VS
2618 * associated 3DSTATE."
2620 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pc
) {
2621 pc
.DepthStallEnable
= true;
2622 pc
.PostSyncOperation
= WriteImmediateData
;
2624 (struct anv_address
) { &cmd_buffer
->device
->workaround_bo
, 0 };
2629 /* Render targets live in the same binding table as fragment descriptors */
2630 if (cmd_buffer
->state
.gfx
.dirty
& ANV_CMD_DIRTY_RENDER_TARGETS
)
2631 cmd_buffer
->state
.descriptors_dirty
|= VK_SHADER_STAGE_FRAGMENT_BIT
;
2633 /* We emit the binding tables and sampler tables first, then emit push
2634 * constants and then finally emit binding table and sampler table
2635 * pointers. It has to happen in this order, since emitting the binding
2636 * tables may change the push constants (in case of storage images). After
2637 * emitting push constants, on SKL+ we have to emit the corresponding
2638 * 3DSTATE_BINDING_TABLE_POINTER_* for the push constants to take effect.
2641 if (cmd_buffer
->state
.descriptors_dirty
)
2642 dirty
= flush_descriptor_sets(cmd_buffer
);
2644 if (dirty
|| cmd_buffer
->state
.push_constants_dirty
) {
2645 /* Because we're pushing UBOs, we have to push whenever either
2646 * descriptors or push constants is dirty.
2648 dirty
|= cmd_buffer
->state
.push_constants_dirty
;
2649 dirty
&= ANV_STAGE_MASK
& VK_SHADER_STAGE_ALL_GRAPHICS
;
2650 cmd_buffer_flush_push_constants(cmd_buffer
, dirty
);
2654 cmd_buffer_emit_descriptor_pointers(cmd_buffer
, dirty
);
2656 if (cmd_buffer
->state
.gfx
.dirty
& ANV_CMD_DIRTY_DYNAMIC_VIEWPORT
)
2657 gen8_cmd_buffer_emit_viewport(cmd_buffer
);
2659 if (cmd_buffer
->state
.gfx
.dirty
& (ANV_CMD_DIRTY_DYNAMIC_VIEWPORT
|
2660 ANV_CMD_DIRTY_PIPELINE
)) {
2661 gen8_cmd_buffer_emit_depth_viewport(cmd_buffer
,
2662 pipeline
->depth_clamp_enable
);
2665 if (cmd_buffer
->state
.gfx
.dirty
& (ANV_CMD_DIRTY_DYNAMIC_SCISSOR
|
2666 ANV_CMD_DIRTY_RENDER_TARGETS
))
2667 gen7_cmd_buffer_emit_scissor(cmd_buffer
);
2669 genX(cmd_buffer_flush_dynamic_state
)(cmd_buffer
);
2671 genX(cmd_buffer_apply_pipe_flushes
)(cmd_buffer
);
2675 emit_vertex_bo(struct anv_cmd_buffer
*cmd_buffer
,
2676 struct anv_address addr
,
2677 uint32_t size
, uint32_t index
)
2679 uint32_t *p
= anv_batch_emitn(&cmd_buffer
->batch
, 5,
2680 GENX(3DSTATE_VERTEX_BUFFERS
));
2682 GENX(VERTEX_BUFFER_STATE_pack
)(&cmd_buffer
->batch
, p
+ 1,
2683 &(struct GENX(VERTEX_BUFFER_STATE
)) {
2684 .VertexBufferIndex
= index
,
2685 .AddressModifyEnable
= true,
2687 .VertexBufferMOCS
= anv_mocs_for_bo(cmd_buffer
->device
, addr
.bo
),
2689 .BufferStartingAddress
= addr
,
2692 .BufferStartingAddress
= addr
,
2693 .EndAddress
= anv_address_add(addr
, size
),
2699 emit_base_vertex_instance_bo(struct anv_cmd_buffer
*cmd_buffer
,
2700 struct anv_address addr
)
2702 emit_vertex_bo(cmd_buffer
, addr
, 8, ANV_SVGS_VB_INDEX
);
2706 emit_base_vertex_instance(struct anv_cmd_buffer
*cmd_buffer
,
2707 uint32_t base_vertex
, uint32_t base_instance
)
2709 struct anv_state id_state
=
2710 anv_cmd_buffer_alloc_dynamic_state(cmd_buffer
, 8, 4);
2712 ((uint32_t *)id_state
.map
)[0] = base_vertex
;
2713 ((uint32_t *)id_state
.map
)[1] = base_instance
;
2715 anv_state_flush(cmd_buffer
->device
, id_state
);
2717 struct anv_address addr
= {
2718 .bo
= &cmd_buffer
->device
->dynamic_state_pool
.block_pool
.bo
,
2719 .offset
= id_state
.offset
,
2722 emit_base_vertex_instance_bo(cmd_buffer
, addr
);
2726 emit_draw_index(struct anv_cmd_buffer
*cmd_buffer
, uint32_t draw_index
)
2728 struct anv_state state
=
2729 anv_cmd_buffer_alloc_dynamic_state(cmd_buffer
, 4, 4);
2731 ((uint32_t *)state
.map
)[0] = draw_index
;
2733 anv_state_flush(cmd_buffer
->device
, state
);
2735 struct anv_address addr
= {
2736 .bo
= &cmd_buffer
->device
->dynamic_state_pool
.block_pool
.bo
,
2737 .offset
= state
.offset
,
2740 emit_vertex_bo(cmd_buffer
, addr
, 4, ANV_DRAWID_VB_INDEX
);
2744 VkCommandBuffer commandBuffer
,
2745 uint32_t vertexCount
,
2746 uint32_t instanceCount
,
2747 uint32_t firstVertex
,
2748 uint32_t firstInstance
)
2750 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
2751 struct anv_pipeline
*pipeline
= cmd_buffer
->state
.gfx
.base
.pipeline
;
2752 const struct brw_vs_prog_data
*vs_prog_data
= get_vs_prog_data(pipeline
);
2754 if (anv_batch_has_error(&cmd_buffer
->batch
))
2757 genX(cmd_buffer_flush_state
)(cmd_buffer
);
2759 if (vs_prog_data
->uses_firstvertex
||
2760 vs_prog_data
->uses_baseinstance
)
2761 emit_base_vertex_instance(cmd_buffer
, firstVertex
, firstInstance
);
2762 if (vs_prog_data
->uses_drawid
)
2763 emit_draw_index(cmd_buffer
, 0);
2765 /* Our implementation of VK_KHR_multiview uses instancing to draw the
2766 * different views. We need to multiply instanceCount by the view count.
2768 instanceCount
*= anv_subpass_view_count(cmd_buffer
->state
.subpass
);
2770 anv_batch_emit(&cmd_buffer
->batch
, GENX(3DPRIMITIVE
), prim
) {
2771 prim
.VertexAccessType
= SEQUENTIAL
;
2772 prim
.PrimitiveTopologyType
= pipeline
->topology
;
2773 prim
.VertexCountPerInstance
= vertexCount
;
2774 prim
.StartVertexLocation
= firstVertex
;
2775 prim
.InstanceCount
= instanceCount
;
2776 prim
.StartInstanceLocation
= firstInstance
;
2777 prim
.BaseVertexLocation
= 0;
2781 void genX(CmdDrawIndexed
)(
2782 VkCommandBuffer commandBuffer
,
2783 uint32_t indexCount
,
2784 uint32_t instanceCount
,
2785 uint32_t firstIndex
,
2786 int32_t vertexOffset
,
2787 uint32_t firstInstance
)
2789 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
2790 struct anv_pipeline
*pipeline
= cmd_buffer
->state
.gfx
.base
.pipeline
;
2791 const struct brw_vs_prog_data
*vs_prog_data
= get_vs_prog_data(pipeline
);
2793 if (anv_batch_has_error(&cmd_buffer
->batch
))
2796 genX(cmd_buffer_flush_state
)(cmd_buffer
);
2798 if (vs_prog_data
->uses_firstvertex
||
2799 vs_prog_data
->uses_baseinstance
)
2800 emit_base_vertex_instance(cmd_buffer
, vertexOffset
, firstInstance
);
2801 if (vs_prog_data
->uses_drawid
)
2802 emit_draw_index(cmd_buffer
, 0);
2804 /* Our implementation of VK_KHR_multiview uses instancing to draw the
2805 * different views. We need to multiply instanceCount by the view count.
2807 instanceCount
*= anv_subpass_view_count(cmd_buffer
->state
.subpass
);
2809 anv_batch_emit(&cmd_buffer
->batch
, GENX(3DPRIMITIVE
), prim
) {
2810 prim
.VertexAccessType
= RANDOM
;
2811 prim
.PrimitiveTopologyType
= pipeline
->topology
;
2812 prim
.VertexCountPerInstance
= indexCount
;
2813 prim
.StartVertexLocation
= firstIndex
;
2814 prim
.InstanceCount
= instanceCount
;
2815 prim
.StartInstanceLocation
= firstInstance
;
2816 prim
.BaseVertexLocation
= vertexOffset
;
2820 /* Auto-Draw / Indirect Registers */
2821 #define GEN7_3DPRIM_END_OFFSET 0x2420
2822 #define GEN7_3DPRIM_START_VERTEX 0x2430
2823 #define GEN7_3DPRIM_VERTEX_COUNT 0x2434
2824 #define GEN7_3DPRIM_INSTANCE_COUNT 0x2438
2825 #define GEN7_3DPRIM_START_INSTANCE 0x243C
2826 #define GEN7_3DPRIM_BASE_VERTEX 0x2440
2828 /* MI_MATH only exists on Haswell+ */
2829 #if GEN_IS_HASWELL || GEN_GEN >= 8
2831 /* Emit dwords to multiply GPR0 by N */
2833 build_alu_multiply_gpr0(uint32_t *dw
, unsigned *dw_count
, uint32_t N
)
2835 VK_OUTARRAY_MAKE(out
, dw
, dw_count
);
2837 #define append_alu(opcode, operand1, operand2) \
2838 vk_outarray_append(&out, alu_dw) *alu_dw = mi_alu(opcode, operand1, operand2)
2841 unsigned top_bit
= 31 - __builtin_clz(N
);
2842 for (int i
= top_bit
- 1; i
>= 0; i
--) {
2843 /* We get our initial data in GPR0 and we write the final data out to
2844 * GPR0 but we use GPR1 as our scratch register.
2846 unsigned src_reg
= i
== top_bit
- 1 ? MI_ALU_REG0
: MI_ALU_REG1
;
2847 unsigned dst_reg
= i
== 0 ? MI_ALU_REG0
: MI_ALU_REG1
;
2849 /* Shift the current value left by 1 */
2850 append_alu(MI_ALU_LOAD
, MI_ALU_SRCA
, src_reg
);
2851 append_alu(MI_ALU_LOAD
, MI_ALU_SRCB
, src_reg
);
2852 append_alu(MI_ALU_ADD
, 0, 0);
2855 /* Store ACCU to R1 and add R0 to R1 */
2856 append_alu(MI_ALU_STORE
, MI_ALU_REG1
, MI_ALU_ACCU
);
2857 append_alu(MI_ALU_LOAD
, MI_ALU_SRCA
, MI_ALU_REG0
);
2858 append_alu(MI_ALU_LOAD
, MI_ALU_SRCB
, MI_ALU_REG1
);
2859 append_alu(MI_ALU_ADD
, 0, 0);
2862 append_alu(MI_ALU_STORE
, dst_reg
, MI_ALU_ACCU
);
2869 emit_mul_gpr0(struct anv_batch
*batch
, uint32_t N
)
2871 uint32_t num_dwords
;
2872 build_alu_multiply_gpr0(NULL
, &num_dwords
, N
);
2874 uint32_t *dw
= anv_batch_emitn(batch
, 1 + num_dwords
, GENX(MI_MATH
));
2875 build_alu_multiply_gpr0(dw
+ 1, &num_dwords
, N
);
2878 #endif /* GEN_IS_HASWELL || GEN_GEN >= 8 */
2881 load_indirect_parameters(struct anv_cmd_buffer
*cmd_buffer
,
2882 struct anv_address addr
,
2885 struct anv_batch
*batch
= &cmd_buffer
->batch
;
2887 emit_lrm(batch
, GEN7_3DPRIM_VERTEX_COUNT
, anv_address_add(addr
, 0));
2889 unsigned view_count
= anv_subpass_view_count(cmd_buffer
->state
.subpass
);
2890 if (view_count
> 1) {
2891 #if GEN_IS_HASWELL || GEN_GEN >= 8
2892 emit_lrm(batch
, CS_GPR(0), anv_address_add(addr
, 4));
2893 emit_mul_gpr0(batch
, view_count
);
2894 emit_lrr(batch
, GEN7_3DPRIM_INSTANCE_COUNT
, CS_GPR(0));
2896 anv_finishme("Multiview + indirect draw requires MI_MATH; "
2897 "MI_MATH is not supported on Ivy Bridge");
2898 emit_lrm(batch
, GEN7_3DPRIM_INSTANCE_COUNT
, anv_address_add(addr
, 4));
2901 emit_lrm(batch
, GEN7_3DPRIM_INSTANCE_COUNT
, anv_address_add(addr
, 4));
2904 emit_lrm(batch
, GEN7_3DPRIM_START_VERTEX
, anv_address_add(addr
, 8));
2907 emit_lrm(batch
, GEN7_3DPRIM_BASE_VERTEX
, anv_address_add(addr
, 12));
2908 emit_lrm(batch
, GEN7_3DPRIM_START_INSTANCE
, anv_address_add(addr
, 16));
2910 emit_lrm(batch
, GEN7_3DPRIM_START_INSTANCE
, anv_address_add(addr
, 12));
2911 emit_lri(batch
, GEN7_3DPRIM_BASE_VERTEX
, 0);
2915 void genX(CmdDrawIndirect
)(
2916 VkCommandBuffer commandBuffer
,
2918 VkDeviceSize offset
,
2922 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
2923 ANV_FROM_HANDLE(anv_buffer
, buffer
, _buffer
);
2924 struct anv_pipeline
*pipeline
= cmd_buffer
->state
.gfx
.base
.pipeline
;
2925 const struct brw_vs_prog_data
*vs_prog_data
= get_vs_prog_data(pipeline
);
2927 if (anv_batch_has_error(&cmd_buffer
->batch
))
2930 genX(cmd_buffer_flush_state
)(cmd_buffer
);
2932 for (uint32_t i
= 0; i
< drawCount
; i
++) {
2933 struct anv_address draw
= anv_address_add(buffer
->address
, offset
);
2935 if (vs_prog_data
->uses_firstvertex
||
2936 vs_prog_data
->uses_baseinstance
)
2937 emit_base_vertex_instance_bo(cmd_buffer
, anv_address_add(draw
, 8));
2938 if (vs_prog_data
->uses_drawid
)
2939 emit_draw_index(cmd_buffer
, i
);
2941 load_indirect_parameters(cmd_buffer
, draw
, false);
2943 anv_batch_emit(&cmd_buffer
->batch
, GENX(3DPRIMITIVE
), prim
) {
2944 prim
.IndirectParameterEnable
= true;
2945 prim
.VertexAccessType
= SEQUENTIAL
;
2946 prim
.PrimitiveTopologyType
= pipeline
->topology
;
2953 void genX(CmdDrawIndexedIndirect
)(
2954 VkCommandBuffer commandBuffer
,
2956 VkDeviceSize offset
,
2960 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
2961 ANV_FROM_HANDLE(anv_buffer
, buffer
, _buffer
);
2962 struct anv_pipeline
*pipeline
= cmd_buffer
->state
.gfx
.base
.pipeline
;
2963 const struct brw_vs_prog_data
*vs_prog_data
= get_vs_prog_data(pipeline
);
2965 if (anv_batch_has_error(&cmd_buffer
->batch
))
2968 genX(cmd_buffer_flush_state
)(cmd_buffer
);
2970 for (uint32_t i
= 0; i
< drawCount
; i
++) {
2971 struct anv_address draw
= anv_address_add(buffer
->address
, offset
);
2973 /* TODO: We need to stomp base vertex to 0 somehow */
2974 if (vs_prog_data
->uses_firstvertex
||
2975 vs_prog_data
->uses_baseinstance
)
2976 emit_base_vertex_instance_bo(cmd_buffer
, anv_address_add(draw
, 12));
2977 if (vs_prog_data
->uses_drawid
)
2978 emit_draw_index(cmd_buffer
, i
);
2980 load_indirect_parameters(cmd_buffer
, draw
, true);
2982 anv_batch_emit(&cmd_buffer
->batch
, GENX(3DPRIMITIVE
), prim
) {
2983 prim
.IndirectParameterEnable
= true;
2984 prim
.VertexAccessType
= RANDOM
;
2985 prim
.PrimitiveTopologyType
= pipeline
->topology
;
2993 flush_compute_descriptor_set(struct anv_cmd_buffer
*cmd_buffer
)
2995 struct anv_pipeline
*pipeline
= cmd_buffer
->state
.compute
.base
.pipeline
;
2996 struct anv_state surfaces
= { 0, }, samplers
= { 0, };
2999 result
= emit_binding_table(cmd_buffer
, MESA_SHADER_COMPUTE
, &surfaces
);
3000 if (result
!= VK_SUCCESS
) {
3001 assert(result
== VK_ERROR_OUT_OF_DEVICE_MEMORY
);
3003 result
= anv_cmd_buffer_new_binding_table_block(cmd_buffer
);
3004 if (result
!= VK_SUCCESS
)
3007 /* Re-emit state base addresses so we get the new surface state base
3008 * address before we start emitting binding tables etc.
3010 genX(cmd_buffer_emit_state_base_address
)(cmd_buffer
);
3012 result
= emit_binding_table(cmd_buffer
, MESA_SHADER_COMPUTE
, &surfaces
);
3013 if (result
!= VK_SUCCESS
) {
3014 anv_batch_set_error(&cmd_buffer
->batch
, result
);
3019 result
= emit_samplers(cmd_buffer
, MESA_SHADER_COMPUTE
, &samplers
);
3020 if (result
!= VK_SUCCESS
) {
3021 anv_batch_set_error(&cmd_buffer
->batch
, result
);
3025 uint32_t iface_desc_data_dw
[GENX(INTERFACE_DESCRIPTOR_DATA_length
)];
3026 struct GENX(INTERFACE_DESCRIPTOR_DATA
) desc
= {
3027 .BindingTablePointer
= surfaces
.offset
,
3028 .SamplerStatePointer
= samplers
.offset
,
3030 GENX(INTERFACE_DESCRIPTOR_DATA_pack
)(NULL
, iface_desc_data_dw
, &desc
);
3032 struct anv_state state
=
3033 anv_cmd_buffer_merge_dynamic(cmd_buffer
, iface_desc_data_dw
,
3034 pipeline
->interface_descriptor_data
,
3035 GENX(INTERFACE_DESCRIPTOR_DATA_length
),
3038 uint32_t size
= GENX(INTERFACE_DESCRIPTOR_DATA_length
) * sizeof(uint32_t);
3039 anv_batch_emit(&cmd_buffer
->batch
,
3040 GENX(MEDIA_INTERFACE_DESCRIPTOR_LOAD
), mid
) {
3041 mid
.InterfaceDescriptorTotalLength
= size
;
3042 mid
.InterfaceDescriptorDataStartAddress
= state
.offset
;
3049 genX(cmd_buffer_flush_compute_state
)(struct anv_cmd_buffer
*cmd_buffer
)
3051 struct anv_pipeline
*pipeline
= cmd_buffer
->state
.compute
.base
.pipeline
;
3052 MAYBE_UNUSED VkResult result
;
3054 assert(pipeline
->active_stages
== VK_SHADER_STAGE_COMPUTE_BIT
);
3056 genX(cmd_buffer_config_l3
)(cmd_buffer
, pipeline
->urb
.l3_config
);
3058 genX(flush_pipeline_select_gpgpu
)(cmd_buffer
);
3060 if (cmd_buffer
->state
.compute
.pipeline_dirty
) {
3061 /* From the Sky Lake PRM Vol 2a, MEDIA_VFE_STATE:
3063 * "A stalling PIPE_CONTROL is required before MEDIA_VFE_STATE unless
3064 * the only bits that are changed are scoreboard related: Scoreboard
3065 * Enable, Scoreboard Type, Scoreboard Mask, Scoreboard * Delta. For
3066 * these scoreboard related states, a MEDIA_STATE_FLUSH is
3069 cmd_buffer
->state
.pending_pipe_bits
|= ANV_PIPE_CS_STALL_BIT
;
3070 genX(cmd_buffer_apply_pipe_flushes
)(cmd_buffer
);
3072 anv_batch_emit_batch(&cmd_buffer
->batch
, &pipeline
->batch
);
3075 if ((cmd_buffer
->state
.descriptors_dirty
& VK_SHADER_STAGE_COMPUTE_BIT
) ||
3076 cmd_buffer
->state
.compute
.pipeline_dirty
) {
3077 /* FIXME: figure out descriptors for gen7 */
3078 result
= flush_compute_descriptor_set(cmd_buffer
);
3079 if (result
!= VK_SUCCESS
)
3082 cmd_buffer
->state
.descriptors_dirty
&= ~VK_SHADER_STAGE_COMPUTE_BIT
;
3085 if (cmd_buffer
->state
.push_constants_dirty
& VK_SHADER_STAGE_COMPUTE_BIT
) {
3086 struct anv_state push_state
=
3087 anv_cmd_buffer_cs_push_constants(cmd_buffer
);
3089 if (push_state
.alloc_size
) {
3090 anv_batch_emit(&cmd_buffer
->batch
, GENX(MEDIA_CURBE_LOAD
), curbe
) {
3091 curbe
.CURBETotalDataLength
= push_state
.alloc_size
;
3092 curbe
.CURBEDataStartAddress
= push_state
.offset
;
3096 cmd_buffer
->state
.push_constants_dirty
&= ~VK_SHADER_STAGE_COMPUTE_BIT
;
3099 cmd_buffer
->state
.compute
.pipeline_dirty
= false;
3101 genX(cmd_buffer_apply_pipe_flushes
)(cmd_buffer
);
3107 verify_cmd_parser(const struct anv_device
*device
,
3108 int required_version
,
3109 const char *function
)
3111 if (device
->instance
->physicalDevice
.cmd_parser_version
< required_version
) {
3112 return vk_errorf(device
->instance
, device
->instance
,
3113 VK_ERROR_FEATURE_NOT_PRESENT
,
3114 "cmd parser version %d is required for %s",
3115 required_version
, function
);
3124 anv_cmd_buffer_push_base_group_id(struct anv_cmd_buffer
*cmd_buffer
,
3125 uint32_t baseGroupX
,
3126 uint32_t baseGroupY
,
3127 uint32_t baseGroupZ
)
3129 if (anv_batch_has_error(&cmd_buffer
->batch
))
3133 anv_cmd_buffer_ensure_push_constant_field(cmd_buffer
, MESA_SHADER_COMPUTE
,
3134 base_work_group_id
);
3135 if (result
!= VK_SUCCESS
) {
3136 cmd_buffer
->batch
.status
= result
;
3140 struct anv_push_constants
*push
=
3141 cmd_buffer
->state
.push_constants
[MESA_SHADER_COMPUTE
];
3142 if (push
->base_work_group_id
[0] != baseGroupX
||
3143 push
->base_work_group_id
[1] != baseGroupY
||
3144 push
->base_work_group_id
[2] != baseGroupZ
) {
3145 push
->base_work_group_id
[0] = baseGroupX
;
3146 push
->base_work_group_id
[1] = baseGroupY
;
3147 push
->base_work_group_id
[2] = baseGroupZ
;
3149 cmd_buffer
->state
.push_constants_dirty
|= VK_SHADER_STAGE_COMPUTE_BIT
;
3153 void genX(CmdDispatch
)(
3154 VkCommandBuffer commandBuffer
,
3159 genX(CmdDispatchBase
)(commandBuffer
, 0, 0, 0, x
, y
, z
);
3162 void genX(CmdDispatchBase
)(
3163 VkCommandBuffer commandBuffer
,
3164 uint32_t baseGroupX
,
3165 uint32_t baseGroupY
,
3166 uint32_t baseGroupZ
,
3167 uint32_t groupCountX
,
3168 uint32_t groupCountY
,
3169 uint32_t groupCountZ
)
3171 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
3172 struct anv_pipeline
*pipeline
= cmd_buffer
->state
.compute
.base
.pipeline
;
3173 const struct brw_cs_prog_data
*prog_data
= get_cs_prog_data(pipeline
);
3175 anv_cmd_buffer_push_base_group_id(cmd_buffer
, baseGroupX
,
3176 baseGroupY
, baseGroupZ
);
3178 if (anv_batch_has_error(&cmd_buffer
->batch
))
3181 if (prog_data
->uses_num_work_groups
) {
3182 struct anv_state state
=
3183 anv_cmd_buffer_alloc_dynamic_state(cmd_buffer
, 12, 4);
3184 uint32_t *sizes
= state
.map
;
3185 sizes
[0] = groupCountX
;
3186 sizes
[1] = groupCountY
;
3187 sizes
[2] = groupCountZ
;
3188 anv_state_flush(cmd_buffer
->device
, state
);
3189 cmd_buffer
->state
.compute
.num_workgroups
= (struct anv_address
) {
3190 .bo
= &cmd_buffer
->device
->dynamic_state_pool
.block_pool
.bo
,
3191 .offset
= state
.offset
,
3195 genX(cmd_buffer_flush_compute_state
)(cmd_buffer
);
3197 anv_batch_emit(&cmd_buffer
->batch
, GENX(GPGPU_WALKER
), ggw
) {
3198 ggw
.SIMDSize
= prog_data
->simd_size
/ 16;
3199 ggw
.ThreadDepthCounterMaximum
= 0;
3200 ggw
.ThreadHeightCounterMaximum
= 0;
3201 ggw
.ThreadWidthCounterMaximum
= prog_data
->threads
- 1;
3202 ggw
.ThreadGroupIDXDimension
= groupCountX
;
3203 ggw
.ThreadGroupIDYDimension
= groupCountY
;
3204 ggw
.ThreadGroupIDZDimension
= groupCountZ
;
3205 ggw
.RightExecutionMask
= pipeline
->cs_right_mask
;
3206 ggw
.BottomExecutionMask
= 0xffffffff;
3209 anv_batch_emit(&cmd_buffer
->batch
, GENX(MEDIA_STATE_FLUSH
), msf
);
3212 #define GPGPU_DISPATCHDIMX 0x2500
3213 #define GPGPU_DISPATCHDIMY 0x2504
3214 #define GPGPU_DISPATCHDIMZ 0x2508
3216 void genX(CmdDispatchIndirect
)(
3217 VkCommandBuffer commandBuffer
,
3219 VkDeviceSize offset
)
3221 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
3222 ANV_FROM_HANDLE(anv_buffer
, buffer
, _buffer
);
3223 struct anv_pipeline
*pipeline
= cmd_buffer
->state
.compute
.base
.pipeline
;
3224 const struct brw_cs_prog_data
*prog_data
= get_cs_prog_data(pipeline
);
3225 struct anv_address addr
= anv_address_add(buffer
->address
, offset
);
3226 struct anv_batch
*batch
= &cmd_buffer
->batch
;
3228 anv_cmd_buffer_push_base_group_id(cmd_buffer
, 0, 0, 0);
3231 /* Linux 4.4 added command parser version 5 which allows the GPGPU
3232 * indirect dispatch registers to be written.
3234 if (verify_cmd_parser(cmd_buffer
->device
, 5,
3235 "vkCmdDispatchIndirect") != VK_SUCCESS
)
3239 if (prog_data
->uses_num_work_groups
)
3240 cmd_buffer
->state
.compute
.num_workgroups
= addr
;
3242 genX(cmd_buffer_flush_compute_state
)(cmd_buffer
);
3244 emit_lrm(batch
, GPGPU_DISPATCHDIMX
, anv_address_add(addr
, 0));
3245 emit_lrm(batch
, GPGPU_DISPATCHDIMY
, anv_address_add(addr
, 4));
3246 emit_lrm(batch
, GPGPU_DISPATCHDIMZ
, anv_address_add(addr
, 8));
3249 /* Clear upper 32-bits of SRC0 and all 64-bits of SRC1 */
3250 emit_lri(batch
, MI_PREDICATE_SRC0
+ 4, 0);
3251 emit_lri(batch
, MI_PREDICATE_SRC1
+ 0, 0);
3252 emit_lri(batch
, MI_PREDICATE_SRC1
+ 4, 0);
3254 /* Load compute_dispatch_indirect_x_size into SRC0 */
3255 emit_lrm(batch
, MI_PREDICATE_SRC0
, anv_address_add(addr
, 0));
3257 /* predicate = (compute_dispatch_indirect_x_size == 0); */
3258 anv_batch_emit(batch
, GENX(MI_PREDICATE
), mip
) {
3259 mip
.LoadOperation
= LOAD_LOAD
;
3260 mip
.CombineOperation
= COMBINE_SET
;
3261 mip
.CompareOperation
= COMPARE_SRCS_EQUAL
;
3264 /* Load compute_dispatch_indirect_y_size into SRC0 */
3265 emit_lrm(batch
, MI_PREDICATE_SRC0
, anv_address_add(addr
, 4));
3267 /* predicate |= (compute_dispatch_indirect_y_size == 0); */
3268 anv_batch_emit(batch
, GENX(MI_PREDICATE
), mip
) {
3269 mip
.LoadOperation
= LOAD_LOAD
;
3270 mip
.CombineOperation
= COMBINE_OR
;
3271 mip
.CompareOperation
= COMPARE_SRCS_EQUAL
;
3274 /* Load compute_dispatch_indirect_z_size into SRC0 */
3275 emit_lrm(batch
, MI_PREDICATE_SRC0
, anv_address_add(addr
, 8));
3277 /* predicate |= (compute_dispatch_indirect_z_size == 0); */
3278 anv_batch_emit(batch
, GENX(MI_PREDICATE
), mip
) {
3279 mip
.LoadOperation
= LOAD_LOAD
;
3280 mip
.CombineOperation
= COMBINE_OR
;
3281 mip
.CompareOperation
= COMPARE_SRCS_EQUAL
;
3284 /* predicate = !predicate; */
3285 #define COMPARE_FALSE 1
3286 anv_batch_emit(batch
, GENX(MI_PREDICATE
), mip
) {
3287 mip
.LoadOperation
= LOAD_LOADINV
;
3288 mip
.CombineOperation
= COMBINE_OR
;
3289 mip
.CompareOperation
= COMPARE_FALSE
;
3293 anv_batch_emit(batch
, GENX(GPGPU_WALKER
), ggw
) {
3294 ggw
.IndirectParameterEnable
= true;
3295 ggw
.PredicateEnable
= GEN_GEN
<= 7;
3296 ggw
.SIMDSize
= prog_data
->simd_size
/ 16;
3297 ggw
.ThreadDepthCounterMaximum
= 0;
3298 ggw
.ThreadHeightCounterMaximum
= 0;
3299 ggw
.ThreadWidthCounterMaximum
= prog_data
->threads
- 1;
3300 ggw
.RightExecutionMask
= pipeline
->cs_right_mask
;
3301 ggw
.BottomExecutionMask
= 0xffffffff;
3304 anv_batch_emit(batch
, GENX(MEDIA_STATE_FLUSH
), msf
);
3308 genX(flush_pipeline_select
)(struct anv_cmd_buffer
*cmd_buffer
,
3311 UNUSED
const struct gen_device_info
*devinfo
= &cmd_buffer
->device
->info
;
3313 if (cmd_buffer
->state
.current_pipeline
== pipeline
)
3316 #if GEN_GEN >= 8 && GEN_GEN < 10
3317 /* From the Broadwell PRM, Volume 2a: Instructions, PIPELINE_SELECT:
3319 * Software must clear the COLOR_CALC_STATE Valid field in
3320 * 3DSTATE_CC_STATE_POINTERS command prior to send a PIPELINE_SELECT
3321 * with Pipeline Select set to GPGPU.
3323 * The internal hardware docs recommend the same workaround for Gen9
3326 if (pipeline
== GPGPU
)
3327 anv_batch_emit(&cmd_buffer
->batch
, GENX(3DSTATE_CC_STATE_POINTERS
), t
);
3330 /* From "BXML » GT » MI » vol1a GPU Overview » [Instruction]
3331 * PIPELINE_SELECT [DevBWR+]":
3335 * Software must ensure all the write caches are flushed through a
3336 * stalling PIPE_CONTROL command followed by another PIPE_CONTROL
3337 * command to invalidate read only caches prior to programming
3338 * MI_PIPELINE_SELECT command to change the Pipeline Select Mode.
3340 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pc
) {
3341 pc
.RenderTargetCacheFlushEnable
= true;
3342 pc
.DepthCacheFlushEnable
= true;
3343 pc
.DCFlushEnable
= true;
3344 pc
.PostSyncOperation
= NoWrite
;
3345 pc
.CommandStreamerStallEnable
= true;
3348 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pc
) {
3349 pc
.TextureCacheInvalidationEnable
= true;
3350 pc
.ConstantCacheInvalidationEnable
= true;
3351 pc
.StateCacheInvalidationEnable
= true;
3352 pc
.InstructionCacheInvalidateEnable
= true;
3353 pc
.PostSyncOperation
= NoWrite
;
3356 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPELINE_SELECT
), ps
) {
3360 ps
.PipelineSelection
= pipeline
;
3364 if (devinfo
->is_geminilake
) {
3367 * "This chicken bit works around a hardware issue with barrier logic
3368 * encountered when switching between GPGPU and 3D pipelines. To
3369 * workaround the issue, this mode bit should be set after a pipeline
3373 anv_pack_struct(&scec
, GENX(SLICE_COMMON_ECO_CHICKEN1
),
3375 pipeline
== GPGPU
? GLK_BARRIER_MODE_GPGPU
3376 : GLK_BARRIER_MODE_3D_HULL
,
3377 .GLKBarrierModeMask
= 1);
3378 emit_lri(&cmd_buffer
->batch
, GENX(SLICE_COMMON_ECO_CHICKEN1_num
), scec
);
3382 cmd_buffer
->state
.current_pipeline
= pipeline
;
3386 genX(flush_pipeline_select_3d
)(struct anv_cmd_buffer
*cmd_buffer
)
3388 genX(flush_pipeline_select
)(cmd_buffer
, _3D
);
3392 genX(flush_pipeline_select_gpgpu
)(struct anv_cmd_buffer
*cmd_buffer
)
3394 genX(flush_pipeline_select
)(cmd_buffer
, GPGPU
);
3398 genX(cmd_buffer_emit_gen7_depth_flush
)(struct anv_cmd_buffer
*cmd_buffer
)
3403 /* From the Haswell PRM, documentation for 3DSTATE_DEPTH_BUFFER:
3405 * "Restriction: Prior to changing Depth/Stencil Buffer state (i.e., any
3406 * combination of 3DSTATE_DEPTH_BUFFER, 3DSTATE_CLEAR_PARAMS,
3407 * 3DSTATE_STENCIL_BUFFER, 3DSTATE_HIER_DEPTH_BUFFER) SW must first
3408 * issue a pipelined depth stall (PIPE_CONTROL with Depth Stall bit
3409 * set), followed by a pipelined depth cache flush (PIPE_CONTROL with
3410 * Depth Flush Bit set, followed by another pipelined depth stall
3411 * (PIPE_CONTROL with Depth Stall Bit set), unless SW can otherwise
3412 * guarantee that the pipeline from WM onwards is already flushed (e.g.,
3413 * via a preceding MI_FLUSH)."
3415 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pipe
) {
3416 pipe
.DepthStallEnable
= true;
3418 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pipe
) {
3419 pipe
.DepthCacheFlushEnable
= true;
3421 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pipe
) {
3422 pipe
.DepthStallEnable
= true;
3427 cmd_buffer_emit_depth_stencil(struct anv_cmd_buffer
*cmd_buffer
)
3429 struct anv_device
*device
= cmd_buffer
->device
;
3430 const struct anv_image_view
*iview
=
3431 anv_cmd_buffer_get_depth_stencil_view(cmd_buffer
);
3432 const struct anv_image
*image
= iview
? iview
->image
: NULL
;
3434 /* FIXME: Width and Height are wrong */
3436 genX(cmd_buffer_emit_gen7_depth_flush
)(cmd_buffer
);
3438 uint32_t *dw
= anv_batch_emit_dwords(&cmd_buffer
->batch
,
3439 device
->isl_dev
.ds
.size
/ 4);
3443 struct isl_depth_stencil_hiz_emit_info info
= { };
3446 info
.view
= &iview
->planes
[0].isl
;
3448 if (image
&& (image
->aspects
& VK_IMAGE_ASPECT_DEPTH_BIT
)) {
3449 uint32_t depth_plane
=
3450 anv_image_aspect_to_plane(image
->aspects
, VK_IMAGE_ASPECT_DEPTH_BIT
);
3451 const struct anv_surface
*surface
= &image
->planes
[depth_plane
].surface
;
3453 info
.depth_surf
= &surface
->isl
;
3455 info
.depth_address
=
3456 anv_batch_emit_reloc(&cmd_buffer
->batch
,
3457 dw
+ device
->isl_dev
.ds
.depth_offset
/ 4,
3458 image
->planes
[depth_plane
].address
.bo
,
3459 image
->planes
[depth_plane
].address
.offset
+
3462 anv_mocs_for_bo(device
, image
->planes
[depth_plane
].address
.bo
);
3465 cmd_buffer
->state
.subpass
->depth_stencil_attachment
->attachment
;
3466 info
.hiz_usage
= cmd_buffer
->state
.attachments
[ds
].aux_usage
;
3467 if (info
.hiz_usage
== ISL_AUX_USAGE_HIZ
) {
3468 info
.hiz_surf
= &image
->planes
[depth_plane
].aux_surface
.isl
;
3471 anv_batch_emit_reloc(&cmd_buffer
->batch
,
3472 dw
+ device
->isl_dev
.ds
.hiz_offset
/ 4,
3473 image
->planes
[depth_plane
].address
.bo
,
3474 image
->planes
[depth_plane
].address
.offset
+
3475 image
->planes
[depth_plane
].aux_surface
.offset
);
3477 info
.depth_clear_value
= ANV_HZ_FC_VAL
;
3481 if (image
&& (image
->aspects
& VK_IMAGE_ASPECT_STENCIL_BIT
)) {
3482 uint32_t stencil_plane
=
3483 anv_image_aspect_to_plane(image
->aspects
, VK_IMAGE_ASPECT_STENCIL_BIT
);
3484 const struct anv_surface
*surface
= &image
->planes
[stencil_plane
].surface
;
3486 info
.stencil_surf
= &surface
->isl
;
3488 info
.stencil_address
=
3489 anv_batch_emit_reloc(&cmd_buffer
->batch
,
3490 dw
+ device
->isl_dev
.ds
.stencil_offset
/ 4,
3491 image
->planes
[stencil_plane
].address
.bo
,
3492 image
->planes
[stencil_plane
].address
.offset
+
3495 anv_mocs_for_bo(device
, image
->planes
[stencil_plane
].address
.bo
);
3498 isl_emit_depth_stencil_hiz_s(&device
->isl_dev
, dw
, &info
);
3500 cmd_buffer
->state
.hiz_enabled
= info
.hiz_usage
== ISL_AUX_USAGE_HIZ
;
3504 * This ANDs the view mask of the current subpass with the pending clear
3505 * views in the attachment to get the mask of views active in the subpass
3506 * that still need to be cleared.
3508 static inline uint32_t
3509 get_multiview_subpass_clear_mask(const struct anv_cmd_state
*cmd_state
,
3510 const struct anv_attachment_state
*att_state
)
3512 return cmd_state
->subpass
->view_mask
& att_state
->pending_clear_views
;
3516 do_first_layer_clear(const struct anv_cmd_state
*cmd_state
,
3517 const struct anv_attachment_state
*att_state
)
3519 if (!cmd_state
->subpass
->view_mask
)
3522 uint32_t pending_clear_mask
=
3523 get_multiview_subpass_clear_mask(cmd_state
, att_state
);
3525 return pending_clear_mask
& 1;
3529 current_subpass_is_last_for_attachment(const struct anv_cmd_state
*cmd_state
,
3532 const uint32_t last_subpass_idx
=
3533 cmd_state
->pass
->attachments
[att_idx
].last_subpass_idx
;
3534 const struct anv_subpass
*last_subpass
=
3535 &cmd_state
->pass
->subpasses
[last_subpass_idx
];
3536 return last_subpass
== cmd_state
->subpass
;
3540 cmd_buffer_begin_subpass(struct anv_cmd_buffer
*cmd_buffer
,
3541 uint32_t subpass_id
)
3543 struct anv_cmd_state
*cmd_state
= &cmd_buffer
->state
;
3544 struct anv_subpass
*subpass
= &cmd_state
->pass
->subpasses
[subpass_id
];
3545 cmd_state
->subpass
= subpass
;
3547 cmd_buffer
->state
.gfx
.dirty
|= ANV_CMD_DIRTY_RENDER_TARGETS
;
3549 /* Our implementation of VK_KHR_multiview uses instancing to draw the
3550 * different views. If the client asks for instancing, we need to use the
3551 * Instance Data Step Rate to ensure that we repeat the client's
3552 * per-instance data once for each view. Since this bit is in
3553 * VERTEX_BUFFER_STATE on gen7, we need to dirty vertex buffers at the top
3557 cmd_buffer
->state
.gfx
.vb_dirty
|= ~0;
3559 /* It is possible to start a render pass with an old pipeline. Because the
3560 * render pass and subpass index are both baked into the pipeline, this is
3561 * highly unlikely. In order to do so, it requires that you have a render
3562 * pass with a single subpass and that you use that render pass twice
3563 * back-to-back and use the same pipeline at the start of the second render
3564 * pass as at the end of the first. In order to avoid unpredictable issues
3565 * with this edge case, we just dirty the pipeline at the start of every
3568 cmd_buffer
->state
.gfx
.dirty
|= ANV_CMD_DIRTY_PIPELINE
;
3570 /* Accumulate any subpass flushes that need to happen before the subpass */
3571 cmd_buffer
->state
.pending_pipe_bits
|=
3572 cmd_buffer
->state
.pass
->subpass_flushes
[subpass_id
];
3574 VkRect2D render_area
= cmd_buffer
->state
.render_area
;
3575 struct anv_framebuffer
*fb
= cmd_buffer
->state
.framebuffer
;
3577 bool is_multiview
= subpass
->view_mask
!= 0;
3579 for (uint32_t i
= 0; i
< subpass
->attachment_count
; ++i
) {
3580 const uint32_t a
= subpass
->attachments
[i
].attachment
;
3581 if (a
== VK_ATTACHMENT_UNUSED
)
3584 assert(a
< cmd_state
->pass
->attachment_count
);
3585 struct anv_attachment_state
*att_state
= &cmd_state
->attachments
[a
];
3587 struct anv_image_view
*iview
= fb
->attachments
[a
];
3588 const struct anv_image
*image
= iview
->image
;
3590 /* A resolve is necessary before use as an input attachment if the clear
3591 * color or auxiliary buffer usage isn't supported by the sampler.
3593 const bool input_needs_resolve
=
3594 (att_state
->fast_clear
&& !att_state
->clear_color_is_zero_one
) ||
3595 att_state
->input_aux_usage
!= att_state
->aux_usage
;
3597 VkImageLayout target_layout
;
3598 if (iview
->aspect_mask
& VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV
&&
3599 !input_needs_resolve
) {
3600 /* Layout transitions before the final only help to enable sampling
3601 * as an input attachment. If the input attachment supports sampling
3602 * using the auxiliary surface, we can skip such transitions by
3603 * making the target layout one that is CCS-aware.
3605 target_layout
= VK_IMAGE_LAYOUT_COLOR_ATTACHMENT_OPTIMAL
;
3607 target_layout
= subpass
->attachments
[i
].layout
;
3610 if (image
->aspects
& VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV
) {
3611 assert(image
->aspects
== VK_IMAGE_ASPECT_COLOR_BIT
);
3613 uint32_t base_layer
, layer_count
;
3614 if (image
->type
== VK_IMAGE_TYPE_3D
) {
3616 layer_count
= anv_minify(iview
->image
->extent
.depth
,
3617 iview
->planes
[0].isl
.base_level
);
3619 base_layer
= iview
->planes
[0].isl
.base_array_layer
;
3620 layer_count
= fb
->layers
;
3623 transition_color_buffer(cmd_buffer
, image
, VK_IMAGE_ASPECT_COLOR_BIT
,
3624 iview
->planes
[0].isl
.base_level
, 1,
3625 base_layer
, layer_count
,
3626 att_state
->current_layout
, target_layout
);
3627 } else if (image
->aspects
& VK_IMAGE_ASPECT_DEPTH_BIT
) {
3628 transition_depth_buffer(cmd_buffer
, image
,
3629 att_state
->current_layout
, target_layout
);
3630 att_state
->aux_usage
=
3631 anv_layout_to_aux_usage(&cmd_buffer
->device
->info
, image
,
3632 VK_IMAGE_ASPECT_DEPTH_BIT
, target_layout
);
3634 att_state
->current_layout
= target_layout
;
3636 if (att_state
->pending_clear_aspects
& VK_IMAGE_ASPECT_COLOR_BIT
) {
3637 assert(att_state
->pending_clear_aspects
== VK_IMAGE_ASPECT_COLOR_BIT
);
3639 /* Multi-planar images are not supported as attachments */
3640 assert(image
->aspects
== VK_IMAGE_ASPECT_COLOR_BIT
);
3641 assert(image
->n_planes
== 1);
3643 uint32_t base_clear_layer
= iview
->planes
[0].isl
.base_array_layer
;
3644 uint32_t clear_layer_count
= fb
->layers
;
3646 if (att_state
->fast_clear
&&
3647 do_first_layer_clear(cmd_state
, att_state
)) {
3648 /* We only support fast-clears on the first layer */
3649 assert(iview
->planes
[0].isl
.base_level
== 0);
3650 assert(iview
->planes
[0].isl
.base_array_layer
== 0);
3652 union isl_color_value clear_color
= {};
3653 anv_clear_color_from_att_state(&clear_color
, att_state
, iview
);
3654 if (iview
->image
->samples
== 1) {
3655 anv_image_ccs_op(cmd_buffer
, image
, VK_IMAGE_ASPECT_COLOR_BIT
,
3656 0, 0, 1, ISL_AUX_OP_FAST_CLEAR
,
3660 anv_image_mcs_op(cmd_buffer
, image
, VK_IMAGE_ASPECT_COLOR_BIT
,
3661 0, 1, ISL_AUX_OP_FAST_CLEAR
,
3666 clear_layer_count
--;
3668 att_state
->pending_clear_views
&= ~1;
3670 if (att_state
->clear_color_is_zero
) {
3671 /* This image has the auxiliary buffer enabled. We can mark the
3672 * subresource as not needing a resolve because the clear color
3673 * will match what's in every RENDER_SURFACE_STATE object when
3674 * it's being used for sampling.
3676 set_image_fast_clear_state(cmd_buffer
, iview
->image
,
3677 VK_IMAGE_ASPECT_COLOR_BIT
,
3678 ANV_FAST_CLEAR_DEFAULT_VALUE
);
3680 set_image_fast_clear_state(cmd_buffer
, iview
->image
,
3681 VK_IMAGE_ASPECT_COLOR_BIT
,
3682 ANV_FAST_CLEAR_ANY
);
3686 /* From the VkFramebufferCreateInfo spec:
3688 * "If the render pass uses multiview, then layers must be one and each
3689 * attachment requires a number of layers that is greater than the
3690 * maximum bit index set in the view mask in the subpasses in which it
3693 * So if multiview is active we ignore the number of layers in the
3694 * framebuffer and instead we honor the view mask from the subpass.
3697 assert(image
->n_planes
== 1);
3698 uint32_t pending_clear_mask
=
3699 get_multiview_subpass_clear_mask(cmd_state
, att_state
);
3702 for_each_bit(layer_idx
, pending_clear_mask
) {
3704 iview
->planes
[0].isl
.base_array_layer
+ layer_idx
;
3706 anv_image_clear_color(cmd_buffer
, image
,
3707 VK_IMAGE_ASPECT_COLOR_BIT
,
3708 att_state
->aux_usage
,
3709 iview
->planes
[0].isl
.format
,
3710 iview
->planes
[0].isl
.swizzle
,
3711 iview
->planes
[0].isl
.base_level
,
3714 vk_to_isl_color(att_state
->clear_value
.color
));
3717 att_state
->pending_clear_views
&= ~pending_clear_mask
;
3718 } else if (clear_layer_count
> 0) {
3719 assert(image
->n_planes
== 1);
3720 anv_image_clear_color(cmd_buffer
, image
, VK_IMAGE_ASPECT_COLOR_BIT
,
3721 att_state
->aux_usage
,
3722 iview
->planes
[0].isl
.format
,
3723 iview
->planes
[0].isl
.swizzle
,
3724 iview
->planes
[0].isl
.base_level
,
3725 base_clear_layer
, clear_layer_count
,
3727 vk_to_isl_color(att_state
->clear_value
.color
));
3729 } else if (att_state
->pending_clear_aspects
& (VK_IMAGE_ASPECT_DEPTH_BIT
|
3730 VK_IMAGE_ASPECT_STENCIL_BIT
)) {
3731 if (att_state
->fast_clear
&& !is_multiview
) {
3732 /* We currently only support HiZ for single-layer images */
3733 if (att_state
->pending_clear_aspects
& VK_IMAGE_ASPECT_DEPTH_BIT
) {
3734 assert(iview
->image
->planes
[0].aux_usage
== ISL_AUX_USAGE_HIZ
);
3735 assert(iview
->planes
[0].isl
.base_level
== 0);
3736 assert(iview
->planes
[0].isl
.base_array_layer
== 0);
3737 assert(fb
->layers
== 1);
3740 anv_image_hiz_clear(cmd_buffer
, image
,
3741 att_state
->pending_clear_aspects
,
3742 iview
->planes
[0].isl
.base_level
,
3743 iview
->planes
[0].isl
.base_array_layer
,
3744 fb
->layers
, render_area
,
3745 att_state
->clear_value
.depthStencil
.stencil
);
3746 } else if (is_multiview
) {
3747 uint32_t pending_clear_mask
=
3748 get_multiview_subpass_clear_mask(cmd_state
, att_state
);
3751 for_each_bit(layer_idx
, pending_clear_mask
) {
3753 iview
->planes
[0].isl
.base_array_layer
+ layer_idx
;
3755 anv_image_clear_depth_stencil(cmd_buffer
, image
,
3756 att_state
->pending_clear_aspects
,
3757 att_state
->aux_usage
,
3758 iview
->planes
[0].isl
.base_level
,
3761 att_state
->clear_value
.depthStencil
.depth
,
3762 att_state
->clear_value
.depthStencil
.stencil
);
3765 att_state
->pending_clear_views
&= ~pending_clear_mask
;
3767 anv_image_clear_depth_stencil(cmd_buffer
, image
,
3768 att_state
->pending_clear_aspects
,
3769 att_state
->aux_usage
,
3770 iview
->planes
[0].isl
.base_level
,
3771 iview
->planes
[0].isl
.base_array_layer
,
3772 fb
->layers
, render_area
,
3773 att_state
->clear_value
.depthStencil
.depth
,
3774 att_state
->clear_value
.depthStencil
.stencil
);
3777 assert(att_state
->pending_clear_aspects
== 0);
3781 (att_state
->pending_load_aspects
& VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV
) &&
3782 image
->planes
[0].aux_surface
.isl
.size_B
> 0 &&
3783 iview
->planes
[0].isl
.base_level
== 0 &&
3784 iview
->planes
[0].isl
.base_array_layer
== 0) {
3785 if (att_state
->aux_usage
!= ISL_AUX_USAGE_NONE
) {
3786 genX(copy_fast_clear_dwords
)(cmd_buffer
, att_state
->color
.state
,
3787 image
, VK_IMAGE_ASPECT_COLOR_BIT
,
3788 false /* copy to ss */);
3791 if (need_input_attachment_state(&cmd_state
->pass
->attachments
[a
]) &&
3792 att_state
->input_aux_usage
!= ISL_AUX_USAGE_NONE
) {
3793 genX(copy_fast_clear_dwords
)(cmd_buffer
, att_state
->input
.state
,
3794 image
, VK_IMAGE_ASPECT_COLOR_BIT
,
3795 false /* copy to ss */);
3799 if (subpass
->attachments
[i
].usage
==
3800 VK_IMAGE_USAGE_COLOR_ATTACHMENT_BIT
) {
3801 /* We assume that if we're starting a subpass, we're going to do some
3802 * rendering so we may end up with compressed data.
3804 genX(cmd_buffer_mark_image_written
)(cmd_buffer
, iview
->image
,
3805 VK_IMAGE_ASPECT_COLOR_BIT
,
3806 att_state
->aux_usage
,
3807 iview
->planes
[0].isl
.base_level
,
3808 iview
->planes
[0].isl
.base_array_layer
,
3810 } else if (subpass
->attachments
[i
].usage
==
3811 VK_IMAGE_USAGE_DEPTH_STENCIL_ATTACHMENT_BIT
) {
3812 /* We may be writing depth or stencil so we need to mark the surface.
3813 * Unfortunately, there's no way to know at this point whether the
3814 * depth or stencil tests used will actually write to the surface.
3816 * Even though stencil may be plane 1, it always shares a base_level
3819 const struct isl_view
*ds_view
= &iview
->planes
[0].isl
;
3820 if (iview
->aspect_mask
& VK_IMAGE_ASPECT_DEPTH_BIT
) {
3821 genX(cmd_buffer_mark_image_written
)(cmd_buffer
, image
,
3822 VK_IMAGE_ASPECT_DEPTH_BIT
,
3823 att_state
->aux_usage
,
3824 ds_view
->base_level
,
3825 ds_view
->base_array_layer
,
3828 if (iview
->aspect_mask
& VK_IMAGE_ASPECT_STENCIL_BIT
) {
3829 /* Even though stencil may be plane 1, it always shares a
3830 * base_level with depth.
3832 genX(cmd_buffer_mark_image_written
)(cmd_buffer
, image
,
3833 VK_IMAGE_ASPECT_STENCIL_BIT
,
3835 ds_view
->base_level
,
3836 ds_view
->base_array_layer
,
3841 /* If multiview is enabled, then we are only done clearing when we no
3842 * longer have pending layers to clear, or when we have processed the
3843 * last subpass that uses this attachment.
3845 if (!is_multiview
||
3846 att_state
->pending_clear_views
== 0 ||
3847 current_subpass_is_last_for_attachment(cmd_state
, a
)) {
3848 att_state
->pending_clear_aspects
= 0;
3851 att_state
->pending_load_aspects
= 0;
3854 cmd_buffer_emit_depth_stencil(cmd_buffer
);
3858 cmd_buffer_end_subpass(struct anv_cmd_buffer
*cmd_buffer
)
3860 struct anv_cmd_state
*cmd_state
= &cmd_buffer
->state
;
3861 struct anv_subpass
*subpass
= cmd_state
->subpass
;
3862 uint32_t subpass_id
= anv_get_subpass_id(&cmd_buffer
->state
);
3864 anv_cmd_buffer_resolve_subpass(cmd_buffer
);
3866 struct anv_framebuffer
*fb
= cmd_buffer
->state
.framebuffer
;
3867 for (uint32_t i
= 0; i
< subpass
->attachment_count
; ++i
) {
3868 const uint32_t a
= subpass
->attachments
[i
].attachment
;
3869 if (a
== VK_ATTACHMENT_UNUSED
)
3872 if (cmd_state
->pass
->attachments
[a
].last_subpass_idx
!= subpass_id
)
3875 assert(a
< cmd_state
->pass
->attachment_count
);
3876 struct anv_attachment_state
*att_state
= &cmd_state
->attachments
[a
];
3877 struct anv_image_view
*iview
= fb
->attachments
[a
];
3878 const struct anv_image
*image
= iview
->image
;
3880 /* Transition the image into the final layout for this render pass */
3881 VkImageLayout target_layout
=
3882 cmd_state
->pass
->attachments
[a
].final_layout
;
3884 if (image
->aspects
& VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV
) {
3885 assert(image
->aspects
== VK_IMAGE_ASPECT_COLOR_BIT
);
3887 uint32_t base_layer
, layer_count
;
3888 if (image
->type
== VK_IMAGE_TYPE_3D
) {
3890 layer_count
= anv_minify(iview
->image
->extent
.depth
,
3891 iview
->planes
[0].isl
.base_level
);
3893 base_layer
= iview
->planes
[0].isl
.base_array_layer
;
3894 layer_count
= fb
->layers
;
3897 transition_color_buffer(cmd_buffer
, image
, VK_IMAGE_ASPECT_COLOR_BIT
,
3898 iview
->planes
[0].isl
.base_level
, 1,
3899 base_layer
, layer_count
,
3900 att_state
->current_layout
, target_layout
);
3901 } else if (image
->aspects
& VK_IMAGE_ASPECT_DEPTH_BIT
) {
3902 transition_depth_buffer(cmd_buffer
, image
,
3903 att_state
->current_layout
, target_layout
);
3907 /* Accumulate any subpass flushes that need to happen after the subpass.
3908 * Yes, they do get accumulated twice in the NextSubpass case but since
3909 * genX_CmdNextSubpass just calls end/begin back-to-back, we just end up
3910 * ORing the bits in twice so it's harmless.
3912 cmd_buffer
->state
.pending_pipe_bits
|=
3913 cmd_buffer
->state
.pass
->subpass_flushes
[subpass_id
+ 1];
3916 void genX(CmdBeginRenderPass
)(
3917 VkCommandBuffer commandBuffer
,
3918 const VkRenderPassBeginInfo
* pRenderPassBegin
,
3919 VkSubpassContents contents
)
3921 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
3922 ANV_FROM_HANDLE(anv_render_pass
, pass
, pRenderPassBegin
->renderPass
);
3923 ANV_FROM_HANDLE(anv_framebuffer
, framebuffer
, pRenderPassBegin
->framebuffer
);
3925 cmd_buffer
->state
.framebuffer
= framebuffer
;
3926 cmd_buffer
->state
.pass
= pass
;
3927 cmd_buffer
->state
.render_area
= pRenderPassBegin
->renderArea
;
3929 genX(cmd_buffer_setup_attachments
)(cmd_buffer
, pass
, pRenderPassBegin
);
3931 /* If we failed to setup the attachments we should not try to go further */
3932 if (result
!= VK_SUCCESS
) {
3933 assert(anv_batch_has_error(&cmd_buffer
->batch
));
3937 genX(flush_pipeline_select_3d
)(cmd_buffer
);
3939 cmd_buffer_begin_subpass(cmd_buffer
, 0);
3942 void genX(CmdBeginRenderPass2KHR
)(
3943 VkCommandBuffer commandBuffer
,
3944 const VkRenderPassBeginInfo
* pRenderPassBeginInfo
,
3945 const VkSubpassBeginInfoKHR
* pSubpassBeginInfo
)
3947 genX(CmdBeginRenderPass
)(commandBuffer
, pRenderPassBeginInfo
,
3948 pSubpassBeginInfo
->contents
);
3951 void genX(CmdNextSubpass
)(
3952 VkCommandBuffer commandBuffer
,
3953 VkSubpassContents contents
)
3955 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
3957 if (anv_batch_has_error(&cmd_buffer
->batch
))
3960 assert(cmd_buffer
->level
== VK_COMMAND_BUFFER_LEVEL_PRIMARY
);
3962 uint32_t prev_subpass
= anv_get_subpass_id(&cmd_buffer
->state
);
3963 cmd_buffer_end_subpass(cmd_buffer
);
3964 cmd_buffer_begin_subpass(cmd_buffer
, prev_subpass
+ 1);
3967 void genX(CmdNextSubpass2KHR
)(
3968 VkCommandBuffer commandBuffer
,
3969 const VkSubpassBeginInfoKHR
* pSubpassBeginInfo
,
3970 const VkSubpassEndInfoKHR
* pSubpassEndInfo
)
3972 genX(CmdNextSubpass
)(commandBuffer
, pSubpassBeginInfo
->contents
);
3975 void genX(CmdEndRenderPass
)(
3976 VkCommandBuffer commandBuffer
)
3978 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
3980 if (anv_batch_has_error(&cmd_buffer
->batch
))
3983 cmd_buffer_end_subpass(cmd_buffer
);
3985 cmd_buffer
->state
.hiz_enabled
= false;
3988 anv_dump_add_framebuffer(cmd_buffer
, cmd_buffer
->state
.framebuffer
);
3991 /* Remove references to render pass specific state. This enables us to
3992 * detect whether or not we're in a renderpass.
3994 cmd_buffer
->state
.framebuffer
= NULL
;
3995 cmd_buffer
->state
.pass
= NULL
;
3996 cmd_buffer
->state
.subpass
= NULL
;
3999 void genX(CmdEndRenderPass2KHR
)(
4000 VkCommandBuffer commandBuffer
,
4001 const VkSubpassEndInfoKHR
* pSubpassEndInfo
)
4003 genX(CmdEndRenderPass
)(commandBuffer
);