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anv: Only enable EWA LOD algorithm when doing anisotropic filtering.
[mesa.git] / src / intel / vulkan / genX_state.c
1 /*
2 * Copyright © 2015 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 */
23
24 #include <assert.h>
25 #include <stdbool.h>
26 #include <string.h>
27 #include <unistd.h>
28 #include <fcntl.h>
29
30 #include "anv_private.h"
31
32 #include "common/gen_sample_positions.h"
33 #include "genxml/gen_macros.h"
34 #include "genxml/genX_pack.h"
35
36 #include "vk_util.h"
37
38 #if GEN_GEN == 10
39 /**
40 * From Gen10 Workarounds page in h/w specs:
41 * WaSampleOffsetIZ:
42 * "Prior to the 3DSTATE_SAMPLE_PATTERN driver must ensure there are no
43 * markers in the pipeline by programming a PIPE_CONTROL with stall."
44 */
45 static void
46 gen10_emit_wa_cs_stall_flush(struct anv_batch *batch)
47 {
48
49 anv_batch_emit(batch, GENX(PIPE_CONTROL), pc) {
50 pc.CommandStreamerStallEnable = true;
51 pc.StallAtPixelScoreboard = true;
52 }
53 }
54
55 /**
56 * From Gen10 Workarounds page in h/w specs:
57 * WaSampleOffsetIZ:_cs_stall_flush
58 * "When 3DSTATE_SAMPLE_PATTERN is programmed, driver must then issue an
59 * MI_LOAD_REGISTER_IMM command to an offset between 0x7000 and 0x7FFF(SVL)
60 * after the command to ensure the state has been delivered prior to any
61 * command causing a marker in the pipeline."
62 */
63 static void
64 gen10_emit_wa_lri_to_cache_mode_zero(struct anv_batch *batch)
65 {
66 /* Before changing the value of CACHE_MODE_0 register, GFX pipeline must
67 * be idle; i.e., full flush is required.
68 */
69 anv_batch_emit(batch, GENX(PIPE_CONTROL), pc) {
70 pc.DepthCacheFlushEnable = true;
71 pc.DCFlushEnable = true;
72 pc.RenderTargetCacheFlushEnable = true;
73 pc.InstructionCacheInvalidateEnable = true;
74 pc.StateCacheInvalidationEnable = true;
75 pc.TextureCacheInvalidationEnable = true;
76 pc.VFCacheInvalidationEnable = true;
77 pc.ConstantCacheInvalidationEnable =true;
78 }
79
80 /* Write to CACHE_MODE_0 (0x7000) */
81 uint32_t cache_mode_0 = 0;
82 anv_pack_struct(&cache_mode_0, GENX(CACHE_MODE_0));
83
84 anv_batch_emit(batch, GENX(MI_LOAD_REGISTER_IMM), lri) {
85 lri.RegisterOffset = GENX(CACHE_MODE_0_num);
86 lri.DataDWord = cache_mode_0;
87 }
88 }
89 #endif
90
91 static void
92 genX(emit_slice_hashing_state)(struct anv_device *device,
93 struct anv_batch *batch)
94 {
95 device->slice_hash = (struct anv_state) { 0 };
96
97 #if GEN_GEN == 11
98 const unsigned *ppipe_subslices = device->info.ppipe_subslices;
99 int subslices_delta = ppipe_subslices[0] - ppipe_subslices[1];
100 if (subslices_delta == 0)
101 return;
102
103 unsigned size = GENX(SLICE_HASH_TABLE_length) * 4;
104 device->slice_hash =
105 anv_state_pool_alloc(&device->dynamic_state_pool, size, 64);
106
107 struct GENX(SLICE_HASH_TABLE) table0 = {
108 .Entry = {
109 { 1, 1, 0, 1, 1, 0, 1, 1, 0, 1, 1, 0, 1, 1, 0, 1 },
110 { 1, 0, 1, 1, 0, 1, 1, 0, 1, 1, 0, 1, 1, 0, 1, 1 },
111 { 0, 1, 1, 0, 1, 1, 0, 1, 1, 0, 1, 1, 0, 1, 1, 0 },
112 { 1, 1, 0, 1, 1, 0, 1, 1, 0, 1, 1, 0, 1, 1, 0, 1 },
113 { 1, 0, 1, 1, 0, 1, 1, 0, 1, 1, 0, 1, 1, 0, 1, 1 },
114 { 0, 1, 1, 0, 1, 1, 0, 1, 1, 0, 1, 1, 0, 1, 1, 0 },
115 { 1, 1, 0, 1, 1, 0, 1, 1, 0, 1, 1, 0, 1, 1, 0, 1 },
116 { 1, 0, 1, 1, 0, 1, 1, 0, 1, 1, 0, 1, 1, 0, 1, 1 },
117 { 0, 1, 1, 0, 1, 1, 0, 1, 1, 0, 1, 1, 0, 1, 1, 0 },
118 { 1, 1, 0, 1, 1, 0, 1, 1, 0, 1, 1, 0, 1, 1, 0, 1 },
119 { 1, 0, 1, 1, 0, 1, 1, 0, 1, 1, 0, 1, 1, 0, 1, 1 },
120 { 0, 1, 1, 0, 1, 1, 0, 1, 1, 0, 1, 1, 0, 1, 1, 0 },
121 { 1, 1, 0, 1, 1, 0, 1, 1, 0, 1, 1, 0, 1, 1, 0, 1 },
122 { 1, 0, 1, 1, 0, 1, 1, 0, 1, 1, 0, 1, 1, 0, 1, 1 },
123 { 0, 1, 1, 0, 1, 1, 0, 1, 1, 0, 1, 1, 0, 1, 1, 0 },
124 { 1, 1, 0, 1, 1, 0, 1, 1, 0, 1, 1, 0, 1, 1, 0, 1 }
125 }
126 };
127
128 struct GENX(SLICE_HASH_TABLE) table1 = {
129 .Entry = {
130 { 0, 0, 1, 0, 0, 1, 0, 0, 1, 0, 0, 1, 0, 0, 1, 0 },
131 { 0, 1, 0, 0, 1, 0, 0, 1, 0, 0, 1, 0, 0, 1, 0, 0 },
132 { 1, 0, 0, 1, 0, 0, 1, 0, 0, 1, 0, 0, 1, 0, 0, 1 },
133 { 0, 0, 1, 0, 0, 1, 0, 0, 1, 0, 0, 1, 0, 0, 1, 0 },
134 { 0, 1, 0, 0, 1, 0, 0, 1, 0, 0, 1, 0, 0, 1, 0, 0 },
135 { 1, 0, 0, 1, 0, 0, 1, 0, 0, 1, 0, 0, 1, 0, 0, 1 },
136 { 0, 0, 1, 0, 0, 1, 0, 0, 1, 0, 0, 1, 0, 0, 1, 0 },
137 { 0, 1, 0, 0, 1, 0, 0, 1, 0, 0, 1, 0, 0, 1, 0, 0 },
138 { 1, 0, 0, 1, 0, 0, 1, 0, 0, 1, 0, 0, 1, 0, 0, 1 },
139 { 0, 0, 1, 0, 0, 1, 0, 0, 1, 0, 0, 1, 0, 0, 1, 0 },
140 { 0, 1, 0, 0, 1, 0, 0, 1, 0, 0, 1, 0, 0, 1, 0, 0 },
141 { 1, 0, 0, 1, 0, 0, 1, 0, 0, 1, 0, 0, 1, 0, 0, 1 },
142 { 0, 0, 1, 0, 0, 1, 0, 0, 1, 0, 0, 1, 0, 0, 1, 0 },
143 { 0, 1, 0, 0, 1, 0, 0, 1, 0, 0, 1, 0, 0, 1, 0, 0 },
144 { 1, 0, 0, 1, 0, 0, 1, 0, 0, 1, 0, 0, 1, 0, 0, 1 },
145 { 0, 0, 1, 0, 0, 1, 0, 0, 1, 0, 0, 1, 0, 0, 1, 0 }
146 }
147 };
148
149 const struct GENX(SLICE_HASH_TABLE) *table =
150 subslices_delta < 0 ? &table0 : &table1;
151 GENX(SLICE_HASH_TABLE_pack)(NULL, device->slice_hash.map, table);
152
153 anv_batch_emit(batch, GENX(3DSTATE_SLICE_TABLE_STATE_POINTERS), ptr) {
154 ptr.SliceHashStatePointerValid = true;
155 ptr.SliceHashTableStatePointer = device->slice_hash.offset;
156 }
157
158 anv_batch_emit(batch, GENX(3DSTATE_3D_MODE), mode) {
159 mode.SliceHashingTableEnable = true;
160 }
161 #endif
162 }
163
164 VkResult
165 genX(init_device_state)(struct anv_device *device)
166 {
167 struct anv_batch batch;
168
169 uint32_t cmds[64];
170 batch.start = batch.next = cmds;
171 batch.end = (void *) cmds + sizeof(cmds);
172
173 anv_batch_emit(&batch, GENX(PIPELINE_SELECT), ps) {
174 #if GEN_GEN >= 9
175 ps.MaskBits = 3;
176 #endif
177 ps.PipelineSelection = _3D;
178 }
179
180 #if GEN_GEN == 9
181 uint32_t cache_mode_1;
182 anv_pack_struct(&cache_mode_1, GENX(CACHE_MODE_1),
183 .FloatBlendOptimizationEnable = true,
184 .FloatBlendOptimizationEnableMask = true,
185 .PartialResolveDisableInVC = true,
186 .PartialResolveDisableInVCMask = true);
187
188 anv_batch_emit(&batch, GENX(MI_LOAD_REGISTER_IMM), lri) {
189 lri.RegisterOffset = GENX(CACHE_MODE_1_num);
190 lri.DataDWord = cache_mode_1;
191 }
192 #endif
193
194 anv_batch_emit(&batch, GENX(3DSTATE_AA_LINE_PARAMETERS), aa);
195
196 anv_batch_emit(&batch, GENX(3DSTATE_DRAWING_RECTANGLE), rect) {
197 rect.ClippedDrawingRectangleYMin = 0;
198 rect.ClippedDrawingRectangleXMin = 0;
199 rect.ClippedDrawingRectangleYMax = UINT16_MAX;
200 rect.ClippedDrawingRectangleXMax = UINT16_MAX;
201 rect.DrawingRectangleOriginY = 0;
202 rect.DrawingRectangleOriginX = 0;
203 }
204
205 #if GEN_GEN >= 8
206 anv_batch_emit(&batch, GENX(3DSTATE_WM_CHROMAKEY), ck);
207
208 #if GEN_GEN == 10
209 gen10_emit_wa_cs_stall_flush(&batch);
210 #endif
211
212 /* See the Vulkan 1.0 spec Table 24.1 "Standard sample locations" and
213 * VkPhysicalDeviceFeatures::standardSampleLocations.
214 */
215 anv_batch_emit(&batch, GENX(3DSTATE_SAMPLE_PATTERN), sp) {
216 GEN_SAMPLE_POS_1X(sp._1xSample);
217 GEN_SAMPLE_POS_2X(sp._2xSample);
218 GEN_SAMPLE_POS_4X(sp._4xSample);
219 GEN_SAMPLE_POS_8X(sp._8xSample);
220 #if GEN_GEN >= 9
221 GEN_SAMPLE_POS_16X(sp._16xSample);
222 #endif
223 }
224
225 /* The BDW+ docs describe how to use the 3DSTATE_WM_HZ_OP instruction in the
226 * section titled, "Optimized Depth Buffer Clear and/or Stencil Buffer
227 * Clear." It mentions that the packet overrides GPU state for the clear
228 * operation and needs to be reset to 0s to clear the overrides. Depending
229 * on the kernel, we may not get a context with the state for this packet
230 * zeroed. Do it ourselves just in case. We've observed this to prevent a
231 * number of GPU hangs on ICL.
232 */
233 anv_batch_emit(&batch, GENX(3DSTATE_WM_HZ_OP), hzp);
234 #endif
235
236 #if GEN_GEN == 10
237 gen10_emit_wa_lri_to_cache_mode_zero(&batch);
238 #endif
239
240 #if GEN_GEN == 11
241 /* The default behavior of bit 5 "Headerless Message for Pre-emptable
242 * Contexts" in SAMPLER MODE register is set to 0, which means
243 * headerless sampler messages are not allowed for pre-emptable
244 * contexts. Set the bit 5 to 1 to allow them.
245 */
246 uint32_t sampler_mode;
247 anv_pack_struct(&sampler_mode, GENX(SAMPLER_MODE),
248 .HeaderlessMessageforPreemptableContexts = true,
249 .HeaderlessMessageforPreemptableContextsMask = true);
250
251 anv_batch_emit(&batch, GENX(MI_LOAD_REGISTER_IMM), lri) {
252 lri.RegisterOffset = GENX(SAMPLER_MODE_num);
253 lri.DataDWord = sampler_mode;
254 }
255
256 /* Bit 1 "Enabled Texel Offset Precision Fix" must be set in
257 * HALF_SLICE_CHICKEN7 register.
258 */
259 uint32_t half_slice_chicken7;
260 anv_pack_struct(&half_slice_chicken7, GENX(HALF_SLICE_CHICKEN7),
261 .EnabledTexelOffsetPrecisionFix = true,
262 .EnabledTexelOffsetPrecisionFixMask = true);
263
264 anv_batch_emit(&batch, GENX(MI_LOAD_REGISTER_IMM), lri) {
265 lri.RegisterOffset = GENX(HALF_SLICE_CHICKEN7_num);
266 lri.DataDWord = half_slice_chicken7;
267 }
268
269 uint32_t tccntlreg;
270 anv_pack_struct(&tccntlreg, GENX(TCCNTLREG),
271 .L3DataPartialWriteMergingEnable = true,
272 .ColorZPartialWriteMergingEnable = true,
273 .URBPartialWriteMergingEnable = true,
274 .TCDisable = true);
275
276 anv_batch_emit(&batch, GENX(MI_LOAD_REGISTER_IMM), lri) {
277 lri.RegisterOffset = GENX(TCCNTLREG_num);
278 lri.DataDWord = tccntlreg;
279 }
280
281 #endif
282 genX(emit_slice_hashing_state)(device, &batch);
283
284 #if GEN_GEN >= 11
285 /* hardware specification recommends disabling repacking for
286 * the compatibility with decompression mechanism in display controller.
287 */
288 if (device->info.disable_ccs_repack) {
289 uint32_t cache_mode_0;
290 anv_pack_struct(&cache_mode_0,
291 GENX(CACHE_MODE_0),
292 .DisableRepackingforCompression = true,
293 .DisableRepackingforCompressionMask = true);
294
295 anv_batch_emit(&batch, GENX(MI_LOAD_REGISTER_IMM), lri) {
296 lri.RegisterOffset = GENX(CACHE_MODE_0_num);
297 lri.DataDWord = cache_mode_0;
298 }
299 }
300 #endif
301
302 /* Set the "CONSTANT_BUFFER Address Offset Disable" bit, so
303 * 3DSTATE_CONSTANT_XS buffer 0 is an absolute address.
304 *
305 * This is only safe on kernels with context isolation support.
306 */
307 if (GEN_GEN >= 8 &&
308 device->instance->physicalDevice.has_context_isolation) {
309 UNUSED uint32_t tmp_reg;
310 #if GEN_GEN >= 9
311 anv_pack_struct(&tmp_reg, GENX(CS_DEBUG_MODE2),
312 .CONSTANT_BUFFERAddressOffsetDisable = true,
313 .CONSTANT_BUFFERAddressOffsetDisableMask = true);
314 anv_batch_emit(&batch, GENX(MI_LOAD_REGISTER_IMM), lri) {
315 lri.RegisterOffset = GENX(CS_DEBUG_MODE2_num);
316 lri.DataDWord = tmp_reg;
317 }
318 #elif GEN_GEN == 8
319 anv_pack_struct(&tmp_reg, GENX(INSTPM),
320 .CONSTANT_BUFFERAddressOffsetDisable = true,
321 .CONSTANT_BUFFERAddressOffsetDisableMask = true);
322 anv_batch_emit(&batch, GENX(MI_LOAD_REGISTER_IMM), lri) {
323 lri.RegisterOffset = GENX(INSTPM_num);
324 lri.DataDWord = tmp_reg;
325 }
326 #endif
327 }
328
329 anv_batch_emit(&batch, GENX(MI_BATCH_BUFFER_END), bbe);
330
331 assert(batch.next <= batch.end);
332
333 return anv_queue_submit_simple_batch(&device->queue, &batch);
334 }
335
336 static uint32_t
337 vk_to_gen_tex_filter(VkFilter filter, bool anisotropyEnable)
338 {
339 switch (filter) {
340 default:
341 assert(!"Invalid filter");
342 case VK_FILTER_NEAREST:
343 return anisotropyEnable ? MAPFILTER_ANISOTROPIC : MAPFILTER_NEAREST;
344 case VK_FILTER_LINEAR:
345 return anisotropyEnable ? MAPFILTER_ANISOTROPIC : MAPFILTER_LINEAR;
346 }
347 }
348
349 static uint32_t
350 vk_to_gen_max_anisotropy(float ratio)
351 {
352 return (anv_clamp_f(ratio, 2, 16) - 2) / 2;
353 }
354
355 static const uint32_t vk_to_gen_mipmap_mode[] = {
356 [VK_SAMPLER_MIPMAP_MODE_NEAREST] = MIPFILTER_NEAREST,
357 [VK_SAMPLER_MIPMAP_MODE_LINEAR] = MIPFILTER_LINEAR
358 };
359
360 static const uint32_t vk_to_gen_tex_address[] = {
361 [VK_SAMPLER_ADDRESS_MODE_REPEAT] = TCM_WRAP,
362 [VK_SAMPLER_ADDRESS_MODE_MIRRORED_REPEAT] = TCM_MIRROR,
363 [VK_SAMPLER_ADDRESS_MODE_CLAMP_TO_EDGE] = TCM_CLAMP,
364 [VK_SAMPLER_ADDRESS_MODE_MIRROR_CLAMP_TO_EDGE] = TCM_MIRROR_ONCE,
365 [VK_SAMPLER_ADDRESS_MODE_CLAMP_TO_BORDER] = TCM_CLAMP_BORDER,
366 };
367
368 /* Vulkan specifies the result of shadow comparisons as:
369 * 1 if ref <op> texel,
370 * 0 otherwise.
371 *
372 * The hardware does:
373 * 0 if texel <op> ref,
374 * 1 otherwise.
375 *
376 * So, these look a bit strange because there's both a negation
377 * and swapping of the arguments involved.
378 */
379 static const uint32_t vk_to_gen_shadow_compare_op[] = {
380 [VK_COMPARE_OP_NEVER] = PREFILTEROPALWAYS,
381 [VK_COMPARE_OP_LESS] = PREFILTEROPLEQUAL,
382 [VK_COMPARE_OP_EQUAL] = PREFILTEROPNOTEQUAL,
383 [VK_COMPARE_OP_LESS_OR_EQUAL] = PREFILTEROPLESS,
384 [VK_COMPARE_OP_GREATER] = PREFILTEROPGEQUAL,
385 [VK_COMPARE_OP_NOT_EQUAL] = PREFILTEROPEQUAL,
386 [VK_COMPARE_OP_GREATER_OR_EQUAL] = PREFILTEROPGREATER,
387 [VK_COMPARE_OP_ALWAYS] = PREFILTEROPNEVER,
388 };
389
390 #if GEN_GEN >= 9
391 static const uint32_t vk_to_gen_sampler_reduction_mode[] = {
392 [VK_SAMPLER_REDUCTION_MODE_WEIGHTED_AVERAGE_EXT] = STD_FILTER,
393 [VK_SAMPLER_REDUCTION_MODE_MIN_EXT] = MINIMUM,
394 [VK_SAMPLER_REDUCTION_MODE_MAX_EXT] = MAXIMUM,
395 };
396 #endif
397
398 VkResult genX(CreateSampler)(
399 VkDevice _device,
400 const VkSamplerCreateInfo* pCreateInfo,
401 const VkAllocationCallbacks* pAllocator,
402 VkSampler* pSampler)
403 {
404 ANV_FROM_HANDLE(anv_device, device, _device);
405 const struct anv_physical_device *pdevice =
406 &device->instance->physicalDevice;
407 struct anv_sampler *sampler;
408
409 assert(pCreateInfo->sType == VK_STRUCTURE_TYPE_SAMPLER_CREATE_INFO);
410
411 sampler = vk_zalloc2(&device->alloc, pAllocator, sizeof(*sampler), 8,
412 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
413 if (!sampler)
414 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
415
416 sampler->n_planes = 1;
417
418 uint32_t border_color_stride = GEN_IS_HASWELL ? 512 : 64;
419 uint32_t border_color_offset = device->border_colors.offset +
420 pCreateInfo->borderColor *
421 border_color_stride;
422
423 #if GEN_GEN >= 9
424 unsigned sampler_reduction_mode = STD_FILTER;
425 bool enable_sampler_reduction = false;
426 #endif
427
428 vk_foreach_struct(ext, pCreateInfo->pNext) {
429 switch (ext->sType) {
430 case VK_STRUCTURE_TYPE_SAMPLER_YCBCR_CONVERSION_INFO: {
431 VkSamplerYcbcrConversionInfo *pSamplerConversion =
432 (VkSamplerYcbcrConversionInfo *) ext;
433 ANV_FROM_HANDLE(anv_ycbcr_conversion, conversion,
434 pSamplerConversion->conversion);
435
436 /* Ignore conversion for non-YUV formats. This fulfills a requirement
437 * for clients that want to utilize same code path for images with
438 * external formats (VK_FORMAT_UNDEFINED) and "regular" RGBA images
439 * where format is known.
440 */
441 if (conversion == NULL || !conversion->format->can_ycbcr)
442 break;
443
444 sampler->n_planes = conversion->format->n_planes;
445 sampler->conversion = conversion;
446 break;
447 }
448 #if GEN_GEN >= 9
449 case VK_STRUCTURE_TYPE_SAMPLER_REDUCTION_MODE_CREATE_INFO_EXT: {
450 VkSamplerReductionModeCreateInfoEXT *sampler_reduction =
451 (VkSamplerReductionModeCreateInfoEXT *) ext;
452 sampler_reduction_mode =
453 vk_to_gen_sampler_reduction_mode[sampler_reduction->reductionMode];
454 enable_sampler_reduction = true;
455 break;
456 }
457 #endif
458 default:
459 anv_debug_ignored_stype(ext->sType);
460 break;
461 }
462 }
463
464 if (pdevice->has_bindless_samplers) {
465 /* If we have bindless, allocate enough samplers. We allocate 32 bytes
466 * for each sampler instead of 16 bytes because we want all bindless
467 * samplers to be 32-byte aligned so we don't have to use indirect
468 * sampler messages on them.
469 */
470 sampler->bindless_state =
471 anv_state_pool_alloc(&device->dynamic_state_pool,
472 sampler->n_planes * 32, 32);
473 }
474
475 for (unsigned p = 0; p < sampler->n_planes; p++) {
476 const bool plane_has_chroma =
477 sampler->conversion && sampler->conversion->format->planes[p].has_chroma;
478 const VkFilter min_filter =
479 plane_has_chroma ? sampler->conversion->chroma_filter : pCreateInfo->minFilter;
480 const VkFilter mag_filter =
481 plane_has_chroma ? sampler->conversion->chroma_filter : pCreateInfo->magFilter;
482 const bool enable_min_filter_addr_rounding = min_filter != VK_FILTER_NEAREST;
483 const bool enable_mag_filter_addr_rounding = mag_filter != VK_FILTER_NEAREST;
484 /* From Broadwell PRM, SAMPLER_STATE:
485 * "Mip Mode Filter must be set to MIPFILTER_NONE for Planar YUV surfaces."
486 */
487 const uint32_t mip_filter_mode =
488 (sampler->conversion &&
489 isl_format_is_yuv(sampler->conversion->format->planes[0].isl_format)) ?
490 MIPFILTER_NONE : vk_to_gen_mipmap_mode[pCreateInfo->mipmapMode];
491
492 struct GENX(SAMPLER_STATE) sampler_state = {
493 .SamplerDisable = false,
494 .TextureBorderColorMode = DX10OGL,
495
496 #if GEN_GEN >= 8
497 .LODPreClampMode = CLAMP_MODE_OGL,
498 #else
499 .LODPreClampEnable = CLAMP_ENABLE_OGL,
500 #endif
501
502 #if GEN_GEN == 8
503 .BaseMipLevel = 0.0,
504 #endif
505 .MipModeFilter = mip_filter_mode,
506 .MagModeFilter = vk_to_gen_tex_filter(mag_filter, pCreateInfo->anisotropyEnable),
507 .MinModeFilter = vk_to_gen_tex_filter(min_filter, pCreateInfo->anisotropyEnable),
508 .TextureLODBias = anv_clamp_f(pCreateInfo->mipLodBias, -16, 15.996),
509 .AnisotropicAlgorithm =
510 pCreateInfo->anisotropyEnable ? EWAApproximation : LEGACY,
511 .MinLOD = anv_clamp_f(pCreateInfo->minLod, 0, 14),
512 .MaxLOD = anv_clamp_f(pCreateInfo->maxLod, 0, 14),
513 .ChromaKeyEnable = 0,
514 .ChromaKeyIndex = 0,
515 .ChromaKeyMode = 0,
516 .ShadowFunction = vk_to_gen_shadow_compare_op[pCreateInfo->compareOp],
517 .CubeSurfaceControlMode = OVERRIDE,
518
519 .BorderColorPointer = border_color_offset,
520
521 #if GEN_GEN >= 8
522 .LODClampMagnificationMode = MIPNONE,
523 #endif
524
525 .MaximumAnisotropy = vk_to_gen_max_anisotropy(pCreateInfo->maxAnisotropy),
526 .RAddressMinFilterRoundingEnable = enable_min_filter_addr_rounding,
527 .RAddressMagFilterRoundingEnable = enable_mag_filter_addr_rounding,
528 .VAddressMinFilterRoundingEnable = enable_min_filter_addr_rounding,
529 .VAddressMagFilterRoundingEnable = enable_mag_filter_addr_rounding,
530 .UAddressMinFilterRoundingEnable = enable_min_filter_addr_rounding,
531 .UAddressMagFilterRoundingEnable = enable_mag_filter_addr_rounding,
532 .TrilinearFilterQuality = 0,
533 .NonnormalizedCoordinateEnable = pCreateInfo->unnormalizedCoordinates,
534 .TCXAddressControlMode = vk_to_gen_tex_address[pCreateInfo->addressModeU],
535 .TCYAddressControlMode = vk_to_gen_tex_address[pCreateInfo->addressModeV],
536 .TCZAddressControlMode = vk_to_gen_tex_address[pCreateInfo->addressModeW],
537
538 #if GEN_GEN >= 9
539 .ReductionType = sampler_reduction_mode,
540 .ReductionTypeEnable = enable_sampler_reduction,
541 #endif
542 };
543
544 GENX(SAMPLER_STATE_pack)(NULL, sampler->state[p], &sampler_state);
545
546 if (sampler->bindless_state.map) {
547 memcpy(sampler->bindless_state.map + p * 32,
548 sampler->state[p], GENX(SAMPLER_STATE_length) * 4);
549 }
550 }
551
552 *pSampler = anv_sampler_to_handle(sampler);
553
554 return VK_SUCCESS;
555 }