src/intel/vulkan/genX_state.c

   1 /*
   2  * Copyright © 2015 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  */
  23
  24 #include <assert.h>
  25 #include <stdbool.h>
  26 #include <string.h>
  27 #include <unistd.h>
  28 #include <fcntl.h>
  29
  30 #include "anv_private.h"
  31
  32 #include "common/gen_sample_positions.h"
  33 #include "genxml/gen_macros.h"
  34 #include "genxml/genX_pack.h"
  35
  36 #include "vk_util.h"
  37
  38 #if GEN_GEN == 10
  39 /**
  40  * From Gen10 Workarounds page in h/w specs:
  41  * WaSampleOffsetIZ:
  42  *    "Prior to the 3DSTATE_SAMPLE_PATTERN driver must ensure there are no
  43  *     markers in the pipeline by programming a PIPE_CONTROL with stall."
  44  */
  45 static void
  46 gen10_emit_wa_cs_stall_flush(struct anv_batch *batch)
  47 {
  48
  49    anv_batch_emit(batch, GENX(PIPE_CONTROL), pc) {
  50       pc.CommandStreamerStallEnable = true;
  51       pc.StallAtPixelScoreboard = true;
  52    }
  53 }
  54
  55 /**
  56  * From Gen10 Workarounds page in h/w specs:
  57  * WaSampleOffsetIZ:_cs_stall_flush
  58  *    "When 3DSTATE_SAMPLE_PATTERN is programmed, driver must then issue an
  59  *     MI_LOAD_REGISTER_IMM command to an offset between 0x7000 and 0x7FFF(SVL)
  60  *     after the command to ensure the state has been delivered prior to any
  61  *     command causing a marker in the pipeline."
  62  */
  63 static void
  64 gen10_emit_wa_lri_to_cache_mode_zero(struct anv_batch *batch)
  65 {
  66    /* Before changing the value of CACHE_MODE_0 register, GFX pipeline must
  67     * be idle; i.e., full flush is required.
  68     */
  69    anv_batch_emit(batch, GENX(PIPE_CONTROL), pc) {
  70       pc.DepthCacheFlushEnable = true;
  71       pc.DCFlushEnable = true;
  72       pc.RenderTargetCacheFlushEnable = true;
  73       pc.InstructionCacheInvalidateEnable = true;
  74       pc.StateCacheInvalidationEnable = true;
  75       pc.TextureCacheInvalidationEnable = true;
  76       pc.VFCacheInvalidationEnable = true;
  77       pc.ConstantCacheInvalidationEnable =true;
  78    }
  79
  80    /* Write to CACHE_MODE_0 (0x7000) */
  81    uint32_t cache_mode_0 = 0;
  82    anv_pack_struct(&cache_mode_0, GENX(CACHE_MODE_0));
  83
  84    anv_batch_emit(batch, GENX(MI_LOAD_REGISTER_IMM), lri) {
  85       lri.RegisterOffset = GENX(CACHE_MODE_0_num);
  86       lri.DataDWord      = cache_mode_0;
  87    }
  88 }
  89 #endif
  90
  91 VkResult
  92 genX(init_device_state)(struct anv_device *device)
  93 {
  94    GENX(MEMORY_OBJECT_CONTROL_STATE_pack)(NULL, &device->default_mocs,
  95                                           &GENX(MOCS));
  96
  97    struct anv_batch batch;
  98
  99    uint32_t cmds[64];
 100    batch.start = batch.next = cmds;
 101    batch.end = (void *) cmds + sizeof(cmds);
 102
 103    anv_batch_emit(&batch, GENX(PIPELINE_SELECT), ps) {
 104 #if GEN_GEN >= 9
 105       ps.MaskBits = 3;
 106 #endif
 107       ps.PipelineSelection = _3D;
 108    }
 109
 110 #if GEN_GEN == 9
 111    uint32_t cache_mode_1;
 112    anv_pack_struct(&cache_mode_1, GENX(CACHE_MODE_1),
 113                    .FloatBlendOptimizationEnable = true,
 114                    .FloatBlendOptimizationEnableMask = true,
 115                    .PartialResolveDisableInVC = true,
 116                    .PartialResolveDisableInVCMask = true);
 117
 118    anv_batch_emit(&batch, GENX(MI_LOAD_REGISTER_IMM), lri) {
 119       lri.RegisterOffset = GENX(CACHE_MODE_1_num);
 120       lri.DataDWord      = cache_mode_1;
 121    }
 122 #endif
 123
 124    anv_batch_emit(&batch, GENX(3DSTATE_AA_LINE_PARAMETERS), aa);
 125
 126    anv_batch_emit(&batch, GENX(3DSTATE_DRAWING_RECTANGLE), rect) {
 127       rect.ClippedDrawingRectangleYMin = 0;
 128       rect.ClippedDrawingRectangleXMin = 0;
 129       rect.ClippedDrawingRectangleYMax = UINT16_MAX;
 130       rect.ClippedDrawingRectangleXMax = UINT16_MAX;
 131       rect.DrawingRectangleOriginY = 0;
 132       rect.DrawingRectangleOriginX = 0;
 133    }
 134
 135 #if GEN_GEN >= 8
 136    anv_batch_emit(&batch, GENX(3DSTATE_WM_CHROMAKEY), ck);
 137
 138 #if GEN_GEN == 10
 139    gen10_emit_wa_cs_stall_flush(&batch);
 140 #endif
 141
 142    /* See the Vulkan 1.0 spec Table 24.1 "Standard sample locations" and
 143     * VkPhysicalDeviceFeatures::standardSampleLocations.
 144     */
 145    anv_batch_emit(&batch, GENX(3DSTATE_SAMPLE_PATTERN), sp) {
 146       GEN_SAMPLE_POS_1X(sp._1xSample);
 147       GEN_SAMPLE_POS_2X(sp._2xSample);
 148       GEN_SAMPLE_POS_4X(sp._4xSample);
 149       GEN_SAMPLE_POS_8X(sp._8xSample);
 150 #if GEN_GEN >= 9
 151       GEN_SAMPLE_POS_16X(sp._16xSample);
 152 #endif
 153    }
 154 #endif
 155
 156 #if GEN_GEN == 10
 157    gen10_emit_wa_lri_to_cache_mode_zero(&batch);
 158 #endif
 159
 160 #if GEN_GEN == 11
 161    /* The default behavior of bit 5 "Headerless Message for Pre-emptable
 162     * Contexts" in SAMPLER MODE register is set to 0, which means
 163     * headerless sampler messages are not allowed for pre-emptable
 164     * contexts. Set the bit 5 to 1 to allow them.
 165     */
 166    uint32_t sampler_mode;
 167    anv_pack_struct(&sampler_mode, GENX(SAMPLER_MODE),
 168                    .HeaderlessMessageforPreemptableContexts = true,
 169                    .HeaderlessMessageforPreemptableContextsMask = true);
 170
 171     anv_batch_emit(&batch, GENX(MI_LOAD_REGISTER_IMM), lri) {
 172       lri.RegisterOffset = GENX(SAMPLER_MODE_num);
 173       lri.DataDWord      = sampler_mode;
 174    }
 175 #endif
 176
 177    /* Set the "CONSTANT_BUFFER Address Offset Disable" bit, so
 178     * 3DSTATE_CONSTANT_XS buffer 0 is an absolute address.
 179     *
 180     * This is only safe on kernels with context isolation support.
 181     */
 182    if (GEN_GEN >= 8 &&
 183        device->instance->physicalDevice.has_context_isolation) {
 184       UNUSED uint32_t tmp_reg;
 185 #if GEN_GEN >= 9
 186       anv_pack_struct(&tmp_reg, GENX(CS_DEBUG_MODE2),
 187                       .CONSTANT_BUFFERAddressOffsetDisable = true,
 188                       .CONSTANT_BUFFERAddressOffsetDisableMask = true);
 189       anv_batch_emit(&batch, GENX(MI_LOAD_REGISTER_IMM), lri) {
 190          lri.RegisterOffset = GENX(CS_DEBUG_MODE2_num);
 191          lri.DataDWord      = tmp_reg;
 192       }
 193 #elif GEN_GEN == 8
 194       anv_pack_struct(&tmp_reg, GENX(INSTPM),
 195                       .CONSTANT_BUFFERAddressOffsetDisable = true,
 196                       .CONSTANT_BUFFERAddressOffsetDisableMask = true);
 197       anv_batch_emit(&batch, GENX(MI_LOAD_REGISTER_IMM), lri) {
 198          lri.RegisterOffset = GENX(INSTPM_num);
 199          lri.DataDWord      = tmp_reg;
 200       }
 201 #endif
 202    }
 203
 204    anv_batch_emit(&batch, GENX(MI_BATCH_BUFFER_END), bbe);
 205
 206    assert(batch.next <= batch.end);
 207
 208    return anv_device_submit_simple_batch(device, &batch);
 209 }
 210
 211 static uint32_t
 212 vk_to_gen_tex_filter(VkFilter filter, bool anisotropyEnable)
 213 {
 214    switch (filter) {
 215    default:
 216       assert(!"Invalid filter");
 217    case VK_FILTER_NEAREST:
 218       return anisotropyEnable ? MAPFILTER_ANISOTROPIC : MAPFILTER_NEAREST;
 219    case VK_FILTER_LINEAR:
 220       return anisotropyEnable ? MAPFILTER_ANISOTROPIC : MAPFILTER_LINEAR;
 221    }
 222 }
 223
 224 static uint32_t
 225 vk_to_gen_max_anisotropy(float ratio)
 226 {
 227    return (anv_clamp_f(ratio, 2, 16) - 2) / 2;
 228 }
 229
 230 static const uint32_t vk_to_gen_mipmap_mode[] = {
 231    [VK_SAMPLER_MIPMAP_MODE_NEAREST]          = MIPFILTER_NEAREST,
 232    [VK_SAMPLER_MIPMAP_MODE_LINEAR]           = MIPFILTER_LINEAR
 233 };
 234
 235 static const uint32_t vk_to_gen_tex_address[] = {
 236    [VK_SAMPLER_ADDRESS_MODE_REPEAT]          = TCM_WRAP,
 237    [VK_SAMPLER_ADDRESS_MODE_MIRRORED_REPEAT] = TCM_MIRROR,
 238    [VK_SAMPLER_ADDRESS_MODE_CLAMP_TO_EDGE]   = TCM_CLAMP,
 239    [VK_SAMPLER_ADDRESS_MODE_MIRROR_CLAMP_TO_EDGE] = TCM_MIRROR_ONCE,
 240    [VK_SAMPLER_ADDRESS_MODE_CLAMP_TO_BORDER] = TCM_CLAMP_BORDER,
 241 };
 242
 243 /* Vulkan specifies the result of shadow comparisons as:
 244  *     1     if   ref <op> texel,
 245  *     0     otherwise.
 246  *
 247  * The hardware does:
 248  *     0     if texel <op> ref,
 249  *     1     otherwise.
 250  *
 251  * So, these look a bit strange because there's both a negation
 252  * and swapping of the arguments involved.
 253  */
 254 static const uint32_t vk_to_gen_shadow_compare_op[] = {
 255    [VK_COMPARE_OP_NEVER]                        = PREFILTEROPALWAYS,
 256    [VK_COMPARE_OP_LESS]                         = PREFILTEROPLEQUAL,
 257    [VK_COMPARE_OP_EQUAL]                        = PREFILTEROPNOTEQUAL,
 258    [VK_COMPARE_OP_LESS_OR_EQUAL]                = PREFILTEROPLESS,
 259    [VK_COMPARE_OP_GREATER]                      = PREFILTEROPGEQUAL,
 260    [VK_COMPARE_OP_NOT_EQUAL]                    = PREFILTEROPEQUAL,
 261    [VK_COMPARE_OP_GREATER_OR_EQUAL]             = PREFILTEROPGREATER,
 262    [VK_COMPARE_OP_ALWAYS]                       = PREFILTEROPNEVER,
 263 };
 264
 265 VkResult genX(CreateSampler)(
 266     VkDevice                                    _device,
 267     const VkSamplerCreateInfo*                  pCreateInfo,
 268     const VkAllocationCallbacks*                pAllocator,
 269     VkSampler*                                  pSampler)
 270 {
 271    ANV_FROM_HANDLE(anv_device, device, _device);
 272    struct anv_sampler *sampler;
 273
 274    assert(pCreateInfo->sType == VK_STRUCTURE_TYPE_SAMPLER_CREATE_INFO);
 275
 276    sampler = vk_zalloc2(&device->alloc, pAllocator, sizeof(*sampler), 8,
 277                         VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
 278    if (!sampler)
 279       return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
 280
 281    sampler->n_planes = 1;
 282
 283    uint32_t border_color_offset = device->border_colors.offset +
 284                                   pCreateInfo->borderColor * 64;
 285
 286    vk_foreach_struct(ext, pCreateInfo->pNext) {
 287       switch (ext->sType) {
 288       case VK_STRUCTURE_TYPE_SAMPLER_YCBCR_CONVERSION_INFO: {
 289          VkSamplerYcbcrConversionInfo *pSamplerConversion =
 290             (VkSamplerYcbcrConversionInfo *) ext;
 291          ANV_FROM_HANDLE(anv_ycbcr_conversion, conversion,
 292                          pSamplerConversion->conversion);
 293
 294          if (conversion == NULL)
 295             break;
 296
 297          sampler->n_planes = conversion->format->n_planes;
 298          sampler->conversion = conversion;
 299          break;
 300       }
 301       default:
 302          anv_debug_ignored_stype(ext->sType);
 303          break;
 304       }
 305    }
 306
 307    for (unsigned p = 0; p < sampler->n_planes; p++) {
 308       const bool plane_has_chroma =
 309          sampler->conversion && sampler->conversion->format->planes[p].has_chroma;
 310       const VkFilter min_filter =
 311          plane_has_chroma ? sampler->conversion->chroma_filter : pCreateInfo->minFilter;
 312       const VkFilter mag_filter =
 313          plane_has_chroma ? sampler->conversion->chroma_filter : pCreateInfo->magFilter;
 314       const bool enable_min_filter_addr_rounding = min_filter != VK_FILTER_NEAREST;
 315       const bool enable_mag_filter_addr_rounding = mag_filter != VK_FILTER_NEAREST;
 316       /* From Broadwell PRM, SAMPLER_STATE:
 317        *   "Mip Mode Filter must be set to MIPFILTER_NONE for Planar YUV surfaces."
 318        */
 319       const uint32_t mip_filter_mode =
 320          (sampler->conversion &&
 321           isl_format_is_yuv(sampler->conversion->format->planes[0].isl_format)) ?
 322          MIPFILTER_NONE : vk_to_gen_mipmap_mode[pCreateInfo->mipmapMode];
 323
 324       struct GENX(SAMPLER_STATE) sampler_state = {
 325          .SamplerDisable = false,
 326          .TextureBorderColorMode = DX10OGL,
 327
 328 #if GEN_GEN >= 8
 329          .LODPreClampMode = CLAMP_MODE_OGL,
 330 #else
 331          .LODPreClampEnable = CLAMP_ENABLE_OGL,
 332 #endif
 333
 334 #if GEN_GEN == 8
 335          .BaseMipLevel = 0.0,
 336 #endif
 337          .MipModeFilter = mip_filter_mode,
 338          .MagModeFilter = vk_to_gen_tex_filter(mag_filter, pCreateInfo->anisotropyEnable),
 339          .MinModeFilter = vk_to_gen_tex_filter(min_filter, pCreateInfo->anisotropyEnable),
 340          .TextureLODBias = anv_clamp_f(pCreateInfo->mipLodBias, -16, 15.996),
 341          .AnisotropicAlgorithm = EWAApproximation,
 342          .MinLOD = anv_clamp_f(pCreateInfo->minLod, 0, 14),
 343          .MaxLOD = anv_clamp_f(pCreateInfo->maxLod, 0, 14),
 344          .ChromaKeyEnable = 0,
 345          .ChromaKeyIndex = 0,
 346          .ChromaKeyMode = 0,
 347          .ShadowFunction = vk_to_gen_shadow_compare_op[pCreateInfo->compareOp],
 348          .CubeSurfaceControlMode = OVERRIDE,
 349
 350          .BorderColorPointer = border_color_offset,
 351
 352 #if GEN_GEN >= 8
 353          .LODClampMagnificationMode = MIPNONE,
 354 #endif
 355
 356          .MaximumAnisotropy = vk_to_gen_max_anisotropy(pCreateInfo->maxAnisotropy),
 357          .RAddressMinFilterRoundingEnable = enable_min_filter_addr_rounding,
 358          .RAddressMagFilterRoundingEnable = enable_mag_filter_addr_rounding,
 359          .VAddressMinFilterRoundingEnable = enable_min_filter_addr_rounding,
 360          .VAddressMagFilterRoundingEnable = enable_mag_filter_addr_rounding,
 361          .UAddressMinFilterRoundingEnable = enable_min_filter_addr_rounding,
 362          .UAddressMagFilterRoundingEnable = enable_mag_filter_addr_rounding,
 363          .TrilinearFilterQuality = 0,
 364          .NonnormalizedCoordinateEnable = pCreateInfo->unnormalizedCoordinates,
 365          .TCXAddressControlMode = vk_to_gen_tex_address[pCreateInfo->addressModeU],
 366          .TCYAddressControlMode = vk_to_gen_tex_address[pCreateInfo->addressModeV],
 367          .TCZAddressControlMode = vk_to_gen_tex_address[pCreateInfo->addressModeW],
 368       };
 369
 370       GENX(SAMPLER_STATE_pack)(NULL, sampler->state[p], &sampler_state);
 371    }
 372
 373    *pSampler = anv_sampler_to_handle(sampler);
 374
 375    return VK_SUCCESS;
 376 }