src/intel/vulkan/genX_state.c

   1 /*
   2  * Copyright © 2015 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  */
  23
  24 #include <assert.h>
  25 #include <stdbool.h>
  26 #include <string.h>
  27 #include <unistd.h>
  28 #include <fcntl.h>
  29
  30 #include "anv_private.h"
  31
  32 #include "common/gen_aux_map.h"
  33 #include "common/gen_sample_positions.h"
  34 #include "genxml/gen_macros.h"
  35 #include "genxml/genX_pack.h"
  36
  37 #include "vk_util.h"
  38
  39 static void
  40 genX(emit_slice_hashing_state)(struct anv_device *device,
  41                                struct anv_batch *batch)
  42 {
  43    device->slice_hash = (struct anv_state) { 0 };
  44
  45 #if GEN_GEN == 11
  46    const unsigned *ppipe_subslices = device->info.ppipe_subslices;
  47    int subslices_delta = ppipe_subslices[0] - ppipe_subslices[1];
  48    if (subslices_delta == 0)
  49       return;
  50
  51    unsigned size = GENX(SLICE_HASH_TABLE_length) * 4;
  52    device->slice_hash =
  53       anv_state_pool_alloc(&device->dynamic_state_pool, size, 64);
  54
  55    struct GENX(SLICE_HASH_TABLE) table0 = {
  56       .Entry = {
  57          { 1, 1, 0, 1, 1, 0, 1, 1, 0, 1, 1, 0, 1, 1, 0, 1 },
  58          { 1, 0, 1, 1, 0, 1, 1, 0, 1, 1, 0, 1, 1, 0, 1, 1 },
  59          { 0, 1, 1, 0, 1, 1, 0, 1, 1, 0, 1, 1, 0, 1, 1, 0 },
  60          { 1, 1, 0, 1, 1, 0, 1, 1, 0, 1, 1, 0, 1, 1, 0, 1 },
  61          { 1, 0, 1, 1, 0, 1, 1, 0, 1, 1, 0, 1, 1, 0, 1, 1 },
  62          { 0, 1, 1, 0, 1, 1, 0, 1, 1, 0, 1, 1, 0, 1, 1, 0 },
  63          { 1, 1, 0, 1, 1, 0, 1, 1, 0, 1, 1, 0, 1, 1, 0, 1 },
  64          { 1, 0, 1, 1, 0, 1, 1, 0, 1, 1, 0, 1, 1, 0, 1, 1 },
  65          { 0, 1, 1, 0, 1, 1, 0, 1, 1, 0, 1, 1, 0, 1, 1, 0 },
  66          { 1, 1, 0, 1, 1, 0, 1, 1, 0, 1, 1, 0, 1, 1, 0, 1 },
  67          { 1, 0, 1, 1, 0, 1, 1, 0, 1, 1, 0, 1, 1, 0, 1, 1 },
  68          { 0, 1, 1, 0, 1, 1, 0, 1, 1, 0, 1, 1, 0, 1, 1, 0 },
  69          { 1, 1, 0, 1, 1, 0, 1, 1, 0, 1, 1, 0, 1, 1, 0, 1 },
  70          { 1, 0, 1, 1, 0, 1, 1, 0, 1, 1, 0, 1, 1, 0, 1, 1 },
  71          { 0, 1, 1, 0, 1, 1, 0, 1, 1, 0, 1, 1, 0, 1, 1, 0 },
  72          { 1, 1, 0, 1, 1, 0, 1, 1, 0, 1, 1, 0, 1, 1, 0, 1 }
  73       }
  74    };
  75
  76    struct GENX(SLICE_HASH_TABLE) table1 = {
  77       .Entry = {
  78          { 0, 0, 1, 0, 0, 1, 0, 0, 1, 0, 0, 1, 0, 0, 1, 0 },
  79          { 0, 1, 0, 0, 1, 0, 0, 1, 0, 0, 1, 0, 0, 1, 0, 0 },
  80          { 1, 0, 0, 1, 0, 0, 1, 0, 0, 1, 0, 0, 1, 0, 0, 1 },
  81          { 0, 0, 1, 0, 0, 1, 0, 0, 1, 0, 0, 1, 0, 0, 1, 0 },
  82          { 0, 1, 0, 0, 1, 0, 0, 1, 0, 0, 1, 0, 0, 1, 0, 0 },
  83          { 1, 0, 0, 1, 0, 0, 1, 0, 0, 1, 0, 0, 1, 0, 0, 1 },
  84          { 0, 0, 1, 0, 0, 1, 0, 0, 1, 0, 0, 1, 0, 0, 1, 0 },
  85          { 0, 1, 0, 0, 1, 0, 0, 1, 0, 0, 1, 0, 0, 1, 0, 0 },
  86          { 1, 0, 0, 1, 0, 0, 1, 0, 0, 1, 0, 0, 1, 0, 0, 1 },
  87          { 0, 0, 1, 0, 0, 1, 0, 0, 1, 0, 0, 1, 0, 0, 1, 0 },
  88          { 0, 1, 0, 0, 1, 0, 0, 1, 0, 0, 1, 0, 0, 1, 0, 0 },
  89          { 1, 0, 0, 1, 0, 0, 1, 0, 0, 1, 0, 0, 1, 0, 0, 1 },
  90          { 0, 0, 1, 0, 0, 1, 0, 0, 1, 0, 0, 1, 0, 0, 1, 0 },
  91          { 0, 1, 0, 0, 1, 0, 0, 1, 0, 0, 1, 0, 0, 1, 0, 0 },
  92          { 1, 0, 0, 1, 0, 0, 1, 0, 0, 1, 0, 0, 1, 0, 0, 1 },
  93          { 0, 0, 1, 0, 0, 1, 0, 0, 1, 0, 0, 1, 0, 0, 1, 0 }
  94       }
  95    };
  96
  97    const struct GENX(SLICE_HASH_TABLE) *table =
  98       subslices_delta < 0 ? &table0 : &table1;
  99    GENX(SLICE_HASH_TABLE_pack)(NULL, device->slice_hash.map, table);
 100
 101    anv_batch_emit(batch, GENX(3DSTATE_SLICE_TABLE_STATE_POINTERS), ptr) {
 102       ptr.SliceHashStatePointerValid = true;
 103       ptr.SliceHashTableStatePointer = device->slice_hash.offset;
 104    }
 105
 106    anv_batch_emit(batch, GENX(3DSTATE_3D_MODE), mode) {
 107       mode.SliceHashingTableEnable = true;
 108    }
 109 #endif
 110 }
 111
 112 VkResult
 113 genX(init_device_state)(struct anv_device *device)
 114 {
 115    struct anv_batch batch;
 116
 117    uint32_t cmds[64];
 118    batch.start = batch.next = cmds;
 119    batch.end = (void *) cmds + sizeof(cmds);
 120
 121    anv_batch_emit(&batch, GENX(PIPELINE_SELECT), ps) {
 122 #if GEN_GEN >= 9
 123       ps.MaskBits = 3;
 124 #endif
 125       ps.PipelineSelection = _3D;
 126    }
 127
 128 #if GEN_GEN == 9
 129    uint32_t cache_mode_1;
 130    anv_pack_struct(&cache_mode_1, GENX(CACHE_MODE_1),
 131                    .FloatBlendOptimizationEnable = true,
 132                    .FloatBlendOptimizationEnableMask = true,
 133                    .PartialResolveDisableInVC = true,
 134                    .PartialResolveDisableInVCMask = true);
 135
 136    anv_batch_emit(&batch, GENX(MI_LOAD_REGISTER_IMM), lri) {
 137       lri.RegisterOffset = GENX(CACHE_MODE_1_num);
 138       lri.DataDWord      = cache_mode_1;
 139    }
 140 #endif
 141
 142    anv_batch_emit(&batch, GENX(3DSTATE_AA_LINE_PARAMETERS), aa);
 143
 144    anv_batch_emit(&batch, GENX(3DSTATE_DRAWING_RECTANGLE), rect) {
 145       rect.ClippedDrawingRectangleYMin = 0;
 146       rect.ClippedDrawingRectangleXMin = 0;
 147       rect.ClippedDrawingRectangleYMax = UINT16_MAX;
 148       rect.ClippedDrawingRectangleXMax = UINT16_MAX;
 149       rect.DrawingRectangleOriginY = 0;
 150       rect.DrawingRectangleOriginX = 0;
 151    }
 152
 153 #if GEN_GEN >= 8
 154    anv_batch_emit(&batch, GENX(3DSTATE_WM_CHROMAKEY), ck);
 155
 156    /* See the Vulkan 1.0 spec Table 24.1 "Standard sample locations" and
 157     * VkPhysicalDeviceFeatures::standardSampleLocations.
 158     */
 159    anv_batch_emit(&batch, GENX(3DSTATE_SAMPLE_PATTERN), sp) {
 160       GEN_SAMPLE_POS_1X(sp._1xSample);
 161       GEN_SAMPLE_POS_2X(sp._2xSample);
 162       GEN_SAMPLE_POS_4X(sp._4xSample);
 163       GEN_SAMPLE_POS_8X(sp._8xSample);
 164 #if GEN_GEN >= 9
 165       GEN_SAMPLE_POS_16X(sp._16xSample);
 166 #endif
 167    }
 168
 169    /* The BDW+ docs describe how to use the 3DSTATE_WM_HZ_OP instruction in the
 170     * section titled, "Optimized Depth Buffer Clear and/or Stencil Buffer
 171     * Clear." It mentions that the packet overrides GPU state for the clear
 172     * operation and needs to be reset to 0s to clear the overrides. Depending
 173     * on the kernel, we may not get a context with the state for this packet
 174     * zeroed. Do it ourselves just in case. We've observed this to prevent a
 175     * number of GPU hangs on ICL.
 176     */
 177    anv_batch_emit(&batch, GENX(3DSTATE_WM_HZ_OP), hzp);
 178 #endif
 179
 180 #if GEN_GEN == 11
 181    /* The default behavior of bit 5 "Headerless Message for Pre-emptable
 182     * Contexts" in SAMPLER MODE register is set to 0, which means
 183     * headerless sampler messages are not allowed for pre-emptable
 184     * contexts. Set the bit 5 to 1 to allow them.
 185     */
 186    uint32_t sampler_mode;
 187    anv_pack_struct(&sampler_mode, GENX(SAMPLER_MODE),
 188                    .HeaderlessMessageforPreemptableContexts = true,
 189                    .HeaderlessMessageforPreemptableContextsMask = true);
 190
 191     anv_batch_emit(&batch, GENX(MI_LOAD_REGISTER_IMM), lri) {
 192       lri.RegisterOffset = GENX(SAMPLER_MODE_num);
 193       lri.DataDWord      = sampler_mode;
 194    }
 195
 196    /* Bit 1 "Enabled Texel Offset Precision Fix" must be set in
 197     * HALF_SLICE_CHICKEN7 register.
 198     */
 199    uint32_t half_slice_chicken7;
 200    anv_pack_struct(&half_slice_chicken7, GENX(HALF_SLICE_CHICKEN7),
 201                    .EnabledTexelOffsetPrecisionFix = true,
 202                    .EnabledTexelOffsetPrecisionFixMask = true);
 203
 204     anv_batch_emit(&batch, GENX(MI_LOAD_REGISTER_IMM), lri) {
 205       lri.RegisterOffset = GENX(HALF_SLICE_CHICKEN7_num);
 206       lri.DataDWord      = half_slice_chicken7;
 207    }
 208
 209    uint32_t tccntlreg;
 210    anv_pack_struct(&tccntlreg, GENX(TCCNTLREG),
 211                    .L3DataPartialWriteMergingEnable = true,
 212                    .ColorZPartialWriteMergingEnable = true,
 213                    .URBPartialWriteMergingEnable = true,
 214                    .TCDisable = true);
 215
 216    anv_batch_emit(&batch, GENX(MI_LOAD_REGISTER_IMM), lri) {
 217       lri.RegisterOffset = GENX(TCCNTLREG_num);
 218       lri.DataDWord      = tccntlreg;
 219    }
 220
 221 #endif
 222    genX(emit_slice_hashing_state)(device, &batch);
 223
 224 #if GEN_GEN >= 11
 225    /* hardware specification recommends disabling repacking for
 226     * the compatibility with decompression mechanism in display controller.
 227     */
 228    if (device->info.disable_ccs_repack) {
 229       uint32_t cache_mode_0;
 230       anv_pack_struct(&cache_mode_0,
 231                       GENX(CACHE_MODE_0),
 232                       .DisableRepackingforCompression = true,
 233                       .DisableRepackingforCompressionMask = true);
 234
 235       anv_batch_emit(&batch, GENX(MI_LOAD_REGISTER_IMM), lri) {
 236          lri.RegisterOffset = GENX(CACHE_MODE_0_num);
 237          lri.DataDWord      = cache_mode_0;
 238       }
 239    }
 240
 241    /* an unknown issue is causing vs push constants to become
 242     * corrupted during object-level preemption. For now, restrict
 243     * to command buffer level preemption to avoid rendering
 244     * corruption.
 245     */
 246    uint32_t cs_chicken1;
 247    anv_pack_struct(&cs_chicken1,
 248                    GENX(CS_CHICKEN1),
 249                    .ReplayMode = MidcmdbufferPreemption,
 250                    .ReplayModeMask = true);
 251
 252    anv_batch_emit(&batch, GENX(MI_LOAD_REGISTER_IMM), lri) {
 253       lri.RegisterOffset = GENX(CS_CHICKEN1_num);
 254       lri.DataDWord      = cs_chicken1;
 255    }
 256 #endif
 257
 258 #if GEN_GEN == 12
 259    uint64_t aux_base_addr = gen_aux_map_get_base(device->aux_map_ctx);
 260    assert(aux_base_addr % (32 * 1024) == 0);
 261    anv_batch_emit(&batch, GENX(MI_LOAD_REGISTER_IMM), lri) {
 262       lri.RegisterOffset = GENX(GFX_AUX_TABLE_BASE_ADDR_num);
 263       lri.DataDWord = aux_base_addr & 0xffffffff;
 264    }
 265    anv_batch_emit(&batch, GENX(MI_LOAD_REGISTER_IMM), lri) {
 266       lri.RegisterOffset = GENX(GFX_AUX_TABLE_BASE_ADDR_num) + 4;
 267       lri.DataDWord = aux_base_addr >> 32;
 268    }
 269 #endif
 270
 271    /* Set the "CONSTANT_BUFFER Address Offset Disable" bit, so
 272     * 3DSTATE_CONSTANT_XS buffer 0 is an absolute address.
 273     *
 274     * This is only safe on kernels with context isolation support.
 275     */
 276    if (GEN_GEN >= 8 && device->physical->has_context_isolation) {
 277       UNUSED uint32_t tmp_reg;
 278 #if GEN_GEN >= 9
 279       anv_pack_struct(&tmp_reg, GENX(CS_DEBUG_MODE2),
 280                       .CONSTANT_BUFFERAddressOffsetDisable = true,
 281                       .CONSTANT_BUFFERAddressOffsetDisableMask = true);
 282       anv_batch_emit(&batch, GENX(MI_LOAD_REGISTER_IMM), lri) {
 283          lri.RegisterOffset = GENX(CS_DEBUG_MODE2_num);
 284          lri.DataDWord      = tmp_reg;
 285       }
 286 #elif GEN_GEN == 8
 287       anv_pack_struct(&tmp_reg, GENX(INSTPM),
 288                       .CONSTANT_BUFFERAddressOffsetDisable = true,
 289                       .CONSTANT_BUFFERAddressOffsetDisableMask = true);
 290       anv_batch_emit(&batch, GENX(MI_LOAD_REGISTER_IMM), lri) {
 291          lri.RegisterOffset = GENX(INSTPM_num);
 292          lri.DataDWord      = tmp_reg;
 293       }
 294 #endif
 295    }
 296
 297 #if GEN_GEN >= 12
 298    const struct gen_l3_config *cfg = gen_get_default_l3_config(&device->info);
 299    if (!cfg) {
 300       /* Platforms with no configs just setup full-way allocation. */
 301       uint32_t l3cr;
 302       anv_pack_struct(&l3cr, GENX(L3ALLOC),
 303                       .L3FullWayAllocationEnable = true);
 304       anv_batch_emit(&batch, GENX(MI_LOAD_REGISTER_IMM), lri) {
 305          lri.RegisterOffset = GENX(L3ALLOC_num);
 306          lri.DataDWord      = l3cr;
 307       }
 308    }
 309 #endif
 310
 311    anv_batch_emit(&batch, GENX(MI_BATCH_BUFFER_END), bbe);
 312
 313    assert(batch.next <= batch.end);
 314
 315    return anv_queue_submit_simple_batch(&device->queue, &batch);
 316 }
 317
 318 static uint32_t
 319 vk_to_gen_tex_filter(VkFilter filter, bool anisotropyEnable)
 320 {
 321    switch (filter) {
 322    default:
 323       assert(!"Invalid filter");
 324    case VK_FILTER_NEAREST:
 325       return anisotropyEnable ? MAPFILTER_ANISOTROPIC : MAPFILTER_NEAREST;
 326    case VK_FILTER_LINEAR:
 327       return anisotropyEnable ? MAPFILTER_ANISOTROPIC : MAPFILTER_LINEAR;
 328    }
 329 }
 330
 331 static uint32_t
 332 vk_to_gen_max_anisotropy(float ratio)
 333 {
 334    return (anv_clamp_f(ratio, 2, 16) - 2) / 2;
 335 }
 336
 337 static const uint32_t vk_to_gen_mipmap_mode[] = {
 338    [VK_SAMPLER_MIPMAP_MODE_NEAREST]          = MIPFILTER_NEAREST,
 339    [VK_SAMPLER_MIPMAP_MODE_LINEAR]           = MIPFILTER_LINEAR
 340 };
 341
 342 static const uint32_t vk_to_gen_tex_address[] = {
 343    [VK_SAMPLER_ADDRESS_MODE_REPEAT]          = TCM_WRAP,
 344    [VK_SAMPLER_ADDRESS_MODE_MIRRORED_REPEAT] = TCM_MIRROR,
 345    [VK_SAMPLER_ADDRESS_MODE_CLAMP_TO_EDGE]   = TCM_CLAMP,
 346    [VK_SAMPLER_ADDRESS_MODE_MIRROR_CLAMP_TO_EDGE] = TCM_MIRROR_ONCE,
 347    [VK_SAMPLER_ADDRESS_MODE_CLAMP_TO_BORDER] = TCM_CLAMP_BORDER,
 348 };
 349
 350 /* Vulkan specifies the result of shadow comparisons as:
 351  *     1     if   ref <op> texel,
 352  *     0     otherwise.
 353  *
 354  * The hardware does:
 355  *     0     if texel <op> ref,
 356  *     1     otherwise.
 357  *
 358  * So, these look a bit strange because there's both a negation
 359  * and swapping of the arguments involved.
 360  */
 361 static const uint32_t vk_to_gen_shadow_compare_op[] = {
 362    [VK_COMPARE_OP_NEVER]                        = PREFILTEROPALWAYS,
 363    [VK_COMPARE_OP_LESS]                         = PREFILTEROPLEQUAL,
 364    [VK_COMPARE_OP_EQUAL]                        = PREFILTEROPNOTEQUAL,
 365    [VK_COMPARE_OP_LESS_OR_EQUAL]                = PREFILTEROPLESS,
 366    [VK_COMPARE_OP_GREATER]                      = PREFILTEROPGEQUAL,
 367    [VK_COMPARE_OP_NOT_EQUAL]                    = PREFILTEROPEQUAL,
 368    [VK_COMPARE_OP_GREATER_OR_EQUAL]             = PREFILTEROPGREATER,
 369    [VK_COMPARE_OP_ALWAYS]                       = PREFILTEROPNEVER,
 370 };
 371
 372 #if GEN_GEN >= 9
 373 static const uint32_t vk_to_gen_sampler_reduction_mode[] = {
 374    [VK_SAMPLER_REDUCTION_MODE_WEIGHTED_AVERAGE_EXT] = STD_FILTER,
 375    [VK_SAMPLER_REDUCTION_MODE_MIN_EXT]              = MINIMUM,
 376    [VK_SAMPLER_REDUCTION_MODE_MAX_EXT]              = MAXIMUM,
 377 };
 378 #endif
 379
 380 VkResult genX(CreateSampler)(
 381     VkDevice                                    _device,
 382     const VkSamplerCreateInfo*                  pCreateInfo,
 383     const VkAllocationCallbacks*                pAllocator,
 384     VkSampler*                                  pSampler)
 385 {
 386    ANV_FROM_HANDLE(anv_device, device, _device);
 387    struct anv_sampler *sampler;
 388
 389    assert(pCreateInfo->sType == VK_STRUCTURE_TYPE_SAMPLER_CREATE_INFO);
 390
 391    sampler = vk_zalloc2(&device->vk.alloc, pAllocator, sizeof(*sampler), 8,
 392                         VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
 393    if (!sampler)
 394       return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
 395
 396    vk_object_base_init(&device->vk, &sampler->base, VK_OBJECT_TYPE_SAMPLER);
 397    sampler->n_planes = 1;
 398
 399    uint32_t border_color_stride = GEN_IS_HASWELL ? 512 : 64;
 400    uint32_t border_color_offset;
 401    ASSERTED bool has_custom_color = false;
 402    if (pCreateInfo->borderColor <= VK_BORDER_COLOR_INT_OPAQUE_WHITE) {
 403       border_color_offset = device->border_colors.offset +
 404                             pCreateInfo->borderColor *
 405                             border_color_stride;
 406    } else {
 407       assert(GEN_GEN >= 8);
 408       sampler->custom_border_color =
 409          anv_state_reserved_pool_alloc(&device->custom_border_colors);
 410       border_color_offset = sampler->custom_border_color.offset;
 411    }
 412
 413 #if GEN_GEN >= 9
 414    unsigned sampler_reduction_mode = STD_FILTER;
 415    bool enable_sampler_reduction = false;
 416 #endif
 417
 418    vk_foreach_struct(ext, pCreateInfo->pNext) {
 419       switch (ext->sType) {
 420       case VK_STRUCTURE_TYPE_SAMPLER_YCBCR_CONVERSION_INFO: {
 421          VkSamplerYcbcrConversionInfo *pSamplerConversion =
 422             (VkSamplerYcbcrConversionInfo *) ext;
 423          ANV_FROM_HANDLE(anv_ycbcr_conversion, conversion,
 424                          pSamplerConversion->conversion);
 425
 426          /* Ignore conversion for non-YUV formats. This fulfills a requirement
 427           * for clients that want to utilize same code path for images with
 428           * external formats (VK_FORMAT_UNDEFINED) and "regular" RGBA images
 429           * where format is known.
 430           */
 431          if (conversion == NULL || !conversion->format->can_ycbcr)
 432             break;
 433
 434          sampler->n_planes = conversion->format->n_planes;
 435          sampler->conversion = conversion;
 436          break;
 437       }
 438 #if GEN_GEN >= 9
 439       case VK_STRUCTURE_TYPE_SAMPLER_REDUCTION_MODE_CREATE_INFO: {
 440          VkSamplerReductionModeCreateInfo *sampler_reduction =
 441             (VkSamplerReductionModeCreateInfo *) ext;
 442          sampler_reduction_mode =
 443             vk_to_gen_sampler_reduction_mode[sampler_reduction->reductionMode];
 444          enable_sampler_reduction = true;
 445          break;
 446       }
 447 #endif
 448       case VK_STRUCTURE_TYPE_SAMPLER_CUSTOM_BORDER_COLOR_CREATE_INFO_EXT: {
 449          VkSamplerCustomBorderColorCreateInfoEXT *custom_border_color =
 450             (VkSamplerCustomBorderColorCreateInfoEXT *) ext;
 451          if (sampler->custom_border_color.map == NULL)
 452             break;
 453          struct gen8_border_color *cbc = sampler->custom_border_color.map;
 454          if (custom_border_color->format == VK_FORMAT_B4G4R4A4_UNORM_PACK16) {
 455             /* B4G4R4A4_UNORM_PACK16 is treated as R4G4B4A4_UNORM_PACK16 with
 456              * a swizzle, but this does not carry over to the sampler for
 457              * border colors, so we need to do the swizzle ourselves here.
 458              */
 459             cbc->uint32[0] = custom_border_color->customBorderColor.uint32[2];
 460             cbc->uint32[1] = custom_border_color->customBorderColor.uint32[1];
 461             cbc->uint32[2] = custom_border_color->customBorderColor.uint32[0];
 462             cbc->uint32[3] = custom_border_color->customBorderColor.uint32[3];
 463          } else {
 464             /* Both structs share the same layout, so just copy them over. */
 465             memcpy(cbc, &custom_border_color->customBorderColor,
 466                    sizeof(VkClearColorValue));
 467          }
 468          has_custom_color = true;
 469          break;
 470       }
 471       default:
 472          anv_debug_ignored_stype(ext->sType);
 473          break;
 474       }
 475    }
 476
 477    assert((sampler->custom_border_color.map == NULL) || has_custom_color);
 478
 479    if (device->physical->has_bindless_samplers) {
 480       /* If we have bindless, allocate enough samplers.  We allocate 32 bytes
 481        * for each sampler instead of 16 bytes because we want all bindless
 482        * samplers to be 32-byte aligned so we don't have to use indirect
 483        * sampler messages on them.
 484        */
 485       sampler->bindless_state =
 486          anv_state_pool_alloc(&device->dynamic_state_pool,
 487                               sampler->n_planes * 32, 32);
 488    }
 489
 490    for (unsigned p = 0; p < sampler->n_planes; p++) {
 491       const bool plane_has_chroma =
 492          sampler->conversion && sampler->conversion->format->planes[p].has_chroma;
 493       const VkFilter min_filter =
 494          plane_has_chroma ? sampler->conversion->chroma_filter : pCreateInfo->minFilter;
 495       const VkFilter mag_filter =
 496          plane_has_chroma ? sampler->conversion->chroma_filter : pCreateInfo->magFilter;
 497       const bool enable_min_filter_addr_rounding = min_filter != VK_FILTER_NEAREST;
 498       const bool enable_mag_filter_addr_rounding = mag_filter != VK_FILTER_NEAREST;
 499       /* From Broadwell PRM, SAMPLER_STATE:
 500        *   "Mip Mode Filter must be set to MIPFILTER_NONE for Planar YUV surfaces."
 501        */
 502       const uint32_t mip_filter_mode =
 503          (sampler->conversion &&
 504           isl_format_is_yuv(sampler->conversion->format->planes[0].isl_format)) ?
 505          MIPFILTER_NONE : vk_to_gen_mipmap_mode[pCreateInfo->mipmapMode];
 506
 507       struct GENX(SAMPLER_STATE) sampler_state = {
 508          .SamplerDisable = false,
 509          .TextureBorderColorMode = DX10OGL,
 510
 511 #if GEN_GEN >= 8
 512          .LODPreClampMode = CLAMP_MODE_OGL,
 513 #else
 514          .LODPreClampEnable = CLAMP_ENABLE_OGL,
 515 #endif
 516
 517 #if GEN_GEN == 8
 518          .BaseMipLevel = 0.0,
 519 #endif
 520          .MipModeFilter = mip_filter_mode,
 521          .MagModeFilter = vk_to_gen_tex_filter(mag_filter, pCreateInfo->anisotropyEnable),
 522          .MinModeFilter = vk_to_gen_tex_filter(min_filter, pCreateInfo->anisotropyEnable),
 523          .TextureLODBias = anv_clamp_f(pCreateInfo->mipLodBias, -16, 15.996),
 524          .AnisotropicAlgorithm =
 525             pCreateInfo->anisotropyEnable ? EWAApproximation : LEGACY,
 526          .MinLOD = anv_clamp_f(pCreateInfo->minLod, 0, 14),
 527          .MaxLOD = anv_clamp_f(pCreateInfo->maxLod, 0, 14),
 528          .ChromaKeyEnable = 0,
 529          .ChromaKeyIndex = 0,
 530          .ChromaKeyMode = 0,
 531          .ShadowFunction =
 532             vk_to_gen_shadow_compare_op[pCreateInfo->compareEnable ?
 533                                         pCreateInfo->compareOp : VK_COMPARE_OP_NEVER],
 534          .CubeSurfaceControlMode = OVERRIDE,
 535
 536          .BorderColorPointer = border_color_offset,
 537
 538 #if GEN_GEN >= 8
 539          .LODClampMagnificationMode = MIPNONE,
 540 #endif
 541
 542          .MaximumAnisotropy = vk_to_gen_max_anisotropy(pCreateInfo->maxAnisotropy),
 543          .RAddressMinFilterRoundingEnable = enable_min_filter_addr_rounding,
 544          .RAddressMagFilterRoundingEnable = enable_mag_filter_addr_rounding,
 545          .VAddressMinFilterRoundingEnable = enable_min_filter_addr_rounding,
 546          .VAddressMagFilterRoundingEnable = enable_mag_filter_addr_rounding,
 547          .UAddressMinFilterRoundingEnable = enable_min_filter_addr_rounding,
 548          .UAddressMagFilterRoundingEnable = enable_mag_filter_addr_rounding,
 549          .TrilinearFilterQuality = 0,
 550          .NonnormalizedCoordinateEnable = pCreateInfo->unnormalizedCoordinates,
 551          .TCXAddressControlMode = vk_to_gen_tex_address[pCreateInfo->addressModeU],
 552          .TCYAddressControlMode = vk_to_gen_tex_address[pCreateInfo->addressModeV],
 553          .TCZAddressControlMode = vk_to_gen_tex_address[pCreateInfo->addressModeW],
 554
 555 #if GEN_GEN >= 9
 556          .ReductionType = sampler_reduction_mode,
 557          .ReductionTypeEnable = enable_sampler_reduction,
 558 #endif
 559       };
 560
 561       GENX(SAMPLER_STATE_pack)(NULL, sampler->state[p], &sampler_state);
 562
 563       if (sampler->bindless_state.map) {
 564          memcpy(sampler->bindless_state.map + p * 32,
 565                 sampler->state[p], GENX(SAMPLER_STATE_length) * 4);
 566       }
 567    }
 568
 569    *pSampler = anv_sampler_to_handle(sampler);
 570
 571    return VK_SUCCESS;
 572 }