963f2831c83b39599e1ac707ff9bf2f2f02b819e
1 from UserDict
import UserDict
4 """ pin interface declaration.
5 * name is the name of the pin
6 * ready, enabled and io all create a (* .... *) prefix
7 * action changes it to an "in" if true
10 def __init__(self
, name
,
18 self
.enabled
= enabled
21 self
.bitspec
= bitspec
if bitspec
else '1'
23 def ifacefmt(self
, fmtfn
=None):
27 status
.append('always_ready')
29 status
.append('always_enabled')
31 status
.append('result="io"')
34 res
+= ','.join(status
)
39 name
= fmtfn(self
.name
)
43 res
+= ' (Bit#(%s) in)' % self
.bitspec
45 res
+= " Bit#(%s) " % self
.bitspec
50 def ifacedef(self
, fmtoutfn
=None, fmtinfn
=None, fmtdecfn
=None):
53 fmtname
= fmtinfn(self
.name
)
55 res
+= fmtdecfn(self
.name
)
56 res
+= '(Bit#(%s) in);\n' % self
.bitspec
57 res
+= ' %s<=in;\n' % fmtname
60 fmtname
= fmtoutfn(self
.name
)
61 res
+= "%s=%s;" % (self
.name
, fmtname
)
64 def wirefmt(self
, fmtoutfn
=None, fmtinfn
=None, fmtdecfn
=None):
65 res
= ' Wire#(Bit#(%s)) ' % self
.bitspec
67 res
+= '%s' % fmtinfn(self
.name
)
69 res
+= '%s' % fmtoutfn(self
.name
)
70 res
+= "<-mkDWire(0);"
73 class Interface(object):
74 """ create an interface from a list of pinspecs.
75 each pinspec is a dictionary, see Pin class arguments
78 def __init__(self
, ifacename
, pinspecs
):
79 self
.ifacename
= ifacename
81 self
.pinspecs
= pinspecs
85 if p
.get('outen') is True: # special case, generate 3 pins
87 for psuffix
in ['out', 'outen', 'in']:
88 _p
['name'] = "%s_%s" % (self
.pname(p
['name']), psuffix
)
89 _p
['action'] = psuffix
!= 'in'
90 self
.pins
.append(Pin(**_p
))
92 _p
['name'] = self
.pname(p
['name'])
93 self
.pins
.append(Pin(**_p
))
95 def pname(self
, name
):
96 return '%s{0}_%s' % (self
.ifacename
, name
)
98 def wirefmt(self
, *args
):
99 res
= '\n'.join(map(self
.wirefmtpin
, self
.pins
)).format(*args
)
101 for p
in self
.pinspecs
:
102 name
= self
.pname(p
['name']).format(*args
)
103 res
+= " GenericIOType %s_io = GenericIOType{\n" % name
105 if p
.get('outen') is True:
106 outname
= self
.ifacefmtoutfn(name
)
107 params
.append('outputval:%s_out,' % outname
)
108 params
.append('output_en:%s_outen,' % outname
)
109 params
.append('input_en:~%s_outen,' % outname
)
110 elif p
.get('action'):
111 outname
= self
.ifacefmtoutfn(name
)
112 params
.append('outputval:%s,' % outname
)
113 params
.append('output_en:1,')
114 params
.append('input_en:0,')
116 params
.append('outputval:0,')
117 params
.append('output_en:0,')
118 params
.append('input_en:1,')
119 params
+= ['pullup_en:0,', 'pulldown_en:0,',
120 'pushpull_en:0,', 'drivestrength:0,',
123 res
+= ' %s\n' % param
127 def ifacefmt(self
, *args
):
128 res
= '\n'.join(map(self
.ifacefmtdecpin
, self
.pins
)).format(*args
)
131 def ifacefmtdecfn(self
, name
):
134 def ifacefmtdecfn2(self
, name
):
137 def ifacefmtoutfn(self
, name
):
140 def ifacefmtinfn(self
, name
):
143 def wirefmtpin(self
, pin
):
144 return pin
.wirefmt(self
.ifacefmtoutfn
, self
.ifacefmtinfn
,
147 def ifacefmtdecpin(self
, pin
):
148 return pin
.ifacefmt(self
.ifacefmtdecfn
)
150 def ifacefmtpin(self
, pin
):
151 return pin
.ifacedef(self
.ifacefmtoutfn
, self
.ifacefmtinfn
,
154 def ifacedef(self
, *args
):
155 res
= '\n'.join(map(self
.ifacefmtpin
, self
.pins
))
156 res
= res
.format(*args
)
157 return '\n' + res
+ '\n'
160 class IOInterface(Interface
):
162 def ifacefmtoutfn(self
, name
):
163 """ for now strip off io{0}_ part """
164 return "cell{0}_mux_out.%s" % name
[6:]
166 def ifacefmtinfn(self
, name
):
167 return "cell{0}_mux_in"
170 class Interfaces(UserDict
):
171 """ contains a list of interface definitions
176 UserDict
.__init
__(self
, {})
177 with
open('interfaces.txt', 'r') as ifile
:
178 for l
in ifile
.readlines():
184 spec
= self
.read_spec(name
)
185 self
.ifaceadd(name
, count
, Interface(name
, spec
))
187 def ifaceadd(self
, name
, count
, iface
):
188 self
.ifacecount
.append((name
, count
))
191 def read_spec(self
, name
):
193 with
open('%s.txt' % name
, 'r') as sfile
:
194 for l
in sfile
.readlines():
201 elif l
[1] == 'inout':
206 def ifacedef(self
, f
, *args
):
207 for (name
, count
) in self
.ifacecount
:
208 for i
in range(count
):
209 f
.write(self
.data
[name
].ifacedef(i
))
211 def ifacefmt(self
, f
, *args
):
213 // interface declaration between %s-{0} and pinmux'''
214 for (name
, count
) in self
.ifacecount
:
215 for i
in range(count
):
216 c
= comment
% name
.upper()
218 f
.write(self
.data
[name
].ifacefmt(i
))
220 def wirefmt(self
, f
, *args
):
221 comment
= '\n // following wires capture signals ' \
222 'to IO CELL if %s-{0} is\n' \
224 for (name
, count
) in self
.ifacecount
:
225 for i
in range(count
):
228 f
.write(self
.data
[name
].wirefmt(i
))
231 # ========= Interface declarations ================ #
233 mux_interface
= Interface('cell', [{'name': 'mux', 'ready':False,
235 'bitspec': '{1}', 'action': True}])
237 io_interface
= IOInterface('io',
238 [{'name': 'outputval', 'enabled': False},
239 {'name': 'output_en', 'enabled': False},
240 {'name': 'input_en', 'enabled': False},
241 {'name': 'pullup_en', 'enabled': False},
242 {'name': 'pulldown_en', 'enabled': False},
243 {'name': 'drivestrength', 'enabled': False},
244 {'name': 'pushpull_en', 'enabled': False},
245 {'name': 'opendrain_en', 'enabled': False},
246 {'name': 'inputval', 'action': True, 'io': True},
249 # == Peripheral Interface definitions == #
250 # these are the interface of the peripherals to the pin mux
251 # Outputs from the peripherals will be inputs to the pinmux
252 # module. Hence the change in direction for most pins
254 ifaces
= Interfaces()
256 # ======================================= #
259 if __name__
== '__main__':
261 uartinterface_decl
= Interface('uart',
263 {'name': 'tx', 'action': True},
266 spiinterface_decl
= Interface('spi',
267 [{'name': 'sclk', 'action': True},
268 {'name': 'mosi', 'action': True},
269 {'name': 'nss', 'action': True},
273 twiinterface_decl
= Interface('twi',
274 [{'name': 'sda', 'outen': True},
275 {'name': 'scl', 'outen': True},
278 sdinterface_decl
= Interface('sd',
279 [{'name': 'clk', 'action': True},
280 {'name': 'cmd', 'action': True},
281 {'name': 'd0', 'outen': True},
282 {'name': 'd1', 'outen': True},
283 {'name': 'd2', 'outen': True},
284 {'name': 'd3', 'outen': True}
287 jtaginterface_decl
= Interface('jtag',
292 {'name': 'tdo', 'action': True}
295 pwminterface_decl
= Interface('pwm',
296 [{'name': "pwm", 'action': True}
299 def _pinmunge(p
, sep
, repl
, dedupe
=True):
300 """ munges the text so it's easier to compare.
301 splits by separator, strips out blanks, re-joins.
306 p
= filter(lambda x
: x
, p
) # filter out blanks
310 """ munges the text so it's easier to compare.
312 # first join lines by semicolons, strip out returns
314 p
= map(lambda x
: x
.replace('\n', ''), p
)
316 # now split first by brackets, then spaces (deduping on spaces)
317 p
= _pinmunge(p
, "(", " ( ", False)
318 p
= _pinmunge(p
, ")", " ) ", False)
319 p
= _pinmunge(p
, " ", " ")
325 for p1
, p2
in zip(l1
, l2
):
331 from interface_def
import io_interface_def
332 print io_interface_def
.format(0)
333 print io_interface
.ifacedef(0)
334 assert io_interface_def
.format(0) == io_interface
.ifacedef(0)
336 mux_interfacetest
= '''
337 method Action cell{0}_mux(Bit#({1}) in);'''
338 print pinmunge(mux_interfacetest
.format(0,1))
339 print pinmunge(mux_interface
.ifacefmt(0, 1))
340 from interface_def
import mux_interface_def
341 print repr(mux_interface_def
.format(0, 1))
342 print repr(mux_interface
.ifacedef(0, 1))
343 assert mux_interface_def
.format(0,1) == mux_interface
.ifacedef(0,1)
345 from wire_def
import uartwires
346 print uartwires
.format(0)
347 print uartinterface_decl
.wirefmt(0)
348 assert uartwires
.format(0) == uartinterface_decl
.wirefmt(0), \
349 zipcmp(uartwires
.format(0), uartinterface_decl
.wirefmt(0))
351 from wire_def
import spiwires
352 print spiwires
.format(0)
353 print spiinterface_decl
.wirefmt(0)
354 assert spiwires
.format(0) == spiinterface_decl
.wirefmt(0), \
355 zipcmp(spiwires
.format(0), spiinterface_decl
.wirefmt(0))
357 from wire_def
import jtagwires
358 print jtagwires
.format(0)
359 print jtaginterface_decl
.wirefmt(0)
360 assert jtagwires
.format(0) == jtaginterface_decl
.wirefmt(0), \
361 zipcmp(jtagwires
.format(0), jtaginterface_decl
.wirefmt(0))
363 from wire_def
import sdwires
364 print sdwires
.format(0)
365 print sdinterface_decl
.wirefmt(0)
366 assert sdwires
.format(0) == sdinterface_decl
.wirefmt(0), \
367 zipcmp(sdwires
.format(0), sdinterface_decl
.wirefmt(0))
369 from wire_def
import pwmwires
370 print pwmwires
.format(0)
371 print pwminterface_decl
.wirefmt(0)
372 assert pwmwires
.format(0) == pwminterface_decl
.wirefmt(0), \
373 zipcmp(pwmwires
.format(0), pwminterface_decl
.wirefmt(0))
375 from wire_def
import twiwires
376 print twiwires
.format(0)
377 print twiinterface_decl
.wirefmt(0)
378 assert twiwires
.format(0) == twiinterface_decl
.wirefmt(0), \
379 zipcmp(twiwires
.format(0), twiinterface_decl
.wirefmt(0))
381 ifaceuart
= ifaces
['uart']
382 print ifaceuart
.ifacedef(0)
383 print uartinterface_decl
.ifacedef(0)
384 assert ifaceuart
.ifacedef(0) == uartinterface_decl
.ifacedef(0)
386 ifacetwi
= ifaces
['twi']
387 print ifacetwi
.ifacedef(0)
388 print twiinterface_decl
.ifacedef(0)
389 assert ifacetwi
.ifacedef(0) == twiinterface_decl
.ifacedef(0)
391 ifacepwm
= ifaces
['pwm']
392 print ifacepwm
.ifacedef(0)
393 print pwminterface_decl
.ifacedef(0)
394 assert ifacepwm
.ifacedef(0) == pwminterface_decl
.ifacedef(0)
396 ifacesd
= ifaces
['sd']
397 print ifacesd
.ifacedef(0)
398 print sdinterface_decl
.ifacedef(0)
399 assert ifacesd
.ifacedef(0) == sdinterface_decl
.ifacedef(0)
401 ifacespi
= ifaces
['spi']
402 print ifacespi
.ifacedef(0)
403 print spiinterface_decl
.ifacedef(0)
404 assert ifacespi
.ifacedef(0) == spiinterface_decl
.ifacedef(0)
406 ifacejtag
= ifaces
['jtag']
407 print ifacejtag
.ifacedef(0)
408 print jtaginterface_decl
.ifacedef(0)
409 assert ifacejtag
.ifacedef(0) == jtaginterface_decl
.ifacedef(0)