1 // See LICENSE for license details.
2 package sifive.blocks.devices.mockaon
6 import coreplex.CoreplexRISCVPlatform
7 import diplomacy.LazyModule
10 HasTopLevelNetworksBundle,
11 HasTopLevelNetworksModule
13 import uncore.tilelink2.{IntXing, TLAsyncCrossingSource, TLFragmenter}
15 case object PeripheryMockAONKey extends Field[MockAONParams]
17 trait HasPeripheryMockAON extends HasTopLevelNetworks {
18 val coreplex: CoreplexRISCVPlatform
20 // We override the clock & Reset here so that all synchronizers, etc
21 // are in the proper clock domain.
22 val mockAONParams= p(PeripheryMockAONKey)
23 val aon = LazyModule(new MockAONWrapper(peripheryBusBytes, mockAONParams))
24 val aon_int = LazyModule(new IntXing)
25 aon.node := TLAsyncCrossingSource()(TLFragmenter(peripheryBusBytes, cacheBlockBytes)(peripheryBus.node))
26 aon_int.intnode := aon.intnode
27 intBus.intnode := aon_int.intnode
30 trait HasPeripheryMockAONBundle extends HasTopLevelNetworksBundle {
31 val aon = new MockAONWrapperBundle()
34 trait HasPeripheryMockAONModule extends HasTopLevelNetworksModule {
35 val outer: HasPeripheryMockAON
36 val io: HasPeripheryMockAONBundle
38 io.aon <> outer.aon.module.io
40 // Explicit clock & reset are unused in MockAONWrapper.
41 // Tie to check this assumption.
42 outer.aon.module.clock := Bool(false).asClock
43 outer.aon.module.reset := Bool(true)
45 outer.coreplex.module.io.rtcToggle := outer.aon.module.io.rtc.asUInt.toBool