src/main/scala/devices/mockaon/MockAONPeriphery.scala

   1 // See LICENSE for license details.
   2 package sifive.blocks.devices.mockaon
   3
   4 import Chisel._
   5 import freechips.rocketchip.config.Field
   6 import freechips.rocketchip.devices.debug.HasPeripheryDebug
   7 import freechips.rocketchip.devices.tilelink.HasPeripheryCLINT
   8 import freechips.rocketchip.diplomacy.{LazyModule, LazyModuleImp}
   9 import freechips.rocketchip.interrupts._
  10 import freechips.rocketchip.subsystem.BaseSubsystem
  11 import freechips.rocketchip.tilelink.{TLAsyncCrossingSource}
  12 import freechips.rocketchip.util.{ResetCatchAndSync, SynchronizerShiftReg}
  13
  14 case object PeripheryMockAONKey extends Field[MockAONParams]
  15
  16 trait HasPeripheryMockAON extends HasPeripheryCLINT with HasPeripheryDebug { this: BaseSubsystem =>
  17   // We override the clock & Reset here so that all synchronizers, etc
  18   // are in the proper clock domain.
  19   val mockAONParams= p(PeripheryMockAONKey)
  20   val aon = LazyModule(new MockAONWrapper(pbus.beatBytes, mockAONParams))
  21   pbus.toVariableWidthSlave(Some("aon")) { aon.node := TLAsyncCrossingSource() }
  22   ibus.fromSync := IntSyncCrossingSink() := aon.intnode
  23 }
  24
  25 trait HasPeripheryMockAONBundle {
  26   val aon: MockAONWrapperBundle
  27   def coreResetCatchAndSync(core_clock: Clock) = {
  28     ResetCatchAndSync(core_clock, aon.rsts.corerst, 20)
  29   }
  30 }
  31
  32 trait HasPeripheryMockAONModuleImp extends LazyModuleImp with HasPeripheryMockAONBundle {
  33   val outer: HasPeripheryMockAON
  34   val aon = IO(new MockAONWrapperBundle)
  35
  36   aon <> outer.aon.module.io
  37
  38   // Explicit clock & reset are unused in MockAONWrapper.
  39   // Tie  to check this assumption.
  40   outer.aon.module.clock := Bool(false).asClock
  41   outer.aon.module.reset := Bool(true)
  42
  43   // Synchronize the external toggle into the clint
  44   val rtc_sync = SynchronizerShiftReg(outer.aon.module.io.rtc.asUInt.toBool, 3, Some("rtc"))
  45   val rtc_last = Reg(init = Bool(false), next=rtc_sync)
  46   val rtc_tick = Reg(init = Bool(false), next=(rtc_sync & (~rtc_last)))
  47
  48   outer.clint.module.io.rtcTick := rtc_tick
  49
  50   outer.aon.module.io.ndreset := outer.debug.module.io.ctrl.ndreset
  51 }