1 // See LICENSE for license details.
2 package sifive.blocks.devices.pwm
5 import freechips.rocketchip.config.Field
6 import freechips.rocketchip.diplomacy.{LazyModule,LazyMultiIOModuleImp}
7 import freechips.rocketchip.chip.HasSystemNetworks
8 import freechips.rocketchip.tilelink.TLFragmenter
9 import freechips.rocketchip.util.HeterogeneousBag
10 import sifive.blocks.devices.pinctrl.{PinCtrl, Pin}
12 class PWMPortIO(val c: PWMParams) extends Bundle {
13 val port = Vec(c.ncmp, Bool()).asOutput
14 override def cloneType: this.type = new PWMPortIO(c).asInstanceOf[this.type]
17 class PWMPins[T <: Pin] (pingen: ()=> T, val c: PWMParams) extends Bundle {
19 val pwm: Vec[T] = Vec(c.ncmp, pingen())
21 override def cloneType: this.type =
22 this.getClass.getConstructors.head.newInstance(pingen, c).asInstanceOf[this.type]
24 def fromPWMPort(port: PWMPortIO) {
25 (pwm zip port.port) foreach {case (pin, port) =>
31 case object PeripheryPWMKey extends Field[Seq[PWMParams]]
33 trait HasPeripheryPWM extends HasSystemNetworks {
34 val pwmParams = p(PeripheryPWMKey)
35 val pwms = pwmParams map { params =>
36 val pwm = LazyModule(new TLPWM(peripheryBusBytes, params))
37 pwm.node := TLFragmenter(peripheryBusBytes, cacheBlockBytes)(peripheryBus.node)
38 intBus.intnode := pwm.intnode
43 trait HasPeripheryPWMBundle {
44 val pwm: HeterogeneousBag[PWMPortIO]
48 trait HasPeripheryPWMModuleImp extends LazyMultiIOModuleImp with HasPeripheryPWMBundle {
49 val outer: HasPeripheryPWM
50 val pwm = IO(HeterogeneousBag(outer.pwmParams.map(new PWMPortIO(_))))
52 (pwm zip outer.pwms) foreach { case (io, device) =>
53 io.port := device.module.io.gpio