1 // See LICENSE for license details.
2 package sifive.blocks.devices.spi
6 class SPIInnerIO(c: SPIParamsBase) extends SPILinkIO(c) {
7 val lock = Bool(OUTPUT)
10 class SPIArbiter(c: SPIParamsBase, n: Int) extends Module {
12 val inner = Vec(n, new SPIInnerIO(c)).flip
13 val outer = new SPILinkIO(c)
14 val sel = UInt(INPUT, log2Up(n))
17 val sel = Reg(init = Vec(Bool(true) +: Seq.fill(n-1)(Bool(false))))
19 io.outer.tx.valid := Mux1H(sel, io.inner.map(_.tx.valid))
20 io.outer.tx.bits := Mux1H(sel, io.inner.map(_.tx.bits))
21 io.outer.cnt := Mux1H(sel, io.inner.map(_.cnt))
22 io.outer.fmt := Mux1H(sel, io.inner.map(_.fmt))
23 io.outer.cs := Mux1H(sel, io.inner.map(_.cs))
25 (io.inner zip sel).foreach { case (inner, s) =>
26 inner.tx.ready := io.outer.tx.ready && s
27 inner.rx.valid := io.outer.rx.valid && s
28 inner.rx.bits := io.outer.rx.bits
29 inner.active := io.outer.active && s
32 val nsel = Vec.tabulate(n)(io.sel === UInt(_))
33 val lock = Mux1H(sel, io.inner.map(_.lock))
36 when (sel.asUInt =/= nsel.asUInt) {
37 io.outer.cs.clear := Bool(true)