1 // See LICENSE for license details.
2 package sifive.blocks.devices.spi
5 import chisel3.experimental.{withClockAndReset}
6 import sifive.blocks.devices.pinctrl.{PinCtrl, Pin}
8 class SPIPins[T <: Pin] (pingen: ()=> T, c: SPIParamsBase) extends SPIBundle(c) {
11 val dq: Vec[T] = Vec(4, pingen())
12 val cs: Vec[T] = Vec(c.csWidth, pingen())
14 def fromSPIPort(spi: SPIPortIO, clock: Clock, reset: Bool,
15 syncStages: Int = 0, driveStrength: Bool = Bool(false)) {
17 withClockAndReset(clock, reset) {
18 sck.outputPin(spi.sck, ds = driveStrength)
20 (dq zip spi.dq).foreach {case (p, s) =>
21 p.outputPin(s.o, pue = Bool(true), ds = driveStrength)
24 s.i := ShiftRegister(p.i.ival, syncStages)
27 (cs zip spi.cs) foreach { case (c, s) =>
28 c.outputPin(s, ds = driveStrength)