1 // See LICENSE for license details.
2 package sifive.blocks.devices.spi
6 import uncore.tilelink2._
10 import rocketchip.PeripheryBusConfig
11 import sifive.blocks.util.{NonBlockingEnqueue, NonBlockingDequeue}
26 lazy val csIdBits = log2Up(csWidth)
27 lazy val lengthBits = log2Floor(frameBits) + 1
28 lazy val countBits = math.max(lengthBits, delayBits)
30 lazy val txDepthBits = log2Floor(txDepth) + 1
31 lazy val rxDepthBits = log2Floor(rxDepth) + 1
33 lazy val bc = new SPIBundleConfig(csWidth)
38 rSize: BigInt = 0x1000,
44 divisorBits: Int = 12,
46 extends SPIConfigBase {
48 require(frameBits >= 4)
49 require(sampleDelay >= 0)
52 case class SPIBundleConfig(csWidth: Int)
54 def union(that: SPIBundleConfig): SPIBundleConfig =
55 SPIBundleConfig(scala.math.max(csWidth, that.csWidth))
57 def toSPIConfig: SPIConfig = new SPIConfig(rAddress = -1,
61 class SPITopBundle(val i: Vec[Vec[Bool]], val r: Vec[TLBundle]) extends Bundle
63 class SPITopModule[B <: SPITopBundle](c: SPIConfigBase, bundle: => B, outer: TLSPIBase)
64 extends LazyModuleImp(outer) {
67 val port = new SPIPortIO(c)
71 val ctrl = Reg(init = SPIControl.init(c))
73 val fifo = Module(new SPIFIFO(c))
74 val mac = Module(new SPIMedia(c))
75 io.port <> mac.io.port
77 fifo.io.ctrl.fmt := ctrl.fmt
78 fifo.io.ctrl.cs <> ctrl.cs
79 fifo.io.ctrl.wm := ctrl.wm
80 mac.io.ctrl.sck := ctrl.sck
81 mac.io.ctrl.dla := ctrl.dla
82 mac.io.ctrl.cs <> ctrl.cs
84 val ie = Reg(init = new SPIInterrupts().fromBits(Bits(0)))
86 io.tl.i(0)(0) := (ip.txwm && ie.txwm) || (ip.rxwm && ie.rxwm)
88 protected val regmapBase = Seq(
89 SPICRs.sckdiv -> Seq(RegField(c.divisorBits, ctrl.sck.div)),
90 SPICRs.sckmode -> Seq(
91 RegField(1, ctrl.sck.pha),
92 RegField(1, ctrl.sck.pol)),
93 SPICRs.csid -> Seq(RegField(c.csIdBits, ctrl.cs.id)),
94 SPICRs.csdef -> ctrl.cs.dflt.map(x => RegField(1, x)),
95 SPICRs.csmode -> Seq(RegField(SPICSMode.width, ctrl.cs.mode)),
96 SPICRs.dcssck -> Seq(RegField(c.delayBits, ctrl.dla.cssck)),
97 SPICRs.dsckcs -> Seq(RegField(c.delayBits, ctrl.dla.sckcs)),
98 SPICRs.dintercs -> Seq(RegField(c.delayBits, ctrl.dla.intercs)),
99 SPICRs.dinterxfr -> Seq(RegField(c.delayBits, ctrl.dla.interxfr)),
102 RegField(SPIProtocol.width, ctrl.fmt.proto),
103 RegField(SPIEndian.width, ctrl.fmt.endian),
104 RegField(SPIDirection.width, ctrl.fmt.iodir)),
105 SPICRs.len -> Seq(RegField(c.lengthBits, ctrl.fmt.len)),
107 SPICRs.txfifo -> NonBlockingEnqueue(fifo.io.tx),
108 SPICRs.rxfifo -> NonBlockingDequeue(fifo.io.rx),
110 SPICRs.txmark -> Seq(RegField(c.txDepthBits, ctrl.wm.tx)),
111 SPICRs.rxmark -> Seq(RegField(c.rxDepthBits, ctrl.wm.rx)),
114 RegField(1, ie.txwm),
115 RegField(1, ie.rxwm)),
117 RegField.r(1, ip.txwm),
118 RegField.r(1, ip.rxwm)))
121 abstract class TLSPIBase(c: SPIConfigBase)(implicit p: Parameters) extends LazyModule {
122 require(isPow2(c.rSize))
123 val rnode = TLRegisterNode(address = AddressSet(c.rAddress, c.rSize-1), beatBytes = p(PeripheryBusConfig).beatBytes)
124 val intnode = IntSourceNode(1)
127 class TLSPI(c: SPIConfig)(implicit p: Parameters) extends TLSPIBase(c)(p) {
128 lazy val module = new SPITopModule(c, new SPITopBundle(intnode.bundleOut, rnode.bundleIn), this) {
129 mac.io.link <> fifo.io.link
130 rnode.regmap(regmapBase:_*)