1 // See LICENSE for license details.
2 package sifive.blocks.devices.uart
6 import diplomacy.{LazyModule, LazyMultiIOModuleImp}
7 import rocketchip.HasSystemNetworks
8 import uncore.tilelink2.TLFragmenter
10 import sifive.blocks.devices.gpio.{GPIOPin, GPIOOutputPinCtrl, GPIOInputPinCtrl}
11 import sifive.blocks.util.ShiftRegisterInit
13 case object PeripheryUARTKey extends Field[Seq[UARTParams]]
15 trait HasPeripheryUART extends HasSystemNetworks {
16 val uartParams = p(PeripheryUARTKey)
17 val uarts = uartParams map { params =>
18 val uart = LazyModule(new TLUART(peripheryBusBytes, params))
19 uart.node := TLFragmenter(peripheryBusBytes, cacheBlockBytes)(peripheryBus.node)
20 intBus.intnode := uart.intnode
25 trait HasPeripheryUARTBundle {
26 val uarts: Vec[UARTPortIO]
28 def tieoffUARTs(dummy: Int = 1) {
29 uarts.foreach { _.rxd := UInt(1) }
32 def UARTtoGPIOPins(sync_stages: Int = 0): Seq[UARTGPIOPort] = uarts.map { u =>
33 val pin = Module(new UARTGPIOPort(sync_stages))
39 trait HasPeripheryUARTModuleImp extends LazyMultiIOModuleImp with HasPeripheryUARTBundle {
40 val outer: HasPeripheryUART
41 val uarts = IO(Vec(outer.uartParams.size, new UARTPortIO))
43 (uarts zip outer.uarts).foreach { case (io, device) =>
44 io <> device.module.io.port
48 class UARTPinsIO extends Bundle {
53 class UARTGPIOPort(syncStages: Int = 0) extends Module {
55 val uart = new UARTPortIO().flip()
56 val pins = new UARTPinsIO
59 GPIOOutputPinCtrl(io.pins.txd, io.uart.txd)
60 val rxd = GPIOInputPinCtrl(io.pins.rxd)
61 io.uart.rxd := ShiftRegisterInit(rxd, syncStages, Bool(true))