1 // See LICENSE for license details.
2 package sifive.blocks.devices.uart
5 import freechips.rocketchip.config.Field
6 import freechips.rocketchip.diplomacy.{LazyModule, LazyMultiIOModuleImp}
7 import freechips.rocketchip.chip.HasSystemNetworks
8 import freechips.rocketchip.tilelink.TLFragmenter
9 import sifive.blocks.devices.gpio.{GPIOPin, GPIOOutputPinCtrl, GPIOInputPinCtrl}
10 import sifive.blocks.util.ShiftRegisterInit
12 case object PeripheryUARTKey extends Field[Seq[UARTParams]]
14 trait HasPeripheryUART extends HasSystemNetworks {
15 val uartParams = p(PeripheryUARTKey)
16 val uarts = uartParams map { params =>
17 val uart = LazyModule(new TLUART(peripheryBusBytes, params))
18 uart.node := TLFragmenter(peripheryBusBytes, cacheBlockBytes)(peripheryBus.node)
19 intBus.intnode := uart.intnode
24 trait HasPeripheryUARTBundle {
25 val uarts: Vec[UARTPortIO]
27 def tieoffUARTs(dummy: Int = 1) {
28 uarts.foreach { _.rxd := UInt(1) }
31 def UARTtoGPIOPins(syncStages: Int = 0): Seq[UARTPinsIO] = uarts.map { u =>
32 val pins = Module(new UARTGPIOPort(syncStages))
38 trait HasPeripheryUARTModuleImp extends LazyMultiIOModuleImp with HasPeripheryUARTBundle {
39 val outer: HasPeripheryUART
40 val uarts = IO(Vec(outer.uartParams.size, new UARTPortIO))
42 (uarts zip outer.uarts).foreach { case (io, device) =>
43 io <> device.module.io.port
47 class UARTPinsIO extends Bundle {
52 class UARTGPIOPort(syncStages: Int = 0) extends Module {
54 val uart = new UARTPortIO().flip()
55 val pins = new UARTPinsIO
58 GPIOOutputPinCtrl(io.pins.txd, io.uart.txd)
59 val rxd = GPIOInputPinCtrl(io.pins.rxd)
60 io.uart.rxd := ShiftRegisterInit(rxd, syncStages, Bool(true))