1 // See LICENSE for license details.
2 package sifive.blocks.devices.uart
6 import diplomacy.LazyModule
9 HasTopLevelNetworksBundle,
10 HasTopLevelNetworksModule
12 import uncore.tilelink2._
14 import sifive.blocks.devices.gpio.{GPIOPin, GPIOOutputPinCtrl, GPIOInputPinCtrl}
15 import sifive.blocks.util.ShiftRegisterInit
17 case object PeripheryUARTKey extends Field[Seq[UARTParams]]
19 trait HasPeripheryUART extends HasTopLevelNetworks {
20 val uartParams = p(PeripheryUARTKey)
21 val uarts = uartParams map { params =>
22 val uart = LazyModule(new TLUART(peripheryBusBytes, params))
23 uart.node := TLFragmenter(peripheryBusBytes, cacheBlockBytes)(peripheryBus.node)
24 intBus.intnode := uart.intnode
29 trait HasPeripheryUARTBundle extends HasTopLevelNetworksBundle {
30 val outer: HasPeripheryUART
31 val uarts = Vec(outer.uartParams.size, new UARTPortIO)
34 trait HasPeripheryUARTModule extends HasTopLevelNetworksModule {
35 val outer: HasPeripheryUART
36 val io: HasPeripheryUARTBundle
37 (io.uarts zip outer.uarts).foreach { case (io, device) =>
38 io <> device.module.io.port
42 class UARTPinsIO extends Bundle {
47 class UARTGPIOPort(syncStages: Int = 0) extends Module {
49 val uart = new UARTPortIO().flip()
50 val pins = new UARTPinsIO
53 GPIOOutputPinCtrl(io.pins.txd, io.uart.txd)
54 val rxd = GPIOInputPinCtrl(io.pins.rxd)
55 io.uart.rxd := ShiftRegisterInit(rxd, syncStages, Bool(true))