1 // See LICENSE for license details.
2 package sifive.blocks.devices.xilinxvc707pciex1
5 import diplomacy.LazyModule
8 HasTopLevelNetworksModule,
9 HasTopLevelNetworksBundle
11 import uncore.tilelink2.TLWidthWidget
13 trait HasPeripheryXilinxVC707PCIeX1 extends HasTopLevelNetworks {
15 val xilinxvc707pcie = LazyModule(new XilinxVC707PCIeX1)
16 l2FrontendBus.node := xilinxvc707pcie.master
17 xilinxvc707pcie.slave := TLWidthWidget(socBusConfig.beatBytes)(socBus.node)
18 xilinxvc707pcie.control := TLWidthWidget(socBusConfig.beatBytes)(socBus.node)
19 intBus.intnode := xilinxvc707pcie.intnode
22 trait HasPeripheryXilinxVC707PCIeX1Bundle extends HasTopLevelNetworksBundle {
23 val xilinxvc707pcie = new XilinxVC707PCIeX1IO
26 trait HasPeripheryXilinxVC707PCIeX1Module extends HasTopLevelNetworksModule {
27 val outer: HasPeripheryXilinxVC707PCIeX1
28 val io: HasPeripheryXilinxVC707PCIeX1Bundle
30 io.xilinxvc707pcie <> outer.xilinxvc707pcie.module.io.port