src/main/scala/unleashed/u500vc707devkit/FPGAChip.scala

   1 // See LICENSE for license details.
   2 package sifive.freedom.unleashed.u500vc707devkit
   3
   4 import Chisel._
   5 import chisel3.experimental.{withClockAndReset}
   6
   7 import freechips.rocketchip.config._
   8 import freechips.rocketchip.diplomacy._
   9
  10 import sifive.blocks.devices.gpio._
  11 import sifive.blocks.devices.pinctrl.{BasePin}
  12
  13 import sifive.fpgashells.shell.xilinx.vc707shell._
  14 import sifive.fpgashells.ip.xilinx.{IOBUF}
  15
  16 //-------------------------------------------------------------------------
  17 // PinGen
  18 //-------------------------------------------------------------------------
  19
  20 object PinGen {
  21   def apply(): BasePin = {
  22     new BasePin()
  23   }
  24 }
  25
  26 //-------------------------------------------------------------------------
  27 // U500VC707DevKitFPGAChip
  28 //-------------------------------------------------------------------------
  29
  30 class U500VC707DevKitFPGAChip(implicit override val p: Parameters)
  31     extends VC707Shell
  32     with HasPCIe
  33     with HasDDR3
  34     with HasDebugJTAG {
  35
  36   //-----------------------------------------------------------------------
  37   // DUT
  38   //-----------------------------------------------------------------------
  39
  40   // Connect the clock to the 50 Mhz output from the PLL
  41   dut_clock := clk50
  42   withClockAndReset(dut_clock, dut_reset) {
  43     val dut = Module(LazyModule(new U500VC707DevKitSystem).module)
  44
  45     //---------------------------------------------------------------------
  46     // Connect peripherals
  47     //---------------------------------------------------------------------
  48
  49     connectDebugJTAG(dut)
  50     connectSPI      (dut)
  51     connectUART     (dut)
  52     connectPCIe     (dut)
  53     connectMIG      (dut)
  54
  55     //---------------------------------------------------------------------
  56     // GPIO
  57     //---------------------------------------------------------------------
  58
  59     val gpioParams = p(PeripheryGPIOKey)
  60     val gpio_pins = Wire(new GPIOPins(() => PinGen(), gpioParams(0)))
  61
  62     GPIOPinsFromPort(gpio_pins, dut.gpio(0))
  63
  64     gpio_pins.pins.foreach { _.i.ival := Bool(false) }
  65     gpio_pins.pins.zipWithIndex.foreach {
  66       case(pin, idx) => led(idx) := pin.o.oval
  67     }
  68
  69     // tie to zero
  70     for( idx <- 7 to 4 ) { led(idx) := false.B }
  71   }
  72
  73 }