1 // See LICENSE for license details.
2 package sifive.blocks.util
7 // MSB indicates full status
8 object NonBlockingEnqueue {
9 def apply(enq: DecoupledIO[UInt], regWidth: Int = 32): Seq[RegField] = {
10 val enqWidth = enq.bits.getWidth
11 val quash = Wire(Bool())
13 require(regWidth > enqWidth)
17 RegWriteFn((valid, data) => {
18 enq.valid := valid && !quash
22 RegField(regWidth - enqWidth - 1),
25 RegWriteFn((valid, data) => {
26 quash := valid && data(0)
32 // MSB indicates empty status
33 object NonBlockingDequeue {
34 def apply(deq: DecoupledIO[UInt], regWidth: Int = 32): Seq[RegField] = {
35 val deqWidth = deq.bits.getWidth
37 require(regWidth > deqWidth)
42 (Bool(true), deq.bits)
44 RegField(regWidth - deqWidth - 1),
45 RegField.r(1, !deq.valid))