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40 * Authors: Erik Hallnor
46 * Definition of BaseCache functions.
49 #include "mem/cache/base.hh"
51 #include "base/compiler.hh"
52 #include "base/logging.hh"
53 #include "debug/Cache.hh"
54 #include "debug/CachePort.hh"
55 #include "debug/CacheVerbose.hh"
56 #include "mem/cache/mshr.hh"
57 #include "mem/cache/prefetch/base.hh"
58 #include "mem/cache/queue_entry.hh"
59 #include "params/BaseCache.hh"
60 #include "sim/core.hh"
67 BaseCache::CacheSlavePort::CacheSlavePort(const std::string
&_name
,
69 const std::string
&_label
)
70 : QueuedSlavePort(_name
, _cache
, queue
), queue(*_cache
, *this, _label
),
71 blocked(false), mustSendRetry(false),
72 sendRetryEvent([this]{ processSendRetry(); }, _name
)
76 BaseCache::BaseCache(const BaseCacheParams
*p
, unsigned blk_size
)
78 cpuSidePort (p
->name
+ ".cpu_side", this, "CpuSidePort"),
79 memSidePort(p
->name
+ ".mem_side", this, "MemSidePort"),
80 mshrQueue("MSHRs", p
->mshrs
, 0, p
->demand_mshr_reserve
), // see below
81 writeBuffer("write buffer", p
->write_buffers
, p
->mshrs
), // see below
83 prefetcher(p
->prefetcher
),
84 prefetchOnAccess(p
->prefetch_on_access
),
85 writebackClean(p
->writeback_clean
),
86 tempBlockWriteback(nullptr),
87 writebackTempBlockAtomicEvent([this]{ writebackTempBlockAtomic(); },
89 EventBase::Delayed_Writeback_Pri
),
91 lookupLatency(p
->tag_latency
),
92 dataLatency(p
->data_latency
),
93 forwardLatency(p
->tag_latency
),
94 fillLatency(p
->data_latency
),
95 responseLatency(p
->response_latency
),
96 numTarget(p
->tgts_per_mshr
),
98 clusivity(p
->clusivity
),
99 isReadOnly(p
->is_read_only
),
102 noTargetMSHR(nullptr),
103 missCount(p
->max_miss_count
),
104 addrRanges(p
->addr_ranges
.begin(), p
->addr_ranges
.end()),
107 // the MSHR queue has no reserve entries as we check the MSHR
108 // queue on every single allocation, whereas the write queue has
109 // as many reserve entries as we have MSHRs, since every MSHR may
110 // eventually require a writeback, and we do not check the write
111 // buffer before committing to an MSHR
113 // forward snoops is overridden in init() once we can query
114 // whether the connected master is actually snooping or not
116 tempBlock
= new TempCacheBlk();
117 tempBlock
->data
= new uint8_t[blkSize
];
119 tags
->setCache(this);
121 prefetcher
->setCache(this);
124 BaseCache::~BaseCache()
126 delete [] tempBlock
->data
;
131 BaseCache::CacheSlavePort::setBlocked()
134 DPRINTF(CachePort
, "Port is blocking new requests\n");
136 // if we already scheduled a retry in this cycle, but it has not yet
137 // happened, cancel it
138 if (sendRetryEvent
.scheduled()) {
139 owner
.deschedule(sendRetryEvent
);
140 DPRINTF(CachePort
, "Port descheduled retry\n");
141 mustSendRetry
= true;
146 BaseCache::CacheSlavePort::clearBlocked()
149 DPRINTF(CachePort
, "Port is accepting new requests\n");
152 // @TODO: need to find a better time (next cycle?)
153 owner
.schedule(sendRetryEvent
, curTick() + 1);
158 BaseCache::CacheSlavePort::processSendRetry()
160 DPRINTF(CachePort
, "Port is sending retry\n");
162 // reset the flag and call retry
163 mustSendRetry
= false;
168 BaseCache::regenerateBlkAddr(CacheBlk
* blk
)
170 if (blk
!= tempBlock
) {
171 return tags
->regenerateBlkAddr(blk
);
173 return tempBlock
->getAddr();
180 if (!cpuSidePort
.isConnected() || !memSidePort
.isConnected())
181 fatal("Cache ports on %s are not connected\n", name());
182 cpuSidePort
.sendRangeChange();
183 forwardSnoops
= cpuSidePort
.isSnooping();
187 BaseCache::getMasterPort(const std::string
&if_name
, PortID idx
)
189 if (if_name
== "mem_side") {
192 return MemObject::getMasterPort(if_name
, idx
);
197 BaseCache::getSlavePort(const std::string
&if_name
, PortID idx
)
199 if (if_name
== "cpu_side") {
202 return MemObject::getSlavePort(if_name
, idx
);
207 BaseCache::inRange(Addr addr
) const
209 for (const auto& r
: addrRanges
) {
210 if (r
.contains(addr
)) {
218 BaseCache::handleTimingReqHit(PacketPtr pkt
, CacheBlk
*blk
, Tick request_time
)
220 if (pkt
->needsResponse()) {
221 pkt
->makeTimingResponse();
222 // @todo: Make someone pay for this
223 pkt
->headerDelay
= pkt
->payloadDelay
= 0;
225 // In this case we are considering request_time that takes
226 // into account the delay of the xbar, if any, and just
227 // lat, neglecting responseLatency, modelling hit latency
228 // just as lookupLatency or or the value of lat overriden
229 // by access(), that calls accessBlock() function.
230 cpuSidePort
.schedTimingResp(pkt
, request_time
, true);
232 DPRINTF(Cache
, "%s satisfied %s, no response needed\n", __func__
,
235 // queue the packet for deletion, as the sending cache is
236 // still relying on it; if the block is found in access(),
237 // CleanEvict and Writeback messages will be deleted
239 pendingDelete
.reset(pkt
);
244 BaseCache::handleTimingReqMiss(PacketPtr pkt
, MSHR
*mshr
, CacheBlk
*blk
,
245 Tick forward_time
, Tick request_time
)
249 /// @note writebacks will be checked in getNextMSHR()
250 /// for any conflicting requests to the same block
252 //@todo remove hw_pf here
254 // Coalesce unless it was a software prefetch (see above).
256 assert(!pkt
->isWriteback());
257 // CleanEvicts corresponding to blocks which have
258 // outstanding requests in MSHRs are simply sunk here
259 if (pkt
->cmd
== MemCmd::CleanEvict
) {
260 pendingDelete
.reset(pkt
);
261 } else if (pkt
->cmd
== MemCmd::WriteClean
) {
262 // A WriteClean should never coalesce with any
263 // outstanding cache maintenance requests.
265 // We use forward_time here because there is an
266 // uncached memory write, forwarded to WriteBuffer.
267 allocateWriteBuffer(pkt
, forward_time
);
269 DPRINTF(Cache
, "%s coalescing MSHR for %s\n", __func__
,
272 assert(pkt
->req
->masterId() < system
->maxMasters());
273 mshr_hits
[pkt
->cmdToIndex()][pkt
->req
->masterId()]++;
275 // We use forward_time here because it is the same
276 // considering new targets. We have multiple
277 // requests for the same address here. It
278 // specifies the latency to allocate an internal
279 // buffer and to schedule an event to the queued
280 // port and also takes into account the additional
281 // delay of the xbar.
282 mshr
->allocateTarget(pkt
, forward_time
, order
++,
283 allocOnFill(pkt
->cmd
));
284 if (mshr
->getNumTargets() == numTarget
) {
286 setBlocked(Blocked_NoTargets
);
287 // need to be careful with this... if this mshr isn't
288 // ready yet (i.e. time > curTick()), we don't want to
289 // move it ahead of mshrs that are ready
290 // mshrQueue.moveToFront(mshr);
296 assert(pkt
->req
->masterId() < system
->maxMasters());
297 mshr_misses
[pkt
->cmdToIndex()][pkt
->req
->masterId()]++;
299 if (pkt
->isEviction() || pkt
->cmd
== MemCmd::WriteClean
) {
300 // We use forward_time here because there is an
301 // writeback or writeclean, forwarded to WriteBuffer.
302 allocateWriteBuffer(pkt
, forward_time
);
304 if (blk
&& blk
->isValid()) {
305 // If we have a write miss to a valid block, we
306 // need to mark the block non-readable. Otherwise
307 // if we allow reads while there's an outstanding
308 // write miss, the read could return stale data
309 // out of the cache block... a more aggressive
310 // system could detect the overlap (if any) and
311 // forward data out of the MSHRs, but we don't do
312 // that yet. Note that we do need to leave the
313 // block valid so that it stays in the cache, in
314 // case we get an upgrade response (and hence no
315 // new data) when the write miss completes.
316 // As long as CPUs do proper store/load forwarding
317 // internally, and have a sufficiently weak memory
318 // model, this is probably unnecessary, but at some
319 // point it must have seemed like we needed it...
320 assert((pkt
->needsWritable() && !blk
->isWritable()) ||
321 pkt
->req
->isCacheMaintenance());
322 blk
->status
&= ~BlkReadable
;
324 // Here we are using forward_time, modelling the latency of
325 // a miss (outbound) just as forwardLatency, neglecting the
326 // lookupLatency component.
327 allocateMissBuffer(pkt
, forward_time
);
333 BaseCache::recvTimingReq(PacketPtr pkt
)
335 // anything that is merely forwarded pays for the forward latency and
336 // the delay provided by the crossbar
337 Tick forward_time
= clockEdge(forwardLatency
) + pkt
->headerDelay
;
339 // We use lookupLatency here because it is used to specify the latency
341 Cycles lat
= lookupLatency
;
342 CacheBlk
*blk
= nullptr;
343 bool satisfied
= false;
345 PacketList writebacks
;
346 // Note that lat is passed by reference here. The function
347 // access() calls accessBlock() which can modify lat value.
348 satisfied
= access(pkt
, blk
, lat
, writebacks
);
350 // copy writebacks to write buffer here to ensure they logically
351 // proceed anything happening below
352 doWritebacks(writebacks
, forward_time
);
355 // Here we charge the headerDelay that takes into account the latencies
356 // of the bus, if the packet comes from it.
357 // The latency charged it is just lat that is the value of lookupLatency
358 // modified by access() function, or if not just lookupLatency.
359 // In case of a hit we are neglecting response latency.
360 // In case of a miss we are neglecting forward latency.
361 Tick request_time
= clockEdge(lat
) + pkt
->headerDelay
;
362 // Here we reset the timing of the packet.
363 pkt
->headerDelay
= pkt
->payloadDelay
= 0;
364 // track time of availability of next prefetch, if any
365 Tick next_pf_time
= MaxTick
;
368 // if need to notify the prefetcher we have to do it before
369 // anything else as later handleTimingReqHit might turn the
370 // packet in a response
372 (prefetchOnAccess
|| (blk
&& blk
->wasPrefetched()))) {
374 blk
->status
&= ~BlkHWPrefetched
;
376 // Don't notify on SWPrefetch
377 if (!pkt
->cmd
.isSWPrefetch()) {
378 assert(!pkt
->req
->isCacheMaintenance());
379 next_pf_time
= prefetcher
->notify(pkt
);
383 handleTimingReqHit(pkt
, blk
, request_time
);
385 handleTimingReqMiss(pkt
, blk
, forward_time
, request_time
);
387 // We should call the prefetcher reguardless if the request is
388 // satisfied or not, reguardless if the request is in the MSHR
389 // or not. The request could be a ReadReq hit, but still not
390 // satisfied (potentially because of a prior write to the same
391 // cache line. So, even when not satisfied, there is an MSHR
392 // already allocated for this, we need to let the prefetcher
393 // know about the request
395 // Don't notify prefetcher on SWPrefetch or cache maintenance
397 if (prefetcher
&& pkt
&&
398 !pkt
->cmd
.isSWPrefetch() &&
399 !pkt
->req
->isCacheMaintenance()) {
400 next_pf_time
= prefetcher
->notify(pkt
);
404 if (next_pf_time
!= MaxTick
) {
405 schedMemSideSendEvent(next_pf_time
);
410 BaseCache::handleUncacheableWriteResp(PacketPtr pkt
)
412 Tick completion_time
= clockEdge(responseLatency
) +
413 pkt
->headerDelay
+ pkt
->payloadDelay
;
415 // Reset the bus additional time as it is now accounted for
416 pkt
->headerDelay
= pkt
->payloadDelay
= 0;
418 cpuSidePort
.schedTimingResp(pkt
, completion_time
, true);
422 BaseCache::recvTimingResp(PacketPtr pkt
)
424 assert(pkt
->isResponse());
426 // all header delay should be paid for by the crossbar, unless
427 // this is a prefetch response from above
428 panic_if(pkt
->headerDelay
!= 0 && pkt
->cmd
!= MemCmd::HardPFResp
,
429 "%s saw a non-zero packet delay\n", name());
431 const bool is_error
= pkt
->isError();
434 DPRINTF(Cache
, "%s: Cache received %s with error\n", __func__
,
438 DPRINTF(Cache
, "%s: Handling response %s\n", __func__
,
441 // if this is a write, we should be looking at an uncacheable
443 if (pkt
->isWrite()) {
444 assert(pkt
->req
->isUncacheable());
445 handleUncacheableWriteResp(pkt
);
449 // we have dealt with any (uncacheable) writes above, from here on
450 // we know we are dealing with an MSHR due to a miss or a prefetch
451 MSHR
*mshr
= dynamic_cast<MSHR
*>(pkt
->popSenderState());
454 if (mshr
== noTargetMSHR
) {
455 // we always clear at least one target
456 clearBlocked(Blocked_NoTargets
);
457 noTargetMSHR
= nullptr;
460 // Initial target is used just for stats
461 MSHR::Target
*initial_tgt
= mshr
->getTarget();
462 int stats_cmd_idx
= initial_tgt
->pkt
->cmdToIndex();
463 Tick miss_latency
= curTick() - initial_tgt
->recvTime
;
465 if (pkt
->req
->isUncacheable()) {
466 assert(pkt
->req
->masterId() < system
->maxMasters());
467 mshr_uncacheable_lat
[stats_cmd_idx
][pkt
->req
->masterId()] +=
470 assert(pkt
->req
->masterId() < system
->maxMasters());
471 mshr_miss_latency
[stats_cmd_idx
][pkt
->req
->masterId()] +=
475 PacketList writebacks
;
477 bool is_fill
= !mshr
->isForward
&&
478 (pkt
->isRead() || pkt
->cmd
== MemCmd::UpgradeResp
);
480 CacheBlk
*blk
= tags
->findBlock(pkt
->getAddr(), pkt
->isSecure());
482 if (is_fill
&& !is_error
) {
483 DPRINTF(Cache
, "Block for addr %#llx being updated in Cache\n",
486 blk
= handleFill(pkt
, blk
, writebacks
, mshr
->allocOnFill());
487 assert(blk
!= nullptr);
490 if (blk
&& blk
->isValid() && pkt
->isClean() && !pkt
->isInvalidate()) {
491 // The block was marked not readable while there was a pending
492 // cache maintenance operation, restore its flag.
493 blk
->status
|= BlkReadable
;
496 if (blk
&& blk
->isWritable() && !pkt
->req
->isCacheInvalidate()) {
497 // If at this point the referenced block is writable and the
498 // response is not a cache invalidate, we promote targets that
499 // were deferred as we couldn't guarrantee a writable copy
500 mshr
->promoteWritable();
503 serviceMSHRTargets(mshr
, pkt
, blk
, writebacks
);
505 if (mshr
->promoteDeferredTargets()) {
506 // avoid later read getting stale data while write miss is
507 // outstanding.. see comment in timingAccess()
509 blk
->status
&= ~BlkReadable
;
511 mshrQueue
.markPending(mshr
);
512 schedMemSideSendEvent(clockEdge() + pkt
->payloadDelay
);
514 // while we deallocate an mshr from the queue we still have to
515 // check the isFull condition before and after as we might
516 // have been using the reserved entries already
517 const bool was_full
= mshrQueue
.isFull();
518 mshrQueue
.deallocate(mshr
);
519 if (was_full
&& !mshrQueue
.isFull()) {
520 clearBlocked(Blocked_NoMSHRs
);
523 // Request the bus for a prefetch if this deallocation freed enough
524 // MSHRs for a prefetch to take place
525 if (prefetcher
&& mshrQueue
.canPrefetch()) {
526 Tick next_pf_time
= std::max(prefetcher
->nextPrefetchReadyTime(),
528 if (next_pf_time
!= MaxTick
)
529 schedMemSideSendEvent(next_pf_time
);
533 // if we used temp block, check to see if its valid and then clear it out
534 if (blk
== tempBlock
&& tempBlock
->isValid()) {
535 evictBlock(blk
, writebacks
);
538 const Tick forward_time
= clockEdge(forwardLatency
) + pkt
->headerDelay
;
539 // copy writebacks to write buffer
540 doWritebacks(writebacks
, forward_time
);
542 DPRINTF(CacheVerbose
, "%s: Leaving with %s\n", __func__
, pkt
->print());
548 BaseCache::recvAtomic(PacketPtr pkt
)
550 // We are in atomic mode so we pay just for lookupLatency here.
551 Cycles lat
= lookupLatency
;
553 // follow the same flow as in recvTimingReq, and check if a cache
554 // above us is responding
555 if (pkt
->cacheResponding() && !pkt
->isClean()) {
556 assert(!pkt
->req
->isCacheInvalidate());
557 DPRINTF(Cache
, "Cache above responding to %s: not responding\n",
560 // if a cache is responding, and it had the line in Owned
561 // rather than Modified state, we need to invalidate any
562 // copies that are not on the same path to memory
563 assert(pkt
->needsWritable() && !pkt
->responderHadWritable());
564 lat
+= ticksToCycles(memSidePort
.sendAtomic(pkt
));
566 return lat
* clockPeriod();
569 // should assert here that there are no outstanding MSHRs or
570 // writebacks... that would mean that someone used an atomic
571 // access in timing mode
573 CacheBlk
*blk
= nullptr;
574 PacketList writebacks
;
575 bool satisfied
= access(pkt
, blk
, lat
, writebacks
);
577 if (pkt
->isClean() && blk
&& blk
->isDirty()) {
578 // A cache clean opearation is looking for a dirty
579 // block. If a dirty block is encountered a WriteClean
580 // will update any copies to the path to the memory
581 // until the point of reference.
582 DPRINTF(CacheVerbose
, "%s: packet %s found block: %s\n",
583 __func__
, pkt
->print(), blk
->print());
584 PacketPtr wb_pkt
= writecleanBlk(blk
, pkt
->req
->getDest(), pkt
->id
);
585 writebacks
.push_back(wb_pkt
);
589 // handle writebacks resulting from the access here to ensure they
590 // logically proceed anything happening below
591 doWritebacksAtomic(writebacks
);
592 assert(writebacks
.empty());
595 lat
+= handleAtomicReqMiss(pkt
, blk
, writebacks
);
598 // Note that we don't invoke the prefetcher at all in atomic mode.
599 // It's not clear how to do it properly, particularly for
600 // prefetchers that aggressively generate prefetch candidates and
601 // rely on bandwidth contention to throttle them; these will tend
602 // to pollute the cache in atomic mode since there is no bandwidth
603 // contention. If we ever do want to enable prefetching in atomic
604 // mode, though, this is the place to do it... see timingAccess()
605 // for an example (though we'd want to issue the prefetch(es)
606 // immediately rather than calling requestMemSideBus() as we do
609 // do any writebacks resulting from the response handling
610 doWritebacksAtomic(writebacks
);
612 // if we used temp block, check to see if its valid and if so
613 // clear it out, but only do so after the call to recvAtomic is
614 // finished so that any downstream observers (such as a snoop
615 // filter), first see the fill, and only then see the eviction
616 if (blk
== tempBlock
&& tempBlock
->isValid()) {
617 // the atomic CPU calls recvAtomic for fetch and load/store
618 // sequentuially, and we may already have a tempBlock
619 // writeback from the fetch that we have not yet sent
620 if (tempBlockWriteback
) {
621 // if that is the case, write the prevoius one back, and
622 // do not schedule any new event
623 writebackTempBlockAtomic();
625 // the writeback/clean eviction happens after the call to
626 // recvAtomic has finished (but before any successive
627 // calls), so that the response handling from the fill is
628 // allowed to happen first
629 schedule(writebackTempBlockAtomicEvent
, curTick());
632 tempBlockWriteback
= evictBlock(blk
);
635 if (pkt
->needsResponse()) {
636 pkt
->makeAtomicResponse();
639 return lat
* clockPeriod();
643 BaseCache::functionalAccess(PacketPtr pkt
, bool from_cpu_side
)
645 Addr blk_addr
= pkt
->getBlockAddr(blkSize
);
646 bool is_secure
= pkt
->isSecure();
647 CacheBlk
*blk
= tags
->findBlock(pkt
->getAddr(), is_secure
);
648 MSHR
*mshr
= mshrQueue
.findMatch(blk_addr
, is_secure
);
650 pkt
->pushLabel(name());
652 CacheBlkPrintWrapper
cbpw(blk
);
654 // Note that just because an L2/L3 has valid data doesn't mean an
655 // L1 doesn't have a more up-to-date modified copy that still
656 // needs to be found. As a result we always update the request if
657 // we have it, but only declare it satisfied if we are the owner.
659 // see if we have data at all (owned or otherwise)
660 bool have_data
= blk
&& blk
->isValid()
661 && pkt
->checkFunctional(&cbpw
, blk_addr
, is_secure
, blkSize
,
664 // data we have is dirty if marked as such or if we have an
665 // in-service MSHR that is pending a modified line
667 have_data
&& (blk
->isDirty() ||
668 (mshr
&& mshr
->inService
&& mshr
->isPendingModified()));
670 bool done
= have_dirty
||
671 cpuSidePort
.checkFunctional(pkt
) ||
672 mshrQueue
.checkFunctional(pkt
, blk_addr
) ||
673 writeBuffer
.checkFunctional(pkt
, blk_addr
) ||
674 memSidePort
.checkFunctional(pkt
);
676 DPRINTF(CacheVerbose
, "%s: %s %s%s%s\n", __func__
, pkt
->print(),
677 (blk
&& blk
->isValid()) ? "valid " : "",
678 have_data
? "data " : "", done
? "done " : "");
680 // We're leaving the cache, so pop cache->name() label
686 // if it came as a request from the CPU side then make sure it
687 // continues towards the memory side
689 memSidePort
.sendFunctional(pkt
);
690 } else if (cpuSidePort
.isSnooping()) {
691 // if it came from the memory side, it must be a snoop request
692 // and we should only forward it if we are forwarding snoops
693 cpuSidePort
.sendFunctionalSnoop(pkt
);
700 BaseCache::cmpAndSwap(CacheBlk
*blk
, PacketPtr pkt
)
702 assert(pkt
->isRequest());
704 uint64_t overwrite_val
;
706 uint64_t condition_val64
;
707 uint32_t condition_val32
;
709 int offset
= pkt
->getOffset(blkSize
);
710 uint8_t *blk_data
= blk
->data
+ offset
;
712 assert(sizeof(uint64_t) >= pkt
->getSize());
714 overwrite_mem
= true;
715 // keep a copy of our possible write value, and copy what is at the
716 // memory address into the packet
717 pkt
->writeData((uint8_t *)&overwrite_val
);
718 pkt
->setData(blk_data
);
720 if (pkt
->req
->isCondSwap()) {
721 if (pkt
->getSize() == sizeof(uint64_t)) {
722 condition_val64
= pkt
->req
->getExtraData();
723 overwrite_mem
= !std::memcmp(&condition_val64
, blk_data
,
725 } else if (pkt
->getSize() == sizeof(uint32_t)) {
726 condition_val32
= (uint32_t)pkt
->req
->getExtraData();
727 overwrite_mem
= !std::memcmp(&condition_val32
, blk_data
,
730 panic("Invalid size for conditional read/write\n");
734 std::memcpy(blk_data
, &overwrite_val
, pkt
->getSize());
735 blk
->status
|= BlkDirty
;
740 BaseCache::getNextQueueEntry()
742 // Check both MSHR queue and write buffer for potential requests,
743 // note that null does not mean there is no request, it could
744 // simply be that it is not ready
745 MSHR
*miss_mshr
= mshrQueue
.getNext();
746 WriteQueueEntry
*wq_entry
= writeBuffer
.getNext();
748 // If we got a write buffer request ready, first priority is a
749 // full write buffer, otherwise we favour the miss requests
750 if (wq_entry
&& (writeBuffer
.isFull() || !miss_mshr
)) {
751 // need to search MSHR queue for conflicting earlier miss.
752 MSHR
*conflict_mshr
=
753 mshrQueue
.findPending(wq_entry
->blkAddr
,
756 if (conflict_mshr
&& conflict_mshr
->order
< wq_entry
->order
) {
757 // Service misses in order until conflict is cleared.
758 return conflict_mshr
;
760 // @todo Note that we ignore the ready time of the conflict here
763 // No conflicts; issue write
765 } else if (miss_mshr
) {
766 // need to check for conflicting earlier writeback
767 WriteQueueEntry
*conflict_mshr
=
768 writeBuffer
.findPending(miss_mshr
->blkAddr
,
769 miss_mshr
->isSecure
);
771 // not sure why we don't check order here... it was in the
772 // original code but commented out.
774 // The only way this happens is if we are
775 // doing a write and we didn't have permissions
776 // then subsequently saw a writeback (owned got evicted)
777 // We need to make sure to perform the writeback first
778 // To preserve the dirty data, then we can issue the write
780 // should we return wq_entry here instead? I.e. do we
781 // have to flush writes in order? I don't think so... not
782 // for Alpha anyway. Maybe for x86?
783 return conflict_mshr
;
785 // @todo Note that we ignore the ready time of the conflict here
788 // No conflicts; issue read
792 // fall through... no pending requests. Try a prefetch.
793 assert(!miss_mshr
&& !wq_entry
);
794 if (prefetcher
&& mshrQueue
.canPrefetch()) {
795 // If we have a miss queue slot, we can try a prefetch
796 PacketPtr pkt
= prefetcher
->getPacket();
798 Addr pf_addr
= pkt
->getBlockAddr(blkSize
);
799 if (!tags
->findBlock(pf_addr
, pkt
->isSecure()) &&
800 !mshrQueue
.findMatch(pf_addr
, pkt
->isSecure()) &&
801 !writeBuffer
.findMatch(pf_addr
, pkt
->isSecure())) {
802 // Update statistic on number of prefetches issued
803 // (hwpf_mshr_misses)
804 assert(pkt
->req
->masterId() < system
->maxMasters());
805 mshr_misses
[pkt
->cmdToIndex()][pkt
->req
->masterId()]++;
807 // allocate an MSHR and return it, note
808 // that we send the packet straight away, so do not
810 return allocateMissBuffer(pkt
, curTick(), false);
812 // free the request and packet
822 BaseCache::satisfyRequest(PacketPtr pkt
, CacheBlk
*blk
, bool, bool)
824 assert(pkt
->isRequest());
826 assert(blk
&& blk
->isValid());
827 // Occasionally this is not true... if we are a lower-level cache
828 // satisfying a string of Read and ReadEx requests from
829 // upper-level caches, a Read will mark the block as shared but we
830 // can satisfy a following ReadEx anyway since we can rely on the
831 // Read requester(s) to have buffered the ReadEx snoop and to
832 // invalidate their blocks after receiving them.
833 // assert(!pkt->needsWritable() || blk->isWritable());
834 assert(pkt
->getOffset(blkSize
) + pkt
->getSize() <= blkSize
);
836 // Check RMW operations first since both isRead() and
837 // isWrite() will be true for them
838 if (pkt
->cmd
== MemCmd::SwapReq
) {
839 cmpAndSwap(blk
, pkt
);
840 } else if (pkt
->isWrite()) {
841 // we have the block in a writable state and can go ahead,
842 // note that the line may be also be considered writable in
843 // downstream caches along the path to memory, but always
844 // Exclusive, and never Modified
845 assert(blk
->isWritable());
846 // Write or WriteLine at the first cache with block in writable state
847 if (blk
->checkWrite(pkt
)) {
848 pkt
->writeDataToBlock(blk
->data
, blkSize
);
850 // Always mark the line as dirty (and thus transition to the
851 // Modified state) even if we are a failed StoreCond so we
852 // supply data to any snoops that have appended themselves to
853 // this cache before knowing the store will fail.
854 blk
->status
|= BlkDirty
;
855 DPRINTF(CacheVerbose
, "%s for %s (write)\n", __func__
, pkt
->print());
856 } else if (pkt
->isRead()) {
858 blk
->trackLoadLocked(pkt
);
861 // all read responses have a data payload
862 assert(pkt
->hasRespData());
863 pkt
->setDataFromBlock(blk
->data
, blkSize
);
864 } else if (pkt
->isUpgrade()) {
866 assert(!pkt
->hasSharers());
868 if (blk
->isDirty()) {
869 // we were in the Owned state, and a cache above us that
870 // has the line in Shared state needs to be made aware
871 // that the data it already has is in fact dirty
872 pkt
->setCacheResponding();
873 blk
->status
&= ~BlkDirty
;
876 assert(pkt
->isInvalidate());
877 invalidateBlock(blk
);
878 DPRINTF(CacheVerbose
, "%s for %s (invalidation)\n", __func__
,
883 /////////////////////////////////////////////////////
885 // Access path: requests coming in from the CPU side
887 /////////////////////////////////////////////////////
890 BaseCache::access(PacketPtr pkt
, CacheBlk
*&blk
, Cycles
&lat
,
891 PacketList
&writebacks
)
894 assert(pkt
->isRequest());
896 chatty_assert(!(isReadOnly
&& pkt
->isWrite()),
897 "Should never see a write in a read-only cache %s\n",
900 // Here lat is the value passed as parameter to accessBlock() function
901 // that can modify its value.
902 blk
= tags
->accessBlock(pkt
->getAddr(), pkt
->isSecure(), lat
);
904 DPRINTF(Cache
, "%s for %s %s\n", __func__
, pkt
->print(),
905 blk
? "hit " + blk
->print() : "miss");
907 if (pkt
->req
->isCacheMaintenance()) {
908 // A cache maintenance operation is always forwarded to the
909 // memory below even if the block is found in dirty state.
911 // We defer any changes to the state of the block until we
912 // create and mark as in service the mshr for the downstream
917 if (pkt
->isEviction()) {
918 // We check for presence of block in above caches before issuing
919 // Writeback or CleanEvict to write buffer. Therefore the only
920 // possible cases can be of a CleanEvict packet coming from above
921 // encountering a Writeback generated in this cache peer cache and
922 // waiting in the write buffer. Cases of upper level peer caches
923 // generating CleanEvict and Writeback or simply CleanEvict and
924 // CleanEvict almost simultaneously will be caught by snoops sent out
926 WriteQueueEntry
*wb_entry
= writeBuffer
.findMatch(pkt
->getAddr(),
929 assert(wb_entry
->getNumTargets() == 1);
930 PacketPtr wbPkt
= wb_entry
->getTarget()->pkt
;
931 assert(wbPkt
->isWriteback());
933 if (pkt
->isCleanEviction()) {
934 // The CleanEvict and WritebackClean snoops into other
935 // peer caches of the same level while traversing the
936 // crossbar. If a copy of the block is found, the
937 // packet is deleted in the crossbar. Hence, none of
938 // the other upper level caches connected to this
939 // cache have the block, so we can clear the
940 // BLOCK_CACHED flag in the Writeback if set and
941 // discard the CleanEvict by returning true.
942 wbPkt
->clearBlockCached();
945 assert(pkt
->cmd
== MemCmd::WritebackDirty
);
946 // Dirty writeback from above trumps our clean
947 // writeback... discard here
948 // Note: markInService will remove entry from writeback buffer.
949 markInService(wb_entry
);
955 // Writeback handling is special case. We can write the block into
956 // the cache without having a writeable copy (or any copy at all).
957 if (pkt
->isWriteback()) {
958 assert(blkSize
== pkt
->getSize());
960 // we could get a clean writeback while we are having
961 // outstanding accesses to a block, do the simple thing for
962 // now and drop the clean writeback so that we do not upset
963 // any ordering/decisions about ownership already taken
964 if (pkt
->cmd
== MemCmd::WritebackClean
&&
965 mshrQueue
.findMatch(pkt
->getAddr(), pkt
->isSecure())) {
966 DPRINTF(Cache
, "Clean writeback %#llx to block with MSHR, "
967 "dropping\n", pkt
->getAddr());
972 // need to do a replacement
973 blk
= allocateBlock(pkt
->getAddr(), pkt
->isSecure(), writebacks
);
975 // no replaceable block available: give up, fwd to next level.
979 tags
->insertBlock(pkt
, blk
);
981 blk
->status
|= (BlkValid
| BlkReadable
);
983 // only mark the block dirty if we got a writeback command,
984 // and leave it as is for a clean writeback
985 if (pkt
->cmd
== MemCmd::WritebackDirty
) {
986 // TODO: the coherent cache can assert(!blk->isDirty());
987 blk
->status
|= BlkDirty
;
989 // if the packet does not have sharers, it is passing
990 // writable, and we got the writeback in Modified or Exclusive
991 // state, if not we are in the Owned or Shared state
992 if (!pkt
->hasSharers()) {
993 blk
->status
|= BlkWritable
;
995 // nothing else to do; writeback doesn't expect response
996 assert(!pkt
->needsResponse());
997 pkt
->writeDataToBlock(blk
->data
, blkSize
);
998 DPRINTF(Cache
, "%s new state is %s\n", __func__
, blk
->print());
1000 // populate the time when the block will be ready to access.
1001 blk
->whenReady
= clockEdge(fillLatency
) + pkt
->headerDelay
+
1004 } else if (pkt
->cmd
== MemCmd::CleanEvict
) {
1006 // Found the block in the tags, need to stop CleanEvict from
1007 // propagating further down the hierarchy. Returning true will
1008 // treat the CleanEvict like a satisfied write request and delete
1012 // We didn't find the block here, propagate the CleanEvict further
1013 // down the memory hierarchy. Returning false will treat the CleanEvict
1014 // like a Writeback which could not find a replaceable block so has to
1015 // go to next level.
1017 } else if (pkt
->cmd
== MemCmd::WriteClean
) {
1018 // WriteClean handling is a special case. We can allocate a
1019 // block directly if it doesn't exist and we can update the
1020 // block immediately. The WriteClean transfers the ownership
1021 // of the block as well.
1022 assert(blkSize
== pkt
->getSize());
1025 if (pkt
->writeThrough()) {
1026 // if this is a write through packet, we don't try to
1027 // allocate if the block is not present
1030 // a writeback that misses needs to allocate a new block
1031 blk
= allocateBlock(pkt
->getAddr(), pkt
->isSecure(),
1034 // no replaceable block available: give up, fwd to
1039 tags
->insertBlock(pkt
, blk
);
1041 blk
->status
|= (BlkValid
| BlkReadable
);
1045 // at this point either this is a writeback or a write-through
1046 // write clean operation and the block is already in this
1047 // cache, we need to update the data and the block flags
1049 // TODO: the coherent cache can assert(!blk->isDirty());
1050 if (!pkt
->writeThrough()) {
1051 blk
->status
|= BlkDirty
;
1053 // nothing else to do; writeback doesn't expect response
1054 assert(!pkt
->needsResponse());
1055 pkt
->writeDataToBlock(blk
->data
, blkSize
);
1056 DPRINTF(Cache
, "%s new state is %s\n", __func__
, blk
->print());
1059 // populate the time when the block will be ready to access.
1060 blk
->whenReady
= clockEdge(fillLatency
) + pkt
->headerDelay
+
1062 // if this a write-through packet it will be sent to cache
1064 return !pkt
->writeThrough();
1065 } else if (blk
&& (pkt
->needsWritable() ? blk
->isWritable() :
1066 blk
->isReadable())) {
1067 // OK to satisfy access
1069 satisfyRequest(pkt
, blk
);
1070 maintainClusivity(pkt
->fromCache(), blk
);
1075 // Can't satisfy access normally... either no block (blk == nullptr)
1076 // or have block but need writable
1080 if (!blk
&& pkt
->isLLSC() && pkt
->isWrite()) {
1081 // complete miss on store conditional... just give up now
1082 pkt
->req
->setExtraData(0);
1090 BaseCache::maintainClusivity(bool from_cache
, CacheBlk
*blk
)
1092 if (from_cache
&& blk
&& blk
->isValid() && !blk
->isDirty() &&
1093 clusivity
== Enums::mostly_excl
) {
1094 // if we have responded to a cache, and our block is still
1095 // valid, but not dirty, and this cache is mostly exclusive
1096 // with respect to the cache above, drop the block
1097 invalidateBlock(blk
);
1102 BaseCache::handleFill(PacketPtr pkt
, CacheBlk
*blk
, PacketList
&writebacks
,
1105 assert(pkt
->isResponse() || pkt
->cmd
== MemCmd::WriteLineReq
);
1106 Addr addr
= pkt
->getAddr();
1107 bool is_secure
= pkt
->isSecure();
1109 CacheBlk::State old_state
= blk
? blk
->status
: 0;
1112 // When handling a fill, we should have no writes to this line.
1113 assert(addr
== pkt
->getBlockAddr(blkSize
));
1114 assert(!writeBuffer
.findMatch(addr
, is_secure
));
1117 // better have read new data...
1118 assert(pkt
->hasData());
1120 // only read responses and write-line requests have data;
1121 // note that we don't write the data here for write-line - that
1122 // happens in the subsequent call to satisfyRequest
1123 assert(pkt
->isRead() || pkt
->cmd
== MemCmd::WriteLineReq
);
1125 // need to do a replacement if allocating, otherwise we stick
1126 // with the temporary storage
1127 blk
= allocate
? allocateBlock(addr
, is_secure
, writebacks
) : nullptr;
1130 // No replaceable block or a mostly exclusive
1131 // cache... just use temporary storage to complete the
1132 // current request and then get rid of it
1133 assert(!tempBlock
->isValid());
1135 tempBlock
->insert(addr
, is_secure
);
1136 DPRINTF(Cache
, "using temp block for %#llx (%s)\n", addr
,
1137 is_secure
? "s" : "ns");
1139 tags
->insertBlock(pkt
, blk
);
1142 // we should never be overwriting a valid block
1143 assert(!blk
->isValid());
1145 // existing block... probably an upgrade
1146 assert(regenerateBlkAddr(blk
) == addr
);
1147 assert(blk
->isSecure() == is_secure
);
1148 // either we're getting new data or the block should already be valid
1149 assert(pkt
->hasData() || blk
->isValid());
1150 // don't clear block status... if block is already dirty we
1151 // don't want to lose that
1154 blk
->status
|= BlkValid
| BlkReadable
;
1156 // sanity check for whole-line writes, which should always be
1157 // marked as writable as part of the fill, and then later marked
1158 // dirty as part of satisfyRequest
1159 if (pkt
->cmd
== MemCmd::WriteLineReq
) {
1160 assert(!pkt
->hasSharers());
1163 // here we deal with setting the appropriate state of the line,
1164 // and we start by looking at the hasSharers flag, and ignore the
1165 // cacheResponding flag (normally signalling dirty data) if the
1166 // packet has sharers, thus the line is never allocated as Owned
1167 // (dirty but not writable), and always ends up being either
1168 // Shared, Exclusive or Modified, see Packet::setCacheResponding
1170 if (!pkt
->hasSharers()) {
1171 // we could get a writable line from memory (rather than a
1172 // cache) even in a read-only cache, note that we set this bit
1173 // even for a read-only cache, possibly revisit this decision
1174 blk
->status
|= BlkWritable
;
1176 // check if we got this via cache-to-cache transfer (i.e., from a
1177 // cache that had the block in Modified or Owned state)
1178 if (pkt
->cacheResponding()) {
1179 // we got the block in Modified state, and invalidated the
1181 blk
->status
|= BlkDirty
;
1183 chatty_assert(!isReadOnly
, "Should never see dirty snoop response "
1184 "in read-only cache %s\n", name());
1188 DPRINTF(Cache
, "Block addr %#llx (%s) moving from state %x to %s\n",
1189 addr
, is_secure
? "s" : "ns", old_state
, blk
->print());
1191 // if we got new data, copy it in (checking for a read response
1192 // and a response that has data is the same in the end)
1193 if (pkt
->isRead()) {
1195 assert(pkt
->hasData());
1196 assert(pkt
->getSize() == blkSize
);
1198 pkt
->writeDataToBlock(blk
->data
, blkSize
);
1200 // We pay for fillLatency here.
1201 blk
->whenReady
= clockEdge() + fillLatency
* clockPeriod() +
1208 BaseCache::allocateBlock(Addr addr
, bool is_secure
, PacketList
&writebacks
)
1210 // Find replacement victim
1211 std::vector
<CacheBlk
*> evict_blks
;
1212 CacheBlk
*victim
= tags
->findVictim(addr
, is_secure
, evict_blks
);
1214 // It is valid to return nullptr if there is no victim
1218 // Check for transient state allocations. If any of the entries listed
1219 // for eviction has a transient state, the allocation fails
1220 for (const auto& blk
: evict_blks
) {
1221 if (blk
->isValid()) {
1222 Addr repl_addr
= regenerateBlkAddr(blk
);
1223 MSHR
*repl_mshr
= mshrQueue
.findMatch(repl_addr
, blk
->isSecure());
1225 // must be an outstanding upgrade or clean request
1226 // on a block we're about to replace...
1227 assert((!blk
->isWritable() && repl_mshr
->needsWritable()) ||
1228 repl_mshr
->isCleaning());
1230 // too hard to replace block with transient state
1231 // allocation failed, block not inserted
1237 // The victim will be replaced by a new entry, so increase the replacement
1238 // counter if a valid block is being replaced
1239 if (victim
->isValid()) {
1240 DPRINTF(Cache
, "replacement: replacing %#llx (%s) with %#llx "
1241 "(%s): %s\n", regenerateBlkAddr(victim
),
1242 victim
->isSecure() ? "s" : "ns",
1243 addr
, is_secure
? "s" : "ns",
1244 victim
->isDirty() ? "writeback" : "clean");
1249 // Evict valid blocks associated to this victim block
1250 for (const auto& blk
: evict_blks
) {
1251 if (blk
->isValid()) {
1252 if (blk
->wasPrefetched()) {
1256 evictBlock(blk
, writebacks
);
1264 BaseCache::invalidateBlock(CacheBlk
*blk
)
1266 if (blk
!= tempBlock
)
1267 tags
->invalidate(blk
);
1272 BaseCache::writebackBlk(CacheBlk
*blk
)
1274 chatty_assert(!isReadOnly
|| writebackClean
,
1275 "Writeback from read-only cache");
1276 assert(blk
&& blk
->isValid() && (blk
->isDirty() || writebackClean
));
1278 writebacks
[Request::wbMasterId
]++;
1280 RequestPtr req
= std::make_shared
<Request
>(
1281 regenerateBlkAddr(blk
), blkSize
, 0, Request::wbMasterId
);
1283 if (blk
->isSecure())
1284 req
->setFlags(Request::SECURE
);
1286 req
->taskId(blk
->task_id
);
1289 new Packet(req
, blk
->isDirty() ?
1290 MemCmd::WritebackDirty
: MemCmd::WritebackClean
);
1292 DPRINTF(Cache
, "Create Writeback %s writable: %d, dirty: %d\n",
1293 pkt
->print(), blk
->isWritable(), blk
->isDirty());
1295 if (blk
->isWritable()) {
1296 // not asserting shared means we pass the block in modified
1297 // state, mark our own block non-writeable
1298 blk
->status
&= ~BlkWritable
;
1300 // we are in the Owned state, tell the receiver
1301 pkt
->setHasSharers();
1304 // make sure the block is not marked dirty
1305 blk
->status
&= ~BlkDirty
;
1308 pkt
->setDataFromBlock(blk
->data
, blkSize
);
1314 BaseCache::writecleanBlk(CacheBlk
*blk
, Request::Flags dest
, PacketId id
)
1316 RequestPtr req
= std::make_shared
<Request
>(
1317 regenerateBlkAddr(blk
), blkSize
, 0, Request::wbMasterId
);
1319 if (blk
->isSecure()) {
1320 req
->setFlags(Request::SECURE
);
1322 req
->taskId(blk
->task_id
);
1324 PacketPtr pkt
= new Packet(req
, MemCmd::WriteClean
, blkSize
, id
);
1327 req
->setFlags(dest
);
1328 pkt
->setWriteThrough();
1331 DPRINTF(Cache
, "Create %s writable: %d, dirty: %d\n", pkt
->print(),
1332 blk
->isWritable(), blk
->isDirty());
1334 if (blk
->isWritable()) {
1335 // not asserting shared means we pass the block in modified
1336 // state, mark our own block non-writeable
1337 blk
->status
&= ~BlkWritable
;
1339 // we are in the Owned state, tell the receiver
1340 pkt
->setHasSharers();
1343 // make sure the block is not marked dirty
1344 blk
->status
&= ~BlkDirty
;
1347 pkt
->setDataFromBlock(blk
->data
, blkSize
);
1354 BaseCache::memWriteback()
1356 tags
->forEachBlk([this](CacheBlk
&blk
) { writebackVisitor(blk
); });
1360 BaseCache::memInvalidate()
1362 tags
->forEachBlk([this](CacheBlk
&blk
) { invalidateVisitor(blk
); });
1366 BaseCache::isDirty() const
1368 return tags
->anyBlk([](CacheBlk
&blk
) { return blk
.isDirty(); });
1372 BaseCache::writebackVisitor(CacheBlk
&blk
)
1374 if (blk
.isDirty()) {
1375 assert(blk
.isValid());
1377 RequestPtr request
= std::make_shared
<Request
>(
1378 regenerateBlkAddr(&blk
), blkSize
, 0, Request::funcMasterId
);
1380 request
->taskId(blk
.task_id
);
1381 if (blk
.isSecure()) {
1382 request
->setFlags(Request::SECURE
);
1385 Packet
packet(request
, MemCmd::WriteReq
);
1386 packet
.dataStatic(blk
.data
);
1388 memSidePort
.sendFunctional(&packet
);
1390 blk
.status
&= ~BlkDirty
;
1395 BaseCache::invalidateVisitor(CacheBlk
&blk
)
1398 warn_once("Invalidating dirty cache lines. " \
1399 "Expect things to break.\n");
1401 if (blk
.isValid()) {
1402 assert(!blk
.isDirty());
1403 invalidateBlock(&blk
);
1408 BaseCache::nextQueueReadyTime() const
1410 Tick nextReady
= std::min(mshrQueue
.nextReadyTime(),
1411 writeBuffer
.nextReadyTime());
1413 // Don't signal prefetch ready time if no MSHRs available
1414 // Will signal once enoguh MSHRs are deallocated
1415 if (prefetcher
&& mshrQueue
.canPrefetch()) {
1416 nextReady
= std::min(nextReady
,
1417 prefetcher
->nextPrefetchReadyTime());
1425 BaseCache::sendMSHRQueuePacket(MSHR
* mshr
)
1429 // use request from 1st target
1430 PacketPtr tgt_pkt
= mshr
->getTarget()->pkt
;
1432 DPRINTF(Cache
, "%s: MSHR %s\n", __func__
, tgt_pkt
->print());
1434 CacheBlk
*blk
= tags
->findBlock(mshr
->blkAddr
, mshr
->isSecure
);
1436 // either a prefetch that is not present upstream, or a normal
1437 // MSHR request, proceed to get the packet to send downstream
1438 PacketPtr pkt
= createMissPacket(tgt_pkt
, blk
, mshr
->needsWritable());
1440 mshr
->isForward
= (pkt
== nullptr);
1442 if (mshr
->isForward
) {
1443 // not a cache block request, but a response is expected
1444 // make copy of current packet to forward, keep current
1445 // copy for response handling
1446 pkt
= new Packet(tgt_pkt
, false, true);
1447 assert(!pkt
->isWrite());
1450 // play it safe and append (rather than set) the sender state,
1451 // as forwarded packets may already have existing state
1452 pkt
->pushSenderState(mshr
);
1454 if (pkt
->isClean() && blk
&& blk
->isDirty()) {
1455 // A cache clean opearation is looking for a dirty block. Mark
1456 // the packet so that the destination xbar can determine that
1457 // there will be a follow-up write packet as well.
1458 pkt
->setSatisfied();
1461 if (!memSidePort
.sendTimingReq(pkt
)) {
1462 // we are awaiting a retry, but we
1463 // delete the packet and will be creating a new packet
1464 // when we get the opportunity
1467 // note that we have now masked any requestBus and
1468 // schedSendEvent (we will wait for a retry before
1469 // doing anything), and this is so even if we do not
1470 // care about this packet and might override it before
1474 // As part of the call to sendTimingReq the packet is
1475 // forwarded to all neighbouring caches (and any caches
1476 // above them) as a snoop. Thus at this point we know if
1477 // any of the neighbouring caches are responding, and if
1478 // so, we know it is dirty, and we can determine if it is
1479 // being passed as Modified, making our MSHR the ordering
1481 bool pending_modified_resp
= !pkt
->hasSharers() &&
1482 pkt
->cacheResponding();
1483 markInService(mshr
, pending_modified_resp
);
1485 if (pkt
->isClean() && blk
&& blk
->isDirty()) {
1486 // A cache clean opearation is looking for a dirty
1487 // block. If a dirty block is encountered a WriteClean
1488 // will update any copies to the path to the memory
1489 // until the point of reference.
1490 DPRINTF(CacheVerbose
, "%s: packet %s found block: %s\n",
1491 __func__
, pkt
->print(), blk
->print());
1492 PacketPtr wb_pkt
= writecleanBlk(blk
, pkt
->req
->getDest(),
1494 PacketList writebacks
;
1495 writebacks
.push_back(wb_pkt
);
1496 doWritebacks(writebacks
, 0);
1504 BaseCache::sendWriteQueuePacket(WriteQueueEntry
* wq_entry
)
1508 // always a single target for write queue entries
1509 PacketPtr tgt_pkt
= wq_entry
->getTarget()->pkt
;
1511 DPRINTF(Cache
, "%s: write %s\n", __func__
, tgt_pkt
->print());
1513 // forward as is, both for evictions and uncacheable writes
1514 if (!memSidePort
.sendTimingReq(tgt_pkt
)) {
1515 // note that we have now masked any requestBus and
1516 // schedSendEvent (we will wait for a retry before
1517 // doing anything), and this is so even if we do not
1518 // care about this packet and might override it before
1522 markInService(wq_entry
);
1528 BaseCache::serialize(CheckpointOut
&cp
) const
1530 bool dirty(isDirty());
1533 warn("*** The cache still contains dirty data. ***\n");
1534 warn(" Make sure to drain the system using the correct flags.\n");
1535 warn(" This checkpoint will not restore correctly " \
1536 "and dirty data in the cache will be lost!\n");
1539 // Since we don't checkpoint the data in the cache, any dirty data
1540 // will be lost when restoring from a checkpoint of a system that
1541 // wasn't drained properly. Flag the checkpoint as invalid if the
1542 // cache contains dirty data.
1543 bool bad_checkpoint(dirty
);
1544 SERIALIZE_SCALAR(bad_checkpoint
);
1548 BaseCache::unserialize(CheckpointIn
&cp
)
1550 bool bad_checkpoint
;
1551 UNSERIALIZE_SCALAR(bad_checkpoint
);
1552 if (bad_checkpoint
) {
1553 fatal("Restoring from checkpoints with dirty caches is not "
1554 "supported in the classic memory system. Please remove any "
1555 "caches or drain them properly before taking checkpoints.\n");
1560 BaseCache::regStats()
1562 MemObject::regStats();
1564 using namespace Stats
;
1567 for (int access_idx
= 0; access_idx
< MemCmd::NUM_MEM_CMDS
; ++access_idx
) {
1568 MemCmd
cmd(access_idx
);
1569 const string
&cstr
= cmd
.toString();
1572 .init(system
->maxMasters())
1573 .name(name() + "." + cstr
+ "_hits")
1574 .desc("number of " + cstr
+ " hits")
1575 .flags(total
| nozero
| nonan
)
1577 for (int i
= 0; i
< system
->maxMasters(); i
++) {
1578 hits
[access_idx
].subname(i
, system
->getMasterName(i
));
1582 // These macros make it easier to sum the right subset of commands and
1583 // to change the subset of commands that are considered "demand" vs
1585 #define SUM_DEMAND(s) \
1586 (s[MemCmd::ReadReq] + s[MemCmd::WriteReq] + s[MemCmd::WriteLineReq] + \
1587 s[MemCmd::ReadExReq] + s[MemCmd::ReadCleanReq] + s[MemCmd::ReadSharedReq])
1589 // should writebacks be included here? prior code was inconsistent...
1590 #define SUM_NON_DEMAND(s) \
1591 (s[MemCmd::SoftPFReq] + s[MemCmd::HardPFReq])
1594 .name(name() + ".demand_hits")
1595 .desc("number of demand (read+write) hits")
1596 .flags(total
| nozero
| nonan
)
1598 demandHits
= SUM_DEMAND(hits
);
1599 for (int i
= 0; i
< system
->maxMasters(); i
++) {
1600 demandHits
.subname(i
, system
->getMasterName(i
));
1604 .name(name() + ".overall_hits")
1605 .desc("number of overall hits")
1606 .flags(total
| nozero
| nonan
)
1608 overallHits
= demandHits
+ SUM_NON_DEMAND(hits
);
1609 for (int i
= 0; i
< system
->maxMasters(); i
++) {
1610 overallHits
.subname(i
, system
->getMasterName(i
));
1614 for (int access_idx
= 0; access_idx
< MemCmd::NUM_MEM_CMDS
; ++access_idx
) {
1615 MemCmd
cmd(access_idx
);
1616 const string
&cstr
= cmd
.toString();
1619 .init(system
->maxMasters())
1620 .name(name() + "." + cstr
+ "_misses")
1621 .desc("number of " + cstr
+ " misses")
1622 .flags(total
| nozero
| nonan
)
1624 for (int i
= 0; i
< system
->maxMasters(); i
++) {
1625 misses
[access_idx
].subname(i
, system
->getMasterName(i
));
1630 .name(name() + ".demand_misses")
1631 .desc("number of demand (read+write) misses")
1632 .flags(total
| nozero
| nonan
)
1634 demandMisses
= SUM_DEMAND(misses
);
1635 for (int i
= 0; i
< system
->maxMasters(); i
++) {
1636 demandMisses
.subname(i
, system
->getMasterName(i
));
1640 .name(name() + ".overall_misses")
1641 .desc("number of overall misses")
1642 .flags(total
| nozero
| nonan
)
1644 overallMisses
= demandMisses
+ SUM_NON_DEMAND(misses
);
1645 for (int i
= 0; i
< system
->maxMasters(); i
++) {
1646 overallMisses
.subname(i
, system
->getMasterName(i
));
1649 // Miss latency statistics
1650 for (int access_idx
= 0; access_idx
< MemCmd::NUM_MEM_CMDS
; ++access_idx
) {
1651 MemCmd
cmd(access_idx
);
1652 const string
&cstr
= cmd
.toString();
1654 missLatency
[access_idx
]
1655 .init(system
->maxMasters())
1656 .name(name() + "." + cstr
+ "_miss_latency")
1657 .desc("number of " + cstr
+ " miss cycles")
1658 .flags(total
| nozero
| nonan
)
1660 for (int i
= 0; i
< system
->maxMasters(); i
++) {
1661 missLatency
[access_idx
].subname(i
, system
->getMasterName(i
));
1666 .name(name() + ".demand_miss_latency")
1667 .desc("number of demand (read+write) miss cycles")
1668 .flags(total
| nozero
| nonan
)
1670 demandMissLatency
= SUM_DEMAND(missLatency
);
1671 for (int i
= 0; i
< system
->maxMasters(); i
++) {
1672 demandMissLatency
.subname(i
, system
->getMasterName(i
));
1676 .name(name() + ".overall_miss_latency")
1677 .desc("number of overall miss cycles")
1678 .flags(total
| nozero
| nonan
)
1680 overallMissLatency
= demandMissLatency
+ SUM_NON_DEMAND(missLatency
);
1681 for (int i
= 0; i
< system
->maxMasters(); i
++) {
1682 overallMissLatency
.subname(i
, system
->getMasterName(i
));
1686 for (int access_idx
= 0; access_idx
< MemCmd::NUM_MEM_CMDS
; ++access_idx
) {
1687 MemCmd
cmd(access_idx
);
1688 const string
&cstr
= cmd
.toString();
1690 accesses
[access_idx
]
1691 .name(name() + "." + cstr
+ "_accesses")
1692 .desc("number of " + cstr
+ " accesses(hits+misses)")
1693 .flags(total
| nozero
| nonan
)
1695 accesses
[access_idx
] = hits
[access_idx
] + misses
[access_idx
];
1697 for (int i
= 0; i
< system
->maxMasters(); i
++) {
1698 accesses
[access_idx
].subname(i
, system
->getMasterName(i
));
1703 .name(name() + ".demand_accesses")
1704 .desc("number of demand (read+write) accesses")
1705 .flags(total
| nozero
| nonan
)
1707 demandAccesses
= demandHits
+ demandMisses
;
1708 for (int i
= 0; i
< system
->maxMasters(); i
++) {
1709 demandAccesses
.subname(i
, system
->getMasterName(i
));
1713 .name(name() + ".overall_accesses")
1714 .desc("number of overall (read+write) accesses")
1715 .flags(total
| nozero
| nonan
)
1717 overallAccesses
= overallHits
+ overallMisses
;
1718 for (int i
= 0; i
< system
->maxMasters(); i
++) {
1719 overallAccesses
.subname(i
, system
->getMasterName(i
));
1722 // miss rate formulas
1723 for (int access_idx
= 0; access_idx
< MemCmd::NUM_MEM_CMDS
; ++access_idx
) {
1724 MemCmd
cmd(access_idx
);
1725 const string
&cstr
= cmd
.toString();
1727 missRate
[access_idx
]
1728 .name(name() + "." + cstr
+ "_miss_rate")
1729 .desc("miss rate for " + cstr
+ " accesses")
1730 .flags(total
| nozero
| nonan
)
1732 missRate
[access_idx
] = misses
[access_idx
] / accesses
[access_idx
];
1734 for (int i
= 0; i
< system
->maxMasters(); i
++) {
1735 missRate
[access_idx
].subname(i
, system
->getMasterName(i
));
1740 .name(name() + ".demand_miss_rate")
1741 .desc("miss rate for demand accesses")
1742 .flags(total
| nozero
| nonan
)
1744 demandMissRate
= demandMisses
/ demandAccesses
;
1745 for (int i
= 0; i
< system
->maxMasters(); i
++) {
1746 demandMissRate
.subname(i
, system
->getMasterName(i
));
1750 .name(name() + ".overall_miss_rate")
1751 .desc("miss rate for overall accesses")
1752 .flags(total
| nozero
| nonan
)
1754 overallMissRate
= overallMisses
/ overallAccesses
;
1755 for (int i
= 0; i
< system
->maxMasters(); i
++) {
1756 overallMissRate
.subname(i
, system
->getMasterName(i
));
1759 // miss latency formulas
1760 for (int access_idx
= 0; access_idx
< MemCmd::NUM_MEM_CMDS
; ++access_idx
) {
1761 MemCmd
cmd(access_idx
);
1762 const string
&cstr
= cmd
.toString();
1764 avgMissLatency
[access_idx
]
1765 .name(name() + "." + cstr
+ "_avg_miss_latency")
1766 .desc("average " + cstr
+ " miss latency")
1767 .flags(total
| nozero
| nonan
)
1769 avgMissLatency
[access_idx
] =
1770 missLatency
[access_idx
] / misses
[access_idx
];
1772 for (int i
= 0; i
< system
->maxMasters(); i
++) {
1773 avgMissLatency
[access_idx
].subname(i
, system
->getMasterName(i
));
1777 demandAvgMissLatency
1778 .name(name() + ".demand_avg_miss_latency")
1779 .desc("average overall miss latency")
1780 .flags(total
| nozero
| nonan
)
1782 demandAvgMissLatency
= demandMissLatency
/ demandMisses
;
1783 for (int i
= 0; i
< system
->maxMasters(); i
++) {
1784 demandAvgMissLatency
.subname(i
, system
->getMasterName(i
));
1787 overallAvgMissLatency
1788 .name(name() + ".overall_avg_miss_latency")
1789 .desc("average overall miss latency")
1790 .flags(total
| nozero
| nonan
)
1792 overallAvgMissLatency
= overallMissLatency
/ overallMisses
;
1793 for (int i
= 0; i
< system
->maxMasters(); i
++) {
1794 overallAvgMissLatency
.subname(i
, system
->getMasterName(i
));
1797 blocked_cycles
.init(NUM_BLOCKED_CAUSES
);
1799 .name(name() + ".blocked_cycles")
1800 .desc("number of cycles access was blocked")
1801 .subname(Blocked_NoMSHRs
, "no_mshrs")
1802 .subname(Blocked_NoTargets
, "no_targets")
1806 blocked_causes
.init(NUM_BLOCKED_CAUSES
);
1808 .name(name() + ".blocked")
1809 .desc("number of cycles access was blocked")
1810 .subname(Blocked_NoMSHRs
, "no_mshrs")
1811 .subname(Blocked_NoTargets
, "no_targets")
1815 .name(name() + ".avg_blocked_cycles")
1816 .desc("average number of cycles each access was blocked")
1817 .subname(Blocked_NoMSHRs
, "no_mshrs")
1818 .subname(Blocked_NoTargets
, "no_targets")
1821 avg_blocked
= blocked_cycles
/ blocked_causes
;
1824 .name(name() + ".unused_prefetches")
1825 .desc("number of HardPF blocks evicted w/o reference")
1830 .init(system
->maxMasters())
1831 .name(name() + ".writebacks")
1832 .desc("number of writebacks")
1833 .flags(total
| nozero
| nonan
)
1835 for (int i
= 0; i
< system
->maxMasters(); i
++) {
1836 writebacks
.subname(i
, system
->getMasterName(i
));
1840 // MSHR hit statistics
1841 for (int access_idx
= 0; access_idx
< MemCmd::NUM_MEM_CMDS
; ++access_idx
) {
1842 MemCmd
cmd(access_idx
);
1843 const string
&cstr
= cmd
.toString();
1845 mshr_hits
[access_idx
]
1846 .init(system
->maxMasters())
1847 .name(name() + "." + cstr
+ "_mshr_hits")
1848 .desc("number of " + cstr
+ " MSHR hits")
1849 .flags(total
| nozero
| nonan
)
1851 for (int i
= 0; i
< system
->maxMasters(); i
++) {
1852 mshr_hits
[access_idx
].subname(i
, system
->getMasterName(i
));
1857 .name(name() + ".demand_mshr_hits")
1858 .desc("number of demand (read+write) MSHR hits")
1859 .flags(total
| nozero
| nonan
)
1861 demandMshrHits
= SUM_DEMAND(mshr_hits
);
1862 for (int i
= 0; i
< system
->maxMasters(); i
++) {
1863 demandMshrHits
.subname(i
, system
->getMasterName(i
));
1867 .name(name() + ".overall_mshr_hits")
1868 .desc("number of overall MSHR hits")
1869 .flags(total
| nozero
| nonan
)
1871 overallMshrHits
= demandMshrHits
+ SUM_NON_DEMAND(mshr_hits
);
1872 for (int i
= 0; i
< system
->maxMasters(); i
++) {
1873 overallMshrHits
.subname(i
, system
->getMasterName(i
));
1876 // MSHR miss statistics
1877 for (int access_idx
= 0; access_idx
< MemCmd::NUM_MEM_CMDS
; ++access_idx
) {
1878 MemCmd
cmd(access_idx
);
1879 const string
&cstr
= cmd
.toString();
1881 mshr_misses
[access_idx
]
1882 .init(system
->maxMasters())
1883 .name(name() + "." + cstr
+ "_mshr_misses")
1884 .desc("number of " + cstr
+ " MSHR misses")
1885 .flags(total
| nozero
| nonan
)
1887 for (int i
= 0; i
< system
->maxMasters(); i
++) {
1888 mshr_misses
[access_idx
].subname(i
, system
->getMasterName(i
));
1893 .name(name() + ".demand_mshr_misses")
1894 .desc("number of demand (read+write) MSHR misses")
1895 .flags(total
| nozero
| nonan
)
1897 demandMshrMisses
= SUM_DEMAND(mshr_misses
);
1898 for (int i
= 0; i
< system
->maxMasters(); i
++) {
1899 demandMshrMisses
.subname(i
, system
->getMasterName(i
));
1903 .name(name() + ".overall_mshr_misses")
1904 .desc("number of overall MSHR misses")
1905 .flags(total
| nozero
| nonan
)
1907 overallMshrMisses
= demandMshrMisses
+ SUM_NON_DEMAND(mshr_misses
);
1908 for (int i
= 0; i
< system
->maxMasters(); i
++) {
1909 overallMshrMisses
.subname(i
, system
->getMasterName(i
));
1912 // MSHR miss latency statistics
1913 for (int access_idx
= 0; access_idx
< MemCmd::NUM_MEM_CMDS
; ++access_idx
) {
1914 MemCmd
cmd(access_idx
);
1915 const string
&cstr
= cmd
.toString();
1917 mshr_miss_latency
[access_idx
]
1918 .init(system
->maxMasters())
1919 .name(name() + "." + cstr
+ "_mshr_miss_latency")
1920 .desc("number of " + cstr
+ " MSHR miss cycles")
1921 .flags(total
| nozero
| nonan
)
1923 for (int i
= 0; i
< system
->maxMasters(); i
++) {
1924 mshr_miss_latency
[access_idx
].subname(i
, system
->getMasterName(i
));
1928 demandMshrMissLatency
1929 .name(name() + ".demand_mshr_miss_latency")
1930 .desc("number of demand (read+write) MSHR miss cycles")
1931 .flags(total
| nozero
| nonan
)
1933 demandMshrMissLatency
= SUM_DEMAND(mshr_miss_latency
);
1934 for (int i
= 0; i
< system
->maxMasters(); i
++) {
1935 demandMshrMissLatency
.subname(i
, system
->getMasterName(i
));
1938 overallMshrMissLatency
1939 .name(name() + ".overall_mshr_miss_latency")
1940 .desc("number of overall MSHR miss cycles")
1941 .flags(total
| nozero
| nonan
)
1943 overallMshrMissLatency
=
1944 demandMshrMissLatency
+ SUM_NON_DEMAND(mshr_miss_latency
);
1945 for (int i
= 0; i
< system
->maxMasters(); i
++) {
1946 overallMshrMissLatency
.subname(i
, system
->getMasterName(i
));
1949 // MSHR uncacheable statistics
1950 for (int access_idx
= 0; access_idx
< MemCmd::NUM_MEM_CMDS
; ++access_idx
) {
1951 MemCmd
cmd(access_idx
);
1952 const string
&cstr
= cmd
.toString();
1954 mshr_uncacheable
[access_idx
]
1955 .init(system
->maxMasters())
1956 .name(name() + "." + cstr
+ "_mshr_uncacheable")
1957 .desc("number of " + cstr
+ " MSHR uncacheable")
1958 .flags(total
| nozero
| nonan
)
1960 for (int i
= 0; i
< system
->maxMasters(); i
++) {
1961 mshr_uncacheable
[access_idx
].subname(i
, system
->getMasterName(i
));
1965 overallMshrUncacheable
1966 .name(name() + ".overall_mshr_uncacheable_misses")
1967 .desc("number of overall MSHR uncacheable misses")
1968 .flags(total
| nozero
| nonan
)
1970 overallMshrUncacheable
=
1971 SUM_DEMAND(mshr_uncacheable
) + SUM_NON_DEMAND(mshr_uncacheable
);
1972 for (int i
= 0; i
< system
->maxMasters(); i
++) {
1973 overallMshrUncacheable
.subname(i
, system
->getMasterName(i
));
1976 // MSHR miss latency statistics
1977 for (int access_idx
= 0; access_idx
< MemCmd::NUM_MEM_CMDS
; ++access_idx
) {
1978 MemCmd
cmd(access_idx
);
1979 const string
&cstr
= cmd
.toString();
1981 mshr_uncacheable_lat
[access_idx
]
1982 .init(system
->maxMasters())
1983 .name(name() + "." + cstr
+ "_mshr_uncacheable_latency")
1984 .desc("number of " + cstr
+ " MSHR uncacheable cycles")
1985 .flags(total
| nozero
| nonan
)
1987 for (int i
= 0; i
< system
->maxMasters(); i
++) {
1988 mshr_uncacheable_lat
[access_idx
].subname(
1989 i
, system
->getMasterName(i
));
1993 overallMshrUncacheableLatency
1994 .name(name() + ".overall_mshr_uncacheable_latency")
1995 .desc("number of overall MSHR uncacheable cycles")
1996 .flags(total
| nozero
| nonan
)
1998 overallMshrUncacheableLatency
=
1999 SUM_DEMAND(mshr_uncacheable_lat
) +
2000 SUM_NON_DEMAND(mshr_uncacheable_lat
);
2001 for (int i
= 0; i
< system
->maxMasters(); i
++) {
2002 overallMshrUncacheableLatency
.subname(i
, system
->getMasterName(i
));
2006 // MSHR access formulas
2007 for (int access_idx
= 0; access_idx
< MemCmd::NUM_MEM_CMDS
; ++access_idx
) {
2008 MemCmd
cmd(access_idx
);
2009 const string
&cstr
= cmd
.toString();
2011 mshrAccesses
[access_idx
]
2012 .name(name() + "." + cstr
+ "_mshr_accesses")
2013 .desc("number of " + cstr
+ " mshr accesses(hits+misses)")
2014 .flags(total
| nozero
| nonan
)
2016 mshrAccesses
[access_idx
] =
2017 mshr_hits
[access_idx
] + mshr_misses
[access_idx
]
2018 + mshr_uncacheable
[access_idx
];
2022 .name(name() + ".demand_mshr_accesses")
2023 .desc("number of demand (read+write) mshr accesses")
2024 .flags(total
| nozero
| nonan
)
2026 demandMshrAccesses
= demandMshrHits
+ demandMshrMisses
;
2029 .name(name() + ".overall_mshr_accesses")
2030 .desc("number of overall (read+write) mshr accesses")
2031 .flags(total
| nozero
| nonan
)
2033 overallMshrAccesses
= overallMshrHits
+ overallMshrMisses
2034 + overallMshrUncacheable
;
2037 // MSHR miss rate formulas
2038 for (int access_idx
= 0; access_idx
< MemCmd::NUM_MEM_CMDS
; ++access_idx
) {
2039 MemCmd
cmd(access_idx
);
2040 const string
&cstr
= cmd
.toString();
2042 mshrMissRate
[access_idx
]
2043 .name(name() + "." + cstr
+ "_mshr_miss_rate")
2044 .desc("mshr miss rate for " + cstr
+ " accesses")
2045 .flags(total
| nozero
| nonan
)
2047 mshrMissRate
[access_idx
] =
2048 mshr_misses
[access_idx
] / accesses
[access_idx
];
2050 for (int i
= 0; i
< system
->maxMasters(); i
++) {
2051 mshrMissRate
[access_idx
].subname(i
, system
->getMasterName(i
));
2056 .name(name() + ".demand_mshr_miss_rate")
2057 .desc("mshr miss rate for demand accesses")
2058 .flags(total
| nozero
| nonan
)
2060 demandMshrMissRate
= demandMshrMisses
/ demandAccesses
;
2061 for (int i
= 0; i
< system
->maxMasters(); i
++) {
2062 demandMshrMissRate
.subname(i
, system
->getMasterName(i
));
2066 .name(name() + ".overall_mshr_miss_rate")
2067 .desc("mshr miss rate for overall accesses")
2068 .flags(total
| nozero
| nonan
)
2070 overallMshrMissRate
= overallMshrMisses
/ overallAccesses
;
2071 for (int i
= 0; i
< system
->maxMasters(); i
++) {
2072 overallMshrMissRate
.subname(i
, system
->getMasterName(i
));
2075 // mshrMiss latency formulas
2076 for (int access_idx
= 0; access_idx
< MemCmd::NUM_MEM_CMDS
; ++access_idx
) {
2077 MemCmd
cmd(access_idx
);
2078 const string
&cstr
= cmd
.toString();
2080 avgMshrMissLatency
[access_idx
]
2081 .name(name() + "." + cstr
+ "_avg_mshr_miss_latency")
2082 .desc("average " + cstr
+ " mshr miss latency")
2083 .flags(total
| nozero
| nonan
)
2085 avgMshrMissLatency
[access_idx
] =
2086 mshr_miss_latency
[access_idx
] / mshr_misses
[access_idx
];
2088 for (int i
= 0; i
< system
->maxMasters(); i
++) {
2089 avgMshrMissLatency
[access_idx
].subname(
2090 i
, system
->getMasterName(i
));
2094 demandAvgMshrMissLatency
2095 .name(name() + ".demand_avg_mshr_miss_latency")
2096 .desc("average overall mshr miss latency")
2097 .flags(total
| nozero
| nonan
)
2099 demandAvgMshrMissLatency
= demandMshrMissLatency
/ demandMshrMisses
;
2100 for (int i
= 0; i
< system
->maxMasters(); i
++) {
2101 demandAvgMshrMissLatency
.subname(i
, system
->getMasterName(i
));
2104 overallAvgMshrMissLatency
2105 .name(name() + ".overall_avg_mshr_miss_latency")
2106 .desc("average overall mshr miss latency")
2107 .flags(total
| nozero
| nonan
)
2109 overallAvgMshrMissLatency
= overallMshrMissLatency
/ overallMshrMisses
;
2110 for (int i
= 0; i
< system
->maxMasters(); i
++) {
2111 overallAvgMshrMissLatency
.subname(i
, system
->getMasterName(i
));
2114 // mshrUncacheable latency formulas
2115 for (int access_idx
= 0; access_idx
< MemCmd::NUM_MEM_CMDS
; ++access_idx
) {
2116 MemCmd
cmd(access_idx
);
2117 const string
&cstr
= cmd
.toString();
2119 avgMshrUncacheableLatency
[access_idx
]
2120 .name(name() + "." + cstr
+ "_avg_mshr_uncacheable_latency")
2121 .desc("average " + cstr
+ " mshr uncacheable latency")
2122 .flags(total
| nozero
| nonan
)
2124 avgMshrUncacheableLatency
[access_idx
] =
2125 mshr_uncacheable_lat
[access_idx
] / mshr_uncacheable
[access_idx
];
2127 for (int i
= 0; i
< system
->maxMasters(); i
++) {
2128 avgMshrUncacheableLatency
[access_idx
].subname(
2129 i
, system
->getMasterName(i
));
2133 overallAvgMshrUncacheableLatency
2134 .name(name() + ".overall_avg_mshr_uncacheable_latency")
2135 .desc("average overall mshr uncacheable latency")
2136 .flags(total
| nozero
| nonan
)
2138 overallAvgMshrUncacheableLatency
=
2139 overallMshrUncacheableLatency
/ overallMshrUncacheable
;
2140 for (int i
= 0; i
< system
->maxMasters(); i
++) {
2141 overallAvgMshrUncacheableLatency
.subname(i
, system
->getMasterName(i
));
2145 .name(name() + ".replacements")
2146 .desc("number of replacements")
2156 BaseCache::CpuSidePort::recvTimingSnoopResp(PacketPtr pkt
)
2158 // Snoops shouldn't happen when bypassing caches
2159 assert(!cache
->system
->bypassCaches());
2161 assert(pkt
->isResponse());
2163 // Express snoop responses from master to slave, e.g., from L1 to L2
2164 cache
->recvTimingSnoopResp(pkt
);
2170 BaseCache::CpuSidePort::tryTiming(PacketPtr pkt
)
2172 if (cache
->system
->bypassCaches() || pkt
->isExpressSnoop()) {
2173 // always let express snoop packets through even if blocked
2175 } else if (blocked
|| mustSendRetry
) {
2176 // either already committed to send a retry, or blocked
2177 mustSendRetry
= true;
2180 mustSendRetry
= false;
2185 BaseCache::CpuSidePort::recvTimingReq(PacketPtr pkt
)
2187 assert(pkt
->isRequest());
2189 if (cache
->system
->bypassCaches()) {
2190 // Just forward the packet if caches are disabled.
2191 // @todo This should really enqueue the packet rather
2192 bool M5_VAR_USED success
= cache
->memSidePort
.sendTimingReq(pkt
);
2195 } else if (tryTiming(pkt
)) {
2196 cache
->recvTimingReq(pkt
);
2203 BaseCache::CpuSidePort::recvAtomic(PacketPtr pkt
)
2205 if (cache
->system
->bypassCaches()) {
2206 // Forward the request if the system is in cache bypass mode.
2207 return cache
->memSidePort
.sendAtomic(pkt
);
2209 return cache
->recvAtomic(pkt
);
2214 BaseCache::CpuSidePort::recvFunctional(PacketPtr pkt
)
2216 if (cache
->system
->bypassCaches()) {
2217 // The cache should be flushed if we are in cache bypass mode,
2218 // so we don't need to check if we need to update anything.
2219 cache
->memSidePort
.sendFunctional(pkt
);
2223 // functional request
2224 cache
->functionalAccess(pkt
, true);
2228 BaseCache::CpuSidePort::getAddrRanges() const
2230 return cache
->getAddrRanges();
2235 CpuSidePort::CpuSidePort(const std::string
&_name
, BaseCache
*_cache
,
2236 const std::string
&_label
)
2237 : CacheSlavePort(_name
, _cache
, _label
), cache(_cache
)
2247 BaseCache::MemSidePort::recvTimingResp(PacketPtr pkt
)
2249 cache
->recvTimingResp(pkt
);
2253 // Express snooping requests to memside port
2255 BaseCache::MemSidePort::recvTimingSnoopReq(PacketPtr pkt
)
2257 // Snoops shouldn't happen when bypassing caches
2258 assert(!cache
->system
->bypassCaches());
2260 // handle snooping requests
2261 cache
->recvTimingSnoopReq(pkt
);
2265 BaseCache::MemSidePort::recvAtomicSnoop(PacketPtr pkt
)
2267 // Snoops shouldn't happen when bypassing caches
2268 assert(!cache
->system
->bypassCaches());
2270 return cache
->recvAtomicSnoop(pkt
);
2274 BaseCache::MemSidePort::recvFunctionalSnoop(PacketPtr pkt
)
2276 // Snoops shouldn't happen when bypassing caches
2277 assert(!cache
->system
->bypassCaches());
2279 // functional snoop (note that in contrast to atomic we don't have
2280 // a specific functionalSnoop method, as they have the same
2281 // behaviour regardless)
2282 cache
->functionalAccess(pkt
, false);
2286 BaseCache::CacheReqPacketQueue::sendDeferredPacket()
2289 assert(!waitingOnRetry
);
2291 // there should never be any deferred request packets in the
2292 // queue, instead we resly on the cache to provide the packets
2293 // from the MSHR queue or write queue
2294 assert(deferredPacketReadyTime() == MaxTick
);
2296 // check for request packets (requests & writebacks)
2297 QueueEntry
* entry
= cache
.getNextQueueEntry();
2300 // can happen if e.g. we attempt a writeback and fail, but
2301 // before the retry, the writeback is eliminated because
2302 // we snoop another cache's ReadEx.
2304 // let our snoop responses go first if there are responses to
2305 // the same addresses
2306 if (checkConflictingSnoop(entry
->blkAddr
)) {
2309 waitingOnRetry
= entry
->sendPacket(cache
);
2312 // if we succeeded and are not waiting for a retry, schedule the
2313 // next send considering when the next queue is ready, note that
2314 // snoop responses have their own packet queue and thus schedule
2316 if (!waitingOnRetry
) {
2317 schedSendEvent(cache
.nextQueueReadyTime());
2321 BaseCache::MemSidePort::MemSidePort(const std::string
&_name
,
2323 const std::string
&_label
)
2324 : CacheMasterPort(_name
, _cache
, _reqQueue
, _snoopRespQueue
),
2325 _reqQueue(*_cache
, *this, _snoopRespQueue
, _label
),
2326 _snoopRespQueue(*_cache
, *this, _label
), cache(_cache
)