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41 * Authors: Ron Dreslinski
48 * Declaration of a request, the overall memory request consisting of
49 the parts of the request that are persistent throughout the transaction.
52 #ifndef __MEM_REQUEST_HH__
53 #define __MEM_REQUEST_HH__
58 #include "base/flags.hh"
59 #include "base/logging.hh"
60 #include "base/types.hh"
61 #include "cpu/inst_seq.hh"
62 #include "sim/core.hh"
65 * Special TaskIds that are used for per-context-switch stats dumps
66 * and Cache Occupancy. Having too many tasks seems to be a problem
67 * with vector stats. 1024 seems to be a reasonable number that
68 * doesn't cause a problem with stats and is large enough to realistic
69 * benchmarks (Linux/Android boot, BBench, etc.)
72 namespace ContextSwitchTaskId {
74 MaxNormalTaskId = 1021, /* Maximum number of normal tasks */
75 Prefetcher = 1022, /* For cache lines brought in by prefetcher */
76 DMA = 1023, /* Mostly Table Walker */
84 typedef std::shared_ptr<Request> RequestPtr;
85 typedef uint16_t MasterID;
90 typedef uint64_t FlagsType;
91 typedef uint8_t ArchFlagsType;
92 typedef ::Flags<FlagsType> Flags;
96 * Architecture specific flags.
98 * These bits int the flag field are reserved for
99 * architecture-specific code. For example, SPARC uses them to
102 ARCH_BITS = 0x000000FF,
103 /** The request was an instruction fetch. */
104 INST_FETCH = 0x00000100,
105 /** The virtual address is also the physical address. */
106 PHYSICAL = 0x00000200,
108 * The request is to an uncacheable address.
110 * @note Uncacheable accesses may be reordered by CPU models. The
111 * STRICT_ORDER flag should be set if such reordering is
114 UNCACHEABLE = 0x00000400,
116 * The request is required to be strictly ordered by <i>CPU
117 * models</i> and is non-speculative.
119 * A strictly ordered request is guaranteed to never be
120 * re-ordered or executed speculatively by a CPU model. The
121 * memory system may still reorder requests in caches unless
122 * the UNCACHEABLE flag is set as well.
124 STRICT_ORDER = 0x00000800,
125 /** This request is to a memory mapped register. */
126 MMAPPED_IPR = 0x00002000,
127 /** This request is made in privileged mode. */
128 PRIVILEGED = 0x00008000,
131 * This is a write that is targeted and zeroing an entire
132 * cache block. There is no need for a read/modify/write
134 CACHE_BLOCK_ZERO = 0x00010000,
136 /** The request should not cause a memory access. */
137 NO_ACCESS = 0x00080000,
139 * This request will lock or unlock the accessed memory. When
140 * used with a load, the access locks the particular chunk of
141 * memory. When used with a store, it unlocks. The rule is
142 * that locked accesses have to be made up of a locked load,
143 * some operation on the data, and then a locked store.
145 LOCKED_RMW = 0x00100000,
146 /** The request is a Load locked/store conditional. */
148 /** This request is for a memory swap. */
149 MEM_SWAP = 0x00400000,
150 MEM_SWAP_COND = 0x00800000,
152 /** The request is a prefetch. */
153 PREFETCH = 0x01000000,
154 /** The request should be prefetched into the exclusive state. */
155 PF_EXCLUSIVE = 0x02000000,
156 /** The request should be marked as LRU. */
157 EVICT_NEXT = 0x04000000,
158 /** The request should be marked with ACQUIRE. */
159 ACQUIRE = 0x00020000,
160 /** The request should be marked with RELEASE. */
161 RELEASE = 0x00040000,
163 /** The request is an atomic that returns data. */
164 ATOMIC_RETURN_OP = 0x40000000,
165 /** The request is an atomic that does not return data. */
166 ATOMIC_NO_RETURN_OP = 0x80000000,
168 /** The request should be marked with KERNEL.
169 * Used to indicate the synchronization associated with a GPU kernel
170 * launch or completion.
175 * The request should be handled by the generic IPR code (only
176 * valid together with MMAPPED_IPR)
178 GENERIC_IPR = 0x08000000,
180 /** The request targets the secure memory space. */
182 /** The request is a page table walk */
183 PT_WALK = 0x20000000,
185 /** The request invalidates a memory location */
186 INVALIDATE = 0x0000000100000000,
187 /** The request cleans a memory location */
188 CLEAN = 0x0000000200000000,
190 /** The request targets the point of unification */
191 DST_POU = 0x0000001000000000,
193 /** The request targets the point of coherence */
194 DST_POC = 0x0000002000000000,
196 /** Bits to define the destination of a request */
197 DST_BITS = 0x0000003000000000,
200 * These flags are *not* cleared when a Request object is
201 * reused (assigned a new address).
203 STICKY_FLAGS = INST_FETCH
205 static const FlagsType STORE_NO_DATA = CACHE_BLOCK_ZERO |
208 /** Master Ids that are statically allocated
211 /** This master id is used for writeback requests by the caches */
214 * This master id is used for functional requests that
215 * don't come from a particular device
218 /** This master id is used for message signaled interrupts */
221 * Invalid master id for assertion checking only. It is
222 * invalid behavior to ever send this id as part of a request.
224 invldMasterId = std::numeric_limits<MasterID>::max()
228 typedef uint32_t MemSpaceConfigFlagsType;
229 typedef ::Flags<MemSpaceConfigFlagsType> MemSpaceConfigFlags;
231 enum : MemSpaceConfigFlagsType {
232 /** Has a synchronization scope been set? */
233 SCOPE_VALID = 0x00000001,
234 /** Access has Wavefront scope visibility */
235 WAVEFRONT_SCOPE = 0x00000002,
236 /** Access has Workgroup scope visibility */
237 WORKGROUP_SCOPE = 0x00000004,
238 /** Access has Device (e.g., GPU) scope visibility */
239 DEVICE_SCOPE = 0x00000008,
240 /** Access has System (e.g., CPU + GPU) scope visibility */
241 SYSTEM_SCOPE = 0x00000010,
243 /** Global Segment */
244 GLOBAL_SEGMENT = 0x00000020,
246 GROUP_SEGMENT = 0x00000040,
247 /** Private Segment */
248 PRIVATE_SEGMENT = 0x00000080,
249 /** Kergarg Segment */
250 KERNARG_SEGMENT = 0x00000100,
251 /** Readonly Segment */
252 READONLY_SEGMENT = 0x00000200,
254 SPILL_SEGMENT = 0x00000400,
256 ARG_SEGMENT = 0x00000800,
260 typedef uint8_t PrivateFlagsType;
261 typedef ::Flags<PrivateFlagsType> PrivateFlags;
263 enum : PrivateFlagsType {
264 /** Whether or not the size is valid. */
265 VALID_SIZE = 0x00000001,
266 /** Whether or not paddr is valid (has been written yet). */
267 VALID_PADDR = 0x00000002,
268 /** Whether or not the vaddr & asid are valid. */
269 VALID_VADDR = 0x00000004,
270 /** Whether or not the instruction sequence number is valid. */
271 VALID_INST_SEQ_NUM = 0x00000008,
272 /** Whether or not the pc is valid. */
273 VALID_PC = 0x00000010,
274 /** Whether or not the context ID is valid. */
275 VALID_CONTEXT_ID = 0x00000020,
276 /** Whether or not the sc result is valid. */
277 VALID_EXTRA_DATA = 0x00000080,
279 * These flags are *not* cleared when a Request object is reused
280 * (assigned a new address).
282 STICKY_PRIVATE_FLAGS = VALID_CONTEXT_ID
288 * Set up a physical (e.g. device) request in a previously
289 * allocated Request object.
292 setPhys(Addr paddr, unsigned size, Flags flags, MasterID mid, Tick time)
298 _flags.clear(~STICKY_FLAGS);
300 privateFlags.clear(~STICKY_PRIVATE_FLAGS);
301 privateFlags.set(VALID_PADDR|VALID_SIZE);
304 //translateDelta = 0;
308 * The physical address of the request. Valid only if validPaddr
314 * The size of the request. This field must be set when vaddr or
315 * paddr is written via setVirt() or setPhys(), so it is always
316 * valid as long as one of the address fields is valid.
320 /** The requestor ID which is unique in the system for all ports
321 * that are capable of issuing a transaction
325 /** Flag structure for the request. */
328 /** Memory space configuraiton flag structure for the request. */
329 MemSpaceConfigFlags _memSpaceConfigFlags;
331 /** Private flags for field validity checking. */
332 PrivateFlags privateFlags;
335 * The time this request was started. Used to calculate
336 * latencies. This field is set to curTick() any time paddr or vaddr
342 * The task id associated with this request
346 /** The address space ID. */
349 /** The virtual address of the request. */
353 * Extra data for the request, such as the return value of
354 * store conditional or the compare value for a CAS. */
357 /** The context ID (for statistics, locks, and wakeups). */
358 ContextID _contextId;
360 /** program counter of initiating access; for tracing/debugging */
363 /** Sequence number of the instruction that creates the request */
364 InstSeqNum _reqInstSeqNum;
366 /** A pointer to an atomic operation */
367 AtomicOpFunctor *atomicOpFunctor;
372 * Minimal constructor. No fields are initialized. (Note that
373 * _flags and privateFlags are cleared by Flags default
377 : _paddr(0), _size(0), _masterId(invldMasterId), _time(0),
378 _taskId(ContextSwitchTaskId::Unknown), _asid(0), _vaddr(0),
379 _extraData(0), _contextId(0), _pc(0),
380 _reqInstSeqNum(0), atomicOpFunctor(nullptr), translateDelta(0),
381 accessDelta(0), depth(0)
384 Request(Addr paddr, unsigned size, Flags flags, MasterID mid,
385 InstSeqNum seq_num, ContextID cid)
386 : _paddr(0), _size(0), _masterId(invldMasterId), _time(0),
387 _taskId(ContextSwitchTaskId::Unknown), _asid(0), _vaddr(0),
388 _extraData(0), _contextId(0), _pc(0),
389 _reqInstSeqNum(seq_num), atomicOpFunctor(nullptr), translateDelta(0),
390 accessDelta(0), depth(0)
392 setPhys(paddr, size, flags, mid, curTick());
394 privateFlags.set(VALID_INST_SEQ_NUM);
398 * Constructor for physical (e.g. device) requests. Initializes
399 * just physical address, size, flags, and timestamp (to curTick()).
400 * These fields are adequate to perform a request.
402 Request(Addr paddr, unsigned size, Flags flags, MasterID mid)
403 : _paddr(0), _size(0), _masterId(invldMasterId), _time(0),
404 _taskId(ContextSwitchTaskId::Unknown), _asid(0), _vaddr(0),
405 _extraData(0), _contextId(0), _pc(0),
406 _reqInstSeqNum(0), atomicOpFunctor(nullptr), translateDelta(0),
407 accessDelta(0), depth(0)
409 setPhys(paddr, size, flags, mid, curTick());
412 Request(Addr paddr, unsigned size, Flags flags, MasterID mid, Tick time)
413 : _paddr(0), _size(0), _masterId(invldMasterId), _time(0),
414 _taskId(ContextSwitchTaskId::Unknown), _asid(0), _vaddr(0),
415 _extraData(0), _contextId(0), _pc(0),
416 _reqInstSeqNum(0), atomicOpFunctor(nullptr), translateDelta(0),
417 accessDelta(0), depth(0)
419 setPhys(paddr, size, flags, mid, time);
422 Request(Addr paddr, unsigned size, Flags flags, MasterID mid, Tick time,
424 : _paddr(0), _size(0), _masterId(invldMasterId), _time(0),
425 _taskId(ContextSwitchTaskId::Unknown), _asid(0), _vaddr(0),
426 _extraData(0), _contextId(0), _pc(pc),
427 _reqInstSeqNum(0), atomicOpFunctor(nullptr), translateDelta(0),
428 accessDelta(0), depth(0)
430 setPhys(paddr, size, flags, mid, time);
431 privateFlags.set(VALID_PC);
434 Request(int asid, Addr vaddr, unsigned size, Flags flags, MasterID mid,
435 Addr pc, ContextID cid)
436 : _paddr(0), _size(0), _masterId(invldMasterId), _time(0),
437 _taskId(ContextSwitchTaskId::Unknown), _asid(0), _vaddr(0),
438 _extraData(0), _contextId(0), _pc(0),
439 _reqInstSeqNum(0), atomicOpFunctor(nullptr), translateDelta(0),
440 accessDelta(0), depth(0)
442 setVirt(asid, vaddr, size, flags, mid, pc);
446 Request(int asid, Addr vaddr, unsigned size, Flags flags, MasterID mid,
447 Addr pc, ContextID cid, AtomicOpFunctor *atomic_op)
448 : atomicOpFunctor(atomic_op)
450 setVirt(asid, vaddr, size, flags, mid, pc);
456 if (hasAtomicOpFunctor()) {
457 delete atomicOpFunctor;
462 * Set up Context numbers.
465 setContext(ContextID context_id)
467 _contextId = context_id;
468 privateFlags.set(VALID_CONTEXT_ID);
472 * Set up a virtual (e.g., CPU) request in a previously
473 * allocated Request object.
476 setVirt(int asid, Addr vaddr, unsigned size, Flags flags, MasterID mid,
486 _flags.clear(~STICKY_FLAGS);
488 privateFlags.clear(~STICKY_PRIVATE_FLAGS);
489 privateFlags.set(VALID_VADDR|VALID_SIZE|VALID_PC);
496 * Set just the physical address. This usually used to record the
497 * result of a translation. However, when using virtualized CPUs
498 * setPhys() is sometimes called to finalize a physical address
499 * without a virtual address, so we can't check if the virtual
506 privateFlags.set(VALID_PADDR);
510 * Generate two requests as if this request had been split into two
511 * pieces. The original request can't have been translated already.
513 void splitOnVaddr(Addr split_addr, RequestPtr &req1, RequestPtr &req2)
515 assert(privateFlags.isSet(VALID_VADDR));
516 assert(privateFlags.noneSet(VALID_PADDR));
517 assert(split_addr > _vaddr && split_addr < _vaddr + _size);
518 req1 = std::make_shared<Request>(*this);
519 req2 = std::make_shared<Request>(*this);
520 req1->_size = split_addr - _vaddr;
521 req2->_vaddr = split_addr;
522 req2->_size = _size - req1->_size;
526 * Accessor for paddr.
531 return privateFlags.isSet(VALID_PADDR);
537 assert(privateFlags.isSet(VALID_PADDR));
542 * Time for the TLB/table walker to successfully translate this request.
547 * Access latency to complete this memory transaction not including
553 * Level of the cache hierachy where this request was responded to
554 * (e.g. 0 = L1; 1 = L2).
564 return privateFlags.isSet(VALID_SIZE);
570 assert(privateFlags.isSet(VALID_SIZE));
574 /** Accessor for time. */
578 assert(privateFlags.isSet(VALID_PADDR|VALID_VADDR));
583 * Accessor for atomic-op functor.
588 return atomicOpFunctor != NULL;
594 assert(atomicOpFunctor != NULL);
595 return atomicOpFunctor;
598 /** Accessor for flags. */
602 assert(privateFlags.isSet(VALID_PADDR|VALID_VADDR));
606 /** Note that unlike other accessors, this function sets *specific
607 flags* (ORs them in); it does not assign its argument to the
608 _flags field. Thus this method should rightly be called
609 setFlags() and not just flags(). */
611 setFlags(Flags flags)
613 assert(privateFlags.isSet(VALID_PADDR|VALID_VADDR));
618 setMemSpaceConfigFlags(MemSpaceConfigFlags extraFlags)
620 assert(privateFlags.isSet(VALID_PADDR | VALID_VADDR));
621 _memSpaceConfigFlags.set(extraFlags);
624 /** Accessor function for vaddr.*/
628 return privateFlags.isSet(VALID_VADDR);
634 assert(privateFlags.isSet(VALID_VADDR));
638 /** Accesssor for the requestor id. */
652 taskId(uint32_t id) {
656 /** Accessor function for asid.*/
660 assert(privateFlags.isSet(VALID_VADDR));
664 /** Accessor function for asid.*/
671 /** Accessor function for architecture-specific flags.*/
675 assert(privateFlags.isSet(VALID_PADDR|VALID_VADDR));
676 return _flags & ARCH_BITS;
679 /** Accessor function to check if sc result is valid. */
681 extraDataValid() const
683 return privateFlags.isSet(VALID_EXTRA_DATA);
686 /** Accessor function for store conditional return value.*/
690 assert(privateFlags.isSet(VALID_EXTRA_DATA));
694 /** Accessor function for store conditional return value.*/
696 setExtraData(uint64_t extraData)
698 _extraData = extraData;
699 privateFlags.set(VALID_EXTRA_DATA);
705 return privateFlags.isSet(VALID_CONTEXT_ID);
708 /** Accessor function for context ID.*/
712 assert(privateFlags.isSet(VALID_CONTEXT_ID));
719 privateFlags.set(VALID_PC);
726 return privateFlags.isSet(VALID_PC);
729 /** Accessor function for pc.*/
733 assert(privateFlags.isSet(VALID_PC));
738 * Increment/Get the depth at which this request is responded to.
739 * This currently happens when the request misses in any cache level.
741 void incAccessDepth() const { depth++; }
742 int getAccessDepth() const { return depth; }
745 * Set/Get the time taken for this request to be successfully translated.
747 void setTranslateLatency() { translateDelta = curTick() - _time; }
748 Tick getTranslateLatency() const { return translateDelta; }
751 * Set/Get the time taken to complete this request's access, not including
752 * the time to successfully translate the request.
754 void setAccessLatency() { accessDelta = curTick() - _time - translateDelta; }
755 Tick getAccessLatency() const { return accessDelta; }
758 * Accessor for the sequence number of instruction that creates the
762 hasInstSeqNum() const
764 return privateFlags.isSet(VALID_INST_SEQ_NUM);
768 getReqInstSeqNum() const
770 assert(privateFlags.isSet(VALID_INST_SEQ_NUM));
771 return _reqInstSeqNum;
775 setReqInstSeqNum(const InstSeqNum seq_num)
777 privateFlags.set(VALID_INST_SEQ_NUM);
778 _reqInstSeqNum = seq_num;
781 /** Accessor functions for flags. Note that these are for testing
782 only; setting flags should be done via setFlags(). */
783 bool isUncacheable() const { return _flags.isSet(UNCACHEABLE); }
784 bool isStrictlyOrdered() const { return _flags.isSet(STRICT_ORDER); }
785 bool isInstFetch() const { return _flags.isSet(INST_FETCH); }
786 bool isPrefetch() const { return _flags.isSet(PREFETCH); }
787 bool isLLSC() const { return _flags.isSet(LLSC); }
788 bool isPriv() const { return _flags.isSet(PRIVILEGED); }
789 bool isLockedRMW() const { return _flags.isSet(LOCKED_RMW); }
790 bool isSwap() const { return _flags.isSet(MEM_SWAP|MEM_SWAP_COND); }
791 bool isCondSwap() const { return _flags.isSet(MEM_SWAP_COND); }
792 bool isMmappedIpr() const { return _flags.isSet(MMAPPED_IPR); }
793 bool isSecure() const { return _flags.isSet(SECURE); }
794 bool isPTWalk() const { return _flags.isSet(PT_WALK); }
795 bool isAcquire() const { return _flags.isSet(ACQUIRE); }
796 bool isRelease() const { return _flags.isSet(RELEASE); }
797 bool isKernel() const { return _flags.isSet(KERNEL); }
798 bool isAtomicReturn() const { return _flags.isSet(ATOMIC_RETURN_OP); }
799 bool isAtomicNoReturn() const { return _flags.isSet(ATOMIC_NO_RETURN_OP); }
804 return _flags.isSet(ATOMIC_RETURN_OP) ||
805 _flags.isSet(ATOMIC_NO_RETURN_OP);
809 * Accessor functions for the destination of a memory request. The
810 * destination flag can specify a point of reference for the
811 * operation (e.g. a cache block clean to the the point of
812 * unification). At the moment the destination is only used by the
813 * cache maintenance operations.
815 bool isToPOU() const { return _flags.isSet(DST_POU); }
816 bool isToPOC() const { return _flags.isSet(DST_POC); }
817 Flags getDest() const { return _flags & DST_BITS; }
820 * Accessor functions for the memory space configuration flags and used by
821 * GPU ISAs such as the Heterogeneous System Architecture (HSA). Note that
822 * these are for testing only; setting extraFlags should be done via
823 * setMemSpaceConfigFlags().
825 bool isScoped() const { return _memSpaceConfigFlags.isSet(SCOPE_VALID); }
828 isWavefrontScope() const
831 return _memSpaceConfigFlags.isSet(WAVEFRONT_SCOPE);
835 isWorkgroupScope() const
838 return _memSpaceConfigFlags.isSet(WORKGROUP_SCOPE);
842 isDeviceScope() const
845 return _memSpaceConfigFlags.isSet(DEVICE_SCOPE);
849 isSystemScope() const
852 return _memSpaceConfigFlags.isSet(SYSTEM_SCOPE);
856 isGlobalSegment() const
858 return _memSpaceConfigFlags.isSet(GLOBAL_SEGMENT) ||
859 (!isGroupSegment() && !isPrivateSegment() &&
860 !isKernargSegment() && !isReadonlySegment() &&
861 !isSpillSegment() && !isArgSegment());
865 isGroupSegment() const
867 return _memSpaceConfigFlags.isSet(GROUP_SEGMENT);
871 isPrivateSegment() const
873 return _memSpaceConfigFlags.isSet(PRIVATE_SEGMENT);
877 isKernargSegment() const
879 return _memSpaceConfigFlags.isSet(KERNARG_SEGMENT);
883 isReadonlySegment() const
885 return _memSpaceConfigFlags.isSet(READONLY_SEGMENT);
889 isSpillSegment() const
891 return _memSpaceConfigFlags.isSet(SPILL_SEGMENT);
897 return _memSpaceConfigFlags.isSet(ARG_SEGMENT);
901 * Accessor functions to determine whether this request is part of
902 * a cache maintenance operation. At the moment three operations
905 * 1) A cache clean operation updates all copies of a memory
906 * location to the point of reference,
907 * 2) A cache invalidate operation invalidates all copies of the
908 * specified block in the memory above the point of reference,
909 * 3) A clean and invalidate operation is a combination of the two
912 bool isCacheClean() const { return _flags.isSet(CLEAN); }
913 bool isCacheInvalidate() const { return _flags.isSet(INVALIDATE); }
914 bool isCacheMaintenance() const { return _flags.isSet(CLEAN|INVALIDATE); }
918 #endif // __MEM_REQUEST_HH__