2 * Copyright © 2012 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
25 #include "intel_batchbuffer.h"
26 #include "intel_fbo.h"
28 #include "blorp_priv.h"
29 #include "brw_compiler.h"
31 #include "brw_state.h"
34 brw_blorp_surface_info_init(struct brw_context
*brw
,
35 struct brw_blorp_surface_info
*info
,
36 const struct brw_blorp_surf
*surf
,
37 unsigned int level
, unsigned int layer
,
38 enum isl_format format
, bool is_render_target
)
40 /* Layer is a physical layer, so if this is a 2D multisample array texture
41 * using INTEL_MSAA_LAYOUT_UMS or INTEL_MSAA_LAYOUT_CMS, then it had better
42 * be a multiple of num_samples.
44 unsigned layer_multiplier
= 1;
45 if (surf
->surf
->msaa_layout
== ISL_MSAA_LAYOUT_ARRAY
) {
46 assert(layer
% surf
->surf
->samples
== 0);
47 layer_multiplier
= surf
->surf
->samples
;
50 if (format
== ISL_FORMAT_UNSUPPORTED
)
51 format
= surf
->surf
->format
;
53 if (format
== ISL_FORMAT_R24_UNORM_X8_TYPELESS
) {
54 /* Unfortunately, ISL_FORMAT_R24_UNORM_X8_TYPELESS it isn't supported as
55 * a render target, which would prevent us from blitting to 24-bit
56 * depth. The miptree consists of 32 bits per pixel, arranged as 24-bit
57 * depth values interleaved with 8 "don't care" bits. Since depth
58 * values don't require any blending, it doesn't matter how we interpret
59 * the bit pattern as long as we copy the right amount of data, so just
60 * map it as 8-bit BGRA.
62 format
= ISL_FORMAT_B8G8R8A8_UNORM
;
63 } else if (surf
->surf
->usage
& ISL_SURF_USAGE_STENCIL_BIT
) {
64 assert(surf
->surf
->format
== ISL_FORMAT_R8_UINT
);
65 /* Prior to Broadwell, we can't render to R8_UINT */
67 format
= ISL_FORMAT_R8_UNORM
;
70 info
->surf
= *surf
->surf
;
72 info
->offset
= surf
->offset
;
74 info
->aux_usage
= surf
->aux_usage
;
75 if (info
->aux_usage
!= ISL_AUX_USAGE_NONE
) {
76 info
->aux_surf
= *surf
->aux_surf
;
77 info
->aux_bo
= surf
->aux_bo
;
78 info
->aux_offset
= surf
->aux_offset
;
81 info
->clear_color
= surf
->clear_color
;
83 info
->view
= (struct isl_view
) {
84 .usage
= is_render_target
? ISL_SURF_USAGE_RENDER_TARGET_BIT
:
85 ISL_SURF_USAGE_TEXTURE_BIT
,
90 ISL_CHANNEL_SELECT_RED
,
91 ISL_CHANNEL_SELECT_GREEN
,
92 ISL_CHANNEL_SELECT_BLUE
,
93 ISL_CHANNEL_SELECT_ALPHA
,
97 if (!is_render_target
&&
98 (info
->surf
.dim
== ISL_SURF_DIM_3D
||
99 info
->surf
.msaa_layout
== ISL_MSAA_LAYOUT_ARRAY
)) {
100 /* 3-D textures don't support base_array layer and neither do 2-D
101 * multisampled textures on IVB so we need to pass it through the
102 * sampler in those cases. These are also two cases where we are
103 * guaranteed that we won't be doing any funny surface hacks.
105 info
->view
.base_array_layer
= 0;
106 info
->view
.array_len
= MAX2(info
->surf
.logical_level0_px
.depth
,
107 info
->surf
.logical_level0_px
.array_len
);
108 info
->z_offset
= layer
/ layer_multiplier
;
110 info
->view
.base_array_layer
= layer
/ layer_multiplier
;
111 info
->view
.array_len
= 1;
118 brw_blorp_params_init(struct brw_blorp_params
*params
)
120 memset(params
, 0, sizeof(*params
));
121 params
->hiz_op
= GEN6_HIZ_OP_NONE
;
122 params
->fast_clear_op
= 0;
123 params
->num_draw_buffers
= 1;
124 params
->num_layers
= 1;
128 brw_blorp_init_wm_prog_key(struct brw_wm_prog_key
*wm_key
)
130 memset(wm_key
, 0, sizeof(*wm_key
));
131 wm_key
->nr_color_regions
= 1;
132 for (int i
= 0; i
< MAX_SAMPLERS
; i
++)
133 wm_key
->tex
.swizzles
[i
] = SWIZZLE_XYZW
;
137 nir_uniform_type_size(const struct glsl_type
*type
)
139 /* Only very basic types are allowed */
140 assert(glsl_type_is_vector_or_scalar(type
));
141 assert(glsl_get_bit_size(type
) == 32);
143 return glsl_get_vector_elements(type
) * 4;
147 brw_blorp_compile_nir_shader(struct brw_context
*brw
, struct nir_shader
*nir
,
148 const struct brw_wm_prog_key
*wm_key
,
150 struct brw_blorp_prog_data
*prog_data
,
151 unsigned *program_size
)
153 const struct brw_compiler
*compiler
= brw
->intelScreen
->compiler
;
155 void *mem_ctx
= ralloc_context(NULL
);
157 /* Calling brw_preprocess_nir and friends is destructive and, if cloning is
158 * enabled, may end up completely replacing the nir_shader. Therefore, we
159 * own it and might as well put it in our context for easy cleanup.
161 ralloc_steal(mem_ctx
, nir
);
163 compiler
->glsl_compiler_options
[MESA_SHADER_FRAGMENT
].NirOptions
;
165 struct brw_wm_prog_data wm_prog_data
;
166 memset(&wm_prog_data
, 0, sizeof(wm_prog_data
));
168 wm_prog_data
.base
.nr_params
= 0;
169 wm_prog_data
.base
.param
= NULL
;
171 /* BLORP always just uses the first two binding table entries */
172 wm_prog_data
.binding_table
.render_target_start
= 0;
173 wm_prog_data
.base
.binding_table
.texture_start
= 1;
175 nir
= brw_preprocess_nir(compiler
, nir
);
176 nir_remove_dead_variables(nir
, nir_var_shader_in
);
177 nir_shader_gather_info(nir
, nir_shader_get_entrypoint(nir
)->impl
);
179 /* Uniforms are required to be lowered before going into compile_fs. For
180 * BLORP, we'll assume that whoever builds the shader sets the location
181 * they want so we just need to lower them and figure out how many we have
184 nir
->num_uniforms
= 0;
185 nir_foreach_variable(var
, &nir
->uniforms
) {
186 var
->data
.driver_location
= var
->data
.location
;
187 unsigned end
= var
->data
.location
+ nir_uniform_type_size(var
->type
);
188 nir
->num_uniforms
= MAX2(nir
->num_uniforms
, end
);
190 nir_lower_io(nir
, nir_var_uniform
, nir_uniform_type_size
);
192 const unsigned *program
=
193 brw_compile_fs(compiler
, brw
, mem_ctx
, wm_key
, &wm_prog_data
, nir
,
194 NULL
, -1, -1, false, use_repclear
, program_size
, NULL
);
196 /* Copy the relavent bits of wm_prog_data over into the blorp prog data */
197 prog_data
->dispatch_8
= wm_prog_data
.dispatch_8
;
198 prog_data
->dispatch_16
= wm_prog_data
.dispatch_16
;
199 prog_data
->first_curbe_grf_0
= wm_prog_data
.base
.dispatch_grf_start_reg
;
200 prog_data
->first_curbe_grf_2
= wm_prog_data
.dispatch_grf_start_reg_2
;
201 prog_data
->ksp_offset_2
= wm_prog_data
.prog_offset_2
;
202 prog_data
->persample_msaa_dispatch
= wm_prog_data
.persample_dispatch
;
203 prog_data
->flat_inputs
= wm_prog_data
.flat_inputs
;
204 prog_data
->num_varying_inputs
= wm_prog_data
.num_varying_inputs
;
205 prog_data
->inputs_read
= nir
->info
.inputs_read
;
207 assert(wm_prog_data
.base
.nr_params
== 0);
212 struct surface_state_info
{
214 unsigned ss_align
; /* Required alignment of RENDER_SURFACE_STATE in bytes */
216 unsigned aux_reloc_dw
;
221 static const struct surface_state_info surface_state_infos
[] = {
223 [7] = {8, 32, 1, 6, GEN7_MOCS_L3
, GEN7_MOCS_L3
},
224 [8] = {13, 64, 8, 10, BDW_MOCS_WB
, BDW_MOCS_PTE
},
225 [9] = {16, 64, 8, 10, SKL_MOCS_WB
, SKL_MOCS_PTE
},
229 brw_blorp_emit_surface_state(struct brw_context
*brw
,
230 const struct brw_blorp_surface_info
*surface
,
231 uint32_t read_domains
, uint32_t write_domain
,
232 bool is_render_target
)
234 const struct surface_state_info ss_info
= surface_state_infos
[brw
->gen
];
236 struct isl_surf surf
= surface
->surf
;
238 if (surf
.dim
== ISL_SURF_DIM_1D
&&
239 surf
.dim_layout
== ISL_DIM_LAYOUT_GEN4_2D
) {
240 assert(surf
.logical_level0_px
.height
== 1);
241 surf
.dim
= ISL_SURF_DIM_2D
;
244 /* Blorp doesn't support HiZ in any of the blit or slow-clear paths */
245 enum isl_aux_usage aux_usage
= surface
->aux_usage
;
246 if (aux_usage
== ISL_AUX_USAGE_HIZ
)
247 aux_usage
= ISL_AUX_USAGE_NONE
;
249 uint32_t surf_offset
;
250 uint32_t *dw
= brw_state_batch(brw
, AUB_TRACE_SURFACE_STATE
,
251 ss_info
.num_dwords
* 4, ss_info
.ss_align
,
254 const uint32_t mocs
= is_render_target
? ss_info
.rb_mocs
: ss_info
.tex_mocs
;
255 uint64_t aux_bo_offset
= surface
->aux_bo
? surface
->aux_bo
->offset64
: 0;
257 isl_surf_fill_state(&brw
->isl_dev
, dw
, .surf
= &surf
, .view
= &surface
->view
,
258 .address
= surface
->bo
->offset64
+ surface
->offset
,
259 .aux_surf
= &surface
->aux_surf
, .aux_usage
= aux_usage
,
260 .aux_address
= aux_bo_offset
+ surface
->aux_offset
,
261 .mocs
= mocs
, .clear_color
= surface
->clear_color
,
262 .x_offset_sa
= surface
->tile_x_sa
,
263 .y_offset_sa
= surface
->tile_y_sa
);
265 /* Emit relocation to surface contents */
266 drm_intel_bo_emit_reloc(brw
->batch
.bo
,
267 surf_offset
+ ss_info
.reloc_dw
* 4,
269 dw
[ss_info
.reloc_dw
] - surface
->bo
->offset64
,
270 read_domains
, write_domain
);
272 if (aux_usage
!= ISL_AUX_USAGE_NONE
) {
273 /* On gen7 and prior, the bottom 12 bits of the MCS base address are
274 * used to store other information. This should be ok, however, because
275 * surface buffer addresses are always 4K page alinged.
277 assert((surface
->aux_offset
& 0xfff) == 0);
278 drm_intel_bo_emit_reloc(brw
->batch
.bo
,
279 surf_offset
+ ss_info
.aux_reloc_dw
* 4,
281 dw
[ss_info
.aux_reloc_dw
] & 0xfff,
282 read_domains
, write_domain
);
289 brw_blorp_exec(struct brw_context
*brw
, const struct brw_blorp_params
*params
)
291 struct gl_context
*ctx
= &brw
->ctx
;
292 const uint32_t estimated_max_batch_usage
= brw
->gen
>= 8 ? 1800 : 1500;
293 bool check_aperture_failed_once
= false;
295 /* Flush the sampler and render caches. We definitely need to flush the
296 * sampler cache so that we get updated contents from the render cache for
297 * the glBlitFramebuffer() source. Also, we are sometimes warned in the
298 * docs to flush the cache between reinterpretations of the same surface
299 * data with different formats, which blorp does for stencil and depth
302 brw_emit_mi_flush(brw
);
304 brw_select_pipeline(brw
, BRW_RENDER_PIPELINE
);
307 intel_batchbuffer_require_space(brw
, estimated_max_batch_usage
, RENDER_RING
);
308 intel_batchbuffer_save_state(brw
);
309 drm_intel_bo
*saved_bo
= brw
->batch
.bo
;
310 uint32_t saved_used
= USED_BATCH(brw
->batch
);
311 uint32_t saved_state_batch_offset
= brw
->batch
.state_batch_offset
;
315 gen6_blorp_exec(brw
, params
);
319 gen75_blorp_exec(brw
, params
);
321 gen7_blorp_exec(brw
, params
);
324 gen8_blorp_exec(brw
, params
);
327 gen9_blorp_exec(brw
, params
);
330 /* BLORP is not supported before Gen6. */
331 unreachable("not reached");
334 /* Make sure we didn't wrap the batch unintentionally, and make sure we
335 * reserved enough space that a wrap will never happen.
337 assert(brw
->batch
.bo
== saved_bo
);
338 assert((USED_BATCH(brw
->batch
) - saved_used
) * 4 +
339 (saved_state_batch_offset
- brw
->batch
.state_batch_offset
) <
340 estimated_max_batch_usage
);
341 /* Shut up compiler warnings on release build */
344 (void)saved_state_batch_offset
;
346 /* Check if the blorp op we just did would make our batch likely to fail to
347 * map all the BOs into the GPU at batch exec time later. If so, flush the
348 * batch and try again with nothing else in the batch.
350 if (dri_bufmgr_check_aperture_space(&brw
->batch
.bo
, 1)) {
351 if (!check_aperture_failed_once
) {
352 check_aperture_failed_once
= true;
353 intel_batchbuffer_reset_to_saved(brw
);
354 intel_batchbuffer_flush(brw
);
357 int ret
= intel_batchbuffer_flush(brw
);
358 WARN_ONCE(ret
== -ENOSPC
,
359 "i965: blorp emit exceeded available aperture space\n");
363 if (unlikely(brw
->always_flush_batch
))
364 intel_batchbuffer_flush(brw
);
366 /* We've smashed all state compared to what the normal 3D pipeline
367 * rendering tracks for GL.
369 brw
->ctx
.NewDriverState
|= BRW_NEW_BLORP
;
370 brw
->no_depth_or_stencil
= false;
373 /* Flush the sampler cache so any texturing from the destination is
376 brw_emit_mi_flush(brw
);
380 blorp_gen6_hiz_op(struct brw_context
*brw
, struct brw_blorp_surf
*surf
,
381 unsigned level
, unsigned layer
, enum gen6_hiz_op op
)
383 struct brw_blorp_params params
;
384 brw_blorp_params_init(¶ms
);
388 brw_blorp_surface_info_init(brw
, ¶ms
.depth
, surf
, level
, layer
,
389 surf
->surf
->format
, true);
391 /* Align the rectangle primitive to 8x4 pixels.
393 * During fast depth clears, the emitted rectangle primitive must be
394 * aligned to 8x4 pixels. From the Ivybridge PRM, Vol 2 Part 1 Section
395 * 11.5.3.1 Depth Buffer Clear (and the matching section in the Sandybridge
397 * If Number of Multisamples is NUMSAMPLES_1, the rectangle must be
398 * aligned to an 8x4 pixel block relative to the upper left corner
399 * of the depth buffer [...]
401 * For hiz resolves, the rectangle must also be 8x4 aligned. Item
402 * WaHizAmbiguate8x4Aligned from the Haswell workarounds page and the
403 * Ivybridge simulator require the alignment.
405 * To be safe, let's just align the rect for all hiz operations and all
406 * hardware generations.
408 * However, for some miptree slices of a Z24 texture, emitting an 8x4
409 * aligned rectangle that covers the slice may clobber adjacent slices if
410 * we strictly adhered to the texture alignments specified in the PRM. The
411 * Ivybridge PRM, Section "Alignment Unit Size", states that
412 * SURFACE_STATE.Surface_Horizontal_Alignment should be 4 for Z24 surfaces,
413 * not 8. But commit 1f112cc increased the alignment from 4 to 8, which
414 * prevents the clobbering.
416 params
.x1
= minify(params
.depth
.surf
.logical_level0_px
.width
,
417 params
.depth
.view
.base_level
);
418 params
.y1
= minify(params
.depth
.surf
.logical_level0_px
.height
,
419 params
.depth
.view
.base_level
);
420 params
.x1
= ALIGN(params
.x1
, 8);
421 params
.y1
= ALIGN(params
.y1
, 4);
423 if (params
.depth
.view
.base_level
== 0) {
424 /* TODO: What about MSAA? */
425 params
.depth
.surf
.logical_level0_px
.width
= params
.x1
;
426 params
.depth
.surf
.logical_level0_px
.height
= params
.y1
;
429 params
.dst
.surf
.samples
= params
.depth
.surf
.samples
;
430 params
.dst
.surf
.logical_level0_px
= params
.depth
.surf
.logical_level0_px
;
432 switch (surf
->surf
->format
) {
433 case ISL_FORMAT_R16_UNORM
:
434 params
.depth_format
= BRW_DEPTHFORMAT_D16_UNORM
;
436 case ISL_FORMAT_R32_FLOAT
:
437 params
.depth_format
= BRW_DEPTHFORMAT_D32_FLOAT
;
439 case ISL_FORMAT_R24_UNORM_X8_TYPELESS
:
440 params
.depth_format
= BRW_DEPTHFORMAT_D24_UNORM_X8_UINT
;
443 unreachable("not reached");
446 brw_blorp_exec(brw
, ¶ms
);