2 Copyright (C) Intel Corp. 2006. All Rights Reserved.
3 Intel funded Tungsten Graphics to
4 develop this 3D driver.
6 Permission is hereby granted, free of charge, to any person obtaining
7 a copy of this software and associated documentation files (the
8 "Software"), to deal in the Software without restriction, including
9 without limitation the rights to use, copy, modify, merge, publish,
10 distribute, sublicense, and/or sell copies of the Software, and to
11 permit persons to whom the Software is furnished to do so, subject to
12 the following conditions:
14 The above copyright notice and this permission notice (including the
15 next paragraph) shall be included in all copies or substantial
16 portions of the Software.
18 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
19 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
20 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
21 IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
22 LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
23 OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
24 WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
26 **********************************************************************/
29 * Keith Whitwell <keithw@vmware.com>
33 #ifndef BRWCONTEXT_INC
34 #define BRWCONTEXT_INC
37 #include "main/macros.h"
38 #include "main/mtypes.h"
39 #include "brw_structs.h"
40 #include "brw_compiler.h"
41 #include "intel_aub.h"
45 /* Evil hack for using libdrm in a c++ compiler. */
49 #include <intel_bufmgr.h>
58 #include "intel_debug.h"
59 #include "intel_screen.h"
60 #include "intel_tex_obj.h"
61 #include "intel_resolve_map.h"
65 * URB - uniform resource buffer. A mid-sized buffer which is
66 * partitioned between the fixed function units and used for passing
67 * values (vertices, primitives, constants) between them.
69 * CURBE - constant URB entry. An urb region (entry) used to hold
70 * constant values which the fixed function units can be instructed to
71 * preload into the GRF when spawning a thread.
73 * VUE - vertex URB entry. An urb entry holding a vertex and usually
74 * a vertex header. The header contains control information and
75 * things like primitive type, Begin/end flags and clip codes.
77 * PUE - primitive URB entry. An urb entry produced by the setup (SF)
78 * unit holding rasterization and interpolation parameters.
80 * GRF - general register file. One of several register files
81 * addressable by programmed threads. The inputs (r0, payload, curbe,
82 * urb) of the thread are preloaded to this area before the thread is
83 * spawned. The registers are individually 8 dwords wide and suitable
84 * for general usage. Registers holding thread input values are not
85 * special and may be overwritten.
87 * MRF - message register file. Threads communicate (and terminate)
88 * by sending messages. Message parameters are placed in contiguous
89 * MRF registers. All program output is via these messages. URB
90 * entries are populated by sending a message to the shared URB
91 * function containing the new data, together with a control word,
92 * often an unmodified copy of R0.
94 * R0 - GRF register 0. Typically holds control information used when
95 * sending messages to other threads.
97 * EU or GEN4 EU: The name of the programmable subsystem of the
98 * i965 hardware. Threads are executed by the EU, the registers
99 * described above are part of the EU architecture.
101 * Fixed function units:
103 * CS - Command streamer. Notional first unit, little software
104 * interaction. Holds the URB entries used for constant data, ie the
107 * VF/VS - Vertex Fetch / Vertex Shader. The fixed function part of
108 * this unit is responsible for pulling vertices out of vertex buffers
109 * in vram and injecting them into the processing pipe as VUEs. If
110 * enabled, it first passes them to a VS thread which is a good place
111 * for the driver to implement any active vertex shader.
113 * HS - Hull Shader (Tessellation Control Shader)
115 * TE - Tessellation Engine (Tessellation Primitive Generation)
117 * DS - Domain Shader (Tessellation Evaluation Shader)
119 * GS - Geometry Shader. This corresponds to a new DX10 concept. If
120 * enabled, incoming strips etc are passed to GS threads in individual
121 * line/triangle/point units. The GS thread may perform arbitary
122 * computation and emit whatever primtives with whatever vertices it
123 * chooses. This makes GS an excellent place to implement GL's
124 * unfilled polygon modes, though of course it is capable of much
125 * more. Additionally, GS is used to translate away primitives not
126 * handled by latter units, including Quads and Lineloops.
128 * CS - Clipper. Mesa's clipping algorithms are imported to run on
129 * this unit. The fixed function part performs cliptesting against
130 * the 6 fixed clipplanes and makes descisions on whether or not the
131 * incoming primitive needs to be passed to a thread for clipping.
132 * User clip planes are handled via cooperation with the VS thread.
134 * SF - Strips Fans or Setup: Triangles are prepared for
135 * rasterization. Interpolation coefficients are calculated.
136 * Flatshading and two-side lighting usually performed here.
138 * WM - Windower. Interpolation of vertex attributes performed here.
139 * Fragment shader implemented here. SIMD aspects of EU taken full
140 * advantage of, as pixels are processed in blocks of 16.
142 * CC - Color Calculator. No EU threads associated with this unit.
143 * Handles blending and (presumably) depth and stencil testing.
148 struct brw_vs_prog_key
;
149 struct brw_vue_prog_key
;
150 struct brw_wm_prog_key
;
151 struct brw_wm_prog_data
;
152 struct brw_cs_prog_key
;
153 struct brw_cs_prog_data
;
157 BRW_COMPUTE_PIPELINE
,
164 BRW_CACHE_BLORP_BLIT_PROG
,
167 BRW_CACHE_FF_GS_PROG
,
178 /* brw_cache_ids must come first - see brw_state_cache.c */
179 BRW_STATE_URB_FENCE
= BRW_MAX_CACHE
,
180 BRW_STATE_FRAGMENT_PROGRAM
,
181 BRW_STATE_GEOMETRY_PROGRAM
,
182 BRW_STATE_TESS_PROGRAMS
,
183 BRW_STATE_VERTEX_PROGRAM
,
184 BRW_STATE_CURBE_OFFSETS
,
185 BRW_STATE_REDUCED_PRIMITIVE
,
186 BRW_STATE_PATCH_PRIMITIVE
,
191 BRW_STATE_BINDING_TABLE_POINTERS
,
194 BRW_STATE_DEFAULT_TESS_LEVELS
,
196 BRW_STATE_INDEX_BUFFER
,
197 BRW_STATE_VS_CONSTBUF
,
198 BRW_STATE_TCS_CONSTBUF
,
199 BRW_STATE_TES_CONSTBUF
,
200 BRW_STATE_GS_CONSTBUF
,
201 BRW_STATE_PROGRAM_CACHE
,
202 BRW_STATE_STATE_BASE_ADDRESS
,
203 BRW_STATE_VUE_MAP_GEOM_OUT
,
204 BRW_STATE_TRANSFORM_FEEDBACK
,
205 BRW_STATE_RASTERIZER_DISCARD
,
207 BRW_STATE_UNIFORM_BUFFER
,
208 BRW_STATE_ATOMIC_BUFFER
,
209 BRW_STATE_IMAGE_UNITS
,
210 BRW_STATE_META_IN_PROGRESS
,
211 BRW_STATE_INTERPOLATION_MAP
,
212 BRW_STATE_PUSH_CONSTANT_ALLOCATION
,
213 BRW_STATE_NUM_SAMPLES
,
214 BRW_STATE_TEXTURE_BUFFER
,
215 BRW_STATE_GEN4_UNIT_STATE
,
219 BRW_STATE_SAMPLER_STATE_TABLE
,
220 BRW_STATE_VS_ATTRIB_WORKAROUNDS
,
221 BRW_STATE_COMPUTE_PROGRAM
,
222 BRW_STATE_CS_WORK_GROUPS
,
229 * BRW_NEW_*_PROG_DATA and BRW_NEW_*_PROGRAM are similar, but distinct.
231 * BRW_NEW_*_PROGRAM relates to the gl_shader_program/gl_program structures.
232 * When the currently bound shader program differs from the previous draw
233 * call, these will be flagged. They cover brw->{stage}_program and
234 * ctx->{Stage}Program->_Current.
236 * BRW_NEW_*_PROG_DATA is flagged when the effective shaders change, from a
237 * driver perspective. Even if the same shader is bound at the API level,
238 * we may need to switch between multiple versions of that shader to handle
239 * changes in non-orthagonal state.
241 * Additionally, multiple shader programs may have identical vertex shaders
242 * (for example), or compile down to the same code in the backend. We combine
243 * those into a single program cache entry.
245 * BRW_NEW_*_PROG_DATA occurs when switching program cache entries, which
246 * covers the brw_*_prog_data structures, and brw->*.prog_offset.
248 #define BRW_NEW_FS_PROG_DATA (1ull << BRW_CACHE_FS_PROG)
249 /* XXX: The BRW_NEW_BLORP_BLIT_PROG_DATA dirty bit is unused (as BLORP doesn't
250 * use the normal state upload paths), but the cache is still used. To avoid
251 * polluting the brw_state_cache code with special cases, we retain the dirty
252 * bit for now. It should eventually be removed.
254 #define BRW_NEW_BLORP_BLIT_PROG_DATA (1ull << BRW_CACHE_BLORP_BLIT_PROG)
255 #define BRW_NEW_SF_PROG_DATA (1ull << BRW_CACHE_SF_PROG)
256 #define BRW_NEW_VS_PROG_DATA (1ull << BRW_CACHE_VS_PROG)
257 #define BRW_NEW_FF_GS_PROG_DATA (1ull << BRW_CACHE_FF_GS_PROG)
258 #define BRW_NEW_GS_PROG_DATA (1ull << BRW_CACHE_GS_PROG)
259 #define BRW_NEW_TCS_PROG_DATA (1ull << BRW_CACHE_TCS_PROG)
260 #define BRW_NEW_TES_PROG_DATA (1ull << BRW_CACHE_TES_PROG)
261 #define BRW_NEW_CLIP_PROG_DATA (1ull << BRW_CACHE_CLIP_PROG)
262 #define BRW_NEW_CS_PROG_DATA (1ull << BRW_CACHE_CS_PROG)
263 #define BRW_NEW_URB_FENCE (1ull << BRW_STATE_URB_FENCE)
264 #define BRW_NEW_FRAGMENT_PROGRAM (1ull << BRW_STATE_FRAGMENT_PROGRAM)
265 #define BRW_NEW_GEOMETRY_PROGRAM (1ull << BRW_STATE_GEOMETRY_PROGRAM)
266 #define BRW_NEW_TESS_PROGRAMS (1ull << BRW_STATE_TESS_PROGRAMS)
267 #define BRW_NEW_VERTEX_PROGRAM (1ull << BRW_STATE_VERTEX_PROGRAM)
268 #define BRW_NEW_CURBE_OFFSETS (1ull << BRW_STATE_CURBE_OFFSETS)
269 #define BRW_NEW_REDUCED_PRIMITIVE (1ull << BRW_STATE_REDUCED_PRIMITIVE)
270 #define BRW_NEW_PATCH_PRIMITIVE (1ull << BRW_STATE_PATCH_PRIMITIVE)
271 #define BRW_NEW_PRIMITIVE (1ull << BRW_STATE_PRIMITIVE)
272 #define BRW_NEW_CONTEXT (1ull << BRW_STATE_CONTEXT)
273 #define BRW_NEW_PSP (1ull << BRW_STATE_PSP)
274 #define BRW_NEW_SURFACES (1ull << BRW_STATE_SURFACES)
275 #define BRW_NEW_BINDING_TABLE_POINTERS (1ull << BRW_STATE_BINDING_TABLE_POINTERS)
276 #define BRW_NEW_INDICES (1ull << BRW_STATE_INDICES)
277 #define BRW_NEW_VERTICES (1ull << BRW_STATE_VERTICES)
278 #define BRW_NEW_DEFAULT_TESS_LEVELS (1ull << BRW_STATE_DEFAULT_TESS_LEVELS)
280 * Used for any batch entry with a relocated pointer that will be used
281 * by any 3D rendering.
283 #define BRW_NEW_BATCH (1ull << BRW_STATE_BATCH)
284 /** \see brw.state.depth_region */
285 #define BRW_NEW_INDEX_BUFFER (1ull << BRW_STATE_INDEX_BUFFER)
286 #define BRW_NEW_VS_CONSTBUF (1ull << BRW_STATE_VS_CONSTBUF)
287 #define BRW_NEW_TCS_CONSTBUF (1ull << BRW_STATE_TCS_CONSTBUF)
288 #define BRW_NEW_TES_CONSTBUF (1ull << BRW_STATE_TES_CONSTBUF)
289 #define BRW_NEW_GS_CONSTBUF (1ull << BRW_STATE_GS_CONSTBUF)
290 #define BRW_NEW_PROGRAM_CACHE (1ull << BRW_STATE_PROGRAM_CACHE)
291 #define BRW_NEW_STATE_BASE_ADDRESS (1ull << BRW_STATE_STATE_BASE_ADDRESS)
292 #define BRW_NEW_VUE_MAP_GEOM_OUT (1ull << BRW_STATE_VUE_MAP_GEOM_OUT)
293 #define BRW_NEW_TRANSFORM_FEEDBACK (1ull << BRW_STATE_TRANSFORM_FEEDBACK)
294 #define BRW_NEW_RASTERIZER_DISCARD (1ull << BRW_STATE_RASTERIZER_DISCARD)
295 #define BRW_NEW_STATS_WM (1ull << BRW_STATE_STATS_WM)
296 #define BRW_NEW_UNIFORM_BUFFER (1ull << BRW_STATE_UNIFORM_BUFFER)
297 #define BRW_NEW_ATOMIC_BUFFER (1ull << BRW_STATE_ATOMIC_BUFFER)
298 #define BRW_NEW_IMAGE_UNITS (1ull << BRW_STATE_IMAGE_UNITS)
299 #define BRW_NEW_META_IN_PROGRESS (1ull << BRW_STATE_META_IN_PROGRESS)
300 #define BRW_NEW_INTERPOLATION_MAP (1ull << BRW_STATE_INTERPOLATION_MAP)
301 #define BRW_NEW_PUSH_CONSTANT_ALLOCATION (1ull << BRW_STATE_PUSH_CONSTANT_ALLOCATION)
302 #define BRW_NEW_NUM_SAMPLES (1ull << BRW_STATE_NUM_SAMPLES)
303 #define BRW_NEW_TEXTURE_BUFFER (1ull << BRW_STATE_TEXTURE_BUFFER)
304 #define BRW_NEW_GEN4_UNIT_STATE (1ull << BRW_STATE_GEN4_UNIT_STATE)
305 #define BRW_NEW_CC_VP (1ull << BRW_STATE_CC_VP)
306 #define BRW_NEW_SF_VP (1ull << BRW_STATE_SF_VP)
307 #define BRW_NEW_CLIP_VP (1ull << BRW_STATE_CLIP_VP)
308 #define BRW_NEW_SAMPLER_STATE_TABLE (1ull << BRW_STATE_SAMPLER_STATE_TABLE)
309 #define BRW_NEW_VS_ATTRIB_WORKAROUNDS (1ull << BRW_STATE_VS_ATTRIB_WORKAROUNDS)
310 #define BRW_NEW_COMPUTE_PROGRAM (1ull << BRW_STATE_COMPUTE_PROGRAM)
311 #define BRW_NEW_CS_WORK_GROUPS (1ull << BRW_STATE_CS_WORK_GROUPS)
312 #define BRW_NEW_URB_SIZE (1ull << BRW_STATE_URB_SIZE)
313 #define BRW_NEW_CC_STATE (1ull << BRW_STATE_CC_STATE)
315 struct brw_state_flags
{
316 /** State update flags signalled by mesa internals */
319 * State update flags signalled as the result of brw_tracked_state updates
324 /** Subclass of Mesa vertex program */
325 struct brw_vertex_program
{
326 struct gl_vertex_program program
;
331 /** Subclass of Mesa tessellation control program */
332 struct brw_tess_ctrl_program
{
333 struct gl_tess_ctrl_program program
;
334 unsigned id
; /**< serial no. to identify tess ctrl progs, never re-used */
338 /** Subclass of Mesa tessellation evaluation program */
339 struct brw_tess_eval_program
{
340 struct gl_tess_eval_program program
;
341 unsigned id
; /**< serial no. to identify tess eval progs, never re-used */
345 /** Subclass of Mesa geometry program */
346 struct brw_geometry_program
{
347 struct gl_geometry_program program
;
348 unsigned id
; /**< serial no. to identify geom progs, never re-used */
352 /** Subclass of Mesa fragment program */
353 struct brw_fragment_program
{
354 struct gl_fragment_program program
;
355 GLuint id
; /**< serial no. to identify frag progs, never re-used */
359 /** Subclass of Mesa compute program */
360 struct brw_compute_program
{
361 struct gl_compute_program program
;
362 unsigned id
; /**< serial no. to identify compute progs, never re-used */
367 struct gl_shader base
;
373 * Bitmask indicating which fragment shader inputs represent varyings (and
374 * hence have to be delivered to the fragment shader by the SF/SBE stage).
376 #define BRW_FS_VARYING_INPUT_MASK \
377 (BITFIELD64_RANGE(0, VARYING_SLOT_MAX) & \
378 ~VARYING_BIT_POS & ~VARYING_BIT_FACE)
382 * Mapping of VUE map slots to interpolation modes.
384 struct interpolation_mode_map
{
385 unsigned char mode
[BRW_VARYING_SLOT_COUNT
];
388 static inline bool brw_any_flat_varyings(struct interpolation_mode_map
*map
)
390 for (int i
= 0; i
< BRW_VARYING_SLOT_COUNT
; i
++)
391 if (map
->mode
[i
] == INTERP_QUALIFIER_FLAT
)
397 static inline bool brw_any_noperspective_varyings(struct interpolation_mode_map
*map
)
399 for (int i
= 0; i
< BRW_VARYING_SLOT_COUNT
; i
++)
400 if (map
->mode
[i
] == INTERP_QUALIFIER_NOPERSPECTIVE
)
407 struct brw_sf_prog_data
{
408 GLuint urb_read_length
;
411 /* Each vertex may have upto 12 attributes, 4 components each,
412 * except WPOS which requires only 2. (11*4 + 2) == 44 ==> 11
415 * Actually we use 4 for each, so call it 12 rows.
417 GLuint urb_entry_size
;
422 * We always program SF to start reading at an offset of 1 (2 varying slots)
423 * from the start of the vertex URB entry. This causes it to skip:
424 * - VARYING_SLOT_PSIZ and BRW_VARYING_SLOT_NDC on gen4-5
425 * - VARYING_SLOT_PSIZ and VARYING_SLOT_POS on gen6+
427 #define BRW_SF_URB_ENTRY_READ_OFFSET 1
430 struct brw_clip_prog_data
{
431 GLuint curb_read_length
; /* user planes? */
433 GLuint urb_read_length
;
437 struct brw_ff_gs_prog_data
{
438 GLuint urb_read_length
;
442 * Gen6 transform feedback: Amount by which the streaming vertex buffer
443 * indices should be incremented each time the GS is invoked.
445 unsigned svbi_postincrement_value
;
448 /** Number of texture sampler units */
449 #define BRW_MAX_TEX_UNIT 32
451 /** Max number of render targets in a shader */
452 #define BRW_MAX_DRAW_BUFFERS 8
454 /** Max number of UBOs in a shader */
455 #define BRW_MAX_UBO 14
457 /** Max number of SSBOs in a shader */
458 #define BRW_MAX_SSBO 12
460 /** Max number of atomic counter buffer objects in a shader */
461 #define BRW_MAX_ABO 16
463 /** Max number of image uniforms in a shader */
464 #define BRW_MAX_IMAGES 32
467 * Max number of binding table entries used for stream output.
469 * From the OpenGL 3.0 spec, table 6.44 (Transform Feedback State), the
470 * minimum value of MAX_TRANSFORM_FEEDBACK_INTERLEAVED_COMPONENTS is 64.
472 * On Gen6, the size of transform feedback data is limited not by the number
473 * of components but by the number of binding table entries we set aside. We
474 * use one binding table entry for a float, one entry for a vector, and one
475 * entry per matrix column. Since the only way we can communicate our
476 * transform feedback capabilities to the client is via
477 * MAX_TRANSFORM_FEEDBACK_INTERLEAVED_COMPONENTS, we need to plan for the
478 * worst case, in which all the varyings are floats, so we use up one binding
479 * table entry per component. Therefore we need to set aside at least 64
480 * binding table entries for use by transform feedback.
482 * Note: since we don't currently pack varyings, it is currently impossible
483 * for the client to actually use up all of these binding table entries--if
484 * all of their varyings were floats, they would run out of varying slots and
485 * fail to link. But that's a bug, so it seems prudent to go ahead and
486 * allocate the number of binding table entries we will need once the bug is
489 #define BRW_MAX_SOL_BINDINGS 64
491 /** Maximum number of actual buffers used for stream output */
492 #define BRW_MAX_SOL_BUFFERS 4
494 #define BRW_MAX_SURFACES (BRW_MAX_DRAW_BUFFERS + \
495 BRW_MAX_TEX_UNIT * 2 + /* normal, gather */ \
500 2 + /* shader time, pull constants */ \
501 1 /* cs num work groups */)
503 #define SURF_INDEX_GEN6_SOL_BINDING(t) (t)
506 * Stride in bytes between shader_time entries.
508 * We separate entries by a cacheline to reduce traffic between EUs writing to
511 #define SHADER_TIME_STRIDE 64
513 struct brw_cache_item
{
515 * Effectively part of the key, cache_id identifies what kind of state
516 * buffer is involved, and also which dirty flag should set.
518 enum brw_cache_id cache_id
;
519 /** 32-bit hash of the key data */
521 GLuint key_size
; /* for variable-sized keys */
528 struct brw_cache_item
*next
;
533 struct brw_context
*brw
;
535 struct brw_cache_item
**items
;
537 GLuint size
, n_items
;
539 uint32_t next_offset
;
544 /* Considered adding a member to this struct to document which flags
545 * an update might raise so that ordering of the state atoms can be
546 * checked or derived at runtime. Dropped the idea in favor of having
547 * a debug mode where the state is monitored for flags which are
548 * raised that have already been tested against.
550 struct brw_tracked_state
{
551 struct brw_state_flags dirty
;
552 void (*emit
)( struct brw_context
*brw
);
555 enum shader_time_shader_type
{
566 struct brw_vertex_buffer
{
567 /** Buffer object containing the uploaded vertex data */
570 /** Byte stride between elements in the uploaded array */
574 struct brw_vertex_element
{
575 const struct gl_client_array
*glarray
;
579 /** Offset of the first element within the buffer object */
583 struct brw_query_object
{
584 struct gl_query_object Base
;
586 /** Last query BO associated with this query. */
589 /** Last index in bo with query data for this object. */
592 /** True if we know the batch has been flushed since we ended the query. */
602 struct intel_batchbuffer
{
603 /** Current batchbuffer being queued up. */
605 /** Last BO submitted to the hardware. Used for glFinish(). */
606 drm_intel_bo
*last_bo
;
609 uint16_t emit
, total
;
611 uint16_t reserved_space
;
615 #define BATCH_SZ (8192*sizeof(uint32_t))
617 uint32_t state_batch_offset
;
618 enum brw_gpu_ring ring
;
619 bool needs_sol_reset
;
627 #define MAX_GS_INPUT_VERTICES 6
629 #define BRW_MAX_XFB_STREAMS 4
631 struct brw_transform_feedback_object
{
632 struct gl_transform_feedback_object base
;
634 /** A buffer to hold SO_WRITE_OFFSET(n) values while paused. */
635 drm_intel_bo
*offset_bo
;
637 /** If true, SO_WRITE_OFFSET(n) should be reset to zero at next use. */
640 /** The most recent primitive mode (GL_TRIANGLES/GL_POINTS/GL_LINES). */
641 GLenum primitive_mode
;
644 * Count of primitives generated during this transform feedback operation.
647 uint64_t prims_generated
[BRW_MAX_XFB_STREAMS
];
648 drm_intel_bo
*prim_count_bo
;
649 unsigned prim_count_buffer_index
; /**< in number of uint64_t units */
653 * Number of vertices written between last Begin/EndTransformFeedback().
655 * Used to implement DrawTransformFeedback().
657 uint64_t vertices_written
[BRW_MAX_XFB_STREAMS
];
658 bool vertices_written_valid
;
662 * Data shared between each programmable stage in the pipeline (vs, gs, and
665 struct brw_stage_state
667 gl_shader_stage stage
;
668 struct brw_stage_prog_data
*prog_data
;
671 * Optional scratch buffer used to store spilled register values and
672 * variably-indexed GRF arrays.
674 drm_intel_bo
*scratch_bo
;
676 /** Offset in the program cache to the program */
677 uint32_t prog_offset
;
679 /** Offset in the batchbuffer to Gen4-5 pipelined state (VS/WM/GS_STATE). */
680 uint32_t state_offset
;
682 uint32_t push_const_offset
; /* Offset in the batchbuffer */
683 int push_const_size
; /* in 256-bit register increments */
685 /* Binding table: pointers to SURFACE_STATE entries. */
686 uint32_t bind_bo_offset
;
687 uint32_t surf_offset
[BRW_MAX_SURFACES
];
689 /** SAMPLER_STATE count and table offset */
690 uint32_t sampler_count
;
691 uint32_t sampler_offset
;
694 enum brw_predicate_state
{
695 /* The first two states are used if we can determine whether to draw
696 * without having to look at the values in the query object buffer. This
697 * will happen if there is no conditional render in progress, if the query
698 * object is already completed or if something else has already added
699 * samples to the preliminary result such as via a BLT command.
701 BRW_PREDICATE_STATE_RENDER
,
702 BRW_PREDICATE_STATE_DONT_RENDER
,
703 /* In this case whether to draw or not depends on the result of an
704 * MI_PREDICATE command so the predicate enable bit needs to be checked.
706 BRW_PREDICATE_STATE_USE_BIT
711 struct brw_l3_config
;
714 * brw_context is derived from gl_context.
718 struct gl_context ctx
; /**< base class, must be first field */
722 void (*update_texture_surface
)(struct gl_context
*ctx
,
724 uint32_t *surf_offset
,
726 uint32_t (*update_renderbuffer_surface
)(struct brw_context
*brw
,
727 struct gl_renderbuffer
*rb
,
728 bool layered
, unsigned unit
,
729 uint32_t surf_index
);
731 void (*emit_texture_surface_state
)(struct brw_context
*brw
,
732 struct intel_mipmap_tree
*mt
,
740 uint32_t *surf_offset
,
741 bool rw
, bool for_gather
);
742 void (*emit_buffer_surface_state
)(struct brw_context
*brw
,
743 uint32_t *out_offset
,
745 unsigned buffer_offset
,
746 unsigned surface_format
,
747 unsigned buffer_size
,
750 void (*emit_null_surface_state
)(struct brw_context
*brw
,
754 uint32_t *out_offset
);
757 * Send the appropriate state packets to configure depth, stencil, and
758 * HiZ buffers (i965+ only)
760 void (*emit_depth_stencil_hiz
)(struct brw_context
*brw
,
761 struct intel_mipmap_tree
*depth_mt
,
762 uint32_t depth_offset
,
763 uint32_t depthbuffer_format
,
764 uint32_t depth_surface_type
,
765 struct intel_mipmap_tree
*stencil_mt
,
766 bool hiz
, bool separate_stencil
,
767 uint32_t width
, uint32_t height
,
768 uint32_t tile_x
, uint32_t tile_y
);
774 drm_intel_context
*hw_ctx
;
776 /** BO for post-sync nonzero writes for gen6 workaround. */
777 drm_intel_bo
*workaround_bo
;
778 uint8_t pipe_controls_since_last_cs_stall
;
781 * Set of drm_intel_bo * that have been rendered to within this batchbuffer
782 * and would need flushing before being used from another cache domain that
783 * isn't coherent with it (i.e. the sampler).
785 struct set
*render_cache
;
788 * Number of resets observed in the system at context creation.
790 * This is tracked in the context so that we can determine that another
791 * reset has occurred.
793 uint32_t reset_count
;
795 struct intel_batchbuffer batch
;
800 uint32_t next_offset
;
804 * Set if rendering has occurred to the drawable's front buffer.
806 * This is used in the DRI2 case to detect that glFlush should also copy
807 * the contents of the fake front buffer to the real front buffer.
809 bool front_buffer_dirty
;
811 /** Framerate throttling: @{ */
812 drm_intel_bo
*throttle_batch
[2];
814 /* Limit the number of outstanding SwapBuffers by waiting for an earlier
815 * frame of rendering to complete. This gives a very precise cap to the
816 * latency between input and output such that rendering never gets more
817 * than a frame behind the user. (With the caveat that we technically are
818 * not using the SwapBuffers itself as a barrier but the first batch
819 * submitted afterwards, which may be immediately prior to the next
822 bool need_swap_throttle
;
824 /** General throttling, not caught by throttling between SwapBuffers */
825 bool need_flush_throttle
;
835 bool always_flush_batch
;
836 bool always_flush_cache
;
837 bool disable_throttling
;
839 bool dual_color_blend_by_location
;
841 driOptionCache optionCache
;
844 GLuint primitive
; /**< Hardware primitive, such as _3DPRIM_TRILIST. */
846 GLenum reduced_primitive
;
849 * Set if we're either a debug context or the INTEL_DEBUG=perf environment
850 * variable is set, this is the flag indicating to do expensive work that
851 * might lead to a perf_debug() call.
855 uint32_t max_gtt_map_object_size
;
867 bool has_separate_stencil
;
868 bool must_use_separate_stencil
;
871 bool has_surface_tile_offset
;
873 bool has_negative_rhw_bug
;
877 bool use_resource_streamer
;
880 * Whether LRI can be used to write register values from the batch buffer.
882 bool can_do_pipelined_register_writes
;
885 * Some versions of Gen hardware don't do centroid interpolation correctly
886 * on unlit pixels, causing incorrect values for derivatives near triangle
887 * edges. Enabling this flag causes the fragment shader to use
888 * non-centroid interpolation for unlit pixels, at the expense of two extra
889 * fragment shader instructions.
891 bool needs_unlit_centroid_workaround
;
895 struct brw_state_flags pipelines
[BRW_NUM_PIPELINES
];
898 enum brw_pipeline last_pipeline
;
900 struct brw_cache cache
;
902 /** IDs for meta stencil blit shader programs. */
903 unsigned meta_stencil_blit_programs
[2];
905 /* Whether a meta-operation is in progress. */
906 bool meta_in_progress
;
908 /* Whether the last depth/stencil packets were both NULL. */
909 bool no_depth_or_stencil
;
911 /* The last PMA stall bits programmed. */
912 uint32_t pma_stall_bits
;
916 /** The value of gl_BaseVertex for the current _mesa_prim. */
919 /** The value of gl_BaseInstance for the current _mesa_prim. */
924 * Buffer and offset used for GL_ARB_shader_draw_parameters
925 * (for now, only gl_BaseVertex).
927 drm_intel_bo
*draw_params_bo
;
928 uint32_t draw_params_offset
;
931 * The value of gl_DrawID for the current _mesa_prim. This always comes
932 * in from it's own vertex buffer since it's not part of the indirect
936 drm_intel_bo
*draw_id_bo
;
937 uint32_t draw_id_offset
;
942 * For gl_NumWorkGroups: If num_work_groups_bo is non NULL, then it is
943 * an indirect call, and num_work_groups_offset is valid. Otherwise,
944 * num_work_groups is set based on glDispatchCompute.
946 drm_intel_bo
*num_work_groups_bo
;
947 GLintptr num_work_groups_offset
;
948 const GLuint
*num_work_groups
;
952 struct brw_vertex_element inputs
[VERT_ATTRIB_MAX
];
953 struct brw_vertex_buffer buffers
[VERT_ATTRIB_MAX
];
955 struct brw_vertex_element
*enabled
[VERT_ATTRIB_MAX
];
959 /* Summary of size and varying of active arrays, so we can check
960 * for changes to this state:
962 unsigned int min_index
, max_index
;
964 /* Offset from start of vertex buffer so we can avoid redefining
965 * the same VB packed over and over again.
967 unsigned int start_vertex_bias
;
970 * Certain vertex attribute formats aren't natively handled by the
971 * hardware and require special VS code to fix up their values.
973 * These bitfields indicate which workarounds are needed.
975 uint8_t attrib_wa_flags
[VERT_ATTRIB_MAX
];
980 * Index buffer for this draw_prims call.
982 * Updates are signaled by BRW_NEW_INDICES.
984 const struct _mesa_index_buffer
*ib
;
986 /* Updates are signaled by BRW_NEW_INDEX_BUFFER. */
990 /* Offset to index buffer index to use in CMD_3D_PRIM so that we can
991 * avoid re-uploading the IB packet over and over if we're actually
992 * referencing the same index buffer.
994 unsigned int start_vertex_offset
;
997 /* Active vertex program:
999 const struct gl_vertex_program
*vertex_program
;
1000 const struct gl_geometry_program
*geometry_program
;
1001 const struct gl_tess_ctrl_program
*tess_ctrl_program
;
1002 const struct gl_tess_eval_program
*tess_eval_program
;
1003 const struct gl_fragment_program
*fragment_program
;
1004 const struct gl_compute_program
*compute_program
;
1007 * Number of samples in ctx->DrawBuffer, updated by BRW_NEW_NUM_SAMPLES so
1008 * that we don't have to reemit that state every time we change FBOs.
1013 * Platform specific constants containing the maximum number of threads
1014 * for each pipeline stage.
1016 unsigned max_vs_threads
;
1017 unsigned max_hs_threads
;
1018 unsigned max_ds_threads
;
1019 unsigned max_gs_threads
;
1020 unsigned max_wm_threads
;
1021 unsigned max_cs_threads
;
1023 /* BRW_NEW_URB_ALLOCATIONS:
1026 GLuint vsize
; /* vertex size plus header in urb registers */
1027 GLuint gsize
; /* GS output size in urb registers */
1028 GLuint hsize
; /* Tessellation control output size in urb registers */
1029 GLuint dsize
; /* Tessellation evaluation output size in urb registers */
1030 GLuint csize
; /* constant buffer size in urb registers */
1031 GLuint sfsize
; /* setup data size in urb registers */
1035 GLuint min_vs_entries
; /* Minimum number of VS entries */
1036 GLuint max_vs_entries
; /* Maximum number of VS entries */
1037 GLuint max_hs_entries
; /* Maximum number of HS entries */
1038 GLuint max_ds_entries
; /* Maximum number of DS entries */
1039 GLuint max_gs_entries
; /* Maximum number of GS entries */
1041 GLuint nr_vs_entries
;
1042 GLuint nr_hs_entries
;
1043 GLuint nr_ds_entries
;
1044 GLuint nr_gs_entries
;
1045 GLuint nr_clip_entries
;
1046 GLuint nr_sf_entries
;
1047 GLuint nr_cs_entries
;
1057 * URB size in the current configuration. The units this is expressed
1058 * in are somewhat inconsistent, see brw_device_info::urb::size.
1060 * FINISHME: Represent the URB size consistently in KB on all platforms.
1064 /* True if the most recently sent _3DSTATE_URB message allocated
1065 * URB space for the GS.
1069 /* True if the most recently sent _3DSTATE_URB message allocated
1070 * URB space for the HS and DS.
1076 /* BRW_NEW_CURBE_OFFSETS:
1079 GLuint wm_start
; /**< pos of first wm const in CURBE buffer */
1080 GLuint wm_size
; /**< number of float[4] consts, multiple of 16 */
1088 * Pointer to the (intel_upload.c-generated) BO containing the uniforms
1089 * for upload to the CURBE.
1091 drm_intel_bo
*curbe_bo
;
1092 /** Offset within curbe_bo of space for current curbe entry */
1093 GLuint curbe_offset
;
1097 * Layout of vertex data exiting the geometry portion of the pipleine.
1098 * This comes from the last enabled shader stage (GS, DS, or VS).
1100 * BRW_NEW_VUE_MAP_GEOM_OUT is flagged when the VUE map changes.
1102 struct brw_vue_map vue_map_geom_out
;
1105 struct brw_stage_state base
;
1106 struct brw_vs_prog_data
*prog_data
;
1110 struct brw_stage_state base
;
1111 struct brw_tcs_prog_data
*prog_data
;
1114 * True if the 3DSTATE_HS command most recently emitted to the 3D
1115 * pipeline enabled the HS; false otherwise.
1121 struct brw_stage_state base
;
1122 struct brw_tes_prog_data
*prog_data
;
1125 * True if the 3DSTATE_DS command most recently emitted to the 3D
1126 * pipeline enabled the DS; false otherwise.
1132 struct brw_stage_state base
;
1133 struct brw_gs_prog_data
*prog_data
;
1136 * True if the 3DSTATE_GS command most recently emitted to the 3D
1137 * pipeline enabled the GS; false otherwise.
1143 struct brw_ff_gs_prog_data
*prog_data
;
1146 /** Offset in the program cache to the CLIP program pre-gen6 */
1147 uint32_t prog_offset
;
1148 uint32_t state_offset
;
1150 uint32_t bind_bo_offset
;
1152 * Surface offsets for the binding table. We only need surfaces to
1153 * implement transform feedback so BRW_MAX_SOL_BINDINGS is all that we
1154 * need in this case.
1156 uint32_t surf_offset
[BRW_MAX_SOL_BINDINGS
];
1160 struct brw_clip_prog_data
*prog_data
;
1162 /** Offset in the program cache to the CLIP program pre-gen6 */
1163 uint32_t prog_offset
;
1165 /* Offset in the batch to the CLIP state on pre-gen6. */
1166 uint32_t state_offset
;
1168 /* As of gen6, this is the offset in the batch to the CLIP VP,
1176 struct brw_sf_prog_data
*prog_data
;
1178 /** Offset in the program cache to the CLIP program pre-gen6 */
1179 uint32_t prog_offset
;
1180 uint32_t state_offset
;
1182 bool viewport_transform_enable
;
1186 struct brw_stage_state base
;
1187 struct brw_wm_prog_data
*prog_data
;
1192 * Buffer object used in place of multisampled null render targets on
1193 * Gen6. See brw_emit_null_surface_state().
1195 drm_intel_bo
*multisampled_null_render_target_bo
;
1196 uint32_t fast_clear_op
;
1202 struct brw_stage_state base
;
1203 struct brw_cs_prog_data
*prog_data
;
1206 /* RS hardware binding table */
1209 uint32_t next_offset
;
1213 uint32_t state_offset
;
1214 uint32_t blend_state_offset
;
1215 uint32_t depth_stencil_state_offset
;
1220 struct brw_query_object
*obj
;
1225 enum brw_predicate_state state
;
1230 /** A map from pipeline statistics counter IDs to MMIO addresses. */
1231 const int *statistics_registers
;
1233 /** The number of active monitors using OA counters. */
1237 * A buffer object storing OA counter snapshots taken at the start and
1238 * end of each batch (creating "bookends" around the batch).
1240 drm_intel_bo
*bookend_bo
;
1242 /** The number of snapshots written to bookend_bo. */
1243 int bookend_snapshots
;
1246 * An array of monitors whose results haven't yet been assembled based on
1247 * the data in buffer objects.
1249 * These may be active, or have already ended. However, the results
1250 * have not been requested.
1252 struct brw_perf_monitor_object
**unresolved
;
1253 int unresolved_elements
;
1254 int unresolved_array_size
;
1257 * Mapping from a uint32_t offset within an OA snapshot to the ID of
1258 * the counter which MI_REPORT_PERF_COUNT stores there.
1260 const int *oa_snapshot_layout
;
1262 /** Number of 32-bit entries in a hardware counter snapshot. */
1263 int entries_per_oa_snapshot
;
1266 int num_atoms
[BRW_NUM_PIPELINES
];
1267 const struct brw_tracked_state render_atoms
[76];
1268 const struct brw_tracked_state compute_atoms
[11];
1270 /* If (INTEL_DEBUG & DEBUG_BATCH) */
1274 enum aub_state_struct_type type
;
1276 } *state_batch_list
;
1277 int state_batch_count
;
1279 uint32_t render_target_format
[MESA_FORMAT_COUNT
];
1280 bool format_supported_as_render_target
[MESA_FORMAT_COUNT
];
1282 /* Interpolation modes, one byte per vue slot.
1283 * Used Gen4/5 by the clip|sf|wm stages. Ignored on Gen6+.
1285 struct interpolation_mode_map interpolation_mode
;
1287 /* PrimitiveRestart */
1290 bool enable_cut_index
;
1293 /** Computed depth/stencil/hiz state from the current attached
1294 * renderbuffers, valid only during the drawing state upload loop after
1295 * brw_workaround_depthstencil_alignment().
1298 struct intel_mipmap_tree
*depth_mt
;
1299 struct intel_mipmap_tree
*stencil_mt
;
1301 /* Inter-tile (page-aligned) byte offsets. */
1302 uint32_t depth_offset
, hiz_offset
, stencil_offset
;
1303 /* Intra-tile x,y offsets for drawing to depth/stencil/hiz */
1304 uint32_t tile_x
, tile_y
;
1307 uint32_t num_instances
;
1311 const struct brw_l3_config
*config
;
1318 enum shader_time_shader_type
*types
;
1319 struct shader_times
*cumulative
;
1325 struct brw_fast_clear_state
*fast_clear_state
;
1327 __DRIcontext
*driContext
;
1328 struct intel_screen
*intelScreen
;
1331 /*======================================================================
1334 void brwInitVtbl( struct brw_context
*brw
);
1337 extern void intelInitClearFuncs(struct dd_function_table
*functions
);
1339 /*======================================================================
1342 extern const char *const brw_vendor_string
;
1344 extern const char *brw_get_renderer_string(unsigned deviceID
);
1347 DRI_CONF_BO_REUSE_DISABLED
,
1348 DRI_CONF_BO_REUSE_ALL
1351 void intel_update_renderbuffers(__DRIcontext
*context
,
1352 __DRIdrawable
*drawable
);
1353 void intel_prepare_render(struct brw_context
*brw
);
1355 void intel_resolve_for_dri2_flush(struct brw_context
*brw
,
1356 __DRIdrawable
*drawable
);
1358 GLboolean
brwCreateContext(gl_api api
,
1359 const struct gl_config
*mesaVis
,
1360 __DRIcontext
*driContextPriv
,
1361 unsigned major_version
,
1362 unsigned minor_version
,
1366 void *sharedContextPrivate
);
1368 /*======================================================================
1371 struct gl_renderbuffer
*brw_get_rb_for_slice(struct brw_context
*brw
,
1372 struct intel_mipmap_tree
*mt
,
1373 unsigned level
, unsigned layer
,
1376 void brw_meta_updownsample(struct brw_context
*brw
,
1377 struct intel_mipmap_tree
*src
,
1378 struct intel_mipmap_tree
*dst
);
1380 void brw_meta_fbo_stencil_blit(struct brw_context
*brw
,
1381 struct gl_framebuffer
*read_fb
,
1382 struct gl_framebuffer
*draw_fb
,
1383 GLfloat srcX0
, GLfloat srcY0
,
1384 GLfloat srcX1
, GLfloat srcY1
,
1385 GLfloat dstX0
, GLfloat dstY0
,
1386 GLfloat dstX1
, GLfloat dstY1
);
1388 void brw_meta_stencil_updownsample(struct brw_context
*brw
,
1389 struct intel_mipmap_tree
*src
,
1390 struct intel_mipmap_tree
*dst
);
1392 bool brw_meta_fast_clear(struct brw_context
*brw
,
1393 struct gl_framebuffer
*fb
,
1395 bool partial_clear
);
1398 brw_meta_resolve_color(struct brw_context
*brw
,
1399 struct intel_mipmap_tree
*mt
);
1401 brw_meta_fast_clear_free(struct brw_context
*brw
);
1404 /*======================================================================
1407 void brw_get_depthstencil_tile_masks(struct intel_mipmap_tree
*depth_mt
,
1408 uint32_t depth_level
,
1409 uint32_t depth_layer
,
1410 struct intel_mipmap_tree
*stencil_mt
,
1411 uint32_t *out_tile_mask_x
,
1412 uint32_t *out_tile_mask_y
);
1413 void brw_workaround_depthstencil_alignment(struct brw_context
*brw
,
1414 GLbitfield clear_mask
);
1416 /* brw_object_purgeable.c */
1417 void brw_init_object_purgeable_functions(struct dd_function_table
*functions
);
1419 /*======================================================================
1422 void brw_init_common_queryobj_functions(struct dd_function_table
*functions
);
1423 void gen4_init_queryobj_functions(struct dd_function_table
*functions
);
1424 void brw_emit_query_begin(struct brw_context
*brw
);
1425 void brw_emit_query_end(struct brw_context
*brw
);
1427 /** gen6_queryobj.c */
1428 void gen6_init_queryobj_functions(struct dd_function_table
*functions
);
1429 void brw_write_timestamp(struct brw_context
*brw
, drm_intel_bo
*bo
, int idx
);
1430 void brw_write_depth_count(struct brw_context
*brw
, drm_intel_bo
*bo
, int idx
);
1431 void brw_store_register_mem64(struct brw_context
*brw
,
1432 drm_intel_bo
*bo
, uint32_t reg
, int idx
);
1434 /** brw_conditional_render.c */
1435 void brw_init_conditional_render_functions(struct dd_function_table
*functions
);
1436 bool brw_check_conditional_render(struct brw_context
*brw
);
1438 /** intel_batchbuffer.c */
1439 void brw_load_register_mem(struct brw_context
*brw
,
1442 uint32_t read_domains
, uint32_t write_domain
,
1444 void brw_load_register_mem64(struct brw_context
*brw
,
1447 uint32_t read_domains
, uint32_t write_domain
,
1450 /*======================================================================
1453 void brw_debug_batch(struct brw_context
*brw
);
1454 void brw_annotate_aub(struct brw_context
*brw
);
1456 /*======================================================================
1459 void brw_validate_textures( struct brw_context
*brw
);
1462 /*======================================================================
1466 key_debug(struct brw_context
*brw
, const char *name
, int a
, int b
)
1469 perf_debug(" %s %d->%d\n", name
, a
, b
);
1475 void brwInitFragProgFuncs( struct dd_function_table
*functions
);
1477 /* Per-thread scratch space is a power-of-two multiple of 1KB. */
1479 brw_get_scratch_size(int size
)
1481 return util_next_power_of_two(size
| 1023);
1483 void brw_get_scratch_bo(struct brw_context
*brw
,
1484 drm_intel_bo
**scratch_bo
, int size
);
1485 void brw_init_shader_time(struct brw_context
*brw
);
1486 int brw_get_shader_time_index(struct brw_context
*brw
,
1487 struct gl_shader_program
*shader_prog
,
1488 struct gl_program
*prog
,
1489 enum shader_time_shader_type type
);
1490 void brw_collect_and_report_shader_time(struct brw_context
*brw
);
1491 void brw_destroy_shader_time(struct brw_context
*brw
);
1495 void brw_upload_urb_fence(struct brw_context
*brw
);
1499 void brw_upload_cs_urb_state(struct brw_context
*brw
);
1501 /* brw_fs_reg_allocate.cpp
1503 void brw_fs_alloc_reg_sets(struct brw_compiler
*compiler
);
1505 /* brw_vec4_reg_allocate.cpp */
1506 void brw_vec4_alloc_reg_set(struct brw_compiler
*compiler
);
1509 int brw_disassemble_inst(FILE *file
, const struct brw_device_info
*devinfo
,
1510 struct brw_inst
*inst
, bool is_compacted
);
1513 gl_clip_plane
*brw_select_clip_planes(struct gl_context
*ctx
);
1515 /* brw_draw_upload.c */
1516 unsigned brw_get_vertex_surface_type(struct brw_context
*brw
,
1517 const struct gl_client_array
*glarray
);
1519 static inline unsigned
1520 brw_get_index_type(GLenum type
)
1522 assert((type
== GL_UNSIGNED_BYTE
)
1523 || (type
== GL_UNSIGNED_SHORT
)
1524 || (type
== GL_UNSIGNED_INT
));
1526 /* The possible values for type are GL_UNSIGNED_BYTE (0x1401),
1527 * GL_UNSIGNED_SHORT (0x1403), and GL_UNSIGNED_INT (0x1405) which we want
1528 * to map to scale factors of 0, 1, and 2, respectively. These scale
1529 * factors are then left-shfited by 8 to be in the correct position in the
1530 * CMD_INDEX_BUFFER packet.
1532 * Subtracting 0x1401 gives 0, 2, and 4. Shifting left by 7 afterwards
1533 * gives 0x00000000, 0x00000100, and 0x00000200. These just happen to be
1534 * the values the need to be written in the CMD_INDEX_BUFFER packet.
1536 return (type
- 0x1401) << 7;
1539 void brw_prepare_vertices(struct brw_context
*brw
);
1541 /* brw_wm_surface_state.c */
1542 void brw_init_surface_formats(struct brw_context
*brw
);
1543 void brw_create_constant_surface(struct brw_context
*brw
,
1547 uint32_t *out_offset
);
1548 void brw_create_buffer_surface(struct brw_context
*brw
,
1552 uint32_t *out_offset
);
1553 void brw_update_buffer_texture_surface(struct gl_context
*ctx
,
1555 uint32_t *surf_offset
);
1557 brw_update_sol_surface(struct brw_context
*brw
,
1558 struct gl_buffer_object
*buffer_obj
,
1559 uint32_t *out_offset
, unsigned num_vector_components
,
1560 unsigned stride_dwords
, unsigned offset_dwords
);
1561 void brw_upload_ubo_surfaces(struct brw_context
*brw
,
1562 struct gl_shader
*shader
,
1563 struct brw_stage_state
*stage_state
,
1564 struct brw_stage_prog_data
*prog_data
);
1565 void brw_upload_abo_surfaces(struct brw_context
*brw
,
1566 struct gl_shader
*shader
,
1567 struct brw_stage_state
*stage_state
,
1568 struct brw_stage_prog_data
*prog_data
);
1569 void brw_upload_image_surfaces(struct brw_context
*brw
,
1570 struct gl_shader
*shader
,
1571 struct brw_stage_state
*stage_state
,
1572 struct brw_stage_prog_data
*prog_data
);
1574 /* brw_surface_formats.c */
1575 bool brw_render_target_supported(struct brw_context
*brw
,
1576 struct gl_renderbuffer
*rb
);
1577 bool brw_losslessly_compressible_format(const struct brw_context
*brw
,
1578 uint32_t brw_format
);
1579 uint32_t brw_depth_format(struct brw_context
*brw
, mesa_format format
);
1580 mesa_format
brw_lower_mesa_image_format(const struct brw_device_info
*devinfo
,
1581 mesa_format format
);
1583 /* brw_performance_monitor.c */
1584 void brw_init_performance_monitors(struct brw_context
*brw
);
1585 void brw_dump_perf_monitors(struct brw_context
*brw
);
1586 void brw_perf_monitor_new_batch(struct brw_context
*brw
);
1587 void brw_perf_monitor_finish_batch(struct brw_context
*brw
);
1589 /* intel_buffer_objects.c */
1590 int brw_bo_map(struct brw_context
*brw
, drm_intel_bo
*bo
, int write_enable
,
1591 const char *bo_name
);
1592 int brw_bo_map_gtt(struct brw_context
*brw
, drm_intel_bo
*bo
,
1593 const char *bo_name
);
1595 /* intel_extensions.c */
1596 extern void intelInitExtensions(struct gl_context
*ctx
);
1599 extern int intel_translate_shadow_compare_func(GLenum func
);
1600 extern int intel_translate_compare_func(GLenum func
);
1601 extern int intel_translate_stencil_op(GLenum op
);
1602 extern int intel_translate_logic_op(GLenum opcode
);
1604 /* intel_syncobj.c */
1605 void intel_init_syncobj_functions(struct dd_function_table
*functions
);
1608 struct gl_transform_feedback_object
*
1609 brw_new_transform_feedback(struct gl_context
*ctx
, GLuint name
);
1611 brw_delete_transform_feedback(struct gl_context
*ctx
,
1612 struct gl_transform_feedback_object
*obj
);
1614 brw_begin_transform_feedback(struct gl_context
*ctx
, GLenum mode
,
1615 struct gl_transform_feedback_object
*obj
);
1617 brw_end_transform_feedback(struct gl_context
*ctx
,
1618 struct gl_transform_feedback_object
*obj
);
1620 brw_get_transform_feedback_vertex_count(struct gl_context
*ctx
,
1621 struct gl_transform_feedback_object
*obj
,
1624 /* gen7_sol_state.c */
1626 gen7_begin_transform_feedback(struct gl_context
*ctx
, GLenum mode
,
1627 struct gl_transform_feedback_object
*obj
);
1629 gen7_end_transform_feedback(struct gl_context
*ctx
,
1630 struct gl_transform_feedback_object
*obj
);
1632 gen7_pause_transform_feedback(struct gl_context
*ctx
,
1633 struct gl_transform_feedback_object
*obj
);
1635 gen7_resume_transform_feedback(struct gl_context
*ctx
,
1636 struct gl_transform_feedback_object
*obj
);
1638 /* brw_blorp_blit.cpp */
1640 brw_blorp_framebuffer(struct brw_context
*brw
,
1641 struct gl_framebuffer
*readFb
,
1642 struct gl_framebuffer
*drawFb
,
1643 GLint srcX0
, GLint srcY0
, GLint srcX1
, GLint srcY1
,
1644 GLint dstX0
, GLint dstY0
, GLint dstX1
, GLint dstY1
,
1645 GLbitfield mask
, GLenum filter
);
1648 brw_blorp_copytexsubimage(struct brw_context
*brw
,
1649 struct gl_renderbuffer
*src_rb
,
1650 struct gl_texture_image
*dst_image
,
1652 int srcX0
, int srcY0
,
1653 int dstX0
, int dstY0
,
1654 int width
, int height
);
1656 /* gen6_multisample_state.c */
1658 gen6_determine_sample_mask(struct brw_context
*brw
);
1661 gen6_emit_3dstate_multisample(struct brw_context
*brw
,
1662 unsigned num_samples
);
1664 gen6_emit_3dstate_sample_mask(struct brw_context
*brw
, unsigned mask
);
1666 gen6_get_sample_position(struct gl_context
*ctx
,
1667 struct gl_framebuffer
*fb
,
1671 gen6_set_sample_maps(struct gl_context
*ctx
);
1673 /* gen8_multisample_state.c */
1674 void gen8_emit_3dstate_multisample(struct brw_context
*brw
, unsigned num_samp
);
1675 void gen8_emit_3dstate_sample_pattern(struct brw_context
*brw
);
1679 gen7_emit_push_constant_state(struct brw_context
*brw
, unsigned vs_size
,
1680 unsigned hs_size
, unsigned ds_size
,
1681 unsigned gs_size
, unsigned fs_size
);
1684 gen7_emit_urb_state(struct brw_context
*brw
,
1685 unsigned nr_vs_entries
,
1686 unsigned vs_size
, unsigned vs_start
,
1687 unsigned nr_hs_entries
,
1688 unsigned hs_size
, unsigned hs_start
,
1689 unsigned nr_ds_entries
,
1690 unsigned ds_size
, unsigned ds_start
,
1691 unsigned nr_gs_entries
,
1692 unsigned gs_size
, unsigned gs_start
);
1697 brw_get_graphics_reset_status(struct gl_context
*ctx
);
1701 brw_init_compute_functions(struct dd_function_table
*functions
);
1703 /*======================================================================
1704 * Inline conversion functions. These are better-typed than the
1705 * macros used previously:
1707 static inline struct brw_context
*
1708 brw_context( struct gl_context
*ctx
)
1710 return (struct brw_context
*)ctx
;
1713 static inline struct brw_vertex_program
*
1714 brw_vertex_program(struct gl_vertex_program
*p
)
1716 return (struct brw_vertex_program
*) p
;
1719 static inline const struct brw_vertex_program
*
1720 brw_vertex_program_const(const struct gl_vertex_program
*p
)
1722 return (const struct brw_vertex_program
*) p
;
1725 static inline struct brw_tess_ctrl_program
*
1726 brw_tess_ctrl_program(struct gl_tess_ctrl_program
*p
)
1728 return (struct brw_tess_ctrl_program
*) p
;
1731 static inline struct brw_tess_eval_program
*
1732 brw_tess_eval_program(struct gl_tess_eval_program
*p
)
1734 return (struct brw_tess_eval_program
*) p
;
1737 static inline struct brw_geometry_program
*
1738 brw_geometry_program(struct gl_geometry_program
*p
)
1740 return (struct brw_geometry_program
*) p
;
1743 static inline struct brw_fragment_program
*
1744 brw_fragment_program(struct gl_fragment_program
*p
)
1746 return (struct brw_fragment_program
*) p
;
1749 static inline const struct brw_fragment_program
*
1750 brw_fragment_program_const(const struct gl_fragment_program
*p
)
1752 return (const struct brw_fragment_program
*) p
;
1755 static inline struct brw_compute_program
*
1756 brw_compute_program(struct gl_compute_program
*p
)
1758 return (struct brw_compute_program
*) p
;
1762 * Pre-gen6, the register file of the EUs was shared between threads,
1763 * and each thread used some subset allocated on a 16-register block
1764 * granularity. The unit states wanted these block counts.
1767 brw_register_blocks(int reg_count
)
1769 return ALIGN(reg_count
, 16) / 16 - 1;
1772 static inline uint32_t
1773 brw_program_reloc(struct brw_context
*brw
, uint32_t state_offset
,
1774 uint32_t prog_offset
)
1776 if (brw
->gen
>= 5) {
1777 /* Using state base address. */
1781 drm_intel_bo_emit_reloc(brw
->batch
.bo
,
1785 I915_GEM_DOMAIN_INSTRUCTION
, 0);
1787 return brw
->cache
.bo
->offset64
+ prog_offset
;
1790 bool brw_do_cubemap_normalize(struct exec_list
*instructions
);
1791 bool brw_lower_texture_gradients(struct brw_context
*brw
,
1792 struct exec_list
*instructions
);
1793 bool brw_do_lower_unnormalized_offset(struct exec_list
*instructions
);
1795 struct opcode_desc
{
1801 extern const struct opcode_desc opcode_descs
[128];
1802 extern const char * const conditional_modifier
[16];
1803 extern const char *const pred_ctrl_align16
[16];
1806 brw_emit_depthbuffer(struct brw_context
*brw
);
1809 brw_emit_depth_stencil_hiz(struct brw_context
*brw
,
1810 struct intel_mipmap_tree
*depth_mt
,
1811 uint32_t depth_offset
, uint32_t depthbuffer_format
,
1812 uint32_t depth_surface_type
,
1813 struct intel_mipmap_tree
*stencil_mt
,
1814 bool hiz
, bool separate_stencil
,
1815 uint32_t width
, uint32_t height
,
1816 uint32_t tile_x
, uint32_t tile_y
);
1819 gen6_emit_depth_stencil_hiz(struct brw_context
*brw
,
1820 struct intel_mipmap_tree
*depth_mt
,
1821 uint32_t depth_offset
, uint32_t depthbuffer_format
,
1822 uint32_t depth_surface_type
,
1823 struct intel_mipmap_tree
*stencil_mt
,
1824 bool hiz
, bool separate_stencil
,
1825 uint32_t width
, uint32_t height
,
1826 uint32_t tile_x
, uint32_t tile_y
);
1829 gen7_emit_depth_stencil_hiz(struct brw_context
*brw
,
1830 struct intel_mipmap_tree
*depth_mt
,
1831 uint32_t depth_offset
, uint32_t depthbuffer_format
,
1832 uint32_t depth_surface_type
,
1833 struct intel_mipmap_tree
*stencil_mt
,
1834 bool hiz
, bool separate_stencil
,
1835 uint32_t width
, uint32_t height
,
1836 uint32_t tile_x
, uint32_t tile_y
);
1838 gen8_emit_depth_stencil_hiz(struct brw_context
*brw
,
1839 struct intel_mipmap_tree
*depth_mt
,
1840 uint32_t depth_offset
, uint32_t depthbuffer_format
,
1841 uint32_t depth_surface_type
,
1842 struct intel_mipmap_tree
*stencil_mt
,
1843 bool hiz
, bool separate_stencil
,
1844 uint32_t width
, uint32_t height
,
1845 uint32_t tile_x
, uint32_t tile_y
);
1847 void gen8_hiz_exec(struct brw_context
*brw
, struct intel_mipmap_tree
*mt
,
1848 unsigned int level
, unsigned int layer
, enum gen6_hiz_op op
);
1850 uint32_t get_hw_prim_for_gl_prim(int mode
);
1853 gen6_upload_push_constants(struct brw_context
*brw
,
1854 const struct gl_program
*prog
,
1855 const struct brw_stage_prog_data
*prog_data
,
1856 struct brw_stage_state
*stage_state
,
1857 enum aub_state_struct_type type
);
1860 gen9_use_linear_1d_layout(const struct brw_context
*brw
,
1861 const struct intel_mipmap_tree
*mt
);
1863 /* brw_pipe_control.c */
1864 int brw_init_pipe_control(struct brw_context
*brw
,
1865 const struct brw_device_info
*info
);
1866 void brw_fini_pipe_control(struct brw_context
*brw
);
1868 void brw_emit_pipe_control_flush(struct brw_context
*brw
, uint32_t flags
);
1869 void brw_emit_pipe_control_write(struct brw_context
*brw
, uint32_t flags
,
1870 drm_intel_bo
*bo
, uint32_t offset
,
1871 uint32_t imm_lower
, uint32_t imm_upper
);
1872 void brw_emit_mi_flush(struct brw_context
*brw
);
1873 void brw_emit_post_sync_nonzero_flush(struct brw_context
*brw
);
1874 void brw_emit_depth_stall_flushes(struct brw_context
*brw
);
1875 void gen7_emit_vs_workaround_flush(struct brw_context
*brw
);
1876 void gen7_emit_cs_stall_flush(struct brw_context
*brw
);