2 Copyright (C) Intel Corp. 2006. All Rights Reserved.
3 Intel funded Tungsten Graphics to
4 develop this 3D driver.
6 Permission is hereby granted, free of charge, to any person obtaining
7 a copy of this software and associated documentation files (the
8 "Software"), to deal in the Software without restriction, including
9 without limitation the rights to use, copy, modify, merge, publish,
10 distribute, sublicense, and/or sell copies of the Software, and to
11 permit persons to whom the Software is furnished to do so, subject to
12 the following conditions:
14 The above copyright notice and this permission notice (including the
15 next paragraph) shall be included in all copies or substantial
16 portions of the Software.
18 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
19 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
20 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
21 IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
22 LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
23 OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
24 WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
26 **********************************************************************/
29 * Keith Whitwell <keithw@vmware.com>
38 #include "brw_defines.h"
40 #include "intel_asm_annotation.h"
46 #define BRW_EU_MAX_INSN_STACK 5
48 /* A helper for accessing the last instruction emitted. This makes it easy
49 * to set various bits on an instruction without having to create temporary
50 * variable and assign the emitted instruction to those.
52 #define brw_last_inst (&p->store[p->nr_insn - 1])
58 unsigned int next_insn_offset
;
62 /* Allow clients to push/pop instruction state:
64 brw_inst stack
[BRW_EU_MAX_INSN_STACK
];
65 bool compressed_stack
[BRW_EU_MAX_INSN_STACK
];
68 bool single_program_flow
;
69 const struct brw_device_info
*devinfo
;
71 /* Control flow stacks:
72 * - if_stack contains IF and ELSE instructions which must be patched
73 * (and popped) once the matching ENDIF instruction is encountered.
75 * Just store the instruction pointer(an index).
79 int if_stack_array_size
;
82 * loop_stack contains the instruction pointers of the starts of loops which
83 * must be patched (and popped) once the matching WHILE instruction is
88 * pre-gen6, the BREAK and CONT instructions had to tell how many IF/ENDIF
89 * blocks they were popping out of, to fix up the mask stack. This tracks
90 * the IF/ENDIF nesting in each current nested loop level.
92 int *if_depth_in_loop
;
94 int loop_stack_array_size
;
97 void brw_pop_insn_state( struct brw_codegen
*p
);
98 void brw_push_insn_state( struct brw_codegen
*p
);
99 void brw_set_default_exec_size(struct brw_codegen
*p
, unsigned value
);
100 void brw_set_default_mask_control( struct brw_codegen
*p
, unsigned value
);
101 void brw_set_default_saturate( struct brw_codegen
*p
, bool enable
);
102 void brw_set_default_access_mode( struct brw_codegen
*p
, unsigned access_mode
);
103 void brw_inst_set_compression(const struct brw_device_info
*devinfo
,
104 brw_inst
*inst
, bool on
);
105 void brw_set_default_compression(struct brw_codegen
*p
, bool on
);
106 void brw_inst_set_group(const struct brw_device_info
*devinfo
,
107 brw_inst
*inst
, unsigned group
);
108 void brw_set_default_group(struct brw_codegen
*p
, unsigned group
);
109 void brw_set_default_compression_control(struct brw_codegen
*p
, enum brw_compression c
);
110 void brw_set_default_predicate_control( struct brw_codegen
*p
, unsigned pc
);
111 void brw_set_default_predicate_inverse(struct brw_codegen
*p
, bool predicate_inverse
);
112 void brw_set_default_flag_reg(struct brw_codegen
*p
, int reg
, int subreg
);
113 void brw_set_default_acc_write_control(struct brw_codegen
*p
, unsigned value
);
115 void brw_init_codegen(const struct brw_device_info
*, struct brw_codegen
*p
,
117 void brw_disassemble(const struct brw_device_info
*devinfo
, void *assembly
,
118 int start
, int end
, FILE *out
);
119 const unsigned *brw_get_program( struct brw_codegen
*p
, unsigned *sz
);
121 brw_inst
*brw_next_insn(struct brw_codegen
*p
, unsigned opcode
);
122 void brw_set_dest(struct brw_codegen
*p
, brw_inst
*insn
, struct brw_reg dest
);
123 void brw_set_src0(struct brw_codegen
*p
, brw_inst
*insn
, struct brw_reg reg
);
125 void gen6_resolve_implied_move(struct brw_codegen
*p
,
127 unsigned msg_reg_nr
);
129 /* Helpers for regular instructions:
132 brw_inst *brw_##OP(struct brw_codegen *p, \
133 struct brw_reg dest, \
134 struct brw_reg src0);
137 brw_inst *brw_##OP(struct brw_codegen *p, \
138 struct brw_reg dest, \
139 struct brw_reg src0, \
140 struct brw_reg src1);
143 brw_inst *brw_##OP(struct brw_codegen *p, \
144 struct brw_reg dest, \
145 struct brw_reg src0, \
146 struct brw_reg src1, \
147 struct brw_reg src2);
150 void brw_##OP(struct brw_codegen *p, struct brw_reg dest, struct brw_reg src0);
200 /* Helpers for SEND instruction:
202 void brw_set_sampler_message(struct brw_codegen
*p
,
204 unsigned binding_table_index
,
207 unsigned response_length
,
209 unsigned header_present
,
211 unsigned return_format
);
213 void brw_set_message_descriptor(struct brw_codegen
*p
,
215 enum brw_message_target sfid
,
217 unsigned response_length
,
221 void brw_set_dp_read_message(struct brw_codegen
*p
,
223 unsigned binding_table_index
,
224 unsigned msg_control
,
226 unsigned target_cache
,
229 unsigned response_length
);
231 void brw_set_dp_write_message(struct brw_codegen
*p
,
233 unsigned binding_table_index
,
234 unsigned msg_control
,
238 unsigned last_render_target
,
239 unsigned response_length
,
240 unsigned end_of_thread
,
241 unsigned send_commit_msg
);
243 void brw_urb_WRITE(struct brw_codegen
*p
,
247 enum brw_urb_write_flags flags
,
249 unsigned response_length
,
254 * Send message to shared unit \p sfid with a possibly indirect descriptor \p
255 * desc. If \p desc is not an immediate it will be transparently loaded to an
256 * address register using an OR instruction. The returned instruction can be
257 * passed as argument to the usual brw_set_*_message() functions in order to
258 * specify any additional descriptor bits -- If \p desc is an immediate this
259 * will be the SEND instruction itself, otherwise it will be the OR
263 brw_send_indirect_message(struct brw_codegen
*p
,
266 struct brw_reg payload
,
267 struct brw_reg desc
);
269 void brw_ff_sync(struct brw_codegen
*p
,
274 unsigned response_length
,
277 void brw_svb_write(struct brw_codegen
*p
,
281 unsigned binding_table_index
,
282 bool send_commit_msg
);
284 void brw_fb_WRITE(struct brw_codegen
*p
,
285 struct brw_reg payload
,
286 struct brw_reg implied_header
,
287 unsigned msg_control
,
288 unsigned binding_table_index
,
290 unsigned response_length
,
292 bool last_render_target
,
293 bool header_present
);
295 void brw_SAMPLE(struct brw_codegen
*p
,
299 unsigned binding_table_index
,
302 unsigned response_length
,
304 unsigned header_present
,
306 unsigned return_format
);
308 void brw_adjust_sampler_state_pointer(struct brw_codegen
*p
,
309 struct brw_reg header
,
310 struct brw_reg sampler_index
);
312 void gen4_math(struct brw_codegen
*p
,
317 unsigned precision
);
319 void gen6_math(struct brw_codegen
*p
,
323 struct brw_reg src1
);
325 void brw_oword_block_read(struct brw_codegen
*p
,
329 uint32_t bind_table_index
);
331 unsigned brw_scratch_surface_idx(const struct brw_codegen
*p
);
333 void brw_oword_block_read_scratch(struct brw_codegen
*p
,
339 void brw_oword_block_write_scratch(struct brw_codegen
*p
,
344 void gen7_block_read_scratch(struct brw_codegen
*p
,
349 void brw_shader_time_add(struct brw_codegen
*p
,
350 struct brw_reg payload
,
351 uint32_t surf_index
);
354 * Return the generation-specific jump distance scaling factor.
356 * Given the number of instructions to jump, we need to scale by
357 * some number to obtain the actual jump distance to program in an
360 static inline unsigned
361 brw_jump_scale(const struct brw_device_info
*devinfo
)
363 /* Broadwell measures jump targets in bytes. */
364 if (devinfo
->gen
>= 8)
367 /* Ironlake and later measure jump targets in 64-bit data chunks (in order
368 * (to support compaction), so each 128-bit instruction requires 2 chunks.
370 if (devinfo
->gen
>= 5)
373 /* Gen4 simply uses the number of 128-bit instructions. */
377 void brw_barrier(struct brw_codegen
*p
, struct brw_reg src
);
379 /* If/else/endif. Works by manipulating the execution flags on each
382 brw_inst
*brw_IF(struct brw_codegen
*p
, unsigned execute_size
);
383 brw_inst
*gen6_IF(struct brw_codegen
*p
, enum brw_conditional_mod conditional
,
384 struct brw_reg src0
, struct brw_reg src1
);
386 void brw_ELSE(struct brw_codegen
*p
);
387 void brw_ENDIF(struct brw_codegen
*p
);
391 brw_inst
*brw_DO(struct brw_codegen
*p
, unsigned execute_size
);
393 brw_inst
*brw_WHILE(struct brw_codegen
*p
);
395 brw_inst
*brw_BREAK(struct brw_codegen
*p
);
396 brw_inst
*brw_CONT(struct brw_codegen
*p
);
397 brw_inst
*gen6_HALT(struct brw_codegen
*p
);
401 void brw_land_fwd_jump(struct brw_codegen
*p
, int jmp_insn_idx
);
403 brw_inst
*brw_JMPI(struct brw_codegen
*p
, struct brw_reg index
,
404 unsigned predicate_control
);
406 void brw_NOP(struct brw_codegen
*p
);
408 void brw_WAIT(struct brw_codegen
*p
);
410 /* Special case: there is never a destination, execution size will be
413 void brw_CMP(struct brw_codegen
*p
,
415 unsigned conditional
,
417 struct brw_reg src1
);
420 brw_untyped_atomic(struct brw_codegen
*p
,
422 struct brw_reg payload
,
423 struct brw_reg surface
,
426 bool response_expected
);
429 brw_untyped_surface_read(struct brw_codegen
*p
,
431 struct brw_reg payload
,
432 struct brw_reg surface
,
434 unsigned num_channels
);
437 brw_untyped_surface_write(struct brw_codegen
*p
,
438 struct brw_reg payload
,
439 struct brw_reg surface
,
441 unsigned num_channels
);
444 brw_typed_atomic(struct brw_codegen
*p
,
446 struct brw_reg payload
,
447 struct brw_reg surface
,
450 bool response_expected
);
453 brw_typed_surface_read(struct brw_codegen
*p
,
455 struct brw_reg payload
,
456 struct brw_reg surface
,
458 unsigned num_channels
);
461 brw_typed_surface_write(struct brw_codegen
*p
,
462 struct brw_reg payload
,
463 struct brw_reg surface
,
465 unsigned num_channels
);
468 brw_memory_fence(struct brw_codegen
*p
,
472 brw_pixel_interpolator_query(struct brw_codegen
*p
,
479 unsigned response_length
);
482 brw_find_live_channel(struct brw_codegen
*p
,
486 brw_broadcast(struct brw_codegen
*p
,
491 /***********************************************************************
495 void brw_copy_indirect_to_indirect(struct brw_codegen
*p
,
496 struct brw_indirect dst_ptr
,
497 struct brw_indirect src_ptr
,
500 void brw_copy_from_indirect(struct brw_codegen
*p
,
502 struct brw_indirect ptr
,
505 void brw_copy4(struct brw_codegen
*p
,
510 void brw_copy8(struct brw_codegen
*p
,
515 void brw_math_invert( struct brw_codegen
*p
,
519 void brw_set_src1(struct brw_codegen
*p
, brw_inst
*insn
, struct brw_reg reg
);
521 void brw_set_uip_jip(struct brw_codegen
*p
);
523 enum brw_conditional_mod
brw_negate_cmod(uint32_t cmod
);
524 enum brw_conditional_mod
brw_swap_cmod(uint32_t cmod
);
526 /* brw_eu_compact.c */
527 void brw_init_compaction_tables(const struct brw_device_info
*devinfo
);
528 void brw_compact_instructions(struct brw_codegen
*p
, int start_offset
,
529 int num_annotations
, struct annotation
*annotation
);
530 void brw_uncompact_instruction(const struct brw_device_info
*devinfo
,
531 brw_inst
*dst
, brw_compact_inst
*src
);
532 bool brw_try_compact_instruction(const struct brw_device_info
*devinfo
,
533 brw_compact_inst
*dst
, brw_inst
*src
);
535 void brw_debug_compact_uncompact(const struct brw_device_info
*devinfo
,
536 brw_inst
*orig
, brw_inst
*uncompacted
);
538 /* brw_eu_validate.c */
539 bool brw_validate_instructions(const struct brw_codegen
*p
, int start_offset
,
540 struct annotation_info
*annotation
);
543 next_offset(const struct brw_device_info
*devinfo
, void *store
, int offset
)
545 brw_inst
*insn
= (brw_inst
*)((char *)store
+ offset
);
547 if (brw_inst_cmpt_control(devinfo
, insn
))
554 /* The union is an implementation detail used by brw_opcode_desc() to handle
555 * opcodes that have been reused for different instructions across hardware
558 * The gens field acts as a tag. If it is non-zero, name points to a string
559 * containing the instruction mnemonic. If it is zero, the table field is
560 * valid and either points to a secondary opcode_desc table with 'size'
561 * elements or is NULL and no such instruction exists for the opcode.
569 const struct opcode_desc
*table
;
577 const struct opcode_desc
*
578 brw_opcode_desc(const struct brw_device_info
*devinfo
, enum opcode opcode
);
581 is_3src(const struct brw_device_info
*devinfo
, enum opcode opcode
)
583 const struct opcode_desc
*desc
= brw_opcode_desc(devinfo
, opcode
);
584 return desc
&& desc
->nsrc
== 3;
587 /** Maximum SEND message length */
588 #define BRW_MAX_MSG_LENGTH 15
590 /** First MRF register used by pull loads */
591 #define FIRST_SPILL_MRF(gen) ((gen) == 6 ? 21 : 13)
593 /** First MRF register used by spills */
594 #define FIRST_PULL_LOAD_MRF(gen) ((gen) == 6 ? 16 : 13)