2 * Copyright © 2010 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
26 * This file drives the GLSL IR -> LIR translation, contains the
27 * optimizations on the LIR, and drives the generation of native code
31 #include "main/macros.h"
32 #include "brw_context.h"
37 #include "brw_vec4_gs_visitor.h"
39 #include "brw_program.h"
40 #include "brw_dead_control_flow.h"
41 #include "compiler/glsl_types.h"
46 fs_inst::init(enum opcode opcode
, uint8_t exec_size
, const fs_reg
&dst
,
47 const fs_reg
*src
, unsigned sources
)
49 memset(this, 0, sizeof(*this));
51 this->src
= new fs_reg
[MAX2(sources
, 3)];
52 for (unsigned i
= 0; i
< sources
; i
++)
53 this->src
[i
] = src
[i
];
55 this->opcode
= opcode
;
57 this->sources
= sources
;
58 this->exec_size
= exec_size
;
60 assert(dst
.file
!= IMM
&& dst
.file
!= UNIFORM
);
62 assert(this->exec_size
!= 0);
64 this->conditional_mod
= BRW_CONDITIONAL_NONE
;
66 /* This will be the case for almost all instructions. */
73 this->regs_written
= DIV_ROUND_UP(dst
.component_size(exec_size
),
77 this->regs_written
= 0;
81 unreachable("Invalid destination register file");
84 this->writes_accumulator
= false;
89 init(BRW_OPCODE_NOP
, 8, dst
, NULL
, 0);
92 fs_inst::fs_inst(enum opcode opcode
, uint8_t exec_size
)
94 init(opcode
, exec_size
, reg_undef
, NULL
, 0);
97 fs_inst::fs_inst(enum opcode opcode
, uint8_t exec_size
, const fs_reg
&dst
)
99 init(opcode
, exec_size
, dst
, NULL
, 0);
102 fs_inst::fs_inst(enum opcode opcode
, uint8_t exec_size
, const fs_reg
&dst
,
105 const fs_reg src
[1] = { src0
};
106 init(opcode
, exec_size
, dst
, src
, 1);
109 fs_inst::fs_inst(enum opcode opcode
, uint8_t exec_size
, const fs_reg
&dst
,
110 const fs_reg
&src0
, const fs_reg
&src1
)
112 const fs_reg src
[2] = { src0
, src1
};
113 init(opcode
, exec_size
, dst
, src
, 2);
116 fs_inst::fs_inst(enum opcode opcode
, uint8_t exec_size
, const fs_reg
&dst
,
117 const fs_reg
&src0
, const fs_reg
&src1
, const fs_reg
&src2
)
119 const fs_reg src
[3] = { src0
, src1
, src2
};
120 init(opcode
, exec_size
, dst
, src
, 3);
123 fs_inst::fs_inst(enum opcode opcode
, uint8_t exec_width
, const fs_reg
&dst
,
124 const fs_reg src
[], unsigned sources
)
126 init(opcode
, exec_width
, dst
, src
, sources
);
129 fs_inst::fs_inst(const fs_inst
&that
)
131 memcpy(this, &that
, sizeof(that
));
133 this->src
= new fs_reg
[MAX2(that
.sources
, 3)];
135 for (unsigned i
= 0; i
< that
.sources
; i
++)
136 this->src
[i
] = that
.src
[i
];
145 fs_inst::resize_sources(uint8_t num_sources
)
147 if (this->sources
!= num_sources
) {
148 fs_reg
*src
= new fs_reg
[MAX2(num_sources
, 3)];
150 for (unsigned i
= 0; i
< MIN2(this->sources
, num_sources
); ++i
)
151 src
[i
] = this->src
[i
];
155 this->sources
= num_sources
;
160 fs_visitor::VARYING_PULL_CONSTANT_LOAD(const fs_builder
&bld
,
162 const fs_reg
&surf_index
,
163 const fs_reg
&varying_offset
,
164 uint32_t const_offset
)
166 /* We have our constant surface use a pitch of 4 bytes, so our index can
167 * be any component of a vector, and then we load 4 contiguous
168 * components starting from that.
170 * We break down the const_offset to a portion added to the variable
171 * offset and a portion done using reg_offset, which means that if you
172 * have GLSL using something like "uniform vec4 a[20]; gl_FragColor =
173 * a[i]", we'll temporarily generate 4 vec4 loads from offset i * 4, and
174 * CSE can later notice that those loads are all the same and eliminate
175 * the redundant ones.
177 fs_reg vec4_offset
= vgrf(glsl_type::uint_type
);
178 bld
.ADD(vec4_offset
, varying_offset
, brw_imm_ud(const_offset
& ~0xf));
181 if (devinfo
->gen
== 4 && bld
.dispatch_width() == 8) {
182 /* Pre-gen5, we can either use a SIMD8 message that requires (header,
183 * u, v, r) as parameters, or we can just use the SIMD16 message
184 * consisting of (header, u). We choose the second, at the cost of a
185 * longer return length.
191 if (devinfo
->gen
>= 7)
192 op
= FS_OPCODE_VARYING_PULL_CONSTANT_LOAD_GEN7
;
194 op
= FS_OPCODE_VARYING_PULL_CONSTANT_LOAD
;
196 int regs_written
= 4 * (bld
.dispatch_width() / 8) * scale
;
197 fs_reg vec4_result
= fs_reg(VGRF
, alloc
.allocate(regs_written
), dst
.type
);
198 fs_inst
*inst
= bld
.emit(op
, vec4_result
, surf_index
, vec4_offset
);
199 inst
->regs_written
= regs_written
;
201 if (devinfo
->gen
< 7) {
202 inst
->base_mrf
= FIRST_PULL_LOAD_MRF(devinfo
->gen
);
203 inst
->header_size
= 1;
204 if (devinfo
->gen
== 4)
207 inst
->mlen
= 1 + bld
.dispatch_width() / 8;
210 bld
.MOV(dst
, offset(vec4_result
, bld
, ((const_offset
& 0xf) / 4) * scale
));
214 * A helper for MOV generation for fixing up broken hardware SEND dependency
218 fs_visitor::DEP_RESOLVE_MOV(const fs_builder
&bld
, int grf
)
220 /* The caller always wants uncompressed to emit the minimal extra
221 * dependencies, and to avoid having to deal with aligning its regs to 2.
223 const fs_builder ubld
= bld
.annotate("send dependency resolve")
226 ubld
.MOV(ubld
.null_reg_f(), fs_reg(VGRF
, grf
, BRW_REGISTER_TYPE_F
));
230 fs_inst::equals(fs_inst
*inst
) const
232 return (opcode
== inst
->opcode
&&
233 dst
.equals(inst
->dst
) &&
234 src
[0].equals(inst
->src
[0]) &&
235 src
[1].equals(inst
->src
[1]) &&
236 src
[2].equals(inst
->src
[2]) &&
237 saturate
== inst
->saturate
&&
238 predicate
== inst
->predicate
&&
239 conditional_mod
== inst
->conditional_mod
&&
240 mlen
== inst
->mlen
&&
241 base_mrf
== inst
->base_mrf
&&
242 target
== inst
->target
&&
244 header_size
== inst
->header_size
&&
245 shadow_compare
== inst
->shadow_compare
&&
246 exec_size
== inst
->exec_size
&&
247 offset
== inst
->offset
);
251 fs_inst::overwrites_reg(const fs_reg
®
) const
253 return reg
.in_range(dst
, regs_written
);
257 fs_inst::is_send_from_grf() const
260 case FS_OPCODE_VARYING_PULL_CONSTANT_LOAD_GEN7
:
261 case SHADER_OPCODE_SHADER_TIME_ADD
:
262 case FS_OPCODE_INTERPOLATE_AT_CENTROID
:
263 case FS_OPCODE_INTERPOLATE_AT_SAMPLE
:
264 case FS_OPCODE_INTERPOLATE_AT_SHARED_OFFSET
:
265 case FS_OPCODE_INTERPOLATE_AT_PER_SLOT_OFFSET
:
266 case SHADER_OPCODE_UNTYPED_ATOMIC
:
267 case SHADER_OPCODE_UNTYPED_SURFACE_READ
:
268 case SHADER_OPCODE_UNTYPED_SURFACE_WRITE
:
269 case SHADER_OPCODE_TYPED_ATOMIC
:
270 case SHADER_OPCODE_TYPED_SURFACE_READ
:
271 case SHADER_OPCODE_TYPED_SURFACE_WRITE
:
272 case SHADER_OPCODE_URB_WRITE_SIMD8
:
273 case SHADER_OPCODE_URB_WRITE_SIMD8_PER_SLOT
:
274 case SHADER_OPCODE_URB_WRITE_SIMD8_MASKED
:
275 case SHADER_OPCODE_URB_WRITE_SIMD8_MASKED_PER_SLOT
:
276 case SHADER_OPCODE_URB_READ_SIMD8
:
277 case SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT
:
279 case FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD
:
280 return src
[1].file
== VGRF
;
281 case FS_OPCODE_FB_WRITE
:
282 return src
[0].file
== VGRF
;
285 return src
[0].file
== VGRF
;
292 * Returns true if this instruction's sources and destinations cannot
293 * safely be the same register.
295 * In most cases, a register can be written over safely by the same
296 * instruction that is its last use. For a single instruction, the
297 * sources are dereferenced before writing of the destination starts
300 * However, there are a few cases where this can be problematic:
302 * - Virtual opcodes that translate to multiple instructions in the
303 * code generator: if src == dst and one instruction writes the
304 * destination before a later instruction reads the source, then
305 * src will have been clobbered.
307 * - SIMD16 compressed instructions with certain regioning (see below).
309 * The register allocator uses this information to set up conflicts between
310 * GRF sources and the destination.
313 fs_inst::has_source_and_destination_hazard() const
316 case FS_OPCODE_PACK_HALF_2x16_SPLIT
:
317 /* Multiple partial writes to the destination */
320 /* The SIMD16 compressed instruction
322 * add(16) g4<1>F g4<8,8,1>F g6<8,8,1>F
324 * is actually decoded in hardware as:
326 * add(8) g4<1>F g4<8,8,1>F g6<8,8,1>F
327 * add(8) g5<1>F g5<8,8,1>F g7<8,8,1>F
329 * Which is safe. However, if we have uniform accesses
330 * happening, we get into trouble:
332 * add(8) g4<1>F g4<0,1,0>F g6<8,8,1>F
333 * add(8) g5<1>F g4<0,1,0>F g7<8,8,1>F
335 * Now our destination for the first instruction overwrote the
336 * second instruction's src0, and we get garbage for those 8
337 * pixels. There's a similar issue for the pre-gen6
338 * pixel_x/pixel_y, which are registers of 16-bit values and thus
339 * would get stomped by the first decode as well.
341 if (exec_size
== 16) {
342 for (int i
= 0; i
< sources
; i
++) {
343 if (src
[i
].file
== VGRF
&& (src
[i
].stride
== 0 ||
344 src
[i
].type
== BRW_REGISTER_TYPE_UW
||
345 src
[i
].type
== BRW_REGISTER_TYPE_W
||
346 src
[i
].type
== BRW_REGISTER_TYPE_UB
||
347 src
[i
].type
== BRW_REGISTER_TYPE_B
)) {
357 fs_inst::is_copy_payload(const brw::simple_allocator
&grf_alloc
) const
359 if (this->opcode
!= SHADER_OPCODE_LOAD_PAYLOAD
)
362 fs_reg reg
= this->src
[0];
363 if (reg
.file
!= VGRF
|| reg
.reg_offset
!= 0 || reg
.stride
== 0)
366 if (grf_alloc
.sizes
[reg
.nr
] != this->regs_written
)
369 for (int i
= 0; i
< this->sources
; i
++) {
370 reg
.type
= this->src
[i
].type
;
371 if (!this->src
[i
].equals(reg
))
374 if (i
< this->header_size
) {
377 reg
= horiz_offset(reg
, this->exec_size
);
385 fs_inst::can_do_source_mods(const struct brw_device_info
*devinfo
)
387 if (devinfo
->gen
== 6 && is_math())
390 if (is_send_from_grf())
393 if (!backend_instruction::can_do_source_mods())
400 fs_inst::can_change_types() const
402 return dst
.type
== src
[0].type
&&
403 !src
[0].abs
&& !src
[0].negate
&& !saturate
&&
404 (opcode
== BRW_OPCODE_MOV
||
405 (opcode
== BRW_OPCODE_SEL
&&
406 dst
.type
== src
[1].type
&&
407 predicate
!= BRW_PREDICATE_NONE
&&
408 !src
[1].abs
&& !src
[1].negate
));
412 fs_inst::has_side_effects() const
414 return this->eot
|| backend_instruction::has_side_effects();
420 memset(this, 0, sizeof(*this));
424 /** Generic unset register constructor. */
428 this->file
= BAD_FILE
;
431 fs_reg::fs_reg(struct ::brw_reg reg
) :
434 this->reg_offset
= 0;
435 this->subreg_offset
= 0;
437 if (this->file
== IMM
&&
438 (this->type
!= BRW_REGISTER_TYPE_V
&&
439 this->type
!= BRW_REGISTER_TYPE_UV
&&
440 this->type
!= BRW_REGISTER_TYPE_VF
)) {
446 fs_reg::equals(const fs_reg
&r
) const
448 return (this->backend_reg::equals(r
) &&
449 subreg_offset
== r
.subreg_offset
&&
454 fs_reg::set_smear(unsigned subreg
)
456 assert(file
!= ARF
&& file
!= FIXED_GRF
&& file
!= IMM
);
457 subreg_offset
= subreg
* type_sz(type
);
463 fs_reg::is_contiguous() const
469 fs_reg::component_size(unsigned width
) const
471 const unsigned stride
= ((file
!= ARF
&& file
!= FIXED_GRF
) ? this->stride
:
474 return MAX2(width
* stride
, 1) * type_sz(type
);
478 type_size_scalar(const struct glsl_type
*type
)
480 unsigned int size
, i
;
482 switch (type
->base_type
) {
485 case GLSL_TYPE_FLOAT
:
487 return type
->components();
488 case GLSL_TYPE_DOUBLE
:
489 return type
->components() * 2;
490 case GLSL_TYPE_ARRAY
:
491 return type_size_scalar(type
->fields
.array
) * type
->length
;
492 case GLSL_TYPE_STRUCT
:
494 for (i
= 0; i
< type
->length
; i
++) {
495 size
+= type_size_scalar(type
->fields
.structure
[i
].type
);
498 case GLSL_TYPE_SAMPLER
:
499 /* Samplers take up no register space, since they're baked in at
503 case GLSL_TYPE_ATOMIC_UINT
:
505 case GLSL_TYPE_SUBROUTINE
:
507 case GLSL_TYPE_IMAGE
:
508 return BRW_IMAGE_PARAM_SIZE
;
510 case GLSL_TYPE_ERROR
:
511 case GLSL_TYPE_INTERFACE
:
512 case GLSL_TYPE_FUNCTION
:
513 unreachable("not reached");
520 * Returns the number of scalar components needed to store type, assuming
521 * that vectors are padded out to vec4.
523 * This has the packing rules of type_size_vec4(), but counts components
524 * similar to type_size_scalar().
527 type_size_vec4_times_4(const struct glsl_type
*type
)
529 return 4 * type_size_vec4(type
);
533 * Create a MOV to read the timestamp register.
535 * The caller is responsible for emitting the MOV. The return value is
536 * the destination of the MOV, with extra parameters set.
539 fs_visitor::get_timestamp(const fs_builder
&bld
)
541 assert(devinfo
->gen
>= 7);
543 fs_reg ts
= fs_reg(retype(brw_vec4_reg(BRW_ARCHITECTURE_REGISTER_FILE
,
546 BRW_REGISTER_TYPE_UD
));
548 fs_reg dst
= fs_reg(VGRF
, alloc
.allocate(1), BRW_REGISTER_TYPE_UD
);
550 /* We want to read the 3 fields we care about even if it's not enabled in
553 bld
.group(4, 0).exec_all().MOV(dst
, ts
);
559 fs_visitor::emit_shader_time_begin()
561 shader_start_time
= get_timestamp(bld
.annotate("shader time start"));
563 /* We want only the low 32 bits of the timestamp. Since it's running
564 * at the GPU clock rate of ~1.2ghz, it will roll over every ~3 seconds,
565 * which is plenty of time for our purposes. It is identical across the
566 * EUs, but since it's tracking GPU core speed it will increment at a
567 * varying rate as render P-states change.
569 shader_start_time
.set_smear(0);
573 fs_visitor::emit_shader_time_end()
575 /* Insert our code just before the final SEND with EOT. */
576 exec_node
*end
= this->instructions
.get_tail();
577 assert(end
&& ((fs_inst
*) end
)->eot
);
578 const fs_builder ibld
= bld
.annotate("shader time end")
579 .exec_all().at(NULL
, end
);
581 fs_reg shader_end_time
= get_timestamp(ibld
);
583 /* We only use the low 32 bits of the timestamp - see
584 * emit_shader_time_begin()).
586 * We could also check if render P-states have changed (or anything
587 * else that might disrupt timing) by setting smear to 2 and checking if
588 * that field is != 0.
590 shader_end_time
.set_smear(0);
592 /* Check that there weren't any timestamp reset events (assuming these
593 * were the only two timestamp reads that happened).
595 fs_reg reset
= shader_end_time
;
597 set_condmod(BRW_CONDITIONAL_Z
,
598 ibld
.AND(ibld
.null_reg_ud(), reset
, brw_imm_ud(1u)));
599 ibld
.IF(BRW_PREDICATE_NORMAL
);
601 fs_reg start
= shader_start_time
;
603 fs_reg diff
= fs_reg(VGRF
, alloc
.allocate(1), BRW_REGISTER_TYPE_UD
);
606 const fs_builder cbld
= ibld
.group(1, 0);
607 cbld
.group(1, 0).ADD(diff
, start
, shader_end_time
);
609 /* If there were no instructions between the two timestamp gets, the diff
610 * is 2 cycles. Remove that overhead, so I can forget about that when
611 * trying to determine the time taken for single instructions.
613 cbld
.ADD(diff
, diff
, brw_imm_ud(-2u));
614 SHADER_TIME_ADD(cbld
, 0, diff
);
615 SHADER_TIME_ADD(cbld
, 1, brw_imm_ud(1u));
616 ibld
.emit(BRW_OPCODE_ELSE
);
617 SHADER_TIME_ADD(cbld
, 2, brw_imm_ud(1u));
618 ibld
.emit(BRW_OPCODE_ENDIF
);
622 fs_visitor::SHADER_TIME_ADD(const fs_builder
&bld
,
623 int shader_time_subindex
,
626 int index
= shader_time_index
* 3 + shader_time_subindex
;
627 struct brw_reg offset
= brw_imm_d(index
* SHADER_TIME_STRIDE
);
630 if (dispatch_width
== 8)
631 payload
= vgrf(glsl_type::uvec2_type
);
633 payload
= vgrf(glsl_type::uint_type
);
635 bld
.emit(SHADER_OPCODE_SHADER_TIME_ADD
, fs_reg(), payload
, offset
, value
);
639 fs_visitor::vfail(const char *format
, va_list va
)
648 msg
= ralloc_vasprintf(mem_ctx
, format
, va
);
649 msg
= ralloc_asprintf(mem_ctx
, "%s compile failed: %s\n", stage_abbrev
, msg
);
651 this->fail_msg
= msg
;
654 fprintf(stderr
, "%s", msg
);
659 fs_visitor::fail(const char *format
, ...)
663 va_start(va
, format
);
669 * Mark this program as impossible to compile in SIMD16 mode.
671 * During the SIMD8 compile (which happens first), we can detect and flag
672 * things that are unsupported in SIMD16 mode, so the compiler can skip
673 * the SIMD16 compile altogether.
675 * During a SIMD16 compile (if one happens anyway), this just calls fail().
678 fs_visitor::no16(const char *msg
)
680 if (dispatch_width
== 16) {
683 simd16_unsupported
= true;
685 compiler
->shader_perf_log(log_data
,
686 "SIMD16 shader failed to compile: %s", msg
);
691 * Returns true if the instruction has a flag that means it won't
692 * update an entire destination register.
694 * For example, dead code elimination and live variable analysis want to know
695 * when a write to a variable screens off any preceding values that were in
699 fs_inst::is_partial_write() const
701 return ((this->predicate
&& this->opcode
!= BRW_OPCODE_SEL
) ||
702 (this->exec_size
* type_sz(this->dst
.type
)) < 32 ||
703 !this->dst
.is_contiguous());
707 fs_inst::components_read(unsigned i
) const
710 case FS_OPCODE_LINTERP
:
716 case FS_OPCODE_PIXEL_X
:
717 case FS_OPCODE_PIXEL_Y
:
721 case FS_OPCODE_FB_WRITE_LOGICAL
:
722 assert(src
[FB_WRITE_LOGICAL_SRC_COMPONENTS
].file
== IMM
);
723 /* First/second FB write color. */
725 return src
[FB_WRITE_LOGICAL_SRC_COMPONENTS
].ud
;
729 case SHADER_OPCODE_TEX_LOGICAL
:
730 case SHADER_OPCODE_TXD_LOGICAL
:
731 case SHADER_OPCODE_TXF_LOGICAL
:
732 case SHADER_OPCODE_TXL_LOGICAL
:
733 case SHADER_OPCODE_TXS_LOGICAL
:
734 case FS_OPCODE_TXB_LOGICAL
:
735 case SHADER_OPCODE_TXF_CMS_LOGICAL
:
736 case SHADER_OPCODE_TXF_CMS_W_LOGICAL
:
737 case SHADER_OPCODE_TXF_UMS_LOGICAL
:
738 case SHADER_OPCODE_TXF_MCS_LOGICAL
:
739 case SHADER_OPCODE_LOD_LOGICAL
:
740 case SHADER_OPCODE_TG4_LOGICAL
:
741 case SHADER_OPCODE_TG4_OFFSET_LOGICAL
:
742 assert(src
[TEX_LOGICAL_SRC_COORD_COMPONENTS
].file
== IMM
&&
743 src
[TEX_LOGICAL_SRC_GRAD_COMPONENTS
].file
== IMM
);
744 /* Texture coordinates. */
745 if (i
== TEX_LOGICAL_SRC_COORDINATE
)
746 return src
[TEX_LOGICAL_SRC_COORD_COMPONENTS
].ud
;
747 /* Texture derivatives. */
748 else if ((i
== TEX_LOGICAL_SRC_LOD
|| i
== TEX_LOGICAL_SRC_LOD2
) &&
749 opcode
== SHADER_OPCODE_TXD_LOGICAL
)
750 return src
[TEX_LOGICAL_SRC_GRAD_COMPONENTS
].ud
;
751 /* Texture offset. */
752 else if (i
== TEX_LOGICAL_SRC_OFFSET_VALUE
)
755 else if (i
== TEX_LOGICAL_SRC_MCS
&& opcode
== SHADER_OPCODE_TXF_CMS_W_LOGICAL
)
760 case SHADER_OPCODE_UNTYPED_SURFACE_READ_LOGICAL
:
761 case SHADER_OPCODE_TYPED_SURFACE_READ_LOGICAL
:
762 assert(src
[3].file
== IMM
);
763 /* Surface coordinates. */
766 /* Surface operation source (ignored for reads). */
772 case SHADER_OPCODE_UNTYPED_SURFACE_WRITE_LOGICAL
:
773 case SHADER_OPCODE_TYPED_SURFACE_WRITE_LOGICAL
:
774 assert(src
[3].file
== IMM
&&
776 /* Surface coordinates. */
779 /* Surface operation source. */
785 case SHADER_OPCODE_UNTYPED_ATOMIC_LOGICAL
:
786 case SHADER_OPCODE_TYPED_ATOMIC_LOGICAL
: {
787 assert(src
[3].file
== IMM
&&
789 const unsigned op
= src
[4].ud
;
790 /* Surface coordinates. */
793 /* Surface operation source. */
794 else if (i
== 1 && op
== BRW_AOP_CMPWR
)
796 else if (i
== 1 && (op
== BRW_AOP_INC
|| op
== BRW_AOP_DEC
||
797 op
== BRW_AOP_PREDEC
))
809 fs_inst::regs_read(int arg
) const
812 case FS_OPCODE_FB_WRITE
:
813 case SHADER_OPCODE_URB_WRITE_SIMD8
:
814 case SHADER_OPCODE_URB_WRITE_SIMD8_PER_SLOT
:
815 case SHADER_OPCODE_URB_WRITE_SIMD8_MASKED
:
816 case SHADER_OPCODE_URB_WRITE_SIMD8_MASKED_PER_SLOT
:
817 case SHADER_OPCODE_URB_READ_SIMD8
:
818 case SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT
:
819 case SHADER_OPCODE_UNTYPED_ATOMIC
:
820 case SHADER_OPCODE_UNTYPED_SURFACE_READ
:
821 case SHADER_OPCODE_UNTYPED_SURFACE_WRITE
:
822 case SHADER_OPCODE_TYPED_ATOMIC
:
823 case SHADER_OPCODE_TYPED_SURFACE_READ
:
824 case SHADER_OPCODE_TYPED_SURFACE_WRITE
:
825 case FS_OPCODE_INTERPOLATE_AT_PER_SLOT_OFFSET
:
830 case FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD_GEN7
:
831 /* The payload is actually stored in src1 */
836 case FS_OPCODE_LINTERP
:
841 case SHADER_OPCODE_LOAD_PAYLOAD
:
842 if (arg
< this->header_size
)
846 case CS_OPCODE_CS_TERMINATE
:
847 case SHADER_OPCODE_BARRIER
:
850 case SHADER_OPCODE_MOV_INDIRECT
:
852 assert(src
[2].file
== IMM
);
853 unsigned region_length
= src
[2].ud
;
855 if (src
[0].file
== UNIFORM
) {
856 assert(region_length
% 4 == 0);
857 return region_length
/ 4;
858 } else if (src
[0].file
== FIXED_GRF
) {
859 /* If the start of the region is not register aligned, then
860 * there's some portion of the register that's technically
861 * unread at the beginning.
863 * However, the register allocator works in terms of whole
864 * registers, and does not use subnr. It assumes that the
865 * read starts at the beginning of the register, and extends
866 * regs_read() whole registers beyond that.
868 * To compensate, we extend the region length to include this
869 * unread portion at the beginning.
872 region_length
+= src
[0].subnr
;
874 return DIV_ROUND_UP(region_length
, REG_SIZE
);
876 assert(!"Invalid register file");
882 if (is_tex() && arg
== 0 && src
[0].file
== VGRF
)
887 switch (src
[arg
].file
) {
897 return DIV_ROUND_UP(components_read(arg
) *
898 src
[arg
].component_size(exec_size
),
901 unreachable("MRF registers are not allowed as sources");
907 fs_inst::reads_flag() const
913 fs_inst::writes_flag() const
915 return (conditional_mod
&& (opcode
!= BRW_OPCODE_SEL
&&
916 opcode
!= BRW_OPCODE_IF
&&
917 opcode
!= BRW_OPCODE_WHILE
)) ||
918 opcode
== FS_OPCODE_MOV_DISPATCH_TO_FLAGS
;
922 * Returns how many MRFs an FS opcode will write over.
924 * Note that this is not the 0 or 1 implied writes in an actual gen
925 * instruction -- the FS opcodes often generate MOVs in addition.
928 fs_visitor::implied_mrf_writes(fs_inst
*inst
)
933 if (inst
->base_mrf
== -1)
936 switch (inst
->opcode
) {
937 case SHADER_OPCODE_RCP
:
938 case SHADER_OPCODE_RSQ
:
939 case SHADER_OPCODE_SQRT
:
940 case SHADER_OPCODE_EXP2
:
941 case SHADER_OPCODE_LOG2
:
942 case SHADER_OPCODE_SIN
:
943 case SHADER_OPCODE_COS
:
944 return 1 * dispatch_width
/ 8;
945 case SHADER_OPCODE_POW
:
946 case SHADER_OPCODE_INT_QUOTIENT
:
947 case SHADER_OPCODE_INT_REMAINDER
:
948 return 2 * dispatch_width
/ 8;
949 case SHADER_OPCODE_TEX
:
951 case SHADER_OPCODE_TXD
:
952 case SHADER_OPCODE_TXF
:
953 case SHADER_OPCODE_TXF_CMS
:
954 case SHADER_OPCODE_TXF_CMS_W
:
955 case SHADER_OPCODE_TXF_MCS
:
956 case SHADER_OPCODE_TG4
:
957 case SHADER_OPCODE_TG4_OFFSET
:
958 case SHADER_OPCODE_TXL
:
959 case SHADER_OPCODE_TXS
:
960 case SHADER_OPCODE_LOD
:
961 case SHADER_OPCODE_SAMPLEINFO
:
963 case FS_OPCODE_FB_WRITE
:
965 case FS_OPCODE_GET_BUFFER_SIZE
:
966 case FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD
:
967 case SHADER_OPCODE_GEN4_SCRATCH_READ
:
969 case FS_OPCODE_VARYING_PULL_CONSTANT_LOAD
:
971 case SHADER_OPCODE_GEN4_SCRATCH_WRITE
:
973 case SHADER_OPCODE_UNTYPED_ATOMIC
:
974 case SHADER_OPCODE_UNTYPED_SURFACE_READ
:
975 case SHADER_OPCODE_UNTYPED_SURFACE_WRITE
:
976 case SHADER_OPCODE_TYPED_ATOMIC
:
977 case SHADER_OPCODE_TYPED_SURFACE_READ
:
978 case SHADER_OPCODE_TYPED_SURFACE_WRITE
:
979 case SHADER_OPCODE_URB_WRITE_SIMD8
:
980 case SHADER_OPCODE_URB_WRITE_SIMD8_PER_SLOT
:
981 case SHADER_OPCODE_URB_WRITE_SIMD8_MASKED
:
982 case SHADER_OPCODE_URB_WRITE_SIMD8_MASKED_PER_SLOT
:
983 case FS_OPCODE_INTERPOLATE_AT_CENTROID
:
984 case FS_OPCODE_INTERPOLATE_AT_SAMPLE
:
985 case FS_OPCODE_INTERPOLATE_AT_SHARED_OFFSET
:
986 case FS_OPCODE_INTERPOLATE_AT_PER_SLOT_OFFSET
:
989 unreachable("not reached");
994 fs_visitor::vgrf(const glsl_type
*const type
)
996 int reg_width
= dispatch_width
/ 8;
997 return fs_reg(VGRF
, alloc
.allocate(type_size_scalar(type
) * reg_width
),
998 brw_type_for_base_type(type
));
1001 fs_reg::fs_reg(enum brw_reg_file file
, int nr
)
1006 this->type
= BRW_REGISTER_TYPE_F
;
1007 this->stride
= (file
== UNIFORM
? 0 : 1);
1010 fs_reg::fs_reg(enum brw_reg_file file
, int nr
, enum brw_reg_type type
)
1016 this->stride
= (file
== UNIFORM
? 0 : 1);
1019 /* For SIMD16, we need to follow from the uniform setup of SIMD8 dispatch.
1020 * This brings in those uniform definitions
1023 fs_visitor::import_uniforms(fs_visitor
*v
)
1025 this->push_constant_loc
= v
->push_constant_loc
;
1026 this->pull_constant_loc
= v
->pull_constant_loc
;
1027 this->uniforms
= v
->uniforms
;
1031 fs_visitor::emit_fragcoord_interpolation(bool pixel_center_integer
,
1032 bool origin_upper_left
)
1034 assert(stage
== MESA_SHADER_FRAGMENT
);
1035 brw_wm_prog_key
*key
= (brw_wm_prog_key
*) this->key
;
1036 fs_reg
*reg
= new(this->mem_ctx
) fs_reg(vgrf(glsl_type::vec4_type
));
1038 bool flip
= !origin_upper_left
^ key
->render_to_fbo
;
1040 /* gl_FragCoord.x */
1041 if (pixel_center_integer
) {
1042 bld
.MOV(wpos
, this->pixel_x
);
1044 bld
.ADD(wpos
, this->pixel_x
, brw_imm_f(0.5f
));
1046 wpos
= offset(wpos
, bld
, 1);
1048 /* gl_FragCoord.y */
1049 if (!flip
&& pixel_center_integer
) {
1050 bld
.MOV(wpos
, this->pixel_y
);
1052 fs_reg pixel_y
= this->pixel_y
;
1053 float offset
= (pixel_center_integer
? 0.0f
: 0.5f
);
1056 pixel_y
.negate
= true;
1057 offset
+= key
->drawable_height
- 1.0f
;
1060 bld
.ADD(wpos
, pixel_y
, brw_imm_f(offset
));
1062 wpos
= offset(wpos
, bld
, 1);
1064 /* gl_FragCoord.z */
1065 if (devinfo
->gen
>= 6) {
1066 bld
.MOV(wpos
, fs_reg(brw_vec8_grf(payload
.source_depth_reg
, 0)));
1068 bld
.emit(FS_OPCODE_LINTERP
, wpos
,
1069 this->delta_xy
[BRW_WM_PERSPECTIVE_PIXEL_BARYCENTRIC
],
1070 interp_reg(VARYING_SLOT_POS
, 2));
1072 wpos
= offset(wpos
, bld
, 1);
1074 /* gl_FragCoord.w: Already set up in emit_interpolation */
1075 bld
.MOV(wpos
, this->wpos_w
);
1081 fs_visitor::emit_linterp(const fs_reg
&attr
, const fs_reg
&interp
,
1082 glsl_interp_qualifier interpolation_mode
,
1083 bool is_centroid
, bool is_sample
)
1085 brw_wm_barycentric_interp_mode barycoord_mode
;
1086 if (devinfo
->gen
>= 6) {
1088 if (interpolation_mode
== INTERP_QUALIFIER_SMOOTH
)
1089 barycoord_mode
= BRW_WM_PERSPECTIVE_CENTROID_BARYCENTRIC
;
1091 barycoord_mode
= BRW_WM_NONPERSPECTIVE_CENTROID_BARYCENTRIC
;
1092 } else if (is_sample
) {
1093 if (interpolation_mode
== INTERP_QUALIFIER_SMOOTH
)
1094 barycoord_mode
= BRW_WM_PERSPECTIVE_SAMPLE_BARYCENTRIC
;
1096 barycoord_mode
= BRW_WM_NONPERSPECTIVE_SAMPLE_BARYCENTRIC
;
1098 if (interpolation_mode
== INTERP_QUALIFIER_SMOOTH
)
1099 barycoord_mode
= BRW_WM_PERSPECTIVE_PIXEL_BARYCENTRIC
;
1101 barycoord_mode
= BRW_WM_NONPERSPECTIVE_PIXEL_BARYCENTRIC
;
1104 /* On Ironlake and below, there is only one interpolation mode.
1105 * Centroid interpolation doesn't mean anything on this hardware --
1106 * there is no multisampling.
1108 barycoord_mode
= BRW_WM_PERSPECTIVE_PIXEL_BARYCENTRIC
;
1110 return bld
.emit(FS_OPCODE_LINTERP
, attr
,
1111 this->delta_xy
[barycoord_mode
], interp
);
1115 fs_visitor::emit_general_interpolation(fs_reg
*attr
, const char *name
,
1116 const glsl_type
*type
,
1117 glsl_interp_qualifier interpolation_mode
,
1118 int *location
, bool mod_centroid
,
1121 assert(stage
== MESA_SHADER_FRAGMENT
);
1122 brw_wm_prog_data
*prog_data
= (brw_wm_prog_data
*) this->prog_data
;
1123 brw_wm_prog_key
*key
= (brw_wm_prog_key
*) this->key
;
1125 if (interpolation_mode
== INTERP_QUALIFIER_NONE
) {
1127 *location
== VARYING_SLOT_COL0
|| *location
== VARYING_SLOT_COL1
;
1128 if (key
->flat_shade
&& is_gl_Color
) {
1129 interpolation_mode
= INTERP_QUALIFIER_FLAT
;
1131 interpolation_mode
= INTERP_QUALIFIER_SMOOTH
;
1135 if (type
->is_array() || type
->is_matrix()) {
1136 const glsl_type
*elem_type
= glsl_get_array_element(type
);
1137 const unsigned length
= glsl_get_length(type
);
1139 for (unsigned i
= 0; i
< length
; i
++) {
1140 emit_general_interpolation(attr
, name
, elem_type
, interpolation_mode
,
1141 location
, mod_centroid
, mod_sample
);
1143 } else if (type
->is_record()) {
1144 for (unsigned i
= 0; i
< type
->length
; i
++) {
1145 const glsl_type
*field_type
= type
->fields
.structure
[i
].type
;
1146 emit_general_interpolation(attr
, name
, field_type
, interpolation_mode
,
1147 location
, mod_centroid
, mod_sample
);
1150 assert(type
->is_scalar() || type
->is_vector());
1152 if (prog_data
->urb_setup
[*location
] == -1) {
1153 /* If there's no incoming setup data for this slot, don't
1154 * emit interpolation for it.
1156 *attr
= offset(*attr
, bld
, type
->vector_elements
);
1161 attr
->type
= brw_type_for_base_type(type
->get_scalar_type());
1163 if (interpolation_mode
== INTERP_QUALIFIER_FLAT
) {
1164 /* Constant interpolation (flat shading) case. The SF has
1165 * handed us defined values in only the constant offset
1166 * field of the setup reg.
1168 for (unsigned int i
= 0; i
< type
->vector_elements
; i
++) {
1169 struct brw_reg interp
= interp_reg(*location
, i
);
1170 interp
= suboffset(interp
, 3);
1171 interp
.type
= attr
->type
;
1172 bld
.emit(FS_OPCODE_CINTERP
, *attr
, fs_reg(interp
));
1173 *attr
= offset(*attr
, bld
, 1);
1176 /* Smooth/noperspective interpolation case. */
1177 for (unsigned int i
= 0; i
< type
->vector_elements
; i
++) {
1178 struct brw_reg interp
= interp_reg(*location
, i
);
1179 if (devinfo
->needs_unlit_centroid_workaround
&& mod_centroid
) {
1180 /* Get the pixel/sample mask into f0 so that we know
1181 * which pixels are lit. Then, for each channel that is
1182 * unlit, replace the centroid data with non-centroid
1185 bld
.emit(FS_OPCODE_MOV_DISPATCH_TO_FLAGS
);
1188 inst
= emit_linterp(*attr
, fs_reg(interp
), interpolation_mode
,
1190 inst
->predicate
= BRW_PREDICATE_NORMAL
;
1191 inst
->predicate_inverse
= true;
1192 if (devinfo
->has_pln
)
1193 inst
->no_dd_clear
= true;
1195 inst
= emit_linterp(*attr
, fs_reg(interp
), interpolation_mode
,
1196 mod_centroid
&& !key
->persample_shading
,
1197 mod_sample
|| key
->persample_shading
);
1198 inst
->predicate
= BRW_PREDICATE_NORMAL
;
1199 inst
->predicate_inverse
= false;
1200 if (devinfo
->has_pln
)
1201 inst
->no_dd_check
= true;
1204 emit_linterp(*attr
, fs_reg(interp
), interpolation_mode
,
1205 mod_centroid
&& !key
->persample_shading
,
1206 mod_sample
|| key
->persample_shading
);
1208 if (devinfo
->gen
< 6 && interpolation_mode
== INTERP_QUALIFIER_SMOOTH
) {
1209 bld
.MUL(*attr
, *attr
, this->pixel_w
);
1211 *attr
= offset(*attr
, bld
, 1);
1219 fs_visitor::emit_frontfacing_interpolation()
1221 fs_reg
*reg
= new(this->mem_ctx
) fs_reg(vgrf(glsl_type::bool_type
));
1223 if (devinfo
->gen
>= 6) {
1224 /* Bit 15 of g0.0 is 0 if the polygon is front facing. We want to create
1225 * a boolean result from this (~0/true or 0/false).
1227 * We can use the fact that bit 15 is the MSB of g0.0:W to accomplish
1228 * this task in only one instruction:
1229 * - a negation source modifier will flip the bit; and
1230 * - a W -> D type conversion will sign extend the bit into the high
1231 * word of the destination.
1233 * An ASR 15 fills the low word of the destination.
1235 fs_reg g0
= fs_reg(retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_W
));
1238 bld
.ASR(*reg
, g0
, brw_imm_d(15));
1240 /* Bit 31 of g1.6 is 0 if the polygon is front facing. We want to create
1241 * a boolean result from this (1/true or 0/false).
1243 * Like in the above case, since the bit is the MSB of g1.6:UD we can use
1244 * the negation source modifier to flip it. Unfortunately the SHR
1245 * instruction only operates on UD (or D with an abs source modifier)
1246 * sources without negation.
1248 * Instead, use ASR (which will give ~0/true or 0/false).
1250 fs_reg g1_6
= fs_reg(retype(brw_vec1_grf(1, 6), BRW_REGISTER_TYPE_D
));
1253 bld
.ASR(*reg
, g1_6
, brw_imm_d(31));
1260 fs_visitor::compute_sample_position(fs_reg dst
, fs_reg int_sample_pos
)
1262 assert(stage
== MESA_SHADER_FRAGMENT
);
1263 brw_wm_prog_key
*key
= (brw_wm_prog_key
*) this->key
;
1264 assert(dst
.type
== BRW_REGISTER_TYPE_F
);
1266 if (key
->compute_pos_offset
) {
1267 /* Convert int_sample_pos to floating point */
1268 bld
.MOV(dst
, int_sample_pos
);
1269 /* Scale to the range [0, 1] */
1270 bld
.MUL(dst
, dst
, brw_imm_f(1 / 16.0f
));
1273 /* From ARB_sample_shading specification:
1274 * "When rendering to a non-multisample buffer, or if multisample
1275 * rasterization is disabled, gl_SamplePosition will always be
1278 bld
.MOV(dst
, brw_imm_f(0.5f
));
1283 fs_visitor::emit_samplepos_setup()
1285 assert(devinfo
->gen
>= 6);
1287 const fs_builder abld
= bld
.annotate("compute sample position");
1288 fs_reg
*reg
= new(this->mem_ctx
) fs_reg(vgrf(glsl_type::vec2_type
));
1290 fs_reg int_sample_x
= vgrf(glsl_type::int_type
);
1291 fs_reg int_sample_y
= vgrf(glsl_type::int_type
);
1293 /* WM will be run in MSDISPMODE_PERSAMPLE. So, only one of SIMD8 or SIMD16
1294 * mode will be enabled.
1296 * From the Ivy Bridge PRM, volume 2 part 1, page 344:
1297 * R31.1:0 Position Offset X/Y for Slot[3:0]
1298 * R31.3:2 Position Offset X/Y for Slot[7:4]
1301 * The X, Y sample positions come in as bytes in thread payload. So, read
1302 * the positions using vstride=16, width=8, hstride=2.
1304 struct brw_reg sample_pos_reg
=
1305 stride(retype(brw_vec1_grf(payload
.sample_pos_reg
, 0),
1306 BRW_REGISTER_TYPE_B
), 16, 8, 2);
1308 if (dispatch_width
== 8) {
1309 abld
.MOV(int_sample_x
, fs_reg(sample_pos_reg
));
1311 abld
.half(0).MOV(half(int_sample_x
, 0), fs_reg(sample_pos_reg
));
1312 abld
.half(1).MOV(half(int_sample_x
, 1),
1313 fs_reg(suboffset(sample_pos_reg
, 16)));
1315 /* Compute gl_SamplePosition.x */
1316 compute_sample_position(pos
, int_sample_x
);
1317 pos
= offset(pos
, abld
, 1);
1318 if (dispatch_width
== 8) {
1319 abld
.MOV(int_sample_y
, fs_reg(suboffset(sample_pos_reg
, 1)));
1321 abld
.half(0).MOV(half(int_sample_y
, 0),
1322 fs_reg(suboffset(sample_pos_reg
, 1)));
1323 abld
.half(1).MOV(half(int_sample_y
, 1),
1324 fs_reg(suboffset(sample_pos_reg
, 17)));
1326 /* Compute gl_SamplePosition.y */
1327 compute_sample_position(pos
, int_sample_y
);
1332 fs_visitor::emit_sampleid_setup()
1334 assert(stage
== MESA_SHADER_FRAGMENT
);
1335 brw_wm_prog_key
*key
= (brw_wm_prog_key
*) this->key
;
1336 assert(devinfo
->gen
>= 6);
1338 const fs_builder abld
= bld
.annotate("compute sample id");
1339 fs_reg
*reg
= new(this->mem_ctx
) fs_reg(vgrf(glsl_type::int_type
));
1341 if (!key
->multisample_fbo
) {
1342 /* As per GL_ARB_sample_shading specification:
1343 * "When rendering to a non-multisample buffer, or if multisample
1344 * rasterization is disabled, gl_SampleID will always be zero."
1346 abld
.MOV(*reg
, brw_imm_d(0));
1347 } else if (devinfo
->gen
>= 8) {
1348 /* Sample ID comes in as 4-bit numbers in g1.0:
1350 * 15:12 Slot 3 SampleID (only used in SIMD16)
1351 * 11:8 Slot 2 SampleID (only used in SIMD16)
1352 * 7:4 Slot 1 SampleID
1353 * 3:0 Slot 0 SampleID
1355 * Each slot corresponds to four channels, so we want to replicate each
1356 * half-byte value to 4 channels in a row:
1358 * dst+0: .7 .6 .5 .4 .3 .2 .1 .0
1359 * 7:4 7:4 7:4 7:4 3:0 3:0 3:0 3:0
1361 * dst+1: .7 .6 .5 .4 .3 .2 .1 .0 (if SIMD16)
1362 * 15:12 15:12 15:12 15:12 11:8 11:8 11:8 11:8
1364 * First, we read g1.0 with a <1,8,0>UB region, causing the first 8
1365 * channels to read the first byte (7:0), and the second group of 8
1366 * channels to read the second byte (15:8). Then, we shift right by
1367 * a vector immediate of <4, 4, 4, 4, 0, 0, 0, 0>, moving the slot 1 / 3
1368 * values into place. Finally, we AND with 0xf to keep the low nibble.
1370 * shr(16) tmp<1>W g1.0<1,8,0>B 0x44440000:V
1371 * and(16) dst<1>D tmp<8,8,1>W 0xf:W
1373 * TODO: These payload bits exist on Gen7 too, but they appear to always
1374 * be zero, so this code fails to work. We should find out why.
1376 fs_reg
tmp(VGRF
, alloc
.allocate(1), BRW_REGISTER_TYPE_W
);
1378 abld
.SHR(tmp
, fs_reg(stride(retype(brw_vec1_grf(1, 0),
1379 BRW_REGISTER_TYPE_B
), 1, 8, 0)),
1380 brw_imm_v(0x44440000));
1381 abld
.AND(*reg
, tmp
, brw_imm_w(0xf));
1383 fs_reg
t1(VGRF
, alloc
.allocate(1), BRW_REGISTER_TYPE_D
);
1385 fs_reg
t2(VGRF
, alloc
.allocate(1), BRW_REGISTER_TYPE_W
);
1387 /* The PS will be run in MSDISPMODE_PERSAMPLE. For example with
1388 * 8x multisampling, subspan 0 will represent sample N (where N
1389 * is 0, 2, 4 or 6), subspan 1 will represent sample 1, 3, 5 or
1390 * 7. We can find the value of N by looking at R0.0 bits 7:6
1391 * ("Starting Sample Pair Index (SSPI)") and multiplying by two
1392 * (since samples are always delivered in pairs). That is, we
1393 * compute 2*((R0.0 & 0xc0) >> 6) == (R0.0 & 0xc0) >> 5. Then
1394 * we need to add N to the sequence (0, 0, 0, 0, 1, 1, 1, 1) in
1395 * case of SIMD8 and sequence (0, 0, 0, 0, 1, 1, 1, 1, 2, 2, 2,
1396 * 2, 3, 3, 3, 3) in case of SIMD16. We compute this sequence by
1397 * populating a temporary variable with the sequence (0, 1, 2, 3),
1398 * and then reading from it using vstride=1, width=4, hstride=0.
1399 * These computations hold good for 4x multisampling as well.
1401 * For 2x MSAA and SIMD16, we want to use the sequence (0, 1, 0, 1):
1402 * the first four slots are sample 0 of subspan 0; the next four
1403 * are sample 1 of subspan 0; the third group is sample 0 of
1404 * subspan 1, and finally sample 1 of subspan 1.
1407 /* SKL+ has an extra bit for the Starting Sample Pair Index to
1408 * accomodate 16x MSAA.
1410 abld
.exec_all().group(1, 0)
1411 .AND(t1
, fs_reg(retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_D
)),
1413 abld
.exec_all().group(1, 0).SHR(t1
, t1
, brw_imm_d(5));
1415 /* This works for both SIMD8 and SIMD16 */
1416 abld
.exec_all().group(4, 0).MOV(t2
, brw_imm_v(0x3210));
1418 /* This special instruction takes care of setting vstride=1,
1419 * width=4, hstride=0 of t2 during an ADD instruction.
1421 abld
.emit(FS_OPCODE_SET_SAMPLE_ID
, *reg
, t1
, t2
);
1428 fs_visitor::emit_samplemaskin_setup()
1430 assert(stage
== MESA_SHADER_FRAGMENT
);
1431 brw_wm_prog_key
*key
= (brw_wm_prog_key
*) this->key
;
1432 assert(devinfo
->gen
>= 6);
1434 fs_reg
*reg
= new(this->mem_ctx
) fs_reg(vgrf(glsl_type::int_type
));
1436 fs_reg
coverage_mask(retype(brw_vec8_grf(payload
.sample_mask_in_reg
, 0),
1437 BRW_REGISTER_TYPE_D
));
1439 if (key
->persample_shading
) {
1440 /* gl_SampleMaskIn[] comes from two sources: the input coverage mask,
1441 * and a mask representing which sample is being processed by the
1442 * current shader invocation.
1444 * From the OES_sample_variables specification:
1445 * "When per-sample shading is active due to the use of a fragment input
1446 * qualified by "sample" or due to the use of the gl_SampleID or
1447 * gl_SamplePosition variables, only the bit for the current sample is
1448 * set in gl_SampleMaskIn."
1450 const fs_builder abld
= bld
.annotate("compute gl_SampleMaskIn");
1452 if (nir_system_values
[SYSTEM_VALUE_SAMPLE_ID
].file
== BAD_FILE
)
1453 nir_system_values
[SYSTEM_VALUE_SAMPLE_ID
] = *emit_sampleid_setup();
1455 fs_reg one
= vgrf(glsl_type::int_type
);
1456 fs_reg enabled_mask
= vgrf(glsl_type::int_type
);
1457 abld
.MOV(one
, brw_imm_d(1));
1458 abld
.SHL(enabled_mask
, one
, nir_system_values
[SYSTEM_VALUE_SAMPLE_ID
]);
1459 abld
.AND(*reg
, enabled_mask
, coverage_mask
);
1461 /* In per-pixel mode, the coverage mask is sufficient. */
1462 *reg
= coverage_mask
;
1468 fs_visitor::resolve_source_modifiers(const fs_reg
&src
)
1470 if (!src
.abs
&& !src
.negate
)
1473 fs_reg temp
= bld
.vgrf(src
.type
);
1480 fs_visitor::emit_discard_jump()
1482 assert(((brw_wm_prog_data
*) this->prog_data
)->uses_kill
);
1484 /* For performance, after a discard, jump to the end of the
1485 * shader if all relevant channels have been discarded.
1487 fs_inst
*discard_jump
= bld
.emit(FS_OPCODE_DISCARD_JUMP
);
1488 discard_jump
->flag_subreg
= 1;
1490 discard_jump
->predicate
= (dispatch_width
== 8)
1491 ? BRW_PREDICATE_ALIGN1_ANY8H
1492 : BRW_PREDICATE_ALIGN1_ANY16H
;
1493 discard_jump
->predicate_inverse
= true;
1497 fs_visitor::emit_gs_thread_end()
1499 assert(stage
== MESA_SHADER_GEOMETRY
);
1501 struct brw_gs_prog_data
*gs_prog_data
=
1502 (struct brw_gs_prog_data
*) prog_data
;
1504 if (gs_compile
->control_data_header_size_bits
> 0) {
1505 emit_gs_control_data_bits(this->final_gs_vertex_count
);
1508 const fs_builder abld
= bld
.annotate("thread end");
1511 if (gs_prog_data
->static_vertex_count
!= -1) {
1512 foreach_in_list_reverse(fs_inst
, prev
, &this->instructions
) {
1513 if (prev
->opcode
== SHADER_OPCODE_URB_WRITE_SIMD8
||
1514 prev
->opcode
== SHADER_OPCODE_URB_WRITE_SIMD8_MASKED
||
1515 prev
->opcode
== SHADER_OPCODE_URB_WRITE_SIMD8_PER_SLOT
||
1516 prev
->opcode
== SHADER_OPCODE_URB_WRITE_SIMD8_MASKED_PER_SLOT
) {
1519 /* Delete now dead instructions. */
1520 foreach_in_list_reverse_safe(exec_node
, dead
, &this->instructions
) {
1526 } else if (prev
->is_control_flow() || prev
->has_side_effects()) {
1530 fs_reg hdr
= abld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
1531 abld
.MOV(hdr
, fs_reg(retype(brw_vec8_grf(1, 0), BRW_REGISTER_TYPE_UD
)));
1532 inst
= abld
.emit(SHADER_OPCODE_URB_WRITE_SIMD8
, reg_undef
, hdr
);
1535 fs_reg payload
= abld
.vgrf(BRW_REGISTER_TYPE_UD
, 2);
1536 fs_reg
*sources
= ralloc_array(mem_ctx
, fs_reg
, 2);
1537 sources
[0] = fs_reg(retype(brw_vec8_grf(1, 0), BRW_REGISTER_TYPE_UD
));
1538 sources
[1] = this->final_gs_vertex_count
;
1539 abld
.LOAD_PAYLOAD(payload
, sources
, 2, 2);
1540 inst
= abld
.emit(SHADER_OPCODE_URB_WRITE_SIMD8
, reg_undef
, payload
);
1548 fs_visitor::assign_curb_setup()
1550 if (dispatch_width
== 8) {
1551 prog_data
->dispatch_grf_start_reg
= payload
.num_regs
;
1553 if (stage
== MESA_SHADER_FRAGMENT
) {
1554 brw_wm_prog_data
*prog_data
= (brw_wm_prog_data
*) this->prog_data
;
1555 prog_data
->dispatch_grf_start_reg_16
= payload
.num_regs
;
1556 } else if (stage
== MESA_SHADER_COMPUTE
) {
1557 brw_cs_prog_data
*prog_data
= (brw_cs_prog_data
*) this->prog_data
;
1558 prog_data
->dispatch_grf_start_reg_16
= payload
.num_regs
;
1560 unreachable("Unsupported shader type!");
1564 prog_data
->curb_read_length
= ALIGN(stage_prog_data
->nr_params
, 8) / 8;
1566 /* Map the offsets in the UNIFORM file to fixed HW regs. */
1567 foreach_block_and_inst(block
, fs_inst
, inst
, cfg
) {
1568 for (unsigned int i
= 0; i
< inst
->sources
; i
++) {
1569 if (inst
->src
[i
].file
== UNIFORM
) {
1570 int uniform_nr
= inst
->src
[i
].nr
+ inst
->src
[i
].reg_offset
;
1572 if (uniform_nr
>= 0 && uniform_nr
< (int) uniforms
) {
1573 constant_nr
= push_constant_loc
[uniform_nr
];
1575 /* Section 5.11 of the OpenGL 4.1 spec says:
1576 * "Out-of-bounds reads return undefined values, which include
1577 * values from other variables of the active program or zero."
1578 * Just return the first push constant.
1583 struct brw_reg brw_reg
= brw_vec1_grf(payload
.num_regs
+
1586 brw_reg
.abs
= inst
->src
[i
].abs
;
1587 brw_reg
.negate
= inst
->src
[i
].negate
;
1589 assert(inst
->src
[i
].stride
== 0);
1590 inst
->src
[i
] = byte_offset(
1591 retype(brw_reg
, inst
->src
[i
].type
),
1592 inst
->src
[i
].subreg_offset
);
1597 /* This may be updated in assign_urb_setup or assign_vs_urb_setup. */
1598 this->first_non_payload_grf
= payload
.num_regs
+ prog_data
->curb_read_length
;
1602 fs_visitor::calculate_urb_setup()
1604 assert(stage
== MESA_SHADER_FRAGMENT
);
1605 brw_wm_prog_data
*prog_data
= (brw_wm_prog_data
*) this->prog_data
;
1606 brw_wm_prog_key
*key
= (brw_wm_prog_key
*) this->key
;
1608 memset(prog_data
->urb_setup
, -1,
1609 sizeof(prog_data
->urb_setup
[0]) * VARYING_SLOT_MAX
);
1612 /* Figure out where each of the incoming setup attributes lands. */
1613 if (devinfo
->gen
>= 6) {
1614 if (_mesa_bitcount_64(nir
->info
.inputs_read
&
1615 BRW_FS_VARYING_INPUT_MASK
) <= 16) {
1616 /* The SF/SBE pipeline stage can do arbitrary rearrangement of the
1617 * first 16 varying inputs, so we can put them wherever we want.
1618 * Just put them in order.
1620 * This is useful because it means that (a) inputs not used by the
1621 * fragment shader won't take up valuable register space, and (b) we
1622 * won't have to recompile the fragment shader if it gets paired with
1623 * a different vertex (or geometry) shader.
1625 for (unsigned int i
= 0; i
< VARYING_SLOT_MAX
; i
++) {
1626 if (nir
->info
.inputs_read
& BRW_FS_VARYING_INPUT_MASK
&
1627 BITFIELD64_BIT(i
)) {
1628 prog_data
->urb_setup
[i
] = urb_next
++;
1632 bool include_vue_header
=
1633 nir
->info
.inputs_read
& (VARYING_BIT_LAYER
| VARYING_BIT_VIEWPORT
);
1635 /* We have enough input varyings that the SF/SBE pipeline stage can't
1636 * arbitrarily rearrange them to suit our whim; we have to put them
1637 * in an order that matches the output of the previous pipeline stage
1638 * (geometry or vertex shader).
1640 struct brw_vue_map prev_stage_vue_map
;
1641 brw_compute_vue_map(devinfo
, &prev_stage_vue_map
,
1642 key
->input_slots_valid
,
1643 nir
->info
.separate_shader
);
1645 include_vue_header
? 0 : 2 * BRW_SF_URB_ENTRY_READ_OFFSET
;
1647 assert(prev_stage_vue_map
.num_slots
<= first_slot
+ 32);
1648 for (int slot
= first_slot
; slot
< prev_stage_vue_map
.num_slots
;
1650 int varying
= prev_stage_vue_map
.slot_to_varying
[slot
];
1651 if (varying
!= BRW_VARYING_SLOT_PAD
&&
1652 (nir
->info
.inputs_read
& BRW_FS_VARYING_INPUT_MASK
&
1653 BITFIELD64_BIT(varying
))) {
1654 prog_data
->urb_setup
[varying
] = slot
- first_slot
;
1657 urb_next
= prev_stage_vue_map
.num_slots
- first_slot
;
1660 /* FINISHME: The sf doesn't map VS->FS inputs for us very well. */
1661 for (unsigned int i
= 0; i
< VARYING_SLOT_MAX
; i
++) {
1662 /* Point size is packed into the header, not as a general attribute */
1663 if (i
== VARYING_SLOT_PSIZ
)
1666 if (key
->input_slots_valid
& BITFIELD64_BIT(i
)) {
1667 /* The back color slot is skipped when the front color is
1668 * also written to. In addition, some slots can be
1669 * written in the vertex shader and not read in the
1670 * fragment shader. So the register number must always be
1671 * incremented, mapped or not.
1673 if (_mesa_varying_slot_in_fs((gl_varying_slot
) i
))
1674 prog_data
->urb_setup
[i
] = urb_next
;
1680 * It's a FS only attribute, and we did interpolation for this attribute
1681 * in SF thread. So, count it here, too.
1683 * See compile_sf_prog() for more info.
1685 if (nir
->info
.inputs_read
& BITFIELD64_BIT(VARYING_SLOT_PNTC
))
1686 prog_data
->urb_setup
[VARYING_SLOT_PNTC
] = urb_next
++;
1689 prog_data
->num_varying_inputs
= urb_next
;
1693 fs_visitor::assign_urb_setup()
1695 assert(stage
== MESA_SHADER_FRAGMENT
);
1696 brw_wm_prog_data
*prog_data
= (brw_wm_prog_data
*) this->prog_data
;
1698 int urb_start
= payload
.num_regs
+ prog_data
->base
.curb_read_length
;
1700 /* Offset all the urb_setup[] index by the actual position of the
1701 * setup regs, now that the location of the constants has been chosen.
1703 foreach_block_and_inst(block
, fs_inst
, inst
, cfg
) {
1704 if (inst
->opcode
== FS_OPCODE_LINTERP
) {
1705 assert(inst
->src
[1].file
== FIXED_GRF
);
1706 inst
->src
[1].nr
+= urb_start
;
1709 if (inst
->opcode
== FS_OPCODE_CINTERP
) {
1710 assert(inst
->src
[0].file
== FIXED_GRF
);
1711 inst
->src
[0].nr
+= urb_start
;
1715 /* Each attribute is 4 setup channels, each of which is half a reg. */
1716 this->first_non_payload_grf
+= prog_data
->num_varying_inputs
* 2;
1720 fs_visitor::convert_attr_sources_to_hw_regs(fs_inst
*inst
)
1722 for (int i
= 0; i
< inst
->sources
; i
++) {
1723 if (inst
->src
[i
].file
== ATTR
) {
1724 int grf
= payload
.num_regs
+
1725 prog_data
->curb_read_length
+
1727 inst
->src
[i
].reg_offset
;
1729 unsigned width
= inst
->src
[i
].stride
== 0 ? 1 : inst
->exec_size
;
1730 struct brw_reg reg
=
1731 stride(byte_offset(retype(brw_vec8_grf(grf
, 0), inst
->src
[i
].type
),
1732 inst
->src
[i
].subreg_offset
),
1733 inst
->exec_size
* inst
->src
[i
].stride
,
1734 width
, inst
->src
[i
].stride
);
1735 reg
.abs
= inst
->src
[i
].abs
;
1736 reg
.negate
= inst
->src
[i
].negate
;
1744 fs_visitor::assign_vs_urb_setup()
1746 brw_vs_prog_data
*vs_prog_data
= (brw_vs_prog_data
*) prog_data
;
1748 assert(stage
== MESA_SHADER_VERTEX
);
1750 /* Each attribute is 4 regs. */
1751 this->first_non_payload_grf
+= 4 * vs_prog_data
->nr_attributes
;
1753 assert(vs_prog_data
->base
.urb_read_length
<= 15);
1755 /* Rewrite all ATTR file references to the hw grf that they land in. */
1756 foreach_block_and_inst(block
, fs_inst
, inst
, cfg
) {
1757 convert_attr_sources_to_hw_regs(inst
);
1762 fs_visitor::assign_tcs_single_patch_urb_setup()
1764 assert(stage
== MESA_SHADER_TESS_CTRL
);
1766 /* Rewrite all ATTR file references to HW_REGs. */
1767 foreach_block_and_inst(block
, fs_inst
, inst
, cfg
) {
1768 convert_attr_sources_to_hw_regs(inst
);
1773 fs_visitor::assign_tes_urb_setup()
1775 assert(stage
== MESA_SHADER_TESS_EVAL
);
1777 brw_vue_prog_data
*vue_prog_data
= (brw_vue_prog_data
*) prog_data
;
1779 first_non_payload_grf
+= 8 * vue_prog_data
->urb_read_length
;
1781 /* Rewrite all ATTR file references to HW_REGs. */
1782 foreach_block_and_inst(block
, fs_inst
, inst
, cfg
) {
1783 convert_attr_sources_to_hw_regs(inst
);
1788 fs_visitor::assign_gs_urb_setup()
1790 assert(stage
== MESA_SHADER_GEOMETRY
);
1792 brw_vue_prog_data
*vue_prog_data
= (brw_vue_prog_data
*) prog_data
;
1794 first_non_payload_grf
+=
1795 8 * vue_prog_data
->urb_read_length
* nir
->info
.gs
.vertices_in
;
1797 foreach_block_and_inst(block
, fs_inst
, inst
, cfg
) {
1798 /* Rewrite all ATTR file references to GRFs. */
1799 convert_attr_sources_to_hw_regs(inst
);
1805 * Split large virtual GRFs into separate components if we can.
1807 * This is mostly duplicated with what brw_fs_vector_splitting does,
1808 * but that's really conservative because it's afraid of doing
1809 * splitting that doesn't result in real progress after the rest of
1810 * the optimization phases, which would cause infinite looping in
1811 * optimization. We can do it once here, safely. This also has the
1812 * opportunity to split interpolated values, or maybe even uniforms,
1813 * which we don't have at the IR level.
1815 * We want to split, because virtual GRFs are what we register
1816 * allocate and spill (due to contiguousness requirements for some
1817 * instructions), and they're what we naturally generate in the
1818 * codegen process, but most virtual GRFs don't actually need to be
1819 * contiguous sets of GRFs. If we split, we'll end up with reduced
1820 * live intervals and better dead code elimination and coalescing.
1823 fs_visitor::split_virtual_grfs()
1825 int num_vars
= this->alloc
.count
;
1827 /* Count the total number of registers */
1829 int vgrf_to_reg
[num_vars
];
1830 for (int i
= 0; i
< num_vars
; i
++) {
1831 vgrf_to_reg
[i
] = reg_count
;
1832 reg_count
+= alloc
.sizes
[i
];
1835 /* An array of "split points". For each register slot, this indicates
1836 * if this slot can be separated from the previous slot. Every time an
1837 * instruction uses multiple elements of a register (as a source or
1838 * destination), we mark the used slots as inseparable. Then we go
1839 * through and split the registers into the smallest pieces we can.
1841 bool split_points
[reg_count
];
1842 memset(split_points
, 0, sizeof(split_points
));
1844 /* Mark all used registers as fully splittable */
1845 foreach_block_and_inst(block
, fs_inst
, inst
, cfg
) {
1846 if (inst
->dst
.file
== VGRF
) {
1847 int reg
= vgrf_to_reg
[inst
->dst
.nr
];
1848 for (unsigned j
= 1; j
< this->alloc
.sizes
[inst
->dst
.nr
]; j
++)
1849 split_points
[reg
+ j
] = true;
1852 for (int i
= 0; i
< inst
->sources
; i
++) {
1853 if (inst
->src
[i
].file
== VGRF
) {
1854 int reg
= vgrf_to_reg
[inst
->src
[i
].nr
];
1855 for (unsigned j
= 1; j
< this->alloc
.sizes
[inst
->src
[i
].nr
]; j
++)
1856 split_points
[reg
+ j
] = true;
1861 foreach_block_and_inst(block
, fs_inst
, inst
, cfg
) {
1862 if (inst
->dst
.file
== VGRF
) {
1863 int reg
= vgrf_to_reg
[inst
->dst
.nr
] + inst
->dst
.reg_offset
;
1864 for (int j
= 1; j
< inst
->regs_written
; j
++)
1865 split_points
[reg
+ j
] = false;
1867 for (int i
= 0; i
< inst
->sources
; i
++) {
1868 if (inst
->src
[i
].file
== VGRF
) {
1869 int reg
= vgrf_to_reg
[inst
->src
[i
].nr
] + inst
->src
[i
].reg_offset
;
1870 for (int j
= 1; j
< inst
->regs_read(i
); j
++)
1871 split_points
[reg
+ j
] = false;
1876 int new_virtual_grf
[reg_count
];
1877 int new_reg_offset
[reg_count
];
1880 for (int i
= 0; i
< num_vars
; i
++) {
1881 /* The first one should always be 0 as a quick sanity check. */
1882 assert(split_points
[reg
] == false);
1885 new_reg_offset
[reg
] = 0;
1890 for (unsigned j
= 1; j
< alloc
.sizes
[i
]; j
++) {
1891 /* If this is a split point, reset the offset to 0 and allocate a
1892 * new virtual GRF for the previous offset many registers
1894 if (split_points
[reg
]) {
1895 assert(offset
<= MAX_VGRF_SIZE
);
1896 int grf
= alloc
.allocate(offset
);
1897 for (int k
= reg
- offset
; k
< reg
; k
++)
1898 new_virtual_grf
[k
] = grf
;
1901 new_reg_offset
[reg
] = offset
;
1906 /* The last one gets the original register number */
1907 assert(offset
<= MAX_VGRF_SIZE
);
1908 alloc
.sizes
[i
] = offset
;
1909 for (int k
= reg
- offset
; k
< reg
; k
++)
1910 new_virtual_grf
[k
] = i
;
1912 assert(reg
== reg_count
);
1914 foreach_block_and_inst(block
, fs_inst
, inst
, cfg
) {
1915 if (inst
->dst
.file
== VGRF
) {
1916 reg
= vgrf_to_reg
[inst
->dst
.nr
] + inst
->dst
.reg_offset
;
1917 inst
->dst
.nr
= new_virtual_grf
[reg
];
1918 inst
->dst
.reg_offset
= new_reg_offset
[reg
];
1919 assert((unsigned)new_reg_offset
[reg
] < alloc
.sizes
[new_virtual_grf
[reg
]]);
1921 for (int i
= 0; i
< inst
->sources
; i
++) {
1922 if (inst
->src
[i
].file
== VGRF
) {
1923 reg
= vgrf_to_reg
[inst
->src
[i
].nr
] + inst
->src
[i
].reg_offset
;
1924 inst
->src
[i
].nr
= new_virtual_grf
[reg
];
1925 inst
->src
[i
].reg_offset
= new_reg_offset
[reg
];
1926 assert((unsigned)new_reg_offset
[reg
] < alloc
.sizes
[new_virtual_grf
[reg
]]);
1930 invalidate_live_intervals();
1934 * Remove unused virtual GRFs and compact the virtual_grf_* arrays.
1936 * During code generation, we create tons of temporary variables, many of
1937 * which get immediately killed and are never used again. Yet, in later
1938 * optimization and analysis passes, such as compute_live_intervals, we need
1939 * to loop over all the virtual GRFs. Compacting them can save a lot of
1943 fs_visitor::compact_virtual_grfs()
1945 bool progress
= false;
1946 int remap_table
[this->alloc
.count
];
1947 memset(remap_table
, -1, sizeof(remap_table
));
1949 /* Mark which virtual GRFs are used. */
1950 foreach_block_and_inst(block
, const fs_inst
, inst
, cfg
) {
1951 if (inst
->dst
.file
== VGRF
)
1952 remap_table
[inst
->dst
.nr
] = 0;
1954 for (int i
= 0; i
< inst
->sources
; i
++) {
1955 if (inst
->src
[i
].file
== VGRF
)
1956 remap_table
[inst
->src
[i
].nr
] = 0;
1960 /* Compact the GRF arrays. */
1962 for (unsigned i
= 0; i
< this->alloc
.count
; i
++) {
1963 if (remap_table
[i
] == -1) {
1964 /* We just found an unused register. This means that we are
1965 * actually going to compact something.
1969 remap_table
[i
] = new_index
;
1970 alloc
.sizes
[new_index
] = alloc
.sizes
[i
];
1971 invalidate_live_intervals();
1976 this->alloc
.count
= new_index
;
1978 /* Patch all the instructions to use the newly renumbered registers */
1979 foreach_block_and_inst(block
, fs_inst
, inst
, cfg
) {
1980 if (inst
->dst
.file
== VGRF
)
1981 inst
->dst
.nr
= remap_table
[inst
->dst
.nr
];
1983 for (int i
= 0; i
< inst
->sources
; i
++) {
1984 if (inst
->src
[i
].file
== VGRF
)
1985 inst
->src
[i
].nr
= remap_table
[inst
->src
[i
].nr
];
1989 /* Patch all the references to delta_xy, since they're used in register
1990 * allocation. If they're unused, switch them to BAD_FILE so we don't
1991 * think some random VGRF is delta_xy.
1993 for (unsigned i
= 0; i
< ARRAY_SIZE(delta_xy
); i
++) {
1994 if (delta_xy
[i
].file
== VGRF
) {
1995 if (remap_table
[delta_xy
[i
].nr
] != -1) {
1996 delta_xy
[i
].nr
= remap_table
[delta_xy
[i
].nr
];
1998 delta_xy
[i
].file
= BAD_FILE
;
2007 * Assign UNIFORM file registers to either push constants or pull constants.
2009 * We allow a fragment shader to have more than the specified minimum
2010 * maximum number of fragment shader uniform components (64). If
2011 * there are too many of these, they'd fill up all of register space.
2012 * So, this will push some of them out to the pull constant buffer and
2013 * update the program to load them.
2016 fs_visitor::assign_constant_locations()
2018 /* Only the first compile gets to decide on locations. */
2019 if (dispatch_width
!= min_dispatch_width
)
2022 bool is_live
[uniforms
];
2023 memset(is_live
, 0, sizeof(is_live
));
2025 /* For each uniform slot, a value of true indicates that the given slot and
2026 * the next slot must remain contiguous. This is used to keep us from
2027 * splitting arrays apart.
2029 bool contiguous
[uniforms
];
2030 memset(contiguous
, 0, sizeof(contiguous
));
2032 /* First, we walk through the instructions and do two things:
2034 * 1) Figure out which uniforms are live.
2036 * 2) Mark any indirectly used ranges of registers as contiguous.
2038 * Note that we don't move constant-indexed accesses to arrays. No
2039 * testing has been done of the performance impact of this choice.
2041 foreach_block_and_inst_safe(block
, fs_inst
, inst
, cfg
) {
2042 for (int i
= 0 ; i
< inst
->sources
; i
++) {
2043 if (inst
->src
[i
].file
!= UNIFORM
)
2046 int constant_nr
= inst
->src
[i
].nr
+ inst
->src
[i
].reg_offset
;
2048 if (inst
->opcode
== SHADER_OPCODE_MOV_INDIRECT
&& i
== 0) {
2049 assert(inst
->src
[2].ud
% 4 == 0);
2050 unsigned last
= constant_nr
+ (inst
->src
[2].ud
/ 4) - 1;
2051 assert(last
< uniforms
);
2053 for (unsigned j
= constant_nr
; j
< last
; j
++) {
2055 contiguous
[j
] = true;
2057 is_live
[last
] = true;
2059 if (constant_nr
>= 0 && constant_nr
< (int) uniforms
) {
2060 int regs_read
= inst
->components_read(i
) *
2061 type_sz(inst
->src
[i
].type
) / 4;
2062 for (int j
= 0; j
< regs_read
; j
++)
2063 is_live
[constant_nr
+ j
] = true;
2069 /* Only allow 16 registers (128 uniform components) as push constants.
2071 * Just demote the end of the list. We could probably do better
2072 * here, demoting things that are rarely used in the program first.
2074 * If changing this value, note the limitation about total_regs in
2077 const unsigned int max_push_components
= 16 * 8;
2079 /* We push small arrays, but no bigger than 16 floats. This is big enough
2080 * for a vec4 but hopefully not large enough to push out other stuff. We
2081 * should probably use a better heuristic at some point.
2083 const unsigned int max_chunk_size
= 16;
2085 unsigned int num_push_constants
= 0;
2086 unsigned int num_pull_constants
= 0;
2088 push_constant_loc
= ralloc_array(mem_ctx
, int, uniforms
);
2089 pull_constant_loc
= ralloc_array(mem_ctx
, int, uniforms
);
2091 int chunk_start
= -1;
2092 for (unsigned u
= 0; u
< uniforms
; u
++) {
2093 push_constant_loc
[u
] = -1;
2094 pull_constant_loc
[u
] = -1;
2099 /* This is the first live uniform in the chunk */
2100 if (chunk_start
< 0)
2103 /* If this element does not need to be contiguous with the next, we
2104 * split at this point and everthing between chunk_start and u forms a
2107 if (!contiguous
[u
]) {
2108 unsigned chunk_size
= u
- chunk_start
+ 1;
2110 /* Decide whether we should push or pull this parameter. In the
2111 * Vulkan driver, push constants are explicitly exposed via the API
2112 * so we push everything. In GL, we only push small arrays.
2114 if (stage_prog_data
->pull_param
== NULL
||
2115 (num_push_constants
+ chunk_size
<= max_push_components
&&
2116 chunk_size
<= max_chunk_size
)) {
2117 assert(num_push_constants
+ chunk_size
<= max_push_components
);
2118 for (unsigned j
= chunk_start
; j
<= u
; j
++)
2119 push_constant_loc
[j
] = num_push_constants
++;
2121 for (unsigned j
= chunk_start
; j
<= u
; j
++)
2122 pull_constant_loc
[j
] = num_pull_constants
++;
2129 stage_prog_data
->nr_params
= num_push_constants
;
2130 stage_prog_data
->nr_pull_params
= num_pull_constants
;
2132 /* Up until now, the param[] array has been indexed by reg + reg_offset
2133 * of UNIFORM registers. Move pull constants into pull_param[] and
2134 * condense param[] to only contain the uniforms we chose to push.
2136 * NOTE: Because we are condensing the params[] array, we know that
2137 * push_constant_loc[i] <= i and we can do it in one smooth loop without
2138 * having to make a copy.
2140 for (unsigned int i
= 0; i
< uniforms
; i
++) {
2141 const gl_constant_value
*value
= stage_prog_data
->param
[i
];
2143 if (pull_constant_loc
[i
] != -1) {
2144 stage_prog_data
->pull_param
[pull_constant_loc
[i
]] = value
;
2145 } else if (push_constant_loc
[i
] != -1) {
2146 stage_prog_data
->param
[push_constant_loc
[i
]] = value
;
2152 * Replace UNIFORM register file access with either UNIFORM_PULL_CONSTANT_LOAD
2153 * or VARYING_PULL_CONSTANT_LOAD instructions which load values into VGRFs.
2156 fs_visitor::lower_constant_loads()
2158 const unsigned index
= stage_prog_data
->binding_table
.pull_constants_start
;
2160 foreach_block_and_inst_safe (block
, fs_inst
, inst
, cfg
) {
2161 /* Set up the annotation tracking for new generated instructions. */
2162 const fs_builder
ibld(this, block
, inst
);
2164 for (int i
= 0; i
< inst
->sources
; i
++) {
2165 if (inst
->src
[i
].file
!= UNIFORM
)
2168 /* We'll handle this case later */
2169 if (inst
->opcode
== SHADER_OPCODE_MOV_INDIRECT
&& i
== 0)
2172 unsigned location
= inst
->src
[i
].nr
+ inst
->src
[i
].reg_offset
;
2173 if (location
>= uniforms
)
2174 continue; /* Out of bounds access */
2176 int pull_index
= pull_constant_loc
[location
];
2178 if (pull_index
== -1)
2181 assert(inst
->src
[i
].stride
== 0);
2183 fs_reg dst
= vgrf(glsl_type::float_type
);
2184 const fs_builder ubld
= ibld
.exec_all().group(8, 0);
2185 struct brw_reg offset
= brw_imm_ud((unsigned)(pull_index
* 4) & ~15);
2186 ubld
.emit(FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD
,
2187 dst
, brw_imm_ud(index
), offset
);
2189 /* Rewrite the instruction to use the temporary VGRF. */
2190 inst
->src
[i
].file
= VGRF
;
2191 inst
->src
[i
].nr
= dst
.nr
;
2192 inst
->src
[i
].reg_offset
= 0;
2193 inst
->src
[i
].set_smear(pull_index
& 3);
2195 brw_mark_surface_used(prog_data
, index
);
2198 if (inst
->opcode
== SHADER_OPCODE_MOV_INDIRECT
&&
2199 inst
->src
[0].file
== UNIFORM
) {
2201 unsigned location
= inst
->src
[0].nr
+ inst
->src
[0].reg_offset
;
2202 if (location
>= uniforms
)
2203 continue; /* Out of bounds access */
2205 int pull_index
= pull_constant_loc
[location
];
2207 if (pull_index
== -1)
2210 VARYING_PULL_CONSTANT_LOAD(ibld
, inst
->dst
,
2214 inst
->remove(block
);
2216 brw_mark_surface_used(prog_data
, index
);
2219 invalidate_live_intervals();
2223 fs_visitor::opt_algebraic()
2225 bool progress
= false;
2227 foreach_block_and_inst(block
, fs_inst
, inst
, cfg
) {
2228 switch (inst
->opcode
) {
2229 case BRW_OPCODE_MOV
:
2230 if (inst
->src
[0].file
!= IMM
)
2233 if (inst
->saturate
) {
2234 if (inst
->dst
.type
!= inst
->src
[0].type
)
2235 assert(!"unimplemented: saturate mixed types");
2237 if (brw_saturate_immediate(inst
->dst
.type
,
2238 &inst
->src
[0].as_brw_reg())) {
2239 inst
->saturate
= false;
2245 case BRW_OPCODE_MUL
:
2246 if (inst
->src
[1].file
!= IMM
)
2250 if (inst
->src
[1].is_one()) {
2251 inst
->opcode
= BRW_OPCODE_MOV
;
2252 inst
->src
[1] = reg_undef
;
2258 if (inst
->src
[1].is_negative_one()) {
2259 inst
->opcode
= BRW_OPCODE_MOV
;
2260 inst
->src
[0].negate
= !inst
->src
[0].negate
;
2261 inst
->src
[1] = reg_undef
;
2267 if (inst
->src
[1].is_zero()) {
2268 inst
->opcode
= BRW_OPCODE_MOV
;
2269 inst
->src
[0] = inst
->src
[1];
2270 inst
->src
[1] = reg_undef
;
2275 if (inst
->src
[0].file
== IMM
) {
2276 assert(inst
->src
[0].type
== BRW_REGISTER_TYPE_F
);
2277 inst
->opcode
= BRW_OPCODE_MOV
;
2278 inst
->src
[0].f
*= inst
->src
[1].f
;
2279 inst
->src
[1] = reg_undef
;
2284 case BRW_OPCODE_ADD
:
2285 if (inst
->src
[1].file
!= IMM
)
2289 if (inst
->src
[1].is_zero()) {
2290 inst
->opcode
= BRW_OPCODE_MOV
;
2291 inst
->src
[1] = reg_undef
;
2296 if (inst
->src
[0].file
== IMM
) {
2297 assert(inst
->src
[0].type
== BRW_REGISTER_TYPE_F
);
2298 inst
->opcode
= BRW_OPCODE_MOV
;
2299 inst
->src
[0].f
+= inst
->src
[1].f
;
2300 inst
->src
[1] = reg_undef
;
2306 if (inst
->src
[0].equals(inst
->src
[1])) {
2307 inst
->opcode
= BRW_OPCODE_MOV
;
2308 inst
->src
[1] = reg_undef
;
2313 case BRW_OPCODE_LRP
:
2314 if (inst
->src
[1].equals(inst
->src
[2])) {
2315 inst
->opcode
= BRW_OPCODE_MOV
;
2316 inst
->src
[0] = inst
->src
[1];
2317 inst
->src
[1] = reg_undef
;
2318 inst
->src
[2] = reg_undef
;
2323 case BRW_OPCODE_CMP
:
2324 if (inst
->conditional_mod
== BRW_CONDITIONAL_GE
&&
2326 inst
->src
[0].negate
&&
2327 inst
->src
[1].is_zero()) {
2328 inst
->src
[0].abs
= false;
2329 inst
->src
[0].negate
= false;
2330 inst
->conditional_mod
= BRW_CONDITIONAL_Z
;
2335 case BRW_OPCODE_SEL
:
2336 if (inst
->src
[0].equals(inst
->src
[1])) {
2337 inst
->opcode
= BRW_OPCODE_MOV
;
2338 inst
->src
[1] = reg_undef
;
2339 inst
->predicate
= BRW_PREDICATE_NONE
;
2340 inst
->predicate_inverse
= false;
2342 } else if (inst
->saturate
&& inst
->src
[1].file
== IMM
) {
2343 switch (inst
->conditional_mod
) {
2344 case BRW_CONDITIONAL_LE
:
2345 case BRW_CONDITIONAL_L
:
2346 switch (inst
->src
[1].type
) {
2347 case BRW_REGISTER_TYPE_F
:
2348 if (inst
->src
[1].f
>= 1.0f
) {
2349 inst
->opcode
= BRW_OPCODE_MOV
;
2350 inst
->src
[1] = reg_undef
;
2351 inst
->conditional_mod
= BRW_CONDITIONAL_NONE
;
2359 case BRW_CONDITIONAL_GE
:
2360 case BRW_CONDITIONAL_G
:
2361 switch (inst
->src
[1].type
) {
2362 case BRW_REGISTER_TYPE_F
:
2363 if (inst
->src
[1].f
<= 0.0f
) {
2364 inst
->opcode
= BRW_OPCODE_MOV
;
2365 inst
->src
[1] = reg_undef
;
2366 inst
->conditional_mod
= BRW_CONDITIONAL_NONE
;
2378 case BRW_OPCODE_MAD
:
2379 if (inst
->src
[1].is_zero() || inst
->src
[2].is_zero()) {
2380 inst
->opcode
= BRW_OPCODE_MOV
;
2381 inst
->src
[1] = reg_undef
;
2382 inst
->src
[2] = reg_undef
;
2384 } else if (inst
->src
[0].is_zero()) {
2385 inst
->opcode
= BRW_OPCODE_MUL
;
2386 inst
->src
[0] = inst
->src
[2];
2387 inst
->src
[2] = reg_undef
;
2389 } else if (inst
->src
[1].is_one()) {
2390 inst
->opcode
= BRW_OPCODE_ADD
;
2391 inst
->src
[1] = inst
->src
[2];
2392 inst
->src
[2] = reg_undef
;
2394 } else if (inst
->src
[2].is_one()) {
2395 inst
->opcode
= BRW_OPCODE_ADD
;
2396 inst
->src
[2] = reg_undef
;
2398 } else if (inst
->src
[1].file
== IMM
&& inst
->src
[2].file
== IMM
) {
2399 inst
->opcode
= BRW_OPCODE_ADD
;
2400 inst
->src
[1].f
*= inst
->src
[2].f
;
2401 inst
->src
[2] = reg_undef
;
2405 case SHADER_OPCODE_BROADCAST
:
2406 if (is_uniform(inst
->src
[0])) {
2407 inst
->opcode
= BRW_OPCODE_MOV
;
2409 inst
->force_writemask_all
= true;
2411 } else if (inst
->src
[1].file
== IMM
) {
2412 inst
->opcode
= BRW_OPCODE_MOV
;
2413 inst
->src
[0] = component(inst
->src
[0],
2416 inst
->force_writemask_all
= true;
2425 /* Swap if src[0] is immediate. */
2426 if (progress
&& inst
->is_commutative()) {
2427 if (inst
->src
[0].file
== IMM
) {
2428 fs_reg tmp
= inst
->src
[1];
2429 inst
->src
[1] = inst
->src
[0];
2438 * Optimize sample messages that have constant zero values for the trailing
2439 * texture coordinates. We can just reduce the message length for these
2440 * instructions instead of reserving a register for it. Trailing parameters
2441 * that aren't sent default to zero anyway. This will cause the dead code
2442 * eliminator to remove the MOV instruction that would otherwise be emitted to
2443 * set up the zero value.
2446 fs_visitor::opt_zero_samples()
2448 /* Gen4 infers the texturing opcode based on the message length so we can't
2451 if (devinfo
->gen
< 5)
2454 bool progress
= false;
2456 foreach_block_and_inst(block
, fs_inst
, inst
, cfg
) {
2457 if (!inst
->is_tex())
2460 fs_inst
*load_payload
= (fs_inst
*) inst
->prev
;
2462 if (load_payload
->is_head_sentinel() ||
2463 load_payload
->opcode
!= SHADER_OPCODE_LOAD_PAYLOAD
)
2466 /* We don't want to remove the message header or the first parameter.
2467 * Removing the first parameter is not allowed, see the Haswell PRM
2468 * volume 7, page 149:
2470 * "Parameter 0 is required except for the sampleinfo message, which
2471 * has no parameter 0"
2473 while (inst
->mlen
> inst
->header_size
+ inst
->exec_size
/ 8 &&
2474 load_payload
->src
[(inst
->mlen
- inst
->header_size
) /
2475 (inst
->exec_size
/ 8) +
2476 inst
->header_size
- 1].is_zero()) {
2477 inst
->mlen
-= inst
->exec_size
/ 8;
2483 invalidate_live_intervals();
2489 * Optimize sample messages which are followed by the final RT write.
2491 * CHV, and GEN9+ can mark a texturing SEND instruction with EOT to have its
2492 * results sent directly to the framebuffer, bypassing the EU. Recognize the
2493 * final texturing results copied to the framebuffer write payload and modify
2494 * them to write to the framebuffer directly.
2497 fs_visitor::opt_sampler_eot()
2499 brw_wm_prog_key
*key
= (brw_wm_prog_key
*) this->key
;
2501 if (stage
!= MESA_SHADER_FRAGMENT
)
2504 if (devinfo
->gen
< 9 && !devinfo
->is_cherryview
)
2507 /* FINISHME: It should be possible to implement this optimization when there
2508 * are multiple drawbuffers.
2510 if (key
->nr_color_regions
!= 1)
2513 /* Look for a texturing instruction immediately before the final FB_WRITE. */
2514 bblock_t
*block
= cfg
->blocks
[cfg
->num_blocks
- 1];
2515 fs_inst
*fb_write
= (fs_inst
*)block
->end();
2516 assert(fb_write
->eot
);
2517 assert(fb_write
->opcode
== FS_OPCODE_FB_WRITE
);
2519 fs_inst
*tex_inst
= (fs_inst
*) fb_write
->prev
;
2521 /* There wasn't one; nothing to do. */
2522 if (unlikely(tex_inst
->is_head_sentinel()) || !tex_inst
->is_tex())
2525 /* 3D Sampler » Messages » Message Format
2527 * “Response Length of zero is allowed on all SIMD8* and SIMD16* sampler
2528 * messages except sample+killpix, resinfo, sampleinfo, LOD, and gather4*”
2530 if (tex_inst
->opcode
== SHADER_OPCODE_TXS
||
2531 tex_inst
->opcode
== SHADER_OPCODE_SAMPLEINFO
||
2532 tex_inst
->opcode
== SHADER_OPCODE_LOD
||
2533 tex_inst
->opcode
== SHADER_OPCODE_TG4
||
2534 tex_inst
->opcode
== SHADER_OPCODE_TG4_OFFSET
)
2537 /* If there's no header present, we need to munge the LOAD_PAYLOAD as well.
2538 * It's very likely to be the previous instruction.
2540 fs_inst
*load_payload
= (fs_inst
*) tex_inst
->prev
;
2541 if (load_payload
->is_head_sentinel() ||
2542 load_payload
->opcode
!= SHADER_OPCODE_LOAD_PAYLOAD
)
2545 assert(!tex_inst
->eot
); /* We can't get here twice */
2546 assert((tex_inst
->offset
& (0xff << 24)) == 0);
2548 const fs_builder
ibld(this, block
, tex_inst
);
2550 tex_inst
->offset
|= fb_write
->target
<< 24;
2551 tex_inst
->eot
= true;
2552 tex_inst
->dst
= ibld
.null_reg_ud();
2553 tex_inst
->regs_written
= 0;
2554 fb_write
->remove(cfg
->blocks
[cfg
->num_blocks
- 1]);
2556 /* If a header is present, marking the eot is sufficient. Otherwise, we need
2557 * to create a new LOAD_PAYLOAD command with the same sources and a space
2558 * saved for the header. Using a new destination register not only makes sure
2559 * we have enough space, but it will make sure the dead code eliminator kills
2560 * the instruction that this will replace.
2562 if (tex_inst
->header_size
!= 0) {
2563 invalidate_live_intervals();
2567 fs_reg send_header
= ibld
.vgrf(BRW_REGISTER_TYPE_F
,
2568 load_payload
->sources
+ 1);
2569 fs_reg
*new_sources
=
2570 ralloc_array(mem_ctx
, fs_reg
, load_payload
->sources
+ 1);
2572 new_sources
[0] = fs_reg();
2573 for (int i
= 0; i
< load_payload
->sources
; i
++)
2574 new_sources
[i
+1] = load_payload
->src
[i
];
2576 /* The LOAD_PAYLOAD helper seems like the obvious choice here. However, it
2577 * requires a lot of information about the sources to appropriately figure
2578 * out the number of registers needed to be used. Given this stage in our
2579 * optimization, we may not have the appropriate GRFs required by
2580 * LOAD_PAYLOAD at this point (copy propagation). Therefore, we need to
2581 * manually emit the instruction.
2583 fs_inst
*new_load_payload
= new(mem_ctx
) fs_inst(SHADER_OPCODE_LOAD_PAYLOAD
,
2584 load_payload
->exec_size
,
2587 load_payload
->sources
+ 1);
2589 new_load_payload
->regs_written
= load_payload
->regs_written
+ 1;
2590 new_load_payload
->header_size
= 1;
2592 tex_inst
->header_size
= 1;
2593 tex_inst
->insert_before(cfg
->blocks
[cfg
->num_blocks
- 1], new_load_payload
);
2594 tex_inst
->src
[0] = send_header
;
2596 invalidate_live_intervals();
2601 fs_visitor::opt_register_renaming()
2603 bool progress
= false;
2606 int remap
[alloc
.count
];
2607 memset(remap
, -1, sizeof(int) * alloc
.count
);
2609 foreach_block_and_inst(block
, fs_inst
, inst
, cfg
) {
2610 if (inst
->opcode
== BRW_OPCODE_IF
|| inst
->opcode
== BRW_OPCODE_DO
) {
2612 } else if (inst
->opcode
== BRW_OPCODE_ENDIF
||
2613 inst
->opcode
== BRW_OPCODE_WHILE
) {
2617 /* Rewrite instruction sources. */
2618 for (int i
= 0; i
< inst
->sources
; i
++) {
2619 if (inst
->src
[i
].file
== VGRF
&&
2620 remap
[inst
->src
[i
].nr
] != -1 &&
2621 remap
[inst
->src
[i
].nr
] != inst
->src
[i
].nr
) {
2622 inst
->src
[i
].nr
= remap
[inst
->src
[i
].nr
];
2627 const int dst
= inst
->dst
.nr
;
2630 inst
->dst
.file
== VGRF
&&
2631 alloc
.sizes
[inst
->dst
.nr
] == inst
->exec_size
/ 8 &&
2632 !inst
->is_partial_write()) {
2633 if (remap
[dst
] == -1) {
2636 remap
[dst
] = alloc
.allocate(inst
->exec_size
/ 8);
2637 inst
->dst
.nr
= remap
[dst
];
2640 } else if (inst
->dst
.file
== VGRF
&&
2642 remap
[dst
] != dst
) {
2643 inst
->dst
.nr
= remap
[dst
];
2649 invalidate_live_intervals();
2651 for (unsigned i
= 0; i
< ARRAY_SIZE(delta_xy
); i
++) {
2652 if (delta_xy
[i
].file
== VGRF
&& remap
[delta_xy
[i
].nr
] != -1) {
2653 delta_xy
[i
].nr
= remap
[delta_xy
[i
].nr
];
2662 * Remove redundant or useless discard jumps.
2664 * For example, we can eliminate jumps in the following sequence:
2666 * discard-jump (redundant with the next jump)
2667 * discard-jump (useless; jumps to the next instruction)
2671 fs_visitor::opt_redundant_discard_jumps()
2673 bool progress
= false;
2675 bblock_t
*last_bblock
= cfg
->blocks
[cfg
->num_blocks
- 1];
2677 fs_inst
*placeholder_halt
= NULL
;
2678 foreach_inst_in_block_reverse(fs_inst
, inst
, last_bblock
) {
2679 if (inst
->opcode
== FS_OPCODE_PLACEHOLDER_HALT
) {
2680 placeholder_halt
= inst
;
2685 if (!placeholder_halt
)
2688 /* Delete any HALTs immediately before the placeholder halt. */
2689 for (fs_inst
*prev
= (fs_inst
*) placeholder_halt
->prev
;
2690 !prev
->is_head_sentinel() && prev
->opcode
== FS_OPCODE_DISCARD_JUMP
;
2691 prev
= (fs_inst
*) placeholder_halt
->prev
) {
2692 prev
->remove(last_bblock
);
2697 invalidate_live_intervals();
2703 fs_visitor::compute_to_mrf()
2705 bool progress
= false;
2708 /* No MRFs on Gen >= 7. */
2709 if (devinfo
->gen
>= 7)
2712 calculate_live_intervals();
2714 foreach_block_and_inst_safe(block
, fs_inst
, inst
, cfg
) {
2718 if (inst
->opcode
!= BRW_OPCODE_MOV
||
2719 inst
->is_partial_write() ||
2720 inst
->dst
.file
!= MRF
|| inst
->src
[0].file
!= VGRF
||
2721 inst
->dst
.type
!= inst
->src
[0].type
||
2722 inst
->src
[0].abs
|| inst
->src
[0].negate
||
2723 !inst
->src
[0].is_contiguous() ||
2724 inst
->src
[0].subreg_offset
)
2727 /* Work out which hardware MRF registers are written by this
2730 int mrf_low
= inst
->dst
.nr
& ~BRW_MRF_COMPR4
;
2732 if (inst
->dst
.nr
& BRW_MRF_COMPR4
) {
2733 mrf_high
= mrf_low
+ 4;
2734 } else if (inst
->exec_size
== 16) {
2735 mrf_high
= mrf_low
+ 1;
2740 /* Can't compute-to-MRF this GRF if someone else was going to
2743 if (this->virtual_grf_end
[inst
->src
[0].nr
] > ip
)
2746 /* Found a move of a GRF to a MRF. Let's see if we can go
2747 * rewrite the thing that made this GRF to write into the MRF.
2749 foreach_inst_in_block_reverse_starting_from(fs_inst
, scan_inst
, inst
) {
2750 if (scan_inst
->dst
.file
== VGRF
&&
2751 scan_inst
->dst
.nr
== inst
->src
[0].nr
) {
2752 /* Found the last thing to write our reg we want to turn
2753 * into a compute-to-MRF.
2756 /* If this one instruction didn't populate all the
2757 * channels, bail. We might be able to rewrite everything
2758 * that writes that reg, but it would require smarter
2759 * tracking to delay the rewriting until complete success.
2761 if (scan_inst
->is_partial_write())
2764 /* Things returning more than one register would need us to
2765 * understand coalescing out more than one MOV at a time.
2767 if (scan_inst
->regs_written
> scan_inst
->exec_size
/ 8)
2770 /* SEND instructions can't have MRF as a destination. */
2771 if (scan_inst
->mlen
)
2774 if (devinfo
->gen
== 6) {
2775 /* gen6 math instructions must have the destination be
2776 * GRF, so no compute-to-MRF for them.
2778 if (scan_inst
->is_math()) {
2783 if (scan_inst
->dst
.reg_offset
== inst
->src
[0].reg_offset
) {
2784 /* Found the creator of our MRF's source value. */
2785 scan_inst
->dst
.file
= MRF
;
2786 scan_inst
->dst
.nr
= inst
->dst
.nr
;
2787 scan_inst
->saturate
|= inst
->saturate
;
2788 inst
->remove(block
);
2794 /* We don't handle control flow here. Most computation of
2795 * values that end up in MRFs are shortly before the MRF
2798 if (block
->start() == scan_inst
)
2801 /* You can't read from an MRF, so if someone else reads our
2802 * MRF's source GRF that we wanted to rewrite, that stops us.
2804 bool interfered
= false;
2805 for (int i
= 0; i
< scan_inst
->sources
; i
++) {
2806 if (scan_inst
->src
[i
].file
== VGRF
&&
2807 scan_inst
->src
[i
].nr
== inst
->src
[0].nr
&&
2808 scan_inst
->src
[i
].reg_offset
== inst
->src
[0].reg_offset
) {
2815 if (scan_inst
->dst
.file
== MRF
) {
2816 /* If somebody else writes our MRF here, we can't
2817 * compute-to-MRF before that.
2819 int scan_mrf_low
= scan_inst
->dst
.nr
& ~BRW_MRF_COMPR4
;
2822 if (scan_inst
->dst
.nr
& BRW_MRF_COMPR4
) {
2823 scan_mrf_high
= scan_mrf_low
+ 4;
2824 } else if (scan_inst
->exec_size
== 16) {
2825 scan_mrf_high
= scan_mrf_low
+ 1;
2827 scan_mrf_high
= scan_mrf_low
;
2830 if (mrf_low
== scan_mrf_low
||
2831 mrf_low
== scan_mrf_high
||
2832 mrf_high
== scan_mrf_low
||
2833 mrf_high
== scan_mrf_high
) {
2838 if (scan_inst
->mlen
> 0 && scan_inst
->base_mrf
!= -1) {
2839 /* Found a SEND instruction, which means that there are
2840 * live values in MRFs from base_mrf to base_mrf +
2841 * scan_inst->mlen - 1. Don't go pushing our MRF write up
2844 if (mrf_low
>= scan_inst
->base_mrf
&&
2845 mrf_low
< scan_inst
->base_mrf
+ scan_inst
->mlen
) {
2848 if (mrf_high
>= scan_inst
->base_mrf
&&
2849 mrf_high
< scan_inst
->base_mrf
+ scan_inst
->mlen
) {
2857 invalidate_live_intervals();
2863 * Eliminate FIND_LIVE_CHANNEL instructions occurring outside any control
2864 * flow. We could probably do better here with some form of divergence
2868 fs_visitor::eliminate_find_live_channel()
2870 bool progress
= false;
2873 foreach_block_and_inst_safe(block
, fs_inst
, inst
, cfg
) {
2874 switch (inst
->opcode
) {
2880 case BRW_OPCODE_ENDIF
:
2881 case BRW_OPCODE_WHILE
:
2885 case FS_OPCODE_DISCARD_JUMP
:
2886 /* This can potentially make control flow non-uniform until the end
2891 case SHADER_OPCODE_FIND_LIVE_CHANNEL
:
2893 inst
->opcode
= BRW_OPCODE_MOV
;
2894 inst
->src
[0] = brw_imm_ud(0u);
2896 inst
->force_writemask_all
= true;
2910 * Once we've generated code, try to convert normal FS_OPCODE_FB_WRITE
2911 * instructions to FS_OPCODE_REP_FB_WRITE.
2914 fs_visitor::emit_repclear_shader()
2916 brw_wm_prog_key
*key
= (brw_wm_prog_key
*) this->key
;
2918 int color_mrf
= base_mrf
+ 2;
2922 mov
= bld
.exec_all().group(4, 0)
2923 .MOV(brw_message_reg(color_mrf
),
2924 fs_reg(UNIFORM
, 0, BRW_REGISTER_TYPE_F
));
2926 struct brw_reg reg
=
2927 brw_reg(BRW_GENERAL_REGISTER_FILE
, 2, 3, 0, 0, BRW_REGISTER_TYPE_F
,
2928 BRW_VERTICAL_STRIDE_8
, BRW_WIDTH_2
, BRW_HORIZONTAL_STRIDE_4
,
2929 BRW_SWIZZLE_XYZW
, WRITEMASK_XYZW
);
2931 mov
= bld
.exec_all().group(4, 0)
2932 .MOV(vec4(brw_message_reg(color_mrf
)), fs_reg(reg
));
2936 if (key
->nr_color_regions
== 1) {
2937 write
= bld
.emit(FS_OPCODE_REP_FB_WRITE
);
2938 write
->saturate
= key
->clamp_fragment_color
;
2939 write
->base_mrf
= color_mrf
;
2941 write
->header_size
= 0;
2944 assume(key
->nr_color_regions
> 0);
2945 for (int i
= 0; i
< key
->nr_color_regions
; ++i
) {
2946 write
= bld
.emit(FS_OPCODE_REP_FB_WRITE
);
2947 write
->saturate
= key
->clamp_fragment_color
;
2948 write
->base_mrf
= base_mrf
;
2950 write
->header_size
= 2;
2958 assign_constant_locations();
2959 assign_curb_setup();
2961 /* Now that we have the uniform assigned, go ahead and force it to a vec4. */
2963 assert(mov
->src
[0].file
== FIXED_GRF
);
2964 mov
->src
[0] = brw_vec4_grf(mov
->src
[0].nr
, 0);
2969 * Walks through basic blocks, looking for repeated MRF writes and
2970 * removing the later ones.
2973 fs_visitor::remove_duplicate_mrf_writes()
2975 fs_inst
*last_mrf_move
[BRW_MAX_MRF(devinfo
->gen
)];
2976 bool progress
= false;
2978 /* Need to update the MRF tracking for compressed instructions. */
2979 if (dispatch_width
== 16)
2982 memset(last_mrf_move
, 0, sizeof(last_mrf_move
));
2984 foreach_block_and_inst_safe (block
, fs_inst
, inst
, cfg
) {
2985 if (inst
->is_control_flow()) {
2986 memset(last_mrf_move
, 0, sizeof(last_mrf_move
));
2989 if (inst
->opcode
== BRW_OPCODE_MOV
&&
2990 inst
->dst
.file
== MRF
) {
2991 fs_inst
*prev_inst
= last_mrf_move
[inst
->dst
.nr
];
2992 if (prev_inst
&& inst
->equals(prev_inst
)) {
2993 inst
->remove(block
);
2999 /* Clear out the last-write records for MRFs that were overwritten. */
3000 if (inst
->dst
.file
== MRF
) {
3001 last_mrf_move
[inst
->dst
.nr
] = NULL
;
3004 if (inst
->mlen
> 0 && inst
->base_mrf
!= -1) {
3005 /* Found a SEND instruction, which will include two or fewer
3006 * implied MRF writes. We could do better here.
3008 for (int i
= 0; i
< implied_mrf_writes(inst
); i
++) {
3009 last_mrf_move
[inst
->base_mrf
+ i
] = NULL
;
3013 /* Clear out any MRF move records whose sources got overwritten. */
3014 if (inst
->dst
.file
== VGRF
) {
3015 for (unsigned int i
= 0; i
< ARRAY_SIZE(last_mrf_move
); i
++) {
3016 if (last_mrf_move
[i
] &&
3017 last_mrf_move
[i
]->src
[0].nr
== inst
->dst
.nr
) {
3018 last_mrf_move
[i
] = NULL
;
3023 if (inst
->opcode
== BRW_OPCODE_MOV
&&
3024 inst
->dst
.file
== MRF
&&
3025 inst
->src
[0].file
== VGRF
&&
3026 !inst
->is_partial_write()) {
3027 last_mrf_move
[inst
->dst
.nr
] = inst
;
3032 invalidate_live_intervals();
3038 clear_deps_for_inst_src(fs_inst
*inst
, bool *deps
, int first_grf
, int grf_len
)
3040 /* Clear the flag for registers that actually got read (as expected). */
3041 for (int i
= 0; i
< inst
->sources
; i
++) {
3043 if (inst
->src
[i
].file
== VGRF
|| inst
->src
[i
].file
== FIXED_GRF
) {
3044 grf
= inst
->src
[i
].nr
;
3049 if (grf
>= first_grf
&&
3050 grf
< first_grf
+ grf_len
) {
3051 deps
[grf
- first_grf
] = false;
3052 if (inst
->exec_size
== 16)
3053 deps
[grf
- first_grf
+ 1] = false;
3059 * Implements this workaround for the original 965:
3061 * "[DevBW, DevCL] Implementation Restrictions: As the hardware does not
3062 * check for post destination dependencies on this instruction, software
3063 * must ensure that there is no destination hazard for the case of ‘write
3064 * followed by a posted write’ shown in the following example.
3067 * 2. send r3.xy <rest of send instruction>
3070 * Due to no post-destination dependency check on the ‘send’, the above
3071 * code sequence could have two instructions (1 and 2) in flight at the
3072 * same time that both consider ‘r3’ as the target of their final writes.
3075 fs_visitor::insert_gen4_pre_send_dependency_workarounds(bblock_t
*block
,
3078 int write_len
= inst
->regs_written
;
3079 int first_write_grf
= inst
->dst
.nr
;
3080 bool needs_dep
[BRW_MAX_MRF(devinfo
->gen
)];
3081 assert(write_len
< (int)sizeof(needs_dep
) - 1);
3083 memset(needs_dep
, false, sizeof(needs_dep
));
3084 memset(needs_dep
, true, write_len
);
3086 clear_deps_for_inst_src(inst
, needs_dep
, first_write_grf
, write_len
);
3088 /* Walk backwards looking for writes to registers we're writing which
3089 * aren't read since being written. If we hit the start of the program,
3090 * we assume that there are no outstanding dependencies on entry to the
3093 foreach_inst_in_block_reverse_starting_from(fs_inst
, scan_inst
, inst
) {
3094 /* If we hit control flow, assume that there *are* outstanding
3095 * dependencies, and force their cleanup before our instruction.
3097 if (block
->start() == scan_inst
) {
3098 for (int i
= 0; i
< write_len
; i
++) {
3100 DEP_RESOLVE_MOV(fs_builder(this, block
, inst
),
3101 first_write_grf
+ i
);
3106 /* We insert our reads as late as possible on the assumption that any
3107 * instruction but a MOV that might have left us an outstanding
3108 * dependency has more latency than a MOV.
3110 if (scan_inst
->dst
.file
== VGRF
) {
3111 for (int i
= 0; i
< scan_inst
->regs_written
; i
++) {
3112 int reg
= scan_inst
->dst
.nr
+ i
;
3114 if (reg
>= first_write_grf
&&
3115 reg
< first_write_grf
+ write_len
&&
3116 needs_dep
[reg
- first_write_grf
]) {
3117 DEP_RESOLVE_MOV(fs_builder(this, block
, inst
), reg
);
3118 needs_dep
[reg
- first_write_grf
] = false;
3119 if (scan_inst
->exec_size
== 16)
3120 needs_dep
[reg
- first_write_grf
+ 1] = false;
3125 /* Clear the flag for registers that actually got read (as expected). */
3126 clear_deps_for_inst_src(scan_inst
, needs_dep
, first_write_grf
, write_len
);
3128 /* Continue the loop only if we haven't resolved all the dependencies */
3130 for (i
= 0; i
< write_len
; i
++) {
3140 * Implements this workaround for the original 965:
3142 * "[DevBW, DevCL] Errata: A destination register from a send can not be
3143 * used as a destination register until after it has been sourced by an
3144 * instruction with a different destination register.
3147 fs_visitor::insert_gen4_post_send_dependency_workarounds(bblock_t
*block
, fs_inst
*inst
)
3149 int write_len
= inst
->regs_written
;
3150 int first_write_grf
= inst
->dst
.nr
;
3151 bool needs_dep
[BRW_MAX_MRF(devinfo
->gen
)];
3152 assert(write_len
< (int)sizeof(needs_dep
) - 1);
3154 memset(needs_dep
, false, sizeof(needs_dep
));
3155 memset(needs_dep
, true, write_len
);
3156 /* Walk forwards looking for writes to registers we're writing which aren't
3157 * read before being written.
3159 foreach_inst_in_block_starting_from(fs_inst
, scan_inst
, inst
) {
3160 /* If we hit control flow, force resolve all remaining dependencies. */
3161 if (block
->end() == scan_inst
) {
3162 for (int i
= 0; i
< write_len
; i
++) {
3164 DEP_RESOLVE_MOV(fs_builder(this, block
, scan_inst
),
3165 first_write_grf
+ i
);
3170 /* Clear the flag for registers that actually got read (as expected). */
3171 clear_deps_for_inst_src(scan_inst
, needs_dep
, first_write_grf
, write_len
);
3173 /* We insert our reads as late as possible since they're reading the
3174 * result of a SEND, which has massive latency.
3176 if (scan_inst
->dst
.file
== VGRF
&&
3177 scan_inst
->dst
.nr
>= first_write_grf
&&
3178 scan_inst
->dst
.nr
< first_write_grf
+ write_len
&&
3179 needs_dep
[scan_inst
->dst
.nr
- first_write_grf
]) {
3180 DEP_RESOLVE_MOV(fs_builder(this, block
, scan_inst
),
3182 needs_dep
[scan_inst
->dst
.nr
- first_write_grf
] = false;
3185 /* Continue the loop only if we haven't resolved all the dependencies */
3187 for (i
= 0; i
< write_len
; i
++) {
3197 fs_visitor::insert_gen4_send_dependency_workarounds()
3199 if (devinfo
->gen
!= 4 || devinfo
->is_g4x
)
3202 bool progress
= false;
3204 /* Note that we're done with register allocation, so GRF fs_regs always
3205 * have a .reg_offset of 0.
3208 foreach_block_and_inst(block
, fs_inst
, inst
, cfg
) {
3209 if (inst
->mlen
!= 0 && inst
->dst
.file
== VGRF
) {
3210 insert_gen4_pre_send_dependency_workarounds(block
, inst
);
3211 insert_gen4_post_send_dependency_workarounds(block
, inst
);
3217 invalidate_live_intervals();
3221 * Turns the generic expression-style uniform pull constant load instruction
3222 * into a hardware-specific series of instructions for loading a pull
3225 * The expression style allows the CSE pass before this to optimize out
3226 * repeated loads from the same offset, and gives the pre-register-allocation
3227 * scheduling full flexibility, while the conversion to native instructions
3228 * allows the post-register-allocation scheduler the best information
3231 * Note that execution masking for setting up pull constant loads is special:
3232 * the channels that need to be written are unrelated to the current execution
3233 * mask, since a later instruction will use one of the result channels as a
3234 * source operand for all 8 or 16 of its channels.
3237 fs_visitor::lower_uniform_pull_constant_loads()
3239 foreach_block_and_inst (block
, fs_inst
, inst
, cfg
) {
3240 if (inst
->opcode
!= FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD
)
3243 if (devinfo
->gen
>= 7) {
3244 /* The offset arg is a vec4-aligned immediate byte offset. */
3245 fs_reg const_offset_reg
= inst
->src
[1];
3246 assert(const_offset_reg
.file
== IMM
&&
3247 const_offset_reg
.type
== BRW_REGISTER_TYPE_UD
);
3248 assert(const_offset_reg
.ud
% 16 == 0);
3250 fs_reg payload
, offset
;
3251 if (devinfo
->gen
>= 9) {
3252 /* We have to use a message header on Skylake to get SIMD4x2
3253 * mode. Reserve space for the register.
3255 offset
= payload
= fs_reg(VGRF
, alloc
.allocate(2));
3256 offset
.reg_offset
++;
3259 offset
= payload
= fs_reg(VGRF
, alloc
.allocate(1));
3263 /* This is actually going to be a MOV, but since only the first dword
3264 * is accessed, we have a special opcode to do just that one. Note
3265 * that this needs to be an operation that will be considered a def
3266 * by live variable analysis, or register allocation will explode.
3268 fs_inst
*setup
= new(mem_ctx
) fs_inst(FS_OPCODE_SET_SIMD4X2_OFFSET
,
3269 8, offset
, const_offset_reg
);
3270 setup
->force_writemask_all
= true;
3272 setup
->ir
= inst
->ir
;
3273 setup
->annotation
= inst
->annotation
;
3274 inst
->insert_before(block
, setup
);
3276 /* Similarly, this will only populate the first 4 channels of the
3277 * result register (since we only use smear values from 0-3), but we
3278 * don't tell the optimizer.
3280 inst
->opcode
= FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD_GEN7
;
3281 inst
->src
[1] = payload
;
3282 inst
->base_mrf
= -1;
3284 invalidate_live_intervals();
3286 /* Before register allocation, we didn't tell the scheduler about the
3287 * MRF we use. We know it's safe to use this MRF because nothing
3288 * else does except for register spill/unspill, which generates and
3289 * uses its MRF within a single IR instruction.
3291 inst
->base_mrf
= FIRST_PULL_LOAD_MRF(devinfo
->gen
) + 1;
3298 fs_visitor::lower_load_payload()
3300 bool progress
= false;
3302 foreach_block_and_inst_safe (block
, fs_inst
, inst
, cfg
) {
3303 if (inst
->opcode
!= SHADER_OPCODE_LOAD_PAYLOAD
)
3306 assert(inst
->dst
.file
== MRF
|| inst
->dst
.file
== VGRF
);
3307 assert(inst
->saturate
== false);
3308 fs_reg dst
= inst
->dst
;
3310 /* Get rid of COMPR4. We'll add it back in if we need it */
3311 if (dst
.file
== MRF
)
3312 dst
.nr
= dst
.nr
& ~BRW_MRF_COMPR4
;
3314 const fs_builder
ibld(this, block
, inst
);
3315 const fs_builder hbld
= ibld
.exec_all().group(8, 0);
3317 for (uint8_t i
= 0; i
< inst
->header_size
; i
++) {
3318 if (inst
->src
[i
].file
!= BAD_FILE
) {
3319 fs_reg mov_dst
= retype(dst
, BRW_REGISTER_TYPE_UD
);
3320 fs_reg mov_src
= retype(inst
->src
[i
], BRW_REGISTER_TYPE_UD
);
3321 hbld
.MOV(mov_dst
, mov_src
);
3323 dst
= offset(dst
, hbld
, 1);
3326 if (inst
->dst
.file
== MRF
&& (inst
->dst
.nr
& BRW_MRF_COMPR4
) &&
3327 inst
->exec_size
> 8) {
3328 /* In this case, the payload portion of the LOAD_PAYLOAD isn't
3329 * a straightforward copy. Instead, the result of the
3330 * LOAD_PAYLOAD is treated as interleaved and the first four
3331 * non-header sources are unpacked as:
3342 * This is used for gen <= 5 fb writes.
3344 assert(inst
->exec_size
== 16);
3345 assert(inst
->header_size
+ 4 <= inst
->sources
);
3346 for (uint8_t i
= inst
->header_size
; i
< inst
->header_size
+ 4; i
++) {
3347 if (inst
->src
[i
].file
!= BAD_FILE
) {
3348 if (devinfo
->has_compr4
) {
3349 fs_reg compr4_dst
= retype(dst
, inst
->src
[i
].type
);
3350 compr4_dst
.nr
|= BRW_MRF_COMPR4
;
3351 ibld
.MOV(compr4_dst
, inst
->src
[i
]);
3353 /* Platform doesn't have COMPR4. We have to fake it */
3354 fs_reg mov_dst
= retype(dst
, inst
->src
[i
].type
);
3355 ibld
.half(0).MOV(mov_dst
, half(inst
->src
[i
], 0));
3357 ibld
.half(1).MOV(mov_dst
, half(inst
->src
[i
], 1));
3364 /* The loop above only ever incremented us through the first set
3365 * of 4 registers. However, thanks to the magic of COMPR4, we
3366 * actually wrote to the first 8 registers, so we need to take
3367 * that into account now.
3371 /* The COMPR4 code took care of the first 4 sources. We'll let
3372 * the regular path handle any remaining sources. Yes, we are
3373 * modifying the instruction but we're about to delete it so
3374 * this really doesn't hurt anything.
3376 inst
->header_size
+= 4;
3379 for (uint8_t i
= inst
->header_size
; i
< inst
->sources
; i
++) {
3380 if (inst
->src
[i
].file
!= BAD_FILE
)
3381 ibld
.MOV(retype(dst
, inst
->src
[i
].type
), inst
->src
[i
]);
3382 dst
= offset(dst
, ibld
, 1);
3385 inst
->remove(block
);
3390 invalidate_live_intervals();
3396 fs_visitor::lower_integer_multiplication()
3398 bool progress
= false;
3400 foreach_block_and_inst_safe(block
, fs_inst
, inst
, cfg
) {
3401 const fs_builder
ibld(this, block
, inst
);
3403 if (inst
->opcode
== BRW_OPCODE_MUL
) {
3404 if (inst
->dst
.is_accumulator() ||
3405 (inst
->dst
.type
!= BRW_REGISTER_TYPE_D
&&
3406 inst
->dst
.type
!= BRW_REGISTER_TYPE_UD
))
3409 /* Gen8's MUL instruction can do a 32-bit x 32-bit -> 32-bit
3410 * operation directly, but CHV/BXT cannot.
3412 if (devinfo
->gen
>= 8 &&
3413 !devinfo
->is_cherryview
&& !devinfo
->is_broxton
)
3416 if (inst
->src
[1].file
== IMM
&&
3417 inst
->src
[1].ud
< (1 << 16)) {
3418 /* The MUL instruction isn't commutative. On Gen <= 6, only the low
3419 * 16-bits of src0 are read, and on Gen >= 7 only the low 16-bits of
3422 * If multiplying by an immediate value that fits in 16-bits, do a
3423 * single MUL instruction with that value in the proper location.
3425 if (devinfo
->gen
< 7) {
3426 fs_reg
imm(VGRF
, alloc
.allocate(dispatch_width
/ 8),
3428 ibld
.MOV(imm
, inst
->src
[1]);
3429 ibld
.MUL(inst
->dst
, imm
, inst
->src
[0]);
3431 ibld
.MUL(inst
->dst
, inst
->src
[0], inst
->src
[1]);
3434 /* Gen < 8 (and some Gen8+ low-power parts like Cherryview) cannot
3435 * do 32-bit integer multiplication in one instruction, but instead
3436 * must do a sequence (which actually calculates a 64-bit result):
3438 * mul(8) acc0<1>D g3<8,8,1>D g4<8,8,1>D
3439 * mach(8) null g3<8,8,1>D g4<8,8,1>D
3440 * mov(8) g2<1>D acc0<8,8,1>D
3442 * But on Gen > 6, the ability to use second accumulator register
3443 * (acc1) for non-float data types was removed, preventing a simple
3444 * implementation in SIMD16. A 16-channel result can be calculated by
3445 * executing the three instructions twice in SIMD8, once with quarter
3446 * control of 1Q for the first eight channels and again with 2Q for
3447 * the second eight channels.
3449 * Which accumulator register is implicitly accessed (by AccWrEnable
3450 * for instance) is determined by the quarter control. Unfortunately
3451 * Ivybridge (and presumably Baytrail) has a hardware bug in which an
3452 * implicit accumulator access by an instruction with 2Q will access
3453 * acc1 regardless of whether the data type is usable in acc1.
3455 * Specifically, the 2Q mach(8) writes acc1 which does not exist for
3456 * integer data types.
3458 * Since we only want the low 32-bits of the result, we can do two
3459 * 32-bit x 16-bit multiplies (like the mul and mach are doing), and
3460 * adjust the high result and add them (like the mach is doing):
3462 * mul(8) g7<1>D g3<8,8,1>D g4.0<8,8,1>UW
3463 * mul(8) g8<1>D g3<8,8,1>D g4.1<8,8,1>UW
3464 * shl(8) g9<1>D g8<8,8,1>D 16D
3465 * add(8) g2<1>D g7<8,8,1>D g8<8,8,1>D
3467 * We avoid the shl instruction by realizing that we only want to add
3468 * the low 16-bits of the "high" result to the high 16-bits of the
3469 * "low" result and using proper regioning on the add:
3471 * mul(8) g7<1>D g3<8,8,1>D g4.0<16,8,2>UW
3472 * mul(8) g8<1>D g3<8,8,1>D g4.1<16,8,2>UW
3473 * add(8) g7.1<2>UW g7.1<16,8,2>UW g8<16,8,2>UW
3475 * Since it does not use the (single) accumulator register, we can
3476 * schedule multi-component multiplications much better.
3479 fs_reg orig_dst
= inst
->dst
;
3480 if (orig_dst
.is_null() || orig_dst
.file
== MRF
) {
3481 inst
->dst
= fs_reg(VGRF
, alloc
.allocate(dispatch_width
/ 8),
3484 fs_reg low
= inst
->dst
;
3485 fs_reg
high(VGRF
, alloc
.allocate(dispatch_width
/ 8),
3488 if (devinfo
->gen
>= 7) {
3489 fs_reg src1_0_w
= inst
->src
[1];
3490 fs_reg src1_1_w
= inst
->src
[1];
3492 if (inst
->src
[1].file
== IMM
) {
3493 src1_0_w
.ud
&= 0xffff;
3496 src1_0_w
.type
= BRW_REGISTER_TYPE_UW
;
3497 if (src1_0_w
.stride
!= 0) {
3498 assert(src1_0_w
.stride
== 1);
3499 src1_0_w
.stride
= 2;
3502 src1_1_w
.type
= BRW_REGISTER_TYPE_UW
;
3503 if (src1_1_w
.stride
!= 0) {
3504 assert(src1_1_w
.stride
== 1);
3505 src1_1_w
.stride
= 2;
3507 src1_1_w
.subreg_offset
+= type_sz(BRW_REGISTER_TYPE_UW
);
3509 ibld
.MUL(low
, inst
->src
[0], src1_0_w
);
3510 ibld
.MUL(high
, inst
->src
[0], src1_1_w
);
3512 fs_reg src0_0_w
= inst
->src
[0];
3513 fs_reg src0_1_w
= inst
->src
[0];
3515 src0_0_w
.type
= BRW_REGISTER_TYPE_UW
;
3516 if (src0_0_w
.stride
!= 0) {
3517 assert(src0_0_w
.stride
== 1);
3518 src0_0_w
.stride
= 2;
3521 src0_1_w
.type
= BRW_REGISTER_TYPE_UW
;
3522 if (src0_1_w
.stride
!= 0) {
3523 assert(src0_1_w
.stride
== 1);
3524 src0_1_w
.stride
= 2;
3526 src0_1_w
.subreg_offset
+= type_sz(BRW_REGISTER_TYPE_UW
);
3528 ibld
.MUL(low
, src0_0_w
, inst
->src
[1]);
3529 ibld
.MUL(high
, src0_1_w
, inst
->src
[1]);
3532 fs_reg dst
= inst
->dst
;
3533 dst
.type
= BRW_REGISTER_TYPE_UW
;
3534 dst
.subreg_offset
= 2;
3537 high
.type
= BRW_REGISTER_TYPE_UW
;
3540 low
.type
= BRW_REGISTER_TYPE_UW
;
3541 low
.subreg_offset
= 2;
3544 ibld
.ADD(dst
, low
, high
);
3546 if (inst
->conditional_mod
|| orig_dst
.file
== MRF
) {
3547 set_condmod(inst
->conditional_mod
,
3548 ibld
.MOV(orig_dst
, inst
->dst
));
3552 } else if (inst
->opcode
== SHADER_OPCODE_MULH
) {
3553 /* Should have been lowered to 8-wide. */
3554 assert(inst
->exec_size
<= 8);
3555 const fs_reg acc
= retype(brw_acc_reg(inst
->exec_size
),
3557 fs_inst
*mul
= ibld
.MUL(acc
, inst
->src
[0], inst
->src
[1]);
3558 fs_inst
*mach
= ibld
.MACH(inst
->dst
, inst
->src
[0], inst
->src
[1]);
3560 if (devinfo
->gen
>= 8) {
3561 /* Until Gen8, integer multiplies read 32-bits from one source,
3562 * and 16-bits from the other, and relying on the MACH instruction
3563 * to generate the high bits of the result.
3565 * On Gen8, the multiply instruction does a full 32x32-bit
3566 * multiply, but in order to do a 64-bit multiply we can simulate
3567 * the previous behavior and then use a MACH instruction.
3569 * FINISHME: Don't use source modifiers on src1.
3571 assert(mul
->src
[1].type
== BRW_REGISTER_TYPE_D
||
3572 mul
->src
[1].type
== BRW_REGISTER_TYPE_UD
);
3573 mul
->src
[1].type
= BRW_REGISTER_TYPE_UW
;
3574 mul
->src
[1].stride
*= 2;
3576 } else if (devinfo
->gen
== 7 && !devinfo
->is_haswell
&&
3577 inst
->force_sechalf
) {
3578 /* Among other things the quarter control bits influence which
3579 * accumulator register is used by the hardware for instructions
3580 * that access the accumulator implicitly (e.g. MACH). A
3581 * second-half instruction would normally map to acc1, which
3582 * doesn't exist on Gen7 and up (the hardware does emulate it for
3583 * floating-point instructions *only* by taking advantage of the
3584 * extra precision of acc0 not normally used for floating point
3587 * HSW and up are careful enough not to try to access an
3588 * accumulator register that doesn't exist, but on earlier Gen7
3589 * hardware we need to make sure that the quarter control bits are
3590 * zero to avoid non-deterministic behaviour and emit an extra MOV
3591 * to get the result masked correctly according to the current
3594 mach
->force_sechalf
= false;
3595 mach
->force_writemask_all
= true;
3596 mach
->dst
= ibld
.vgrf(inst
->dst
.type
);
3597 ibld
.MOV(inst
->dst
, mach
->dst
);
3603 inst
->remove(block
);
3608 invalidate_live_intervals();
3614 fs_visitor::lower_minmax()
3616 assert(devinfo
->gen
< 6);
3618 bool progress
= false;
3620 foreach_block_and_inst_safe(block
, fs_inst
, inst
, cfg
) {
3621 const fs_builder
ibld(this, block
, inst
);
3623 if (inst
->opcode
== BRW_OPCODE_SEL
&&
3624 inst
->predicate
== BRW_PREDICATE_NONE
) {
3625 /* FIXME: Using CMP doesn't preserve the NaN propagation semantics of
3626 * the original SEL.L/GE instruction
3628 ibld
.CMP(ibld
.null_reg_d(), inst
->src
[0], inst
->src
[1],
3629 inst
->conditional_mod
);
3630 inst
->predicate
= BRW_PREDICATE_NORMAL
;
3631 inst
->conditional_mod
= BRW_CONDITIONAL_NONE
;
3638 invalidate_live_intervals();
3644 setup_color_payload(const fs_builder
&bld
, const brw_wm_prog_key
*key
,
3645 fs_reg
*dst
, fs_reg color
, unsigned components
)
3647 if (key
->clamp_fragment_color
) {
3648 fs_reg tmp
= bld
.vgrf(BRW_REGISTER_TYPE_F
, 4);
3649 assert(color
.type
== BRW_REGISTER_TYPE_F
);
3651 for (unsigned i
= 0; i
< components
; i
++)
3653 bld
.MOV(offset(tmp
, bld
, i
), offset(color
, bld
, i
)));
3658 for (unsigned i
= 0; i
< components
; i
++)
3659 dst
[i
] = offset(color
, bld
, i
);
3663 lower_fb_write_logical_send(const fs_builder
&bld
, fs_inst
*inst
,
3664 const brw_wm_prog_data
*prog_data
,
3665 const brw_wm_prog_key
*key
,
3666 const fs_visitor::thread_payload
&payload
)
3668 assert(inst
->src
[FB_WRITE_LOGICAL_SRC_COMPONENTS
].file
== IMM
);
3669 const brw_device_info
*devinfo
= bld
.shader
->devinfo
;
3670 const fs_reg
&color0
= inst
->src
[FB_WRITE_LOGICAL_SRC_COLOR0
];
3671 const fs_reg
&color1
= inst
->src
[FB_WRITE_LOGICAL_SRC_COLOR1
];
3672 const fs_reg
&src0_alpha
= inst
->src
[FB_WRITE_LOGICAL_SRC_SRC0_ALPHA
];
3673 const fs_reg
&src_depth
= inst
->src
[FB_WRITE_LOGICAL_SRC_SRC_DEPTH
];
3674 const fs_reg
&dst_depth
= inst
->src
[FB_WRITE_LOGICAL_SRC_DST_DEPTH
];
3675 const fs_reg
&src_stencil
= inst
->src
[FB_WRITE_LOGICAL_SRC_SRC_STENCIL
];
3676 fs_reg sample_mask
= inst
->src
[FB_WRITE_LOGICAL_SRC_OMASK
];
3677 const unsigned components
=
3678 inst
->src
[FB_WRITE_LOGICAL_SRC_COMPONENTS
].ud
;
3680 /* We can potentially have a message length of up to 15, so we have to set
3681 * base_mrf to either 0 or 1 in order to fit in m0..m15.
3684 int header_size
= 2, payload_header_size
;
3685 unsigned length
= 0;
3687 /* From the Sandy Bridge PRM, volume 4, page 198:
3689 * "Dispatched Pixel Enables. One bit per pixel indicating
3690 * which pixels were originally enabled when the thread was
3691 * dispatched. This field is only required for the end-of-
3692 * thread message and on all dual-source messages."
3694 if (devinfo
->gen
>= 6 &&
3695 (devinfo
->is_haswell
|| devinfo
->gen
>= 8 || !prog_data
->uses_kill
) &&
3696 color1
.file
== BAD_FILE
&&
3697 key
->nr_color_regions
== 1) {
3701 if (header_size
!= 0) {
3702 assert(header_size
== 2);
3703 /* Allocate 2 registers for a header */
3707 if (payload
.aa_dest_stencil_reg
) {
3708 sources
[length
] = fs_reg(VGRF
, bld
.shader
->alloc
.allocate(1));
3709 bld
.group(8, 0).exec_all().annotate("FB write stencil/AA alpha")
3710 .MOV(sources
[length
],
3711 fs_reg(brw_vec8_grf(payload
.aa_dest_stencil_reg
, 0)));
3715 if (prog_data
->uses_omask
) {
3716 sources
[length
] = fs_reg(VGRF
, bld
.shader
->alloc
.allocate(1),
3717 BRW_REGISTER_TYPE_UD
);
3719 /* Hand over gl_SampleMask. Only the lower 16 bits of each channel are
3720 * relevant. Since it's unsigned single words one vgrf is always
3721 * 16-wide, but only the lower or higher 8 channels will be used by the
3722 * hardware when doing a SIMD8 write depending on whether we have
3723 * selected the subspans for the first or second half respectively.
3725 assert(sample_mask
.file
!= BAD_FILE
&& type_sz(sample_mask
.type
) == 4);
3726 sample_mask
.type
= BRW_REGISTER_TYPE_UW
;
3727 sample_mask
.stride
*= 2;
3729 bld
.exec_all().annotate("FB write oMask")
3730 .MOV(half(retype(sources
[length
], BRW_REGISTER_TYPE_UW
),
3731 inst
->force_sechalf
),
3736 payload_header_size
= length
;
3738 if (src0_alpha
.file
!= BAD_FILE
) {
3739 /* FIXME: This is being passed at the wrong location in the payload and
3740 * doesn't work when gl_SampleMask and MRTs are used simultaneously.
3741 * It's supposed to be immediately before oMask but there seems to be no
3742 * reasonable way to pass them in the correct order because LOAD_PAYLOAD
3743 * requires header sources to form a contiguous segment at the beginning
3744 * of the message and src0_alpha has per-channel semantics.
3746 setup_color_payload(bld
, key
, &sources
[length
], src0_alpha
, 1);
3750 setup_color_payload(bld
, key
, &sources
[length
], color0
, components
);
3753 if (color1
.file
!= BAD_FILE
) {
3754 setup_color_payload(bld
, key
, &sources
[length
], color1
, components
);
3758 if (src_depth
.file
!= BAD_FILE
) {
3759 sources
[length
] = src_depth
;
3763 if (dst_depth
.file
!= BAD_FILE
) {
3764 sources
[length
] = dst_depth
;
3768 if (src_stencil
.file
!= BAD_FILE
) {
3769 assert(devinfo
->gen
>= 9);
3770 assert(bld
.dispatch_width() != 16);
3772 /* XXX: src_stencil is only available on gen9+. dst_depth is never
3773 * available on gen9+. As such it's impossible to have both enabled at the
3774 * same time and therefore length cannot overrun the array.
3776 assert(length
< 15);
3778 sources
[length
] = bld
.vgrf(BRW_REGISTER_TYPE_UD
);
3779 bld
.exec_all().annotate("FB write OS")
3780 .emit(FS_OPCODE_PACK_STENCIL_REF
, sources
[length
],
3781 retype(src_stencil
, BRW_REGISTER_TYPE_UB
));
3786 if (devinfo
->gen
>= 7) {
3787 /* Send from the GRF */
3788 fs_reg payload
= fs_reg(VGRF
, -1, BRW_REGISTER_TYPE_F
);
3789 load
= bld
.LOAD_PAYLOAD(payload
, sources
, length
, payload_header_size
);
3790 payload
.nr
= bld
.shader
->alloc
.allocate(load
->regs_written
);
3791 load
->dst
= payload
;
3793 inst
->src
[0] = payload
;
3794 inst
->resize_sources(1);
3795 inst
->base_mrf
= -1;
3797 /* Send from the MRF */
3798 load
= bld
.LOAD_PAYLOAD(fs_reg(MRF
, 1, BRW_REGISTER_TYPE_F
),
3799 sources
, length
, payload_header_size
);
3801 /* On pre-SNB, we have to interlace the color values. LOAD_PAYLOAD
3802 * will do this for us if we just give it a COMPR4 destination.
3804 if (devinfo
->gen
< 6 && bld
.dispatch_width() == 16)
3805 load
->dst
.nr
|= BRW_MRF_COMPR4
;
3807 inst
->resize_sources(0);
3811 inst
->opcode
= FS_OPCODE_FB_WRITE
;
3812 inst
->mlen
= load
->regs_written
;
3813 inst
->header_size
= header_size
;
3817 lower_sampler_logical_send_gen4(const fs_builder
&bld
, fs_inst
*inst
, opcode op
,
3818 const fs_reg
&coordinate
,
3819 const fs_reg
&shadow_c
,
3820 const fs_reg
&lod
, const fs_reg
&lod2
,
3821 const fs_reg
&surface
,
3822 const fs_reg
&sampler
,
3823 unsigned coord_components
,
3824 unsigned grad_components
)
3826 const bool has_lod
= (op
== SHADER_OPCODE_TXL
|| op
== FS_OPCODE_TXB
||
3827 op
== SHADER_OPCODE_TXF
|| op
== SHADER_OPCODE_TXS
);
3828 fs_reg
msg_begin(MRF
, 1, BRW_REGISTER_TYPE_F
);
3829 fs_reg msg_end
= msg_begin
;
3832 msg_end
= offset(msg_end
, bld
.group(8, 0), 1);
3834 for (unsigned i
= 0; i
< coord_components
; i
++)
3835 bld
.MOV(retype(offset(msg_end
, bld
, i
), coordinate
.type
),
3836 offset(coordinate
, bld
, i
));
3838 msg_end
= offset(msg_end
, bld
, coord_components
);
3840 /* Messages other than SAMPLE and RESINFO in SIMD16 and TXD in SIMD8
3841 * require all three components to be present and zero if they are unused.
3843 if (coord_components
> 0 &&
3844 (has_lod
|| shadow_c
.file
!= BAD_FILE
||
3845 (op
== SHADER_OPCODE_TEX
&& bld
.dispatch_width() == 8))) {
3846 for (unsigned i
= coord_components
; i
< 3; i
++)
3847 bld
.MOV(offset(msg_end
, bld
, i
), brw_imm_f(0.0f
));
3849 msg_end
= offset(msg_end
, bld
, 3 - coord_components
);
3852 if (op
== SHADER_OPCODE_TXD
) {
3853 /* TXD unsupported in SIMD16 mode. */
3854 assert(bld
.dispatch_width() == 8);
3856 /* the slots for u and v are always present, but r is optional */
3857 if (coord_components
< 2)
3858 msg_end
= offset(msg_end
, bld
, 2 - coord_components
);
3861 * dPdx = dudx, dvdx, drdx
3862 * dPdy = dudy, dvdy, drdy
3864 * 1-arg: Does not exist.
3866 * 2-arg: dudx dvdx dudy dvdy
3867 * dPdx.x dPdx.y dPdy.x dPdy.y
3870 * 3-arg: dudx dvdx drdx dudy dvdy drdy
3871 * dPdx.x dPdx.y dPdx.z dPdy.x dPdy.y dPdy.z
3872 * m5 m6 m7 m8 m9 m10
3874 for (unsigned i
= 0; i
< grad_components
; i
++)
3875 bld
.MOV(offset(msg_end
, bld
, i
), offset(lod
, bld
, i
));
3877 msg_end
= offset(msg_end
, bld
, MAX2(grad_components
, 2));
3879 for (unsigned i
= 0; i
< grad_components
; i
++)
3880 bld
.MOV(offset(msg_end
, bld
, i
), offset(lod2
, bld
, i
));
3882 msg_end
= offset(msg_end
, bld
, MAX2(grad_components
, 2));
3886 /* Bias/LOD with shadow comparitor is unsupported in SIMD16 -- *Without*
3887 * shadow comparitor (including RESINFO) it's unsupported in SIMD8 mode.
3889 assert(shadow_c
.file
!= BAD_FILE
? bld
.dispatch_width() == 8 :
3890 bld
.dispatch_width() == 16);
3892 const brw_reg_type type
=
3893 (op
== SHADER_OPCODE_TXF
|| op
== SHADER_OPCODE_TXS
?
3894 BRW_REGISTER_TYPE_UD
: BRW_REGISTER_TYPE_F
);
3895 bld
.MOV(retype(msg_end
, type
), lod
);
3896 msg_end
= offset(msg_end
, bld
, 1);
3899 if (shadow_c
.file
!= BAD_FILE
) {
3900 if (op
== SHADER_OPCODE_TEX
&& bld
.dispatch_width() == 8) {
3901 /* There's no plain shadow compare message, so we use shadow
3902 * compare with a bias of 0.0.
3904 bld
.MOV(msg_end
, brw_imm_f(0.0f
));
3905 msg_end
= offset(msg_end
, bld
, 1);
3908 bld
.MOV(msg_end
, shadow_c
);
3909 msg_end
= offset(msg_end
, bld
, 1);
3913 inst
->src
[0] = reg_undef
;
3914 inst
->src
[1] = surface
;
3915 inst
->src
[2] = sampler
;
3916 inst
->resize_sources(3);
3917 inst
->base_mrf
= msg_begin
.nr
;
3918 inst
->mlen
= msg_end
.nr
- msg_begin
.nr
;
3919 inst
->header_size
= 1;
3923 lower_sampler_logical_send_gen5(const fs_builder
&bld
, fs_inst
*inst
, opcode op
,
3925 const fs_reg
&shadow_c
,
3926 fs_reg lod
, fs_reg lod2
,
3927 const fs_reg
&sample_index
,
3928 const fs_reg
&surface
,
3929 const fs_reg
&sampler
,
3930 const fs_reg
&offset_value
,
3931 unsigned coord_components
,
3932 unsigned grad_components
)
3934 fs_reg
message(MRF
, 2, BRW_REGISTER_TYPE_F
);
3935 fs_reg msg_coords
= message
;
3936 unsigned header_size
= 0;
3938 if (offset_value
.file
!= BAD_FILE
) {
3939 /* The offsets set up by the visitor are in the m1 header, so we can't
3946 for (unsigned i
= 0; i
< coord_components
; i
++) {
3947 bld
.MOV(retype(offset(msg_coords
, bld
, i
), coordinate
.type
), coordinate
);
3948 coordinate
= offset(coordinate
, bld
, 1);
3950 fs_reg msg_end
= offset(msg_coords
, bld
, coord_components
);
3951 fs_reg msg_lod
= offset(msg_coords
, bld
, 4);
3953 if (shadow_c
.file
!= BAD_FILE
) {
3954 fs_reg msg_shadow
= msg_lod
;
3955 bld
.MOV(msg_shadow
, shadow_c
);
3956 msg_lod
= offset(msg_shadow
, bld
, 1);
3961 case SHADER_OPCODE_TXL
:
3963 bld
.MOV(msg_lod
, lod
);
3964 msg_end
= offset(msg_lod
, bld
, 1);
3966 case SHADER_OPCODE_TXD
:
3969 * dPdx = dudx, dvdx, drdx
3970 * dPdy = dudy, dvdy, drdy
3972 * Load up these values:
3973 * - dudx dudy dvdx dvdy drdx drdy
3974 * - dPdx.x dPdy.x dPdx.y dPdy.y dPdx.z dPdy.z
3977 for (unsigned i
= 0; i
< grad_components
; i
++) {
3978 bld
.MOV(msg_end
, lod
);
3979 lod
= offset(lod
, bld
, 1);
3980 msg_end
= offset(msg_end
, bld
, 1);
3982 bld
.MOV(msg_end
, lod2
);
3983 lod2
= offset(lod2
, bld
, 1);
3984 msg_end
= offset(msg_end
, bld
, 1);
3987 case SHADER_OPCODE_TXS
:
3988 msg_lod
= retype(msg_end
, BRW_REGISTER_TYPE_UD
);
3989 bld
.MOV(msg_lod
, lod
);
3990 msg_end
= offset(msg_lod
, bld
, 1);
3992 case SHADER_OPCODE_TXF
:
3993 msg_lod
= offset(msg_coords
, bld
, 3);
3994 bld
.MOV(retype(msg_lod
, BRW_REGISTER_TYPE_UD
), lod
);
3995 msg_end
= offset(msg_lod
, bld
, 1);
3997 case SHADER_OPCODE_TXF_CMS
:
3998 msg_lod
= offset(msg_coords
, bld
, 3);
4000 bld
.MOV(retype(msg_lod
, BRW_REGISTER_TYPE_UD
), brw_imm_ud(0u));
4002 bld
.MOV(retype(offset(msg_lod
, bld
, 1), BRW_REGISTER_TYPE_UD
), sample_index
);
4003 msg_end
= offset(msg_lod
, bld
, 2);
4010 inst
->src
[0] = reg_undef
;
4011 inst
->src
[1] = surface
;
4012 inst
->src
[2] = sampler
;
4013 inst
->resize_sources(3);
4014 inst
->base_mrf
= message
.nr
;
4015 inst
->mlen
= msg_end
.nr
- message
.nr
;
4016 inst
->header_size
= header_size
;
4018 /* Message length > MAX_SAMPLER_MESSAGE_SIZE disallowed by hardware. */
4019 assert(inst
->mlen
<= MAX_SAMPLER_MESSAGE_SIZE
);
4023 is_high_sampler(const struct brw_device_info
*devinfo
, const fs_reg
&sampler
)
4025 if (devinfo
->gen
< 8 && !devinfo
->is_haswell
)
4028 return sampler
.file
!= IMM
|| sampler
.ud
>= 16;
4032 lower_sampler_logical_send_gen7(const fs_builder
&bld
, fs_inst
*inst
, opcode op
,
4034 const fs_reg
&shadow_c
,
4035 fs_reg lod
, fs_reg lod2
,
4036 const fs_reg
&sample_index
,
4038 const fs_reg
&surface
,
4039 const fs_reg
&sampler
,
4040 fs_reg offset_value
,
4041 unsigned coord_components
,
4042 unsigned grad_components
)
4044 const brw_device_info
*devinfo
= bld
.shader
->devinfo
;
4045 int reg_width
= bld
.dispatch_width() / 8;
4046 unsigned header_size
= 0, length
= 0;
4047 fs_reg sources
[MAX_SAMPLER_MESSAGE_SIZE
];
4048 for (unsigned i
= 0; i
< ARRAY_SIZE(sources
); i
++)
4049 sources
[i
] = bld
.vgrf(BRW_REGISTER_TYPE_F
);
4051 if (op
== SHADER_OPCODE_TG4
|| op
== SHADER_OPCODE_TG4_OFFSET
||
4052 offset_value
.file
!= BAD_FILE
||
4053 is_high_sampler(devinfo
, sampler
)) {
4054 /* For general texture offsets (no txf workaround), we need a header to
4055 * put them in. Note that we're only reserving space for it in the
4056 * message payload as it will be initialized implicitly by the
4059 * TG4 needs to place its channel select in the header, for interaction
4060 * with ARB_texture_swizzle. The sampler index is only 4-bits, so for
4061 * larger sampler numbers we need to offset the Sampler State Pointer in
4065 sources
[0] = fs_reg();
4068 /* If we're requesting fewer than four channels worth of response,
4069 * and we have an explicit header, we need to set up the sampler
4070 * writemask. It's reversed from normal: 1 means "don't write".
4072 if (inst
->regs_written
!= 4 * reg_width
) {
4073 assert((inst
->regs_written
% reg_width
) == 0);
4074 unsigned mask
= ~((1 << (inst
->regs_written
/ reg_width
)) - 1) & 0xf;
4075 inst
->offset
|= mask
<< 12;
4079 if (shadow_c
.file
!= BAD_FILE
) {
4080 bld
.MOV(sources
[length
], shadow_c
);
4084 bool coordinate_done
= false;
4086 /* The sampler can only meaningfully compute LOD for fragment shader
4087 * messages. For all other stages, we change the opcode to TXL and
4088 * hardcode the LOD to 0.
4090 if (bld
.shader
->stage
!= MESA_SHADER_FRAGMENT
&&
4091 op
== SHADER_OPCODE_TEX
) {
4092 op
= SHADER_OPCODE_TXL
;
4093 lod
= brw_imm_f(0.0f
);
4096 /* Set up the LOD info */
4099 case SHADER_OPCODE_TXL
:
4100 bld
.MOV(sources
[length
], lod
);
4103 case SHADER_OPCODE_TXD
:
4104 /* TXD should have been lowered in SIMD16 mode. */
4105 assert(bld
.dispatch_width() == 8);
4107 /* Load dPdx and the coordinate together:
4108 * [hdr], [ref], x, dPdx.x, dPdy.x, y, dPdx.y, dPdy.y, z, dPdx.z, dPdy.z
4110 for (unsigned i
= 0; i
< coord_components
; i
++) {
4111 bld
.MOV(sources
[length
], coordinate
);
4112 coordinate
= offset(coordinate
, bld
, 1);
4115 /* For cube map array, the coordinate is (u,v,r,ai) but there are
4116 * only derivatives for (u, v, r).
4118 if (i
< grad_components
) {
4119 bld
.MOV(sources
[length
], lod
);
4120 lod
= offset(lod
, bld
, 1);
4123 bld
.MOV(sources
[length
], lod2
);
4124 lod2
= offset(lod2
, bld
, 1);
4129 coordinate_done
= true;
4131 case SHADER_OPCODE_TXS
:
4132 bld
.MOV(retype(sources
[length
], BRW_REGISTER_TYPE_UD
), lod
);
4135 case SHADER_OPCODE_TXF
:
4136 /* Unfortunately, the parameters for LD are intermixed: u, lod, v, r.
4137 * On Gen9 they are u, v, lod, r
4139 bld
.MOV(retype(sources
[length
], BRW_REGISTER_TYPE_D
), coordinate
);
4140 coordinate
= offset(coordinate
, bld
, 1);
4143 if (devinfo
->gen
>= 9) {
4144 if (coord_components
>= 2) {
4145 bld
.MOV(retype(sources
[length
], BRW_REGISTER_TYPE_D
), coordinate
);
4146 coordinate
= offset(coordinate
, bld
, 1);
4151 bld
.MOV(retype(sources
[length
], BRW_REGISTER_TYPE_D
), lod
);
4154 for (unsigned i
= devinfo
->gen
>= 9 ? 2 : 1; i
< coord_components
; i
++) {
4155 bld
.MOV(retype(sources
[length
], BRW_REGISTER_TYPE_D
), coordinate
);
4156 coordinate
= offset(coordinate
, bld
, 1);
4160 coordinate_done
= true;
4162 case SHADER_OPCODE_TXF_CMS
:
4163 case SHADER_OPCODE_TXF_CMS_W
:
4164 case SHADER_OPCODE_TXF_UMS
:
4165 case SHADER_OPCODE_TXF_MCS
:
4166 if (op
== SHADER_OPCODE_TXF_UMS
||
4167 op
== SHADER_OPCODE_TXF_CMS
||
4168 op
== SHADER_OPCODE_TXF_CMS_W
) {
4169 bld
.MOV(retype(sources
[length
], BRW_REGISTER_TYPE_UD
), sample_index
);
4173 if (op
== SHADER_OPCODE_TXF_CMS
|| op
== SHADER_OPCODE_TXF_CMS_W
) {
4174 /* Data from the multisample control surface. */
4175 bld
.MOV(retype(sources
[length
], BRW_REGISTER_TYPE_UD
), mcs
);
4178 /* On Gen9+ we'll use ld2dms_w instead which has two registers for
4181 if (op
== SHADER_OPCODE_TXF_CMS_W
) {
4182 bld
.MOV(retype(sources
[length
], BRW_REGISTER_TYPE_UD
),
4185 offset(mcs
, bld
, 1));
4190 /* There is no offsetting for this message; just copy in the integer
4191 * texture coordinates.
4193 for (unsigned i
= 0; i
< coord_components
; i
++) {
4194 bld
.MOV(retype(sources
[length
], BRW_REGISTER_TYPE_D
), coordinate
);
4195 coordinate
= offset(coordinate
, bld
, 1);
4199 coordinate_done
= true;
4201 case SHADER_OPCODE_TG4_OFFSET
:
4202 /* gather4_po_c should have been lowered in SIMD16 mode. */
4203 assert(bld
.dispatch_width() == 8 || shadow_c
.file
== BAD_FILE
);
4205 /* More crazy intermixing */
4206 for (unsigned i
= 0; i
< 2; i
++) { /* u, v */
4207 bld
.MOV(sources
[length
], coordinate
);
4208 coordinate
= offset(coordinate
, bld
, 1);
4212 for (unsigned i
= 0; i
< 2; i
++) { /* offu, offv */
4213 bld
.MOV(retype(sources
[length
], BRW_REGISTER_TYPE_D
), offset_value
);
4214 offset_value
= offset(offset_value
, bld
, 1);
4218 if (coord_components
== 3) { /* r if present */
4219 bld
.MOV(sources
[length
], coordinate
);
4220 coordinate
= offset(coordinate
, bld
, 1);
4224 coordinate_done
= true;
4230 /* Set up the coordinate (except for cases where it was done above) */
4231 if (!coordinate_done
) {
4232 for (unsigned i
= 0; i
< coord_components
; i
++) {
4233 bld
.MOV(sources
[length
], coordinate
);
4234 coordinate
= offset(coordinate
, bld
, 1);
4241 mlen
= length
* reg_width
- header_size
;
4243 mlen
= length
* reg_width
;
4245 const fs_reg src_payload
= fs_reg(VGRF
, bld
.shader
->alloc
.allocate(mlen
),
4246 BRW_REGISTER_TYPE_F
);
4247 bld
.LOAD_PAYLOAD(src_payload
, sources
, length
, header_size
);
4249 /* Generate the SEND. */
4251 inst
->src
[0] = src_payload
;
4252 inst
->src
[1] = surface
;
4253 inst
->src
[2] = sampler
;
4254 inst
->resize_sources(3);
4255 inst
->base_mrf
= -1;
4257 inst
->header_size
= header_size
;
4259 /* Message length > MAX_SAMPLER_MESSAGE_SIZE disallowed by hardware. */
4260 assert(inst
->mlen
<= MAX_SAMPLER_MESSAGE_SIZE
);
4264 lower_sampler_logical_send(const fs_builder
&bld
, fs_inst
*inst
, opcode op
)
4266 const brw_device_info
*devinfo
= bld
.shader
->devinfo
;
4267 const fs_reg
&coordinate
= inst
->src
[TEX_LOGICAL_SRC_COORDINATE
];
4268 const fs_reg
&shadow_c
= inst
->src
[TEX_LOGICAL_SRC_SHADOW_C
];
4269 const fs_reg
&lod
= inst
->src
[TEX_LOGICAL_SRC_LOD
];
4270 const fs_reg
&lod2
= inst
->src
[TEX_LOGICAL_SRC_LOD2
];
4271 const fs_reg
&sample_index
= inst
->src
[TEX_LOGICAL_SRC_SAMPLE_INDEX
];
4272 const fs_reg
&mcs
= inst
->src
[TEX_LOGICAL_SRC_MCS
];
4273 const fs_reg
&surface
= inst
->src
[TEX_LOGICAL_SRC_SURFACE
];
4274 const fs_reg
&sampler
= inst
->src
[TEX_LOGICAL_SRC_SAMPLER
];
4275 const fs_reg
&offset_value
= inst
->src
[TEX_LOGICAL_SRC_OFFSET_VALUE
];
4276 assert(inst
->src
[TEX_LOGICAL_SRC_COORD_COMPONENTS
].file
== IMM
);
4277 const unsigned coord_components
= inst
->src
[TEX_LOGICAL_SRC_COORD_COMPONENTS
].ud
;
4278 assert(inst
->src
[TEX_LOGICAL_SRC_GRAD_COMPONENTS
].file
== IMM
);
4279 const unsigned grad_components
= inst
->src
[TEX_LOGICAL_SRC_GRAD_COMPONENTS
].ud
;
4281 if (devinfo
->gen
>= 7) {
4282 lower_sampler_logical_send_gen7(bld
, inst
, op
, coordinate
,
4283 shadow_c
, lod
, lod2
, sample_index
,
4284 mcs
, surface
, sampler
, offset_value
,
4285 coord_components
, grad_components
);
4286 } else if (devinfo
->gen
>= 5) {
4287 lower_sampler_logical_send_gen5(bld
, inst
, op
, coordinate
,
4288 shadow_c
, lod
, lod2
, sample_index
,
4289 surface
, sampler
, offset_value
,
4290 coord_components
, grad_components
);
4292 lower_sampler_logical_send_gen4(bld
, inst
, op
, coordinate
,
4293 shadow_c
, lod
, lod2
,
4295 coord_components
, grad_components
);
4300 * Initialize the header present in some typed and untyped surface
4304 emit_surface_header(const fs_builder
&bld
, const fs_reg
&sample_mask
)
4306 fs_builder ubld
= bld
.exec_all().group(8, 0);
4307 const fs_reg dst
= ubld
.vgrf(BRW_REGISTER_TYPE_UD
);
4308 ubld
.MOV(dst
, brw_imm_d(0));
4309 ubld
.MOV(component(dst
, 7), sample_mask
);
4314 lower_surface_logical_send(const fs_builder
&bld
, fs_inst
*inst
, opcode op
,
4315 const fs_reg
&sample_mask
)
4317 /* Get the logical send arguments. */
4318 const fs_reg
&addr
= inst
->src
[0];
4319 const fs_reg
&src
= inst
->src
[1];
4320 const fs_reg
&surface
= inst
->src
[2];
4321 const UNUSED fs_reg
&dims
= inst
->src
[3];
4322 const fs_reg
&arg
= inst
->src
[4];
4324 /* Calculate the total number of components of the payload. */
4325 const unsigned addr_sz
= inst
->components_read(0);
4326 const unsigned src_sz
= inst
->components_read(1);
4327 const unsigned header_sz
= (sample_mask
.file
== BAD_FILE
? 0 : 1);
4328 const unsigned sz
= header_sz
+ addr_sz
+ src_sz
;
4330 /* Allocate space for the payload. */
4331 fs_reg
*const components
= new fs_reg
[sz
];
4332 const fs_reg payload
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, sz
);
4335 /* Construct the payload. */
4337 components
[n
++] = emit_surface_header(bld
, sample_mask
);
4339 for (unsigned i
= 0; i
< addr_sz
; i
++)
4340 components
[n
++] = offset(addr
, bld
, i
);
4342 for (unsigned i
= 0; i
< src_sz
; i
++)
4343 components
[n
++] = offset(src
, bld
, i
);
4345 bld
.LOAD_PAYLOAD(payload
, components
, sz
, header_sz
);
4347 /* Update the original instruction. */
4349 inst
->mlen
= header_sz
+ (addr_sz
+ src_sz
) * inst
->exec_size
/ 8;
4350 inst
->header_size
= header_sz
;
4352 inst
->src
[0] = payload
;
4353 inst
->src
[1] = surface
;
4355 inst
->resize_sources(3);
4357 delete[] components
;
4361 fs_visitor::lower_logical_sends()
4363 bool progress
= false;
4365 foreach_block_and_inst_safe(block
, fs_inst
, inst
, cfg
) {
4366 const fs_builder
ibld(this, block
, inst
);
4368 switch (inst
->opcode
) {
4369 case FS_OPCODE_FB_WRITE_LOGICAL
:
4370 assert(stage
== MESA_SHADER_FRAGMENT
);
4371 lower_fb_write_logical_send(ibld
, inst
,
4372 (const brw_wm_prog_data
*)prog_data
,
4373 (const brw_wm_prog_key
*)key
,
4377 case SHADER_OPCODE_TEX_LOGICAL
:
4378 lower_sampler_logical_send(ibld
, inst
, SHADER_OPCODE_TEX
);
4381 case SHADER_OPCODE_TXD_LOGICAL
:
4382 lower_sampler_logical_send(ibld
, inst
, SHADER_OPCODE_TXD
);
4385 case SHADER_OPCODE_TXF_LOGICAL
:
4386 lower_sampler_logical_send(ibld
, inst
, SHADER_OPCODE_TXF
);
4389 case SHADER_OPCODE_TXL_LOGICAL
:
4390 lower_sampler_logical_send(ibld
, inst
, SHADER_OPCODE_TXL
);
4393 case SHADER_OPCODE_TXS_LOGICAL
:
4394 lower_sampler_logical_send(ibld
, inst
, SHADER_OPCODE_TXS
);
4397 case FS_OPCODE_TXB_LOGICAL
:
4398 lower_sampler_logical_send(ibld
, inst
, FS_OPCODE_TXB
);
4401 case SHADER_OPCODE_TXF_CMS_LOGICAL
:
4402 lower_sampler_logical_send(ibld
, inst
, SHADER_OPCODE_TXF_CMS
);
4405 case SHADER_OPCODE_TXF_CMS_W_LOGICAL
:
4406 lower_sampler_logical_send(ibld
, inst
, SHADER_OPCODE_TXF_CMS_W
);
4409 case SHADER_OPCODE_TXF_UMS_LOGICAL
:
4410 lower_sampler_logical_send(ibld
, inst
, SHADER_OPCODE_TXF_UMS
);
4413 case SHADER_OPCODE_TXF_MCS_LOGICAL
:
4414 lower_sampler_logical_send(ibld
, inst
, SHADER_OPCODE_TXF_MCS
);
4417 case SHADER_OPCODE_LOD_LOGICAL
:
4418 lower_sampler_logical_send(ibld
, inst
, SHADER_OPCODE_LOD
);
4421 case SHADER_OPCODE_TG4_LOGICAL
:
4422 lower_sampler_logical_send(ibld
, inst
, SHADER_OPCODE_TG4
);
4425 case SHADER_OPCODE_TG4_OFFSET_LOGICAL
:
4426 lower_sampler_logical_send(ibld
, inst
, SHADER_OPCODE_TG4_OFFSET
);
4429 case SHADER_OPCODE_UNTYPED_SURFACE_READ_LOGICAL
:
4430 lower_surface_logical_send(ibld
, inst
,
4431 SHADER_OPCODE_UNTYPED_SURFACE_READ
,
4435 case SHADER_OPCODE_UNTYPED_SURFACE_WRITE_LOGICAL
:
4436 lower_surface_logical_send(ibld
, inst
,
4437 SHADER_OPCODE_UNTYPED_SURFACE_WRITE
,
4438 ibld
.sample_mask_reg());
4441 case SHADER_OPCODE_UNTYPED_ATOMIC_LOGICAL
:
4442 lower_surface_logical_send(ibld
, inst
,
4443 SHADER_OPCODE_UNTYPED_ATOMIC
,
4444 ibld
.sample_mask_reg());
4447 case SHADER_OPCODE_TYPED_SURFACE_READ_LOGICAL
:
4448 lower_surface_logical_send(ibld
, inst
,
4449 SHADER_OPCODE_TYPED_SURFACE_READ
,
4453 case SHADER_OPCODE_TYPED_SURFACE_WRITE_LOGICAL
:
4454 lower_surface_logical_send(ibld
, inst
,
4455 SHADER_OPCODE_TYPED_SURFACE_WRITE
,
4456 ibld
.sample_mask_reg());
4459 case SHADER_OPCODE_TYPED_ATOMIC_LOGICAL
:
4460 lower_surface_logical_send(ibld
, inst
,
4461 SHADER_OPCODE_TYPED_ATOMIC
,
4462 ibld
.sample_mask_reg());
4473 invalidate_live_intervals();
4479 * Get the closest native SIMD width supported by the hardware for instruction
4480 * \p inst. The instruction will be left untouched by
4481 * fs_visitor::lower_simd_width() if the returned value is equal to the
4482 * original execution size.
4485 get_lowered_simd_width(const struct brw_device_info
*devinfo
,
4486 const fs_inst
*inst
)
4488 switch (inst
->opcode
) {
4489 case BRW_OPCODE_MOV
:
4490 case BRW_OPCODE_SEL
:
4491 case BRW_OPCODE_NOT
:
4492 case BRW_OPCODE_AND
:
4494 case BRW_OPCODE_XOR
:
4495 case BRW_OPCODE_SHR
:
4496 case BRW_OPCODE_SHL
:
4497 case BRW_OPCODE_ASR
:
4498 case BRW_OPCODE_CMP
:
4499 case BRW_OPCODE_CMPN
:
4500 case BRW_OPCODE_CSEL
:
4501 case BRW_OPCODE_F32TO16
:
4502 case BRW_OPCODE_F16TO32
:
4503 case BRW_OPCODE_BFREV
:
4504 case BRW_OPCODE_BFE
:
4505 case BRW_OPCODE_BFI1
:
4506 case BRW_OPCODE_BFI2
:
4507 case BRW_OPCODE_ADD
:
4508 case BRW_OPCODE_MUL
:
4509 case BRW_OPCODE_AVG
:
4510 case BRW_OPCODE_FRC
:
4511 case BRW_OPCODE_RNDU
:
4512 case BRW_OPCODE_RNDD
:
4513 case BRW_OPCODE_RNDE
:
4514 case BRW_OPCODE_RNDZ
:
4515 case BRW_OPCODE_LZD
:
4516 case BRW_OPCODE_FBH
:
4517 case BRW_OPCODE_FBL
:
4518 case BRW_OPCODE_CBIT
:
4519 case BRW_OPCODE_SAD2
:
4520 case BRW_OPCODE_MAD
:
4521 case BRW_OPCODE_LRP
:
4522 case SHADER_OPCODE_RCP
:
4523 case SHADER_OPCODE_RSQ
:
4524 case SHADER_OPCODE_SQRT
:
4525 case SHADER_OPCODE_EXP2
:
4526 case SHADER_OPCODE_LOG2
:
4527 case SHADER_OPCODE_POW
:
4528 case SHADER_OPCODE_INT_QUOTIENT
:
4529 case SHADER_OPCODE_INT_REMAINDER
:
4530 case SHADER_OPCODE_SIN
:
4531 case SHADER_OPCODE_COS
:
4532 case FS_OPCODE_PACK
: {
4533 /* According to the PRMs:
4534 * "A. In Direct Addressing mode, a source cannot span more than 2
4535 * adjacent GRF registers.
4536 * B. A destination cannot span more than 2 adjacent GRF registers."
4538 * Look for the source or destination with the largest register region
4539 * which is the one that is going to limit the overal execution size of
4540 * the instruction due to this rule.
4542 unsigned reg_count
= inst
->regs_written
;
4544 for (unsigned i
= 0; i
< inst
->sources
; i
++)
4545 reg_count
= MAX2(reg_count
, (unsigned)inst
->regs_read(i
));
4547 /* Calculate the maximum execution size of the instruction based on the
4548 * factor by which it goes over the hardware limit of 2 GRFs.
4550 return inst
->exec_size
/ DIV_ROUND_UP(reg_count
, 2);
4552 case SHADER_OPCODE_MULH
:
4553 /* MULH is lowered to the MUL/MACH sequence using the accumulator, which
4554 * is 8-wide on Gen7+.
4556 return (devinfo
->gen
>= 7 ? 8 : inst
->exec_size
);
4558 case FS_OPCODE_FB_WRITE_LOGICAL
:
4559 /* Gen6 doesn't support SIMD16 depth writes but we cannot handle them
4562 assert(devinfo
->gen
!= 6 ||
4563 inst
->src
[FB_WRITE_LOGICAL_SRC_SRC_DEPTH
].file
== BAD_FILE
||
4564 inst
->exec_size
== 8);
4565 /* Dual-source FB writes are unsupported in SIMD16 mode. */
4566 return (inst
->src
[FB_WRITE_LOGICAL_SRC_COLOR1
].file
!= BAD_FILE
?
4567 8 : inst
->exec_size
);
4569 case SHADER_OPCODE_TXD_LOGICAL
:
4570 /* TXD is unsupported in SIMD16 mode. */
4573 case SHADER_OPCODE_TG4_OFFSET_LOGICAL
: {
4574 /* gather4_po_c is unsupported in SIMD16 mode. */
4575 const fs_reg
&shadow_c
= inst
->src
[TEX_LOGICAL_SRC_SHADOW_C
];
4576 return (shadow_c
.file
!= BAD_FILE
? 8 : inst
->exec_size
);
4578 case SHADER_OPCODE_TXL_LOGICAL
:
4579 case FS_OPCODE_TXB_LOGICAL
: {
4580 /* Gen4 doesn't have SIMD8 non-shadow-compare bias/LOD instructions, and
4581 * Gen4-6 can't support TXL and TXB with shadow comparison in SIMD16
4582 * mode because the message exceeds the maximum length of 11.
4584 const fs_reg
&shadow_c
= inst
->src
[TEX_LOGICAL_SRC_SHADOW_C
];
4585 if (devinfo
->gen
== 4 && shadow_c
.file
== BAD_FILE
)
4587 else if (devinfo
->gen
< 7 && shadow_c
.file
!= BAD_FILE
)
4590 return inst
->exec_size
;
4592 case SHADER_OPCODE_TXF_LOGICAL
:
4593 case SHADER_OPCODE_TXS_LOGICAL
:
4594 /* Gen4 doesn't have SIMD8 variants for the RESINFO and LD-with-LOD
4595 * messages. Use SIMD16 instead.
4597 if (devinfo
->gen
== 4)
4600 return inst
->exec_size
;
4602 case SHADER_OPCODE_TXF_CMS_W_LOGICAL
: {
4603 /* This opcode can take up to 6 arguments which means that in some
4604 * circumstances it can end up with a message that is too long in SIMD16
4607 const unsigned coord_components
=
4608 inst
->src
[TEX_LOGICAL_SRC_COORD_COMPONENTS
].ud
;
4609 /* First three arguments are the sample index and the two arguments for
4612 if ((coord_components
+ 3) * 2 > MAX_SAMPLER_MESSAGE_SIZE
)
4615 return inst
->exec_size
;
4618 case SHADER_OPCODE_TYPED_ATOMIC_LOGICAL
:
4619 case SHADER_OPCODE_TYPED_SURFACE_READ_LOGICAL
:
4620 case SHADER_OPCODE_TYPED_SURFACE_WRITE_LOGICAL
:
4623 case SHADER_OPCODE_MOV_INDIRECT
:
4624 /* Prior to Broadwell, we only have 8 address subregisters */
4625 return devinfo
->gen
< 8 ? 8 : MIN2(inst
->exec_size
, 16);
4628 return inst
->exec_size
;
4633 * The \p rows array of registers represents a \p num_rows by \p num_columns
4634 * matrix in row-major order, write it in column-major order into the register
4635 * passed as destination. \p stride gives the separation between matrix
4636 * elements in the input in fs_builder::dispatch_width() units.
4639 emit_transpose(const fs_builder
&bld
,
4640 const fs_reg
&dst
, const fs_reg
*rows
,
4641 unsigned num_rows
, unsigned num_columns
, unsigned stride
)
4643 fs_reg
*const components
= new fs_reg
[num_rows
* num_columns
];
4645 for (unsigned i
= 0; i
< num_columns
; ++i
) {
4646 for (unsigned j
= 0; j
< num_rows
; ++j
)
4647 components
[num_rows
* i
+ j
] = offset(rows
[j
], bld
, stride
* i
);
4650 bld
.LOAD_PAYLOAD(dst
, components
, num_rows
* num_columns
, 0);
4652 delete[] components
;
4656 fs_visitor::lower_simd_width()
4658 bool progress
= false;
4660 foreach_block_and_inst_safe(block
, fs_inst
, inst
, cfg
) {
4661 const unsigned lower_width
= get_lowered_simd_width(devinfo
, inst
);
4663 if (lower_width
!= inst
->exec_size
) {
4664 /* Builder matching the original instruction. We may also need to
4665 * emit an instruction of width larger than the original, set the
4666 * execution size of the builder to the highest of both for now so
4667 * we're sure that both cases can be handled.
4669 const fs_builder ibld
= bld
.at(block
, inst
)
4670 .exec_all(inst
->force_writemask_all
)
4671 .group(MAX2(inst
->exec_size
, lower_width
),
4672 inst
->force_sechalf
);
4674 /* Split the copies in chunks of the execution width of either the
4675 * original or the lowered instruction, whichever is lower.
4677 const unsigned copy_width
= MIN2(lower_width
, inst
->exec_size
);
4678 const unsigned n
= inst
->exec_size
/ copy_width
;
4679 const unsigned dst_size
= inst
->regs_written
* REG_SIZE
/
4680 inst
->dst
.component_size(inst
->exec_size
);
4683 assert(n
> 0 && n
<= ARRAY_SIZE(dsts
) &&
4684 !inst
->writes_accumulator
&& !inst
->mlen
);
4686 for (unsigned i
= 0; i
< n
; i
++) {
4687 /* Emit a copy of the original instruction with the lowered width.
4688 * If the EOT flag was set throw it away except for the last
4689 * instruction to avoid killing the thread prematurely.
4691 fs_inst split_inst
= *inst
;
4692 split_inst
.exec_size
= lower_width
;
4693 split_inst
.eot
= inst
->eot
&& i
== n
- 1;
4695 /* Select the correct channel enables for the i-th group, then
4696 * transform the sources and destination and emit the lowered
4699 const fs_builder lbld
= ibld
.group(lower_width
, i
);
4701 for (unsigned j
= 0; j
< inst
->sources
; j
++) {
4702 if (inst
->src
[j
].file
!= BAD_FILE
&&
4703 !is_uniform(inst
->src
[j
])) {
4704 /* Get the i-th copy_width-wide chunk of the source. */
4705 const fs_reg src
= horiz_offset(inst
->src
[j
], copy_width
* i
);
4706 const unsigned src_size
= inst
->components_read(j
);
4708 /* Use a trivial transposition to copy one every n
4709 * copy_width-wide components of the register into a
4710 * temporary passed as source to the lowered instruction.
4712 split_inst
.src
[j
] = lbld
.vgrf(inst
->src
[j
].type
, src_size
);
4713 emit_transpose(lbld
.group(copy_width
, 0),
4714 split_inst
.src
[j
], &src
, 1, src_size
, n
);
4718 if (inst
->regs_written
) {
4719 /* Allocate enough space to hold the result of the lowered
4720 * instruction and fix up the number of registers written.
4722 split_inst
.dst
= dsts
[i
] =
4723 lbld
.vgrf(inst
->dst
.type
, dst_size
);
4724 split_inst
.regs_written
=
4725 DIV_ROUND_UP(inst
->regs_written
* lower_width
,
4729 lbld
.emit(split_inst
);
4732 if (inst
->regs_written
) {
4733 /* Distance between useful channels in the temporaries, skipping
4734 * garbage if the lowered instruction is wider than the original.
4736 const unsigned m
= lower_width
/ copy_width
;
4738 /* Interleave the components of the result from the lowered
4739 * instructions. We need to set exec_all() when copying more than
4740 * one half per component, because LOAD_PAYLOAD (in terms of which
4741 * emit_transpose is implemented) can only use the same channel
4742 * enable signals for all of its non-header sources.
4744 emit_transpose(ibld
.exec_all(inst
->exec_size
> copy_width
)
4745 .group(copy_width
, 0),
4746 inst
->dst
, dsts
, n
, dst_size
, m
);
4749 inst
->remove(block
);
4755 invalidate_live_intervals();
4761 fs_visitor::dump_instructions()
4763 dump_instructions(NULL
);
4767 fs_visitor::dump_instructions(const char *name
)
4769 FILE *file
= stderr
;
4770 if (name
&& geteuid() != 0) {
4771 file
= fopen(name
, "w");
4777 calculate_register_pressure();
4778 int ip
= 0, max_pressure
= 0;
4779 foreach_block_and_inst(block
, backend_instruction
, inst
, cfg
) {
4780 max_pressure
= MAX2(max_pressure
, regs_live_at_ip
[ip
]);
4781 fprintf(file
, "{%3d} %4d: ", regs_live_at_ip
[ip
], ip
);
4782 dump_instruction(inst
, file
);
4785 fprintf(file
, "Maximum %3d registers live at once.\n", max_pressure
);
4788 foreach_in_list(backend_instruction
, inst
, &instructions
) {
4789 fprintf(file
, "%4d: ", ip
++);
4790 dump_instruction(inst
, file
);
4794 if (file
!= stderr
) {
4800 fs_visitor::dump_instruction(backend_instruction
*be_inst
)
4802 dump_instruction(be_inst
, stderr
);
4806 fs_visitor::dump_instruction(backend_instruction
*be_inst
, FILE *file
)
4808 fs_inst
*inst
= (fs_inst
*)be_inst
;
4810 if (inst
->predicate
) {
4811 fprintf(file
, "(%cf0.%d) ",
4812 inst
->predicate_inverse
? '-' : '+',
4816 fprintf(file
, "%s", brw_instruction_name(devinfo
, inst
->opcode
));
4818 fprintf(file
, ".sat");
4819 if (inst
->conditional_mod
) {
4820 fprintf(file
, "%s", conditional_modifier
[inst
->conditional_mod
]);
4821 if (!inst
->predicate
&&
4822 (devinfo
->gen
< 5 || (inst
->opcode
!= BRW_OPCODE_SEL
&&
4823 inst
->opcode
!= BRW_OPCODE_IF
&&
4824 inst
->opcode
!= BRW_OPCODE_WHILE
))) {
4825 fprintf(file
, ".f0.%d", inst
->flag_subreg
);
4828 fprintf(file
, "(%d) ", inst
->exec_size
);
4831 fprintf(file
, "(mlen: %d) ", inst
->mlen
);
4834 switch (inst
->dst
.file
) {
4836 fprintf(file
, "vgrf%d", inst
->dst
.nr
);
4837 if (alloc
.sizes
[inst
->dst
.nr
] != inst
->regs_written
||
4838 inst
->dst
.subreg_offset
)
4839 fprintf(file
, "+%d.%d",
4840 inst
->dst
.reg_offset
, inst
->dst
.subreg_offset
);
4843 fprintf(file
, "g%d", inst
->dst
.nr
);
4846 fprintf(file
, "m%d", inst
->dst
.nr
);
4849 fprintf(file
, "(null)");
4852 fprintf(file
, "***u%d***", inst
->dst
.nr
+ inst
->dst
.reg_offset
);
4855 fprintf(file
, "***attr%d***", inst
->dst
.nr
+ inst
->dst
.reg_offset
);
4858 switch (inst
->dst
.nr
) {
4860 fprintf(file
, "null");
4862 case BRW_ARF_ADDRESS
:
4863 fprintf(file
, "a0.%d", inst
->dst
.subnr
);
4865 case BRW_ARF_ACCUMULATOR
:
4866 fprintf(file
, "acc%d", inst
->dst
.subnr
);
4869 fprintf(file
, "f%d.%d", inst
->dst
.nr
& 0xf, inst
->dst
.subnr
);
4872 fprintf(file
, "arf%d.%d", inst
->dst
.nr
& 0xf, inst
->dst
.subnr
);
4875 if (inst
->dst
.subnr
)
4876 fprintf(file
, "+%d", inst
->dst
.subnr
);
4879 unreachable("not reached");
4881 if (inst
->dst
.stride
!= 1)
4882 fprintf(file
, "<%u>", inst
->dst
.stride
);
4883 fprintf(file
, ":%s, ", brw_reg_type_letters(inst
->dst
.type
));
4885 for (int i
= 0; i
< inst
->sources
; i
++) {
4886 if (inst
->src
[i
].negate
)
4888 if (inst
->src
[i
].abs
)
4890 switch (inst
->src
[i
].file
) {
4892 fprintf(file
, "vgrf%d", inst
->src
[i
].nr
);
4893 if (alloc
.sizes
[inst
->src
[i
].nr
] != (unsigned)inst
->regs_read(i
) ||
4894 inst
->src
[i
].subreg_offset
)
4895 fprintf(file
, "+%d.%d", inst
->src
[i
].reg_offset
,
4896 inst
->src
[i
].subreg_offset
);
4899 fprintf(file
, "g%d", inst
->src
[i
].nr
);
4902 fprintf(file
, "***m%d***", inst
->src
[i
].nr
);
4905 fprintf(file
, "attr%d+%d", inst
->src
[i
].nr
, inst
->src
[i
].reg_offset
);
4908 fprintf(file
, "u%d", inst
->src
[i
].nr
+ inst
->src
[i
].reg_offset
);
4909 if (inst
->src
[i
].subreg_offset
) {
4910 fprintf(file
, "+%d.%d", inst
->src
[i
].reg_offset
,
4911 inst
->src
[i
].subreg_offset
);
4915 fprintf(file
, "(null)");
4918 switch (inst
->src
[i
].type
) {
4919 case BRW_REGISTER_TYPE_F
:
4920 fprintf(file
, "%-gf", inst
->src
[i
].f
);
4922 case BRW_REGISTER_TYPE_DF
:
4923 fprintf(file
, "%fdf", inst
->src
[i
].df
);
4925 case BRW_REGISTER_TYPE_W
:
4926 case BRW_REGISTER_TYPE_D
:
4927 fprintf(file
, "%dd", inst
->src
[i
].d
);
4929 case BRW_REGISTER_TYPE_UW
:
4930 case BRW_REGISTER_TYPE_UD
:
4931 fprintf(file
, "%uu", inst
->src
[i
].ud
);
4933 case BRW_REGISTER_TYPE_VF
:
4934 fprintf(file
, "[%-gF, %-gF, %-gF, %-gF]",
4935 brw_vf_to_float((inst
->src
[i
].ud
>> 0) & 0xff),
4936 brw_vf_to_float((inst
->src
[i
].ud
>> 8) & 0xff),
4937 brw_vf_to_float((inst
->src
[i
].ud
>> 16) & 0xff),
4938 brw_vf_to_float((inst
->src
[i
].ud
>> 24) & 0xff));
4941 fprintf(file
, "???");
4946 switch (inst
->src
[i
].nr
) {
4948 fprintf(file
, "null");
4950 case BRW_ARF_ADDRESS
:
4951 fprintf(file
, "a0.%d", inst
->src
[i
].subnr
);
4953 case BRW_ARF_ACCUMULATOR
:
4954 fprintf(file
, "acc%d", inst
->src
[i
].subnr
);
4957 fprintf(file
, "f%d.%d", inst
->src
[i
].nr
& 0xf, inst
->src
[i
].subnr
);
4960 fprintf(file
, "arf%d.%d", inst
->src
[i
].nr
& 0xf, inst
->src
[i
].subnr
);
4963 if (inst
->src
[i
].subnr
)
4964 fprintf(file
, "+%d", inst
->src
[i
].subnr
);
4967 if (inst
->src
[i
].abs
)
4970 if (inst
->src
[i
].file
!= IMM
) {
4972 if (inst
->src
[i
].file
== ARF
|| inst
->src
[i
].file
== FIXED_GRF
) {
4973 unsigned hstride
= inst
->src
[i
].hstride
;
4974 stride
= (hstride
== 0 ? 0 : (1 << (hstride
- 1)));
4976 stride
= inst
->src
[i
].stride
;
4979 fprintf(file
, "<%u>", stride
);
4981 fprintf(file
, ":%s", brw_reg_type_letters(inst
->src
[i
].type
));
4984 if (i
< inst
->sources
- 1 && inst
->src
[i
+ 1].file
!= BAD_FILE
)
4985 fprintf(file
, ", ");
4990 if (inst
->force_writemask_all
)
4991 fprintf(file
, "NoMask ");
4993 if (dispatch_width
== 16 && inst
->exec_size
== 8) {
4994 if (inst
->force_sechalf
)
4995 fprintf(file
, "2ndhalf ");
4997 fprintf(file
, "1sthalf ");
5000 fprintf(file
, "\n");
5004 * Possibly returns an instruction that set up @param reg.
5006 * Sometimes we want to take the result of some expression/variable
5007 * dereference tree and rewrite the instruction generating the result
5008 * of the tree. When processing the tree, we know that the
5009 * instructions generated are all writing temporaries that are dead
5010 * outside of this tree. So, if we have some instructions that write
5011 * a temporary, we're free to point that temp write somewhere else.
5013 * Note that this doesn't guarantee that the instruction generated
5014 * only reg -- it might be the size=4 destination of a texture instruction.
5017 fs_visitor::get_instruction_generating_reg(fs_inst
*start
,
5022 end
->is_partial_write() ||
5023 !reg
.equals(end
->dst
)) {
5031 fs_visitor::setup_fs_payload_gen6()
5033 assert(stage
== MESA_SHADER_FRAGMENT
);
5034 brw_wm_prog_data
*prog_data
= (brw_wm_prog_data
*) this->prog_data
;
5035 brw_wm_prog_key
*key
= (brw_wm_prog_key
*) this->key
;
5037 unsigned barycentric_interp_modes
=
5038 (stage
== MESA_SHADER_FRAGMENT
) ?
5039 ((brw_wm_prog_data
*) this->prog_data
)->barycentric_interp_modes
: 0;
5041 assert(devinfo
->gen
>= 6);
5043 /* R0-1: masks, pixel X/Y coordinates. */
5044 payload
.num_regs
= 2;
5045 /* R2: only for 32-pixel dispatch.*/
5047 /* R3-26: barycentric interpolation coordinates. These appear in the
5048 * same order that they appear in the brw_wm_barycentric_interp_mode
5049 * enum. Each set of coordinates occupies 2 registers if dispatch width
5050 * == 8 and 4 registers if dispatch width == 16. Coordinates only
5051 * appear if they were enabled using the "Barycentric Interpolation
5052 * Mode" bits in WM_STATE.
5054 for (int i
= 0; i
< BRW_WM_BARYCENTRIC_INTERP_MODE_COUNT
; ++i
) {
5055 if (barycentric_interp_modes
& (1 << i
)) {
5056 payload
.barycentric_coord_reg
[i
] = payload
.num_regs
;
5057 payload
.num_regs
+= 2;
5058 if (dispatch_width
== 16) {
5059 payload
.num_regs
+= 2;
5064 /* R27: interpolated depth if uses source depth */
5065 prog_data
->uses_src_depth
=
5066 (nir
->info
.inputs_read
& (1 << VARYING_SLOT_POS
)) != 0;
5067 if (prog_data
->uses_src_depth
) {
5068 payload
.source_depth_reg
= payload
.num_regs
;
5070 if (dispatch_width
== 16) {
5071 /* R28: interpolated depth if not SIMD8. */
5076 /* R29: interpolated W set if GEN6_WM_USES_SOURCE_W. */
5077 prog_data
->uses_src_w
=
5078 (nir
->info
.inputs_read
& (1 << VARYING_SLOT_POS
)) != 0;
5079 if (prog_data
->uses_src_w
) {
5080 payload
.source_w_reg
= payload
.num_regs
;
5082 if (dispatch_width
== 16) {
5083 /* R30: interpolated W if not SIMD8. */
5088 prog_data
->uses_pos_offset
= key
->compute_pos_offset
;
5089 /* R31: MSAA position offsets. */
5090 if (prog_data
->uses_pos_offset
) {
5091 payload
.sample_pos_reg
= payload
.num_regs
;
5095 /* R32: MSAA input coverage mask */
5096 prog_data
->uses_sample_mask
=
5097 (nir
->info
.system_values_read
& SYSTEM_BIT_SAMPLE_MASK_IN
) != 0;
5098 if (prog_data
->uses_sample_mask
) {
5099 assert(devinfo
->gen
>= 7);
5100 payload
.sample_mask_in_reg
= payload
.num_regs
;
5102 if (dispatch_width
== 16) {
5103 /* R33: input coverage mask if not SIMD8. */
5108 /* R34-: bary for 32-pixel. */
5109 /* R58-59: interp W for 32-pixel. */
5111 if (nir
->info
.outputs_written
& BITFIELD64_BIT(FRAG_RESULT_DEPTH
)) {
5112 source_depth_to_render_target
= true;
5117 fs_visitor::setup_vs_payload()
5119 /* R0: thread header, R1: urb handles */
5120 payload
.num_regs
= 2;
5124 * We are building the local ID push constant data using the simplest possible
5125 * method. We simply push the local IDs directly as they should appear in the
5126 * registers for the uvec3 gl_LocalInvocationID variable.
5128 * Therefore, for SIMD8, we use 3 full registers, and for SIMD16 we use 6
5129 * registers worth of push constant space.
5131 * Note: Any updates to brw_cs_prog_local_id_payload_dwords,
5132 * fill_local_id_payload or fs_visitor::emit_cs_local_invocation_id_setup need
5135 * FINISHME: There are a few easy optimizations to consider.
5137 * 1. If gl_WorkGroupSize x, y or z is 1, we can just use zero, and there is
5138 * no need for using push constant space for that dimension.
5140 * 2. Since GL_MAX_COMPUTE_WORK_GROUP_SIZE is currently 1024 or less, we can
5141 * easily use 16-bit words rather than 32-bit dwords in the push constant
5144 * 3. If gl_WorkGroupSize x, y or z is small, then we can use bytes for
5145 * conveying the data, and thereby reduce push constant usage.
5149 fs_visitor::setup_gs_payload()
5151 assert(stage
== MESA_SHADER_GEOMETRY
);
5153 struct brw_gs_prog_data
*gs_prog_data
=
5154 (struct brw_gs_prog_data
*) prog_data
;
5155 struct brw_vue_prog_data
*vue_prog_data
=
5156 (struct brw_vue_prog_data
*) prog_data
;
5158 /* R0: thread header, R1: output URB handles */
5159 payload
.num_regs
= 2;
5161 if (gs_prog_data
->include_primitive_id
) {
5162 /* R2: Primitive ID 0..7 */
5166 /* Use a maximum of 32 registers for push-model inputs. */
5167 const unsigned max_push_components
= 32;
5169 /* If pushing our inputs would take too many registers, reduce the URB read
5170 * length (which is in HWords, or 8 registers), and resort to pulling.
5172 * Note that the GS reads <URB Read Length> HWords for every vertex - so we
5173 * have to multiply by VerticesIn to obtain the total storage requirement.
5175 if (8 * vue_prog_data
->urb_read_length
* nir
->info
.gs
.vertices_in
>
5176 max_push_components
) {
5177 gs_prog_data
->base
.include_vue_handles
= true;
5179 /* R3..RN: ICP Handles for each incoming vertex (when using pull model) */
5180 payload
.num_regs
+= nir
->info
.gs
.vertices_in
;
5182 vue_prog_data
->urb_read_length
=
5183 ROUND_DOWN_TO(max_push_components
/ nir
->info
.gs
.vertices_in
, 8) / 8;
5188 fs_visitor::setup_cs_payload()
5190 assert(devinfo
->gen
>= 7);
5191 brw_cs_prog_data
*prog_data
= (brw_cs_prog_data
*) this->prog_data
;
5193 payload
.num_regs
= 1;
5195 if (nir
->info
.system_values_read
& SYSTEM_BIT_LOCAL_INVOCATION_ID
) {
5196 prog_data
->local_invocation_id_regs
= dispatch_width
* 3 / 8;
5197 payload
.local_invocation_id_reg
= payload
.num_regs
;
5198 payload
.num_regs
+= prog_data
->local_invocation_id_regs
;
5203 fs_visitor::calculate_register_pressure()
5205 invalidate_live_intervals();
5206 calculate_live_intervals();
5208 unsigned num_instructions
= 0;
5209 foreach_block(block
, cfg
)
5210 num_instructions
+= block
->instructions
.length();
5212 regs_live_at_ip
= rzalloc_array(mem_ctx
, int, num_instructions
);
5214 for (unsigned reg
= 0; reg
< alloc
.count
; reg
++) {
5215 for (int ip
= virtual_grf_start
[reg
]; ip
<= virtual_grf_end
[reg
]; ip
++)
5216 regs_live_at_ip
[ip
] += alloc
.sizes
[reg
];
5221 * Look for repeated FS_OPCODE_MOV_DISPATCH_TO_FLAGS and drop the later ones.
5223 * The needs_unlit_centroid_workaround ends up producing one of these per
5224 * channel of centroid input, so it's good to clean them up.
5226 * An assumption here is that nothing ever modifies the dispatched pixels
5227 * value that FS_OPCODE_MOV_DISPATCH_TO_FLAGS reads from, but the hardware
5228 * dictates that anyway.
5231 fs_visitor::opt_drop_redundant_mov_to_flags()
5233 bool flag_mov_found
[2] = {false};
5234 bool progress
= false;
5236 /* Instructions removed by this pass can only be added if this were true */
5237 if (!devinfo
->needs_unlit_centroid_workaround
)
5240 foreach_block_and_inst_safe(block
, fs_inst
, inst
, cfg
) {
5241 if (inst
->is_control_flow()) {
5242 memset(flag_mov_found
, 0, sizeof(flag_mov_found
));
5243 } else if (inst
->opcode
== FS_OPCODE_MOV_DISPATCH_TO_FLAGS
) {
5244 if (!flag_mov_found
[inst
->flag_subreg
]) {
5245 flag_mov_found
[inst
->flag_subreg
] = true;
5247 inst
->remove(block
);
5250 } else if (inst
->writes_flag()) {
5251 flag_mov_found
[inst
->flag_subreg
] = false;
5259 fs_visitor::optimize()
5261 /* Start by validating the shader we currently have. */
5264 /* bld is the common builder object pointing at the end of the program we
5265 * used to translate it into i965 IR. For the optimization and lowering
5266 * passes coming next, any code added after the end of the program without
5267 * having explicitly called fs_builder::at() clearly points at a mistake.
5268 * Ideally optimization passes wouldn't be part of the visitor so they
5269 * wouldn't have access to bld at all, but they do, so just in case some
5270 * pass forgets to ask for a location explicitly set it to NULL here to
5271 * make it trip. The dispatch width is initialized to a bogus value to
5272 * make sure that optimizations set the execution controls explicitly to
5273 * match the code they are manipulating instead of relying on the defaults.
5275 bld
= fs_builder(this, 64);
5277 assign_constant_locations();
5278 lower_constant_loads();
5282 split_virtual_grfs();
5285 #define OPT(pass, args...) ({ \
5287 bool this_progress = pass(args); \
5289 if (unlikely(INTEL_DEBUG & DEBUG_OPTIMIZER) && this_progress) { \
5290 char filename[64]; \
5291 snprintf(filename, 64, "%s%d-%s-%02d-%02d-" #pass, \
5292 stage_abbrev, dispatch_width, nir->info.name, iteration, pass_num); \
5294 backend_shader::dump_instructions(filename); \
5299 progress = progress || this_progress; \
5303 if (unlikely(INTEL_DEBUG
& DEBUG_OPTIMIZER
)) {
5305 snprintf(filename
, 64, "%s%d-%s-00-00-start",
5306 stage_abbrev
, dispatch_width
, nir
->info
.name
);
5308 backend_shader::dump_instructions(filename
);
5311 bool progress
= false;
5315 OPT(opt_drop_redundant_mov_to_flags
);
5317 OPT(lower_simd_width
);
5318 OPT(lower_logical_sends
);
5325 OPT(remove_duplicate_mrf_writes
);
5329 OPT(opt_copy_propagate
);
5330 OPT(opt_predicated_break
, this);
5331 OPT(opt_cmod_propagation
);
5332 OPT(dead_code_eliminate
);
5333 OPT(opt_peephole_sel
);
5334 OPT(dead_control_flow_eliminate
, this);
5335 OPT(opt_register_renaming
);
5336 OPT(opt_redundant_discard_jumps
);
5337 OPT(opt_saturate_propagation
);
5338 OPT(opt_zero_samples
);
5339 OPT(register_coalesce
);
5340 OPT(compute_to_mrf
);
5341 OPT(eliminate_find_live_channel
);
5343 OPT(compact_virtual_grfs
);
5348 OPT(opt_sampler_eot
);
5350 if (OPT(lower_load_payload
)) {
5351 split_virtual_grfs();
5352 OPT(register_coalesce
);
5353 OPT(compute_to_mrf
);
5354 OPT(dead_code_eliminate
);
5357 if (OPT(lower_pack
)) {
5358 OPT(register_coalesce
);
5359 OPT(dead_code_eliminate
);
5362 if (OPT(lower_d2f
)) {
5363 OPT(opt_copy_propagate
);
5364 OPT(dead_code_eliminate
);
5367 OPT(opt_combine_constants
);
5368 OPT(lower_integer_multiplication
);
5370 if (devinfo
->gen
<= 5 && OPT(lower_minmax
)) {
5371 OPT(opt_cmod_propagation
);
5373 OPT(opt_copy_propagate
);
5374 OPT(dead_code_eliminate
);
5377 lower_uniform_pull_constant_loads();
5383 * Three source instruction must have a GRF/MRF destination register.
5384 * ARF NULL is not allowed. Fix that up by allocating a temporary GRF.
5387 fs_visitor::fixup_3src_null_dest()
5389 bool progress
= false;
5391 foreach_block_and_inst_safe (block
, fs_inst
, inst
, cfg
) {
5392 if (inst
->is_3src(devinfo
) && inst
->dst
.is_null()) {
5393 inst
->dst
= fs_reg(VGRF
, alloc
.allocate(dispatch_width
/ 8),
5400 invalidate_live_intervals();
5404 fs_visitor::allocate_registers()
5406 bool allocated_without_spills
;
5408 static const enum instruction_scheduler_mode pre_modes
[] = {
5410 SCHEDULE_PRE_NON_LIFO
,
5414 /* Try each scheduling heuristic to see if it can successfully register
5415 * allocate without spilling. They should be ordered by decreasing
5416 * performance but increasing likelihood of allocating.
5418 for (unsigned i
= 0; i
< ARRAY_SIZE(pre_modes
); i
++) {
5419 schedule_instructions(pre_modes
[i
]);
5422 assign_regs_trivial();
5423 allocated_without_spills
= true;
5425 allocated_without_spills
= assign_regs(false);
5427 if (allocated_without_spills
)
5431 if (!allocated_without_spills
) {
5432 /* We assume that any spilling is worse than just dropping back to
5433 * SIMD8. There's probably actually some intermediate point where
5434 * SIMD16 with a couple of spills is still better.
5436 if (dispatch_width
== 16 && min_dispatch_width
<= 8) {
5437 fail("Failure to register allocate. Reduce number of "
5438 "live scalar values to avoid this.");
5440 compiler
->shader_perf_log(log_data
,
5441 "%s shader triggered register spilling. "
5442 "Try reducing the number of live scalar "
5443 "values to improve performance.\n",
5447 /* Since we're out of heuristics, just go spill registers until we
5448 * get an allocation.
5450 while (!assign_regs(true)) {
5456 /* This must come after all optimization and register allocation, since
5457 * it inserts dead code that happens to have side effects, and it does
5458 * so based on the actual physical registers in use.
5460 insert_gen4_send_dependency_workarounds();
5465 schedule_instructions(SCHEDULE_POST
);
5467 if (last_scratch
> 0)
5468 prog_data
->total_scratch
= brw_get_scratch_size(last_scratch
);
5472 fs_visitor::run_vs(gl_clip_plane
*clip_planes
)
5474 assert(stage
== MESA_SHADER_VERTEX
);
5478 if (shader_time_index
>= 0)
5479 emit_shader_time_begin();
5486 compute_clip_distance(clip_planes
);
5490 if (shader_time_index
>= 0)
5491 emit_shader_time_end();
5497 assign_curb_setup();
5498 assign_vs_urb_setup();
5500 fixup_3src_null_dest();
5501 allocate_registers();
5507 fs_visitor::run_tcs_single_patch()
5509 assert(stage
== MESA_SHADER_TESS_CTRL
);
5511 struct brw_tcs_prog_data
*tcs_prog_data
=
5512 (struct brw_tcs_prog_data
*) prog_data
;
5514 /* r1-r4 contain the ICP handles. */
5515 payload
.num_regs
= 5;
5517 if (shader_time_index
>= 0)
5518 emit_shader_time_begin();
5520 /* Initialize gl_InvocationID */
5521 fs_reg channels_uw
= bld
.vgrf(BRW_REGISTER_TYPE_UW
);
5522 fs_reg channels_ud
= bld
.vgrf(BRW_REGISTER_TYPE_UD
);
5523 bld
.MOV(channels_uw
, fs_reg(brw_imm_uv(0x76543210)));
5524 bld
.MOV(channels_ud
, channels_uw
);
5526 if (tcs_prog_data
->instances
== 1) {
5527 invocation_id
= channels_ud
;
5529 invocation_id
= bld
.vgrf(BRW_REGISTER_TYPE_UD
);
5531 /* Get instance number from g0.2 bits 23:17, and multiply it by 8. */
5532 fs_reg t
= bld
.vgrf(BRW_REGISTER_TYPE_UD
);
5533 fs_reg instance_times_8
= bld
.vgrf(BRW_REGISTER_TYPE_UD
);
5534 bld
.AND(t
, fs_reg(retype(brw_vec1_grf(0, 2), BRW_REGISTER_TYPE_UD
)),
5535 brw_imm_ud(INTEL_MASK(23, 17)));
5536 bld
.SHR(instance_times_8
, t
, brw_imm_ud(17 - 3));
5538 bld
.ADD(invocation_id
, instance_times_8
, channels_ud
);
5541 /* Fix the disptach mask */
5542 if (nir
->info
.tcs
.vertices_out
% 8) {
5543 bld
.CMP(bld
.null_reg_ud(), invocation_id
,
5544 brw_imm_ud(nir
->info
.tcs
.vertices_out
), BRW_CONDITIONAL_L
);
5545 bld
.IF(BRW_PREDICATE_NORMAL
);
5550 if (nir
->info
.tcs
.vertices_out
% 8) {
5551 bld
.emit(BRW_OPCODE_ENDIF
);
5554 /* Emit EOT write; set TR DS Cache bit */
5556 fs_reg(retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_UD
)),
5557 fs_reg(brw_imm_ud(WRITEMASK_X
<< 16)),
5558 fs_reg(brw_imm_ud(0)),
5560 fs_reg payload
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 3);
5561 bld
.LOAD_PAYLOAD(payload
, srcs
, 3, 2);
5563 fs_inst
*inst
= bld
.emit(SHADER_OPCODE_URB_WRITE_SIMD8_MASKED
,
5564 bld
.null_reg_ud(), payload
);
5566 inst
->base_mrf
= -1;
5569 if (shader_time_index
>= 0)
5570 emit_shader_time_end();
5579 assign_curb_setup();
5580 assign_tcs_single_patch_urb_setup();
5582 fixup_3src_null_dest();
5583 allocate_registers();
5589 fs_visitor::run_tes()
5591 assert(stage
== MESA_SHADER_TESS_EVAL
);
5593 /* R0: thread header, R1-3: gl_TessCoord.xyz, R4: URB handles */
5594 payload
.num_regs
= 5;
5596 if (shader_time_index
>= 0)
5597 emit_shader_time_begin();
5606 if (shader_time_index
>= 0)
5607 emit_shader_time_end();
5613 assign_curb_setup();
5614 assign_tes_urb_setup();
5616 fixup_3src_null_dest();
5617 allocate_registers();
5623 fs_visitor::run_gs()
5625 assert(stage
== MESA_SHADER_GEOMETRY
);
5629 this->final_gs_vertex_count
= vgrf(glsl_type::uint_type
);
5631 if (gs_compile
->control_data_header_size_bits
> 0) {
5632 /* Create a VGRF to store accumulated control data bits. */
5633 this->control_data_bits
= vgrf(glsl_type::uint_type
);
5635 /* If we're outputting more than 32 control data bits, then EmitVertex()
5636 * will set control_data_bits to 0 after emitting the first vertex.
5637 * Otherwise, we need to initialize it to 0 here.
5639 if (gs_compile
->control_data_header_size_bits
<= 32) {
5640 const fs_builder abld
= bld
.annotate("initialize control data bits");
5641 abld
.MOV(this->control_data_bits
, brw_imm_ud(0u));
5645 if (shader_time_index
>= 0)
5646 emit_shader_time_begin();
5650 emit_gs_thread_end();
5652 if (shader_time_index
>= 0)
5653 emit_shader_time_end();
5662 assign_curb_setup();
5663 assign_gs_urb_setup();
5665 fixup_3src_null_dest();
5666 allocate_registers();
5672 fs_visitor::run_fs(bool do_rep_send
)
5674 brw_wm_prog_data
*wm_prog_data
= (brw_wm_prog_data
*) this->prog_data
;
5675 brw_wm_prog_key
*wm_key
= (brw_wm_prog_key
*) this->key
;
5677 assert(stage
== MESA_SHADER_FRAGMENT
);
5679 if (devinfo
->gen
>= 6)
5680 setup_fs_payload_gen6();
5682 setup_fs_payload_gen4();
5686 } else if (do_rep_send
) {
5687 assert(dispatch_width
== 16);
5688 emit_repclear_shader();
5690 if (shader_time_index
>= 0)
5691 emit_shader_time_begin();
5693 calculate_urb_setup();
5694 if (nir
->info
.inputs_read
> 0) {
5695 if (devinfo
->gen
< 6)
5696 emit_interpolation_setup_gen4();
5698 emit_interpolation_setup_gen6();
5701 /* We handle discards by keeping track of the still-live pixels in f0.1.
5702 * Initialize it with the dispatched pixels.
5704 if (wm_prog_data
->uses_kill
) {
5705 fs_inst
*discard_init
= bld
.emit(FS_OPCODE_MOV_DISPATCH_TO_FLAGS
);
5706 discard_init
->flag_subreg
= 1;
5709 /* Generate FS IR for main(). (the visitor only descends into
5710 * functions called "main").
5717 if (wm_prog_data
->uses_kill
)
5718 bld
.emit(FS_OPCODE_PLACEHOLDER_HALT
);
5720 if (wm_key
->alpha_test_func
)
5725 if (shader_time_index
>= 0)
5726 emit_shader_time_end();
5732 assign_curb_setup();
5735 fixup_3src_null_dest();
5736 allocate_registers();
5742 if (dispatch_width
== 8)
5743 wm_prog_data
->reg_blocks
= brw_register_blocks(grf_used
);
5745 wm_prog_data
->reg_blocks_16
= brw_register_blocks(grf_used
);
5751 fs_visitor::run_cs()
5753 assert(stage
== MESA_SHADER_COMPUTE
);
5757 if (shader_time_index
>= 0)
5758 emit_shader_time_begin();
5760 if (devinfo
->is_haswell
&& prog_data
->total_shared
> 0) {
5761 /* Move SLM index from g0.0[27:24] to sr0.1[11:8] */
5762 const fs_builder abld
= bld
.exec_all().group(1, 0);
5763 abld
.MOV(retype(suboffset(brw_sr0_reg(), 1), BRW_REGISTER_TYPE_UW
),
5764 suboffset(retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_UW
), 1));
5772 emit_cs_terminate();
5774 if (shader_time_index
>= 0)
5775 emit_shader_time_end();
5781 assign_curb_setup();
5783 fixup_3src_null_dest();
5784 allocate_registers();
5793 * Return a bitfield where bit n is set if barycentric interpolation mode n
5794 * (see enum brw_wm_barycentric_interp_mode) is needed by the fragment shader.
5797 brw_compute_barycentric_interp_modes(const struct brw_device_info
*devinfo
,
5798 bool shade_model_flat
,
5799 bool persample_shading
,
5800 const nir_shader
*shader
)
5802 unsigned barycentric_interp_modes
= 0;
5804 nir_foreach_variable(var
, &shader
->inputs
) {
5805 enum glsl_interp_qualifier interp_qualifier
=
5806 (enum glsl_interp_qualifier
)var
->data
.interpolation
;
5807 bool is_centroid
= var
->data
.centroid
&& !persample_shading
;
5808 bool is_sample
= var
->data
.sample
|| persample_shading
;
5809 bool is_gl_Color
= (var
->data
.location
== VARYING_SLOT_COL0
) ||
5810 (var
->data
.location
== VARYING_SLOT_COL1
);
5812 /* Ignore WPOS and FACE, because they don't require interpolation. */
5813 if (var
->data
.location
== VARYING_SLOT_POS
||
5814 var
->data
.location
== VARYING_SLOT_FACE
)
5817 /* Determine the set (or sets) of barycentric coordinates needed to
5818 * interpolate this variable. Note that when
5819 * brw->needs_unlit_centroid_workaround is set, centroid interpolation
5820 * uses PIXEL interpolation for unlit pixels and CENTROID interpolation
5821 * for lit pixels, so we need both sets of barycentric coordinates.
5823 if (interp_qualifier
== INTERP_QUALIFIER_NOPERSPECTIVE
) {
5825 barycentric_interp_modes
|=
5826 1 << BRW_WM_NONPERSPECTIVE_CENTROID_BARYCENTRIC
;
5827 } else if (is_sample
) {
5828 barycentric_interp_modes
|=
5829 1 << BRW_WM_NONPERSPECTIVE_SAMPLE_BARYCENTRIC
;
5831 if ((!is_centroid
&& !is_sample
) ||
5832 devinfo
->needs_unlit_centroid_workaround
) {
5833 barycentric_interp_modes
|=
5834 1 << BRW_WM_NONPERSPECTIVE_PIXEL_BARYCENTRIC
;
5836 } else if (interp_qualifier
== INTERP_QUALIFIER_SMOOTH
||
5837 (!(shade_model_flat
&& is_gl_Color
) &&
5838 interp_qualifier
== INTERP_QUALIFIER_NONE
)) {
5840 barycentric_interp_modes
|=
5841 1 << BRW_WM_PERSPECTIVE_CENTROID_BARYCENTRIC
;
5842 } else if (is_sample
) {
5843 barycentric_interp_modes
|=
5844 1 << BRW_WM_PERSPECTIVE_SAMPLE_BARYCENTRIC
;
5846 if ((!is_centroid
&& !is_sample
) ||
5847 devinfo
->needs_unlit_centroid_workaround
) {
5848 barycentric_interp_modes
|=
5849 1 << BRW_WM_PERSPECTIVE_PIXEL_BARYCENTRIC
;
5854 return barycentric_interp_modes
;
5858 brw_compute_flat_inputs(struct brw_wm_prog_data
*prog_data
,
5859 bool shade_model_flat
, const nir_shader
*shader
)
5861 prog_data
->flat_inputs
= 0;
5863 nir_foreach_variable(var
, &shader
->inputs
) {
5864 enum glsl_interp_qualifier interp_qualifier
=
5865 (enum glsl_interp_qualifier
)var
->data
.interpolation
;
5866 bool is_gl_Color
= (var
->data
.location
== VARYING_SLOT_COL0
) ||
5867 (var
->data
.location
== VARYING_SLOT_COL1
);
5869 int input_index
= prog_data
->urb_setup
[var
->data
.location
];
5871 if (input_index
< 0)
5875 if (interp_qualifier
== INTERP_QUALIFIER_FLAT
||
5876 (shade_model_flat
&& is_gl_Color
&&
5877 interp_qualifier
== INTERP_QUALIFIER_NONE
))
5878 prog_data
->flat_inputs
|= (1 << input_index
);
5883 computed_depth_mode(const nir_shader
*shader
)
5885 if (shader
->info
.outputs_written
& BITFIELD64_BIT(FRAG_RESULT_DEPTH
)) {
5886 switch (shader
->info
.fs
.depth_layout
) {
5887 case FRAG_DEPTH_LAYOUT_NONE
:
5888 case FRAG_DEPTH_LAYOUT_ANY
:
5889 return BRW_PSCDEPTH_ON
;
5890 case FRAG_DEPTH_LAYOUT_GREATER
:
5891 return BRW_PSCDEPTH_ON_GE
;
5892 case FRAG_DEPTH_LAYOUT_LESS
:
5893 return BRW_PSCDEPTH_ON_LE
;
5894 case FRAG_DEPTH_LAYOUT_UNCHANGED
:
5895 return BRW_PSCDEPTH_OFF
;
5898 return BRW_PSCDEPTH_OFF
;
5902 brw_compile_fs(const struct brw_compiler
*compiler
, void *log_data
,
5904 const struct brw_wm_prog_key
*key
,
5905 struct brw_wm_prog_data
*prog_data
,
5906 const nir_shader
*src_shader
,
5907 struct gl_program
*prog
,
5908 int shader_time_index8
, int shader_time_index16
,
5910 unsigned *final_assembly_size
,
5913 nir_shader
*shader
= nir_shader_clone(mem_ctx
, src_shader
);
5914 shader
= brw_nir_apply_sampler_key(shader
, compiler
->devinfo
, &key
->tex
,
5916 brw_nir_lower_fs_inputs(shader
);
5917 brw_nir_lower_fs_outputs(shader
);
5918 shader
= brw_postprocess_nir(shader
, compiler
->devinfo
, true);
5920 /* key->alpha_test_func means simulating alpha testing via discards,
5921 * so the shader definitely kills pixels.
5923 prog_data
->uses_kill
= shader
->info
.fs
.uses_discard
|| key
->alpha_test_func
;
5924 prog_data
->uses_omask
= key
->multisample_fbo
&&
5925 shader
->info
.outputs_written
& BITFIELD64_BIT(FRAG_RESULT_SAMPLE_MASK
);
5926 prog_data
->computed_depth_mode
= computed_depth_mode(shader
);
5927 prog_data
->computed_stencil
=
5928 shader
->info
.outputs_written
& BITFIELD64_BIT(FRAG_RESULT_STENCIL
);
5930 prog_data
->early_fragment_tests
= shader
->info
.fs
.early_fragment_tests
;
5932 prog_data
->barycentric_interp_modes
=
5933 brw_compute_barycentric_interp_modes(compiler
->devinfo
,
5935 key
->persample_shading
,
5938 fs_visitor
v(compiler
, log_data
, mem_ctx
, key
,
5939 &prog_data
->base
, prog
, shader
, 8,
5940 shader_time_index8
);
5941 if (!v
.run_fs(false /* do_rep_send */)) {
5943 *error_str
= ralloc_strdup(mem_ctx
, v
.fail_msg
);
5948 cfg_t
*simd16_cfg
= NULL
;
5949 fs_visitor
v2(compiler
, log_data
, mem_ctx
, key
,
5950 &prog_data
->base
, prog
, shader
, 16,
5951 shader_time_index16
);
5952 if (likely(!(INTEL_DEBUG
& DEBUG_NO16
) || use_rep_send
)) {
5953 if (!v
.simd16_unsupported
) {
5954 /* Try a SIMD16 compile */
5955 v2
.import_uniforms(&v
);
5956 if (!v2
.run_fs(use_rep_send
)) {
5957 compiler
->shader_perf_log(log_data
,
5958 "SIMD16 shader failed to compile: %s",
5961 simd16_cfg
= v2
.cfg
;
5966 /* We have to compute the flat inputs after the visitor is finished running
5967 * because it relies on prog_data->urb_setup which is computed in
5968 * fs_visitor::calculate_urb_setup().
5970 brw_compute_flat_inputs(prog_data
, key
->flat_shade
, shader
);
5973 int no_simd8
= (INTEL_DEBUG
& DEBUG_NO8
) || use_rep_send
;
5974 if ((no_simd8
|| compiler
->devinfo
->gen
< 5) && simd16_cfg
) {
5976 prog_data
->no_8
= true;
5979 prog_data
->no_8
= false;
5982 fs_generator
g(compiler
, log_data
, mem_ctx
, (void *) key
, &prog_data
->base
,
5983 v
.promoted_constants
, v
.runtime_check_aads_emit
,
5984 MESA_SHADER_FRAGMENT
);
5986 if (unlikely(INTEL_DEBUG
& DEBUG_WM
)) {
5987 g
.enable_debug(ralloc_asprintf(mem_ctx
, "%s fragment shader %s",
5988 shader
->info
.label
? shader
->info
.label
:
5990 shader
->info
.name
));
5994 g
.generate_code(simd8_cfg
, 8);
5996 prog_data
->prog_offset_16
= g
.generate_code(simd16_cfg
, 16);
5998 return g
.get_assembly(final_assembly_size
);
6002 fs_visitor::emit_cs_local_invocation_id_setup()
6004 assert(stage
== MESA_SHADER_COMPUTE
);
6006 fs_reg
*reg
= new(this->mem_ctx
) fs_reg(vgrf(glsl_type::uvec3_type
));
6008 struct brw_reg src
=
6009 brw_vec8_grf(payload
.local_invocation_id_reg
, 0);
6010 src
= retype(src
, BRW_REGISTER_TYPE_UD
);
6012 src
.nr
+= dispatch_width
/ 8;
6013 bld
.MOV(offset(*reg
, bld
, 1), src
);
6014 src
.nr
+= dispatch_width
/ 8;
6015 bld
.MOV(offset(*reg
, bld
, 2), src
);
6021 fs_visitor::emit_cs_work_group_id_setup()
6023 assert(stage
== MESA_SHADER_COMPUTE
);
6025 fs_reg
*reg
= new(this->mem_ctx
) fs_reg(vgrf(glsl_type::uvec3_type
));
6027 struct brw_reg
r0_1(retype(brw_vec1_grf(0, 1), BRW_REGISTER_TYPE_UD
));
6028 struct brw_reg
r0_6(retype(brw_vec1_grf(0, 6), BRW_REGISTER_TYPE_UD
));
6029 struct brw_reg
r0_7(retype(brw_vec1_grf(0, 7), BRW_REGISTER_TYPE_UD
));
6031 bld
.MOV(*reg
, r0_1
);
6032 bld
.MOV(offset(*reg
, bld
, 1), r0_6
);
6033 bld
.MOV(offset(*reg
, bld
, 2), r0_7
);
6039 brw_compile_cs(const struct brw_compiler
*compiler
, void *log_data
,
6041 const struct brw_cs_prog_key
*key
,
6042 struct brw_cs_prog_data
*prog_data
,
6043 const nir_shader
*src_shader
,
6044 int shader_time_index
,
6045 unsigned *final_assembly_size
,
6048 nir_shader
*shader
= nir_shader_clone(mem_ctx
, src_shader
);
6049 shader
= brw_nir_apply_sampler_key(shader
, compiler
->devinfo
, &key
->tex
,
6051 brw_nir_lower_cs_shared(shader
);
6052 prog_data
->base
.total_shared
+= shader
->num_shared
;
6053 shader
= brw_postprocess_nir(shader
, compiler
->devinfo
, true);
6055 prog_data
->local_size
[0] = shader
->info
.cs
.local_size
[0];
6056 prog_data
->local_size
[1] = shader
->info
.cs
.local_size
[1];
6057 prog_data
->local_size
[2] = shader
->info
.cs
.local_size
[2];
6058 unsigned local_workgroup_size
=
6059 shader
->info
.cs
.local_size
[0] * shader
->info
.cs
.local_size
[1] *
6060 shader
->info
.cs
.local_size
[2];
6062 unsigned max_cs_threads
= compiler
->devinfo
->max_cs_threads
;
6063 unsigned simd_required
= DIV_ROUND_UP(local_workgroup_size
, max_cs_threads
);
6066 const char *fail_msg
= NULL
;
6068 /* Now the main event: Visit the shader IR and generate our CS IR for it.
6070 fs_visitor
v8(compiler
, log_data
, mem_ctx
, key
, &prog_data
->base
,
6071 NULL
, /* Never used in core profile */
6072 shader
, 8, shader_time_index
);
6073 if (simd_required
<= 8) {
6075 fail_msg
= v8
.fail_msg
;
6078 prog_data
->simd_size
= 8;
6082 fs_visitor
v16(compiler
, log_data
, mem_ctx
, key
, &prog_data
->base
,
6083 NULL
, /* Never used in core profile */
6084 shader
, 16, shader_time_index
);
6085 if (likely(!(INTEL_DEBUG
& DEBUG_NO16
)) &&
6086 !fail_msg
&& !v8
.simd16_unsupported
&&
6087 local_workgroup_size
<= 16 * max_cs_threads
) {
6088 /* Try a SIMD16 compile */
6089 if (simd_required
<= 8)
6090 v16
.import_uniforms(&v8
);
6091 if (!v16
.run_cs()) {
6092 compiler
->shader_perf_log(log_data
,
6093 "SIMD16 shader failed to compile: %s",
6097 "Couldn't generate SIMD16 program and not "
6098 "enough threads for SIMD8";
6102 prog_data
->simd_size
= 16;
6106 if (unlikely(cfg
== NULL
)) {
6109 *error_str
= ralloc_strdup(mem_ctx
, fail_msg
);
6114 fs_generator
g(compiler
, log_data
, mem_ctx
, (void*) key
, &prog_data
->base
,
6115 v8
.promoted_constants
, v8
.runtime_check_aads_emit
,
6116 MESA_SHADER_COMPUTE
);
6117 if (INTEL_DEBUG
& DEBUG_CS
) {
6118 char *name
= ralloc_asprintf(mem_ctx
, "%s compute shader %s",
6119 shader
->info
.label
? shader
->info
.label
:
6122 g
.enable_debug(name
);
6125 g
.generate_code(cfg
, prog_data
->simd_size
);
6127 return g
.get_assembly(final_assembly_size
);
6131 brw_cs_fill_local_id_payload(const struct brw_cs_prog_data
*prog_data
,
6132 void *buffer
, uint32_t threads
, uint32_t stride
)
6134 if (prog_data
->local_invocation_id_regs
== 0)
6137 /* 'stride' should be an integer number of registers, that is, a multiple
6140 assert(stride
% 32 == 0);
6142 unsigned x
= 0, y
= 0, z
= 0;
6143 for (unsigned t
= 0; t
< threads
; t
++) {
6144 uint32_t *param
= (uint32_t *) buffer
+ stride
* t
/ 4;
6146 for (unsigned i
= 0; i
< prog_data
->simd_size
; i
++) {
6147 param
[0 * prog_data
->simd_size
+ i
] = x
;
6148 param
[1 * prog_data
->simd_size
+ i
] = y
;
6149 param
[2 * prog_data
->simd_size
+ i
] = z
;
6152 if (x
== prog_data
->local_size
[0]) {
6155 if (y
== prog_data
->local_size
[1]) {
6158 if (z
== prog_data
->local_size
[2])