src/mesa/drivers/dri/i965/brw_pipe_control.c

   1 /*
   2  * Copyright © 2010 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  */
  23
  24 #include "brw_context.h"
  25 #include "intel_batchbuffer.h"
  26 #include "intel_fbo.h"
  27 #include "intel_reg.h"
  28
  29 /**
  30  * According to the latest documentation, any PIPE_CONTROL with the
  31  * "Command Streamer Stall" bit set must also have another bit set,
  32  * with five different options:
  33  *
  34  *  - Render Target Cache Flush
  35  *  - Depth Cache Flush
  36  *  - Stall at Pixel Scoreboard
  37  *  - Post-Sync Operation
  38  *  - Depth Stall
  39  *  - DC Flush Enable
  40  *
  41  * I chose "Stall at Pixel Scoreboard" since we've used it effectively
  42  * in the past, but the choice is fairly arbitrary.
  43  */
  44 static void
  45 gen8_add_cs_stall_workaround_bits(uint32_t *flags)
  46 {
  47    uint32_t wa_bits = PIPE_CONTROL_RENDER_TARGET_FLUSH |
  48                       PIPE_CONTROL_DEPTH_CACHE_FLUSH |
  49                       PIPE_CONTROL_WRITE_IMMEDIATE |
  50                       PIPE_CONTROL_WRITE_DEPTH_COUNT |
  51                       PIPE_CONTROL_WRITE_TIMESTAMP |
  52                       PIPE_CONTROL_STALL_AT_SCOREBOARD |
  53                       PIPE_CONTROL_DEPTH_STALL |
  54                       PIPE_CONTROL_DATA_CACHE_INVALIDATE;
  55
  56    /* If we're doing a CS stall, and don't already have one of the
  57     * workaround bits set, add "Stall at Pixel Scoreboard."
  58     */
  59    if ((*flags & PIPE_CONTROL_CS_STALL) != 0 && (*flags & wa_bits) == 0)
  60       *flags |= PIPE_CONTROL_STALL_AT_SCOREBOARD;
  61 }
  62
  63 /* Implement the WaCsStallAtEveryFourthPipecontrol workaround on IVB, BYT:
  64  *
  65  * "Every 4th PIPE_CONTROL command, not counting the PIPE_CONTROL with
  66  *  only read-cache-invalidate bit(s) set, must have a CS_STALL bit set."
  67  *
  68  * Note that the kernel does CS stalls between batches, so we only need
  69  * to count them within a batch.
  70  */
  71 static uint32_t
  72 gen7_cs_stall_every_four_pipe_controls(struct brw_context *brw, uint32_t flags)
  73 {
  74    if (brw->gen == 7 && !brw->is_haswell) {
  75       if (flags & PIPE_CONTROL_CS_STALL) {
  76          /* If we're doing a CS stall, reset the counter and carry on. */
  77          brw->pipe_controls_since_last_cs_stall = 0;
  78          return 0;
  79       }
  80
  81       /* If this is the fourth pipe control without a CS stall, do one now. */
  82       if (++brw->pipe_controls_since_last_cs_stall == 4) {
  83          brw->pipe_controls_since_last_cs_stall = 0;
  84          return PIPE_CONTROL_CS_STALL;
  85       }
  86    }
  87    return 0;
  88 }
  89
  90 /**
  91  * Emit a PIPE_CONTROL with various flushing flags.
  92  *
  93  * The caller is responsible for deciding what flags are appropriate for the
  94  * given generation.
  95  */
  96 void
  97 brw_emit_pipe_control_flush(struct brw_context *brw, uint32_t flags)
  98 {
  99    if (brw->gen >= 8) {
 100       gen8_add_cs_stall_workaround_bits(&flags);
 101
 102       BEGIN_BATCH(6);
 103       OUT_BATCH(_3DSTATE_PIPE_CONTROL | (6 - 2));
 104       OUT_BATCH(flags);
 105       OUT_BATCH(0);
 106       OUT_BATCH(0);
 107       OUT_BATCH(0);
 108       OUT_BATCH(0);
 109       ADVANCE_BATCH();
 110    } else if (brw->gen >= 6) {
 111       flags |= gen7_cs_stall_every_four_pipe_controls(brw, flags);
 112
 113       BEGIN_BATCH(5);
 114       OUT_BATCH(_3DSTATE_PIPE_CONTROL | (5 - 2));
 115       OUT_BATCH(flags);
 116       OUT_BATCH(0);
 117       OUT_BATCH(0);
 118       OUT_BATCH(0);
 119       ADVANCE_BATCH();
 120    } else {
 121       BEGIN_BATCH(4);
 122       OUT_BATCH(_3DSTATE_PIPE_CONTROL | flags | (4 - 2));
 123       OUT_BATCH(0);
 124       OUT_BATCH(0);
 125       OUT_BATCH(0);
 126       ADVANCE_BATCH();
 127    }
 128 }
 129
 130 /**
 131  * Emit a PIPE_CONTROL that writes to a buffer object.
 132  *
 133  * \p flags should contain one of the following items:
 134  *  - PIPE_CONTROL_WRITE_IMMEDIATE
 135  *  - PIPE_CONTROL_WRITE_TIMESTAMP
 136  *  - PIPE_CONTROL_WRITE_DEPTH_COUNT
 137  */
 138 void
 139 brw_emit_pipe_control_write(struct brw_context *brw, uint32_t flags,
 140                             drm_intel_bo *bo, uint32_t offset,
 141                             uint32_t imm_lower, uint32_t imm_upper)
 142 {
 143    if (brw->gen >= 8) {
 144       gen8_add_cs_stall_workaround_bits(&flags);
 145
 146       BEGIN_BATCH(6);
 147       OUT_BATCH(_3DSTATE_PIPE_CONTROL | (6 - 2));
 148       OUT_BATCH(flags);
 149       OUT_RELOC64(bo, I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION,
 150                   offset);
 151       OUT_BATCH(imm_lower);
 152       OUT_BATCH(imm_upper);
 153       ADVANCE_BATCH();
 154    } else if (brw->gen >= 6) {
 155       flags |= gen7_cs_stall_every_four_pipe_controls(brw, flags);
 156
 157       /* PPGTT/GGTT is selected by DW2 bit 2 on Sandybridge, but DW1 bit 24
 158        * on later platforms.  We always use PPGTT on Gen7+.
 159        */
 160       unsigned gen6_gtt = brw->gen == 6 ? PIPE_CONTROL_GLOBAL_GTT_WRITE : 0;
 161
 162       BEGIN_BATCH(5);
 163       OUT_BATCH(_3DSTATE_PIPE_CONTROL | (5 - 2));
 164       OUT_BATCH(flags);
 165       OUT_RELOC(bo, I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION,
 166                 gen6_gtt | offset);
 167       OUT_BATCH(imm_lower);
 168       OUT_BATCH(imm_upper);
 169       ADVANCE_BATCH();
 170    } else {
 171       BEGIN_BATCH(4);
 172       OUT_BATCH(_3DSTATE_PIPE_CONTROL | flags | (4 - 2));
 173       OUT_RELOC(bo, I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION,
 174                 PIPE_CONTROL_GLOBAL_GTT_WRITE | offset);
 175       OUT_BATCH(imm_lower);
 176       OUT_BATCH(imm_upper);
 177       ADVANCE_BATCH();
 178    }
 179 }
 180
 181 /**
 182  * Restriction [DevSNB, DevIVB]:
 183  *
 184  * Prior to changing Depth/Stencil Buffer state (i.e. any combination of
 185  * 3DSTATE_DEPTH_BUFFER, 3DSTATE_CLEAR_PARAMS, 3DSTATE_STENCIL_BUFFER,
 186  * 3DSTATE_HIER_DEPTH_BUFFER) SW must first issue a pipelined depth stall
 187  * (PIPE_CONTROL with Depth Stall bit set), followed by a pipelined depth
 188  * cache flush (PIPE_CONTROL with Depth Flush Bit set), followed by
 189  * another pipelined depth stall (PIPE_CONTROL with Depth Stall bit set),
 190  * unless SW can otherwise guarantee that the pipeline from WM onwards is
 191  * already flushed (e.g., via a preceding MI_FLUSH).
 192  */
 193 void
 194 brw_emit_depth_stall_flushes(struct brw_context *brw)
 195 {
 196    assert(brw->gen >= 6 && brw->gen <= 9);
 197
 198    /* Starting on BDW, these pipe controls are unnecessary.
 199     *
 200     *   WM HW will internally manage the draining pipe and flushing of the caches
 201     *   when this command is issued. The PIPE_CONTROL restrictions are removed.
 202     */
 203    if (brw->gen >= 8)
 204       return;
 205
 206    brw_emit_pipe_control_flush(brw, PIPE_CONTROL_DEPTH_STALL);
 207    brw_emit_pipe_control_flush(brw, PIPE_CONTROL_DEPTH_CACHE_FLUSH);
 208    brw_emit_pipe_control_flush(brw, PIPE_CONTROL_DEPTH_STALL);
 209 }
 210
 211 /**
 212  * From the Ivybridge PRM, Volume 2 Part 1, Section 3.2 (VS Stage Input):
 213  * "A PIPE_CONTROL with Post-Sync Operation set to 1h and a depth
 214  *  stall needs to be sent just prior to any 3DSTATE_VS, 3DSTATE_URB_VS,
 215  *  3DSTATE_CONSTANT_VS, 3DSTATE_BINDING_TABLE_POINTER_VS,
 216  *  3DSTATE_SAMPLER_STATE_POINTER_VS command.  Only one PIPE_CONTROL needs
 217  *  to be sent before any combination of VS associated 3DSTATE."
 218  */
 219 void
 220 gen7_emit_vs_workaround_flush(struct brw_context *brw)
 221 {
 222    assert(brw->gen == 7);
 223    brw_emit_pipe_control_write(brw,
 224                                PIPE_CONTROL_WRITE_IMMEDIATE
 225                                | PIPE_CONTROL_DEPTH_STALL,
 226                                brw->workaround_bo, 0,
 227                                0, 0);
 228 }
 229
 230
 231 /**
 232  * Emit a PIPE_CONTROL command for gen7 with the CS Stall bit set.
 233  */
 234 void
 235 gen7_emit_cs_stall_flush(struct brw_context *brw)
 236 {
 237    brw_emit_pipe_control_write(brw,
 238                                PIPE_CONTROL_CS_STALL
 239                                | PIPE_CONTROL_WRITE_IMMEDIATE,
 240                                brw->workaround_bo, 0,
 241                                0, 0);
 242 }
 243
 244
 245 /**
 246  * Emits a PIPE_CONTROL with a non-zero post-sync operation, for
 247  * implementing two workarounds on gen6.  From section 1.4.7.1
 248  * "PIPE_CONTROL" of the Sandy Bridge PRM volume 2 part 1:
 249  *
 250  * [DevSNB-C+{W/A}] Before any depth stall flush (including those
 251  * produced by non-pipelined state commands), software needs to first
 252  * send a PIPE_CONTROL with no bits set except Post-Sync Operation !=
 253  * 0.
 254  *
 255  * [Dev-SNB{W/A}]: Before a PIPE_CONTROL with Write Cache Flush Enable
 256  * =1, a PIPE_CONTROL with any non-zero post-sync-op is required.
 257  *
 258  * And the workaround for these two requires this workaround first:
 259  *
 260  * [Dev-SNB{W/A}]: Pipe-control with CS-stall bit set must be sent
 261  * BEFORE the pipe-control with a post-sync op and no write-cache
 262  * flushes.
 263  *
 264  * And this last workaround is tricky because of the requirements on
 265  * that bit.  From section 1.4.7.2.3 "Stall" of the Sandy Bridge PRM
 266  * volume 2 part 1:
 267  *
 268  *     "1 of the following must also be set:
 269  *      - Render Target Cache Flush Enable ([12] of DW1)
 270  *      - Depth Cache Flush Enable ([0] of DW1)
 271  *      - Stall at Pixel Scoreboard ([1] of DW1)
 272  *      - Depth Stall ([13] of DW1)
 273  *      - Post-Sync Operation ([13] of DW1)
 274  *      - Notify Enable ([8] of DW1)"
 275  *
 276  * The cache flushes require the workaround flush that triggered this
 277  * one, so we can't use it.  Depth stall would trigger the same.
 278  * Post-sync nonzero is what triggered this second workaround, so we
 279  * can't use that one either.  Notify enable is IRQs, which aren't
 280  * really our business.  That leaves only stall at scoreboard.
 281  */
 282 void
 283 brw_emit_post_sync_nonzero_flush(struct brw_context *brw)
 284 {
 285    brw_emit_pipe_control_flush(brw,
 286                                PIPE_CONTROL_CS_STALL |
 287                                PIPE_CONTROL_STALL_AT_SCOREBOARD);
 288
 289    brw_emit_pipe_control_write(brw, PIPE_CONTROL_WRITE_IMMEDIATE,
 290                                brw->workaround_bo, 0, 0, 0);
 291 }
 292
 293 /* Emit a pipelined flush to either flush render and texture cache for
 294  * reading from a FBO-drawn texture, or flush so that frontbuffer
 295  * render appears on the screen in DRI1.
 296  *
 297  * This is also used for the always_flush_cache driconf debug option.
 298  */
 299 void
 300 brw_emit_mi_flush(struct brw_context *brw)
 301 {
 302    if (brw->batch.ring == BLT_RING && brw->gen >= 6) {
 303       BEGIN_BATCH_BLT(4);
 304       OUT_BATCH(MI_FLUSH_DW);
 305       OUT_BATCH(0);
 306       OUT_BATCH(0);
 307       OUT_BATCH(0);
 308       ADVANCE_BATCH();
 309    } else {
 310       int flags = PIPE_CONTROL_NO_WRITE | PIPE_CONTROL_RENDER_TARGET_FLUSH;
 311       if (brw->gen >= 6) {
 312          if (brw->gen == 9) {
 313             /* Hardware workaround: SKL
 314              *
 315              * Emit Pipe Control with all bits set to zero before emitting
 316              * a Pipe Control with VF Cache Invalidate set.
 317              */
 318             brw_emit_pipe_control_flush(brw, 0);
 319          }
 320
 321          flags |= PIPE_CONTROL_INSTRUCTION_INVALIDATE |
 322                   PIPE_CONTROL_DEPTH_CACHE_FLUSH |
 323                   PIPE_CONTROL_VF_CACHE_INVALIDATE |
 324                   PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE |
 325                   PIPE_CONTROL_CS_STALL;
 326
 327          if (brw->gen == 6) {
 328             /* Hardware workaround: SNB B-Spec says:
 329              *
 330              * [Dev-SNB{W/A}]: Before a PIPE_CONTROL with Write Cache
 331              * Flush Enable =1, a PIPE_CONTROL with any non-zero
 332              * post-sync-op is required.
 333              */
 334             brw_emit_post_sync_nonzero_flush(brw);
 335          }
 336       }
 337       brw_emit_pipe_control_flush(brw, flags);
 338    }
 339
 340    brw_render_cache_set_clear(brw);
 341 }
 342
 343 int
 344 brw_init_pipe_control(struct brw_context *brw,
 345                       const struct brw_device_info *devinfo)
 346 {
 347    if (devinfo->gen < 6)
 348       return 0;
 349
 350    /* We can't just use brw_state_batch to get a chunk of space for
 351     * the gen6 workaround because it involves actually writing to
 352     * the buffer, and the kernel doesn't let us write to the batch.
 353     */
 354    brw->workaround_bo = drm_intel_bo_alloc(brw->bufmgr,
 355                                            "pipe_control workaround",
 356                                            4096, 4096);
 357    if (brw->workaround_bo == NULL)
 358       return -ENOMEM;
 359
 360    brw->pipe_controls_since_last_cs_stall = 0;
 361
 362    return 0;
 363 }
 364
 365 void
 366 brw_fini_pipe_control(struct brw_context *brw)
 367 {
 368    drm_intel_bo_unreference(brw->workaround_bo);
 369 }