2 * Copyright © 2010 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * Eric Anholt <eric@anholt.net>
30 #include "glsl/glsl_types.h"
31 #include "glsl/ir_optimization.h"
35 /** @file brw_fs_schedule_instructions.cpp
37 * List scheduling of FS instructions.
39 * The basic model of the list scheduler is to take a basic block,
40 * compute a DAG of the dependencies (RAW ordering with latency, WAW
41 * ordering with latency, WAR ordering), and make a list of the DAG heads.
42 * Heuristically pick a DAG head, then put all the children that are
43 * now DAG heads into the list of things to schedule.
45 * The heuristic is the important part. We're trying to be cheap,
46 * since actually computing the optimal scheduling is NP complete.
47 * What we do is track a "current clock". When we schedule a node, we
48 * update the earliest-unblocked clock time of its children, and
49 * increment the clock. Then, when trying to schedule, we just pick
50 * the earliest-unblocked instruction to schedule.
52 * Note that often there will be many things which could execute
53 * immediately, and there are a range of heuristic options to choose
54 * from in picking among those.
57 static bool debug
= false;
59 class instruction_scheduler
;
61 class schedule_node
: public exec_node
64 schedule_node(backend_instruction
*inst
, instruction_scheduler
*sched
);
65 void set_latency_gen4();
66 void set_latency_gen7(bool is_haswell
);
68 backend_instruction
*inst
;
69 schedule_node
**children
;
78 * Which iteration of pushing groups of children onto the candidates list
79 * this node was a part of.
81 unsigned cand_generation
;
84 * This is the sum of the instruction's latency plus the maximum delay of
85 * its children, or just the issue_time if it's a leaf node.
91 schedule_node::set_latency_gen4()
94 int math_latency
= 22;
96 switch (inst
->opcode
) {
97 case SHADER_OPCODE_RCP
:
98 this->latency
= 1 * chans
* math_latency
;
100 case SHADER_OPCODE_RSQ
:
101 this->latency
= 2 * chans
* math_latency
;
103 case SHADER_OPCODE_INT_QUOTIENT
:
104 case SHADER_OPCODE_SQRT
:
105 case SHADER_OPCODE_LOG2
:
106 /* full precision log. partial is 2. */
107 this->latency
= 3 * chans
* math_latency
;
109 case SHADER_OPCODE_INT_REMAINDER
:
110 case SHADER_OPCODE_EXP2
:
111 /* full precision. partial is 3, same throughput. */
112 this->latency
= 4 * chans
* math_latency
;
114 case SHADER_OPCODE_POW
:
115 this->latency
= 8 * chans
* math_latency
;
117 case SHADER_OPCODE_SIN
:
118 case SHADER_OPCODE_COS
:
119 /* minimum latency, max is 12 rounds. */
120 this->latency
= 5 * chans
* math_latency
;
129 schedule_node::set_latency_gen7(bool is_haswell
)
131 switch (inst
->opcode
) {
134 * (since the last two src operands are in different register banks):
135 * mad(8) g4<1>F g2.2<4,1,1>F.x g2<4,1,1>F.x g3.1<4,1,1>F.x { align16 WE_normal 1Q };
137 * 3 cycles on IVB, 4 on HSW
138 * (since the last two src operands are in the same register bank):
139 * mad(8) g4<1>F g2.2<4,1,1>F.x g2<4,1,1>F.x g2.1<4,1,1>F.x { align16 WE_normal 1Q };
141 * 18 cycles on IVB, 16 on HSW
142 * (since the last two src operands are in different register banks):
143 * mad(8) g4<1>F g2.2<4,1,1>F.x g2<4,1,1>F.x g3.1<4,1,1>F.x { align16 WE_normal 1Q };
144 * mov(8) null g4<4,5,1>F { align16 WE_normal 1Q };
146 * 20 cycles on IVB, 18 on HSW
147 * (since the last two src operands are in the same register bank):
148 * mad(8) g4<1>F g2.2<4,1,1>F.x g2<4,1,1>F.x g2.1<4,1,1>F.x { align16 WE_normal 1Q };
149 * mov(8) null g4<4,4,1>F { align16 WE_normal 1Q };
152 /* Our register allocator doesn't know about register banks, so use the
155 latency
= is_haswell
? 16 : 18;
160 * (since the last two src operands are in different register banks):
161 * lrp(8) g4<1>F g2.2<4,1,1>F.x g2<4,1,1>F.x g3.1<4,1,1>F.x { align16 WE_normal 1Q };
163 * 3 cycles on IVB, 4 on HSW
164 * (since the last two src operands are in the same register bank):
165 * lrp(8) g4<1>F g2.2<4,1,1>F.x g2<4,1,1>F.x g2.1<4,1,1>F.x { align16 WE_normal 1Q };
167 * 16 cycles on IVB, 14 on HSW
168 * (since the last two src operands are in different register banks):
169 * lrp(8) g4<1>F g2.2<4,1,1>F.x g2<4,1,1>F.x g3.1<4,1,1>F.x { align16 WE_normal 1Q };
170 * mov(8) null g4<4,4,1>F { align16 WE_normal 1Q };
173 * (since the last two src operands are in the same register bank):
174 * lrp(8) g4<1>F g2.2<4,1,1>F.x g2<4,1,1>F.x g2.1<4,1,1>F.x { align16 WE_normal 1Q };
175 * mov(8) null g4<4,4,1>F { align16 WE_normal 1Q };
178 /* Our register allocator doesn't know about register banks, so use the
184 case SHADER_OPCODE_RCP
:
185 case SHADER_OPCODE_RSQ
:
186 case SHADER_OPCODE_SQRT
:
187 case SHADER_OPCODE_LOG2
:
188 case SHADER_OPCODE_EXP2
:
189 case SHADER_OPCODE_SIN
:
190 case SHADER_OPCODE_COS
:
192 * math inv(8) g4<1>F g2<0,1,0>F null { align1 WE_normal 1Q };
195 * math inv(8) g4<1>F g2<0,1,0>F null { align1 WE_normal 1Q };
196 * mov(8) null g4<8,8,1>F { align1 WE_normal 1Q };
198 * Same for exp2, log2, rsq, sqrt, sin, cos.
200 latency
= is_haswell
? 14 : 16;
203 case SHADER_OPCODE_POW
:
205 * math pow(8) g4<1>F g2<0,1,0>F g2.1<0,1,0>F { align1 WE_normal 1Q };
208 * math pow(8) g4<1>F g2<0,1,0>F g2.1<0,1,0>F { align1 WE_normal 1Q };
209 * mov(8) null g4<8,8,1>F { align1 WE_normal 1Q };
211 latency
= is_haswell
? 22 : 24;
214 case SHADER_OPCODE_TEX
:
215 case SHADER_OPCODE_TXD
:
216 case SHADER_OPCODE_TXF
:
217 case SHADER_OPCODE_TXL
:
219 * mov(8) g115<1>F 0F { align1 WE_normal 1Q };
220 * mov(8) g114<1>F 0F { align1 WE_normal 1Q };
221 * send(8) g4<1>UW g114<8,8,1>F
222 * sampler (10, 0, 0, 1) mlen 2 rlen 4 { align1 WE_normal 1Q };
224 * 697 +/-49 cycles (min 610, n=26):
225 * mov(8) g115<1>F 0F { align1 WE_normal 1Q };
226 * mov(8) g114<1>F 0F { align1 WE_normal 1Q };
227 * send(8) g4<1>UW g114<8,8,1>F
228 * sampler (10, 0, 0, 1) mlen 2 rlen 4 { align1 WE_normal 1Q };
229 * mov(8) null g4<8,8,1>F { align1 WE_normal 1Q };
231 * So the latency on our first texture load of the batchbuffer takes
232 * ~700 cycles, since the caches are cold at that point.
234 * 840 +/- 92 cycles (min 720, n=25):
235 * mov(8) g115<1>F 0F { align1 WE_normal 1Q };
236 * mov(8) g114<1>F 0F { align1 WE_normal 1Q };
237 * send(8) g4<1>UW g114<8,8,1>F
238 * sampler (10, 0, 0, 1) mlen 2 rlen 4 { align1 WE_normal 1Q };
239 * mov(8) null g4<8,8,1>F { align1 WE_normal 1Q };
240 * send(8) g4<1>UW g114<8,8,1>F
241 * sampler (10, 0, 0, 1) mlen 2 rlen 4 { align1 WE_normal 1Q };
242 * mov(8) null g4<8,8,1>F { align1 WE_normal 1Q };
244 * On the second load, it takes just an extra ~140 cycles, and after
245 * accounting for the 14 cycles of the MOV's latency, that makes ~130.
247 * 683 +/- 49 cycles (min = 602, n=47):
248 * mov(8) g115<1>F 0F { align1 WE_normal 1Q };
249 * mov(8) g114<1>F 0F { align1 WE_normal 1Q };
250 * send(8) g4<1>UW g114<8,8,1>F
251 * sampler (10, 0, 0, 1) mlen 2 rlen 4 { align1 WE_normal 1Q };
252 * send(8) g50<1>UW g114<8,8,1>F
253 * sampler (10, 0, 0, 1) mlen 2 rlen 4 { align1 WE_normal 1Q };
254 * mov(8) null g4<8,8,1>F { align1 WE_normal 1Q };
256 * The unit appears to be pipelined, since this matches up with the
257 * cache-cold case, despite there being two loads here. If you replace
258 * the g4 in the MOV to null with g50, it's still 693 +/- 52 (n=39).
260 * So, take some number between the cache-hot 140 cycles and the
261 * cache-cold 700 cycles. No particular tuning was done on this.
263 * I haven't done significant testing of the non-TEX opcodes. TXL at
264 * least looked about the same as TEX.
269 case SHADER_OPCODE_TXS
:
270 /* Testing textureSize(sampler2D, 0), one load was 420 +/- 41
272 * mov(8) g114<1>UD 0D { align1 WE_normal 1Q };
273 * send(8) g6<1>UW g114<8,8,1>F
274 * sampler (10, 0, 10, 1) mlen 1 rlen 4 { align1 WE_normal 1Q };
275 * mov(16) g6<1>F g6<8,8,1>D { align1 WE_normal 1Q };
278 * Two loads was 535 +/- 30 cycles (n=19):
279 * mov(16) g114<1>UD 0D { align1 WE_normal 1H };
280 * send(16) g6<1>UW g114<8,8,1>F
281 * sampler (10, 0, 10, 2) mlen 2 rlen 8 { align1 WE_normal 1H };
282 * mov(16) g114<1>UD 0D { align1 WE_normal 1H };
283 * mov(16) g6<1>F g6<8,8,1>D { align1 WE_normal 1H };
284 * send(16) g8<1>UW g114<8,8,1>F
285 * sampler (10, 0, 10, 2) mlen 2 rlen 8 { align1 WE_normal 1H };
286 * mov(16) g8<1>F g8<8,8,1>D { align1 WE_normal 1H };
287 * add(16) g6<1>F g6<8,8,1>F g8<8,8,1>F { align1 WE_normal 1H };
289 * Since the only caches that should matter are just the
290 * instruction/state cache containing the surface state, assume that we
291 * always have hot caches.
296 case FS_OPCODE_VARYING_PULL_CONSTANT_LOAD
:
297 case FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD
:
298 case VS_OPCODE_PULL_CONSTANT_LOAD
:
299 /* testing using varying-index pull constants:
302 * mov(8) g4<1>D g2.1<0,1,0>F { align1 WE_normal 1Q };
303 * send(8) g4<1>F g4<8,8,1>D
304 * data (9, 2, 3) mlen 1 rlen 1 { align1 WE_normal 1Q };
307 * mov(8) g4<1>D g2.1<0,1,0>F { align1 WE_normal 1Q };
308 * send(8) g4<1>F g4<8,8,1>D
309 * data (9, 2, 3) mlen 1 rlen 1 { align1 WE_normal 1Q };
310 * mov(8) null g4<8,8,1>F { align1 WE_normal 1Q };
313 * mov(8) g4<1>D g2.1<0,1,0>F { align1 WE_normal 1Q };
314 * send(8) g4<1>F g4<8,8,1>D
315 * data (9, 2, 3) mlen 1 rlen 1 { align1 WE_normal 1Q };
316 * mov(8) null g4<8,8,1>F { align1 WE_normal 1Q };
317 * send(8) g4<1>F g4<8,8,1>D
318 * data (9, 2, 3) mlen 1 rlen 1 { align1 WE_normal 1Q };
319 * mov(8) null g4<8,8,1>F { align1 WE_normal 1Q };
321 * So, if it's cache-hot, it's about 140. If it's cache cold, it's
322 * about 460. We expect to mostly be cache hot, so pick something more
328 case SHADER_OPCODE_GEN7_SCRATCH_READ
:
329 /* Testing a load from offset 0, that had been previously written:
331 * send(8) g114<1>UW g0<8,8,1>F data (0, 0, 0) mlen 1 rlen 1 { align1 WE_normal 1Q };
332 * mov(8) null g114<8,8,1>F { align1 WE_normal 1Q };
334 * The cycles spent seemed to be grouped around 40-50 (as low as 38),
335 * then around 140. Presumably this is cache hit vs miss.
340 case SHADER_OPCODE_UNTYPED_ATOMIC
:
342 * mov(8) g112<1>ud 0x00000000ud { align1 WE_all 1Q };
343 * mov(1) g112.7<1>ud g1.7<0,1,0>ud { align1 WE_all };
344 * mov(8) g113<1>ud 0x00000000ud { align1 WE_normal 1Q };
345 * send(8) g4<1>ud g112<8,8,1>ud
346 * data (38, 5, 6) mlen 2 rlen 1 { align1 WE_normal 1Q };
348 * Running it 100 times as fragment shader on a 128x128 quad
349 * gives an average latency of 13867 cycles per atomic op,
350 * standard deviation 3%. Note that this is a rather
351 * pessimistic estimate, the actual latency in cases with few
352 * collisions between threads and favorable pipelining has been
353 * seen to be reduced by a factor of 100.
358 case SHADER_OPCODE_UNTYPED_SURFACE_READ
:
360 * mov(8) g112<1>UD 0x00000000UD { align1 WE_all 1Q };
361 * mov(1) g112.7<1>UD g1.7<0,1,0>UD { align1 WE_all };
362 * mov(8) g113<1>UD 0x00000000UD { align1 WE_normal 1Q };
363 * send(8) g4<1>UD g112<8,8,1>UD
364 * data (38, 6, 5) mlen 2 rlen 1 { align1 WE_normal 1Q };
366 * . [repeats 8 times]
368 * mov(8) g112<1>UD 0x00000000UD { align1 WE_all 1Q };
369 * mov(1) g112.7<1>UD g1.7<0,1,0>UD { align1 WE_all };
370 * mov(8) g113<1>UD 0x00000000UD { align1 WE_normal 1Q };
371 * send(8) g4<1>UD g112<8,8,1>UD
372 * data (38, 6, 5) mlen 2 rlen 1 { align1 WE_normal 1Q };
374 * Running it 100 times as fragment shader on a 128x128 quad
375 * gives an average latency of 583 cycles per surface read,
376 * standard deviation 0.9%.
378 latency
= is_haswell
? 300 : 600;
383 * mul(8) g4<1>F g2<0,1,0>F 0.5F { align1 WE_normal 1Q };
386 * mul(8) g4<1>F g2<0,1,0>F 0.5F { align1 WE_normal 1Q };
387 * mov(8) null g4<8,8,1>F { align1 WE_normal 1Q };
394 class instruction_scheduler
{
396 instruction_scheduler(backend_visitor
*v
, int grf_count
,
397 instruction_scheduler_mode mode
)
400 this->mem_ctx
= ralloc_context(NULL
);
401 this->grf_count
= grf_count
;
402 this->instructions
.make_empty();
403 this->instructions_to_schedule
= 0;
404 this->post_reg_alloc
= (mode
== SCHEDULE_POST
);
407 if (!post_reg_alloc
) {
408 this->remaining_grf_uses
= rzalloc_array(mem_ctx
, int, grf_count
);
409 this->grf_active
= rzalloc_array(mem_ctx
, bool, grf_count
);
411 this->remaining_grf_uses
= NULL
;
412 this->grf_active
= NULL
;
416 ~instruction_scheduler()
418 ralloc_free(this->mem_ctx
);
420 void add_barrier_deps(schedule_node
*n
);
421 void add_dep(schedule_node
*before
, schedule_node
*after
, int latency
);
422 void add_dep(schedule_node
*before
, schedule_node
*after
);
424 void run(exec_list
*instructions
);
425 void add_inst(backend_instruction
*inst
);
426 void compute_delay(schedule_node
*node
);
427 virtual void calculate_deps() = 0;
428 virtual schedule_node
*choose_instruction_to_schedule() = 0;
431 * Returns how many cycles it takes the instruction to issue.
433 * Instructions in gen hardware are handled one simd4 vector at a time,
434 * with 1 cycle per vector dispatched. Thus SIMD8 pixel shaders take 2
435 * cycles to dispatch and SIMD16 (compressed) instructions take 4.
437 virtual int issue_time(backend_instruction
*inst
) = 0;
439 virtual void count_remaining_grf_uses(backend_instruction
*inst
) = 0;
440 virtual void update_register_pressure(backend_instruction
*inst
) = 0;
441 virtual int get_register_pressure_benefit(backend_instruction
*inst
) = 0;
443 void schedule_instructions(backend_instruction
*next_block_header
);
448 int instructions_to_schedule
;
451 exec_list instructions
;
454 instruction_scheduler_mode mode
;
457 * Number of instructions left to schedule that reference each vgrf.
459 * Used so that we can prefer scheduling instructions that will end the
460 * live intervals of multiple variables, to reduce register pressure.
462 int *remaining_grf_uses
;
465 * Tracks whether each VGRF has had an instruction scheduled that uses it.
467 * This is used to estimate whether scheduling a new instruction will
468 * increase register pressure.
473 class fs_instruction_scheduler
: public instruction_scheduler
476 fs_instruction_scheduler(fs_visitor
*v
, int grf_count
,
477 instruction_scheduler_mode mode
);
478 void calculate_deps();
479 bool is_compressed(fs_inst
*inst
);
480 schedule_node
*choose_instruction_to_schedule();
481 int issue_time(backend_instruction
*inst
);
484 void count_remaining_grf_uses(backend_instruction
*inst
);
485 void update_register_pressure(backend_instruction
*inst
);
486 int get_register_pressure_benefit(backend_instruction
*inst
);
489 fs_instruction_scheduler::fs_instruction_scheduler(fs_visitor
*v
,
491 instruction_scheduler_mode mode
)
492 : instruction_scheduler(v
, grf_count
, mode
),
498 fs_instruction_scheduler::count_remaining_grf_uses(backend_instruction
*be
)
500 fs_inst
*inst
= (fs_inst
*)be
;
502 if (!remaining_grf_uses
)
505 if (inst
->dst
.file
== GRF
)
506 remaining_grf_uses
[inst
->dst
.reg
]++;
508 for (int i
= 0; i
< 3; i
++) {
509 if (inst
->src
[i
].file
!= GRF
)
512 remaining_grf_uses
[inst
->src
[i
].reg
]++;
517 fs_instruction_scheduler::update_register_pressure(backend_instruction
*be
)
519 fs_inst
*inst
= (fs_inst
*)be
;
521 if (!remaining_grf_uses
)
524 if (inst
->dst
.file
== GRF
) {
525 remaining_grf_uses
[inst
->dst
.reg
]--;
526 grf_active
[inst
->dst
.reg
] = true;
529 for (int i
= 0; i
< 3; i
++) {
530 if (inst
->src
[i
].file
== GRF
) {
531 remaining_grf_uses
[inst
->src
[i
].reg
]--;
532 grf_active
[inst
->src
[i
].reg
] = true;
538 fs_instruction_scheduler::get_register_pressure_benefit(backend_instruction
*be
)
540 fs_inst
*inst
= (fs_inst
*)be
;
543 if (inst
->dst
.file
== GRF
) {
544 if (remaining_grf_uses
[inst
->dst
.reg
] == 1)
545 benefit
+= v
->virtual_grf_sizes
[inst
->dst
.reg
];
546 if (!grf_active
[inst
->dst
.reg
])
547 benefit
-= v
->virtual_grf_sizes
[inst
->dst
.reg
];
550 for (int i
= 0; i
< 3; i
++) {
551 if (inst
->src
[i
].file
!= GRF
)
554 if (remaining_grf_uses
[inst
->src
[i
].reg
] == 1)
555 benefit
+= v
->virtual_grf_sizes
[inst
->src
[i
].reg
];
556 if (!grf_active
[inst
->src
[i
].reg
])
557 benefit
-= v
->virtual_grf_sizes
[inst
->src
[i
].reg
];
563 class vec4_instruction_scheduler
: public instruction_scheduler
566 vec4_instruction_scheduler(vec4_visitor
*v
, int grf_count
);
567 void calculate_deps();
568 schedule_node
*choose_instruction_to_schedule();
569 int issue_time(backend_instruction
*inst
);
572 void count_remaining_grf_uses(backend_instruction
*inst
);
573 void update_register_pressure(backend_instruction
*inst
);
574 int get_register_pressure_benefit(backend_instruction
*inst
);
577 vec4_instruction_scheduler::vec4_instruction_scheduler(vec4_visitor
*v
,
579 : instruction_scheduler(v
, grf_count
, SCHEDULE_POST
),
585 vec4_instruction_scheduler::count_remaining_grf_uses(backend_instruction
*be
)
590 vec4_instruction_scheduler::update_register_pressure(backend_instruction
*be
)
595 vec4_instruction_scheduler::get_register_pressure_benefit(backend_instruction
*be
)
600 schedule_node::schedule_node(backend_instruction
*inst
,
601 instruction_scheduler
*sched
)
603 struct brw_context
*brw
= sched
->bv
->brw
;
606 this->child_array_size
= 0;
607 this->children
= NULL
;
608 this->child_latency
= NULL
;
609 this->child_count
= 0;
610 this->parent_count
= 0;
611 this->unblocked_time
= 0;
612 this->cand_generation
= 0;
615 /* We can't measure Gen6 timings directly but expect them to be much
616 * closer to Gen7 than Gen4.
618 if (!sched
->post_reg_alloc
)
620 else if (brw
->gen
>= 6)
621 set_latency_gen7(brw
->is_haswell
);
627 instruction_scheduler::add_inst(backend_instruction
*inst
)
629 schedule_node
*n
= new(mem_ctx
) schedule_node(inst
, this);
631 assert(!inst
->is_head_sentinel());
632 assert(!inst
->is_tail_sentinel());
634 this->instructions_to_schedule
++;
637 instructions
.push_tail(n
);
640 /** Recursive computation of the delay member of a node. */
642 instruction_scheduler::compute_delay(schedule_node
*n
)
644 if (!n
->child_count
) {
645 n
->delay
= issue_time(n
->inst
);
647 for (int i
= 0; i
< n
->child_count
; i
++) {
648 if (!n
->children
[i
]->delay
)
649 compute_delay(n
->children
[i
]);
650 n
->delay
= MAX2(n
->delay
, n
->latency
+ n
->children
[i
]->delay
);
656 * Add a dependency between two instruction nodes.
658 * The @after node will be scheduled after @before. We will try to
659 * schedule it @latency cycles after @before, but no guarantees there.
662 instruction_scheduler::add_dep(schedule_node
*before
, schedule_node
*after
,
665 if (!before
|| !after
)
668 assert(before
!= after
);
670 for (int i
= 0; i
< before
->child_count
; i
++) {
671 if (before
->children
[i
] == after
) {
672 before
->child_latency
[i
] = MAX2(before
->child_latency
[i
], latency
);
677 if (before
->child_array_size
<= before
->child_count
) {
678 if (before
->child_array_size
< 16)
679 before
->child_array_size
= 16;
681 before
->child_array_size
*= 2;
683 before
->children
= reralloc(mem_ctx
, before
->children
,
685 before
->child_array_size
);
686 before
->child_latency
= reralloc(mem_ctx
, before
->child_latency
,
687 int, before
->child_array_size
);
690 before
->children
[before
->child_count
] = after
;
691 before
->child_latency
[before
->child_count
] = latency
;
692 before
->child_count
++;
693 after
->parent_count
++;
697 instruction_scheduler::add_dep(schedule_node
*before
, schedule_node
*after
)
702 add_dep(before
, after
, before
->latency
);
706 * Sometimes we really want this node to execute after everything that
707 * was before it and before everything that followed it. This adds
711 instruction_scheduler::add_barrier_deps(schedule_node
*n
)
713 schedule_node
*prev
= (schedule_node
*)n
->prev
;
714 schedule_node
*next
= (schedule_node
*)n
->next
;
717 while (!prev
->is_head_sentinel()) {
719 prev
= (schedule_node
*)prev
->prev
;
724 while (!next
->is_tail_sentinel()) {
726 next
= (schedule_node
*)next
->next
;
731 /* instruction scheduling needs to be aware of when an MRF write
732 * actually writes 2 MRFs.
735 fs_instruction_scheduler::is_compressed(fs_inst
*inst
)
737 return (v
->dispatch_width
== 16 &&
738 !inst
->force_uncompressed
&&
739 !inst
->force_sechalf
);
743 fs_instruction_scheduler::calculate_deps()
745 /* Pre-register-allocation, this tracks the last write per VGRF (so
746 * different reg_offsets within it can interfere when they shouldn't).
747 * After register allocation, reg_offsets are gone and we track individual
750 schedule_node
*last_grf_write
[grf_count
];
751 schedule_node
*last_mrf_write
[BRW_MAX_MRF
];
752 schedule_node
*last_conditional_mod
[2] = { NULL
, NULL
};
753 /* Fixed HW registers are assumed to be separate from the virtual
754 * GRFs, so they can be tracked separately. We don't really write
755 * to fixed GRFs much, so don't bother tracking them on a more
758 schedule_node
*last_fixed_grf_write
= NULL
;
759 int reg_width
= v
->dispatch_width
/ 8;
761 /* The last instruction always needs to still be the last
762 * instruction. Either it's flow control (IF, ELSE, ENDIF, DO,
763 * WHILE) and scheduling other things after it would disturb the
764 * basic block, or it's FB_WRITE and we should do a better job at
765 * dead code elimination anyway.
767 schedule_node
*last
= (schedule_node
*)instructions
.get_tail();
768 add_barrier_deps(last
);
770 memset(last_grf_write
, 0, sizeof(last_grf_write
));
771 memset(last_mrf_write
, 0, sizeof(last_mrf_write
));
773 /* top-to-bottom dependencies: RAW and WAW. */
774 foreach_list(node
, &instructions
) {
775 schedule_node
*n
= (schedule_node
*)node
;
776 fs_inst
*inst
= (fs_inst
*)n
->inst
;
778 if (inst
->opcode
== FS_OPCODE_PLACEHOLDER_HALT
||
779 inst
->has_side_effects())
782 /* read-after-write deps. */
783 for (int i
= 0; i
< 3; i
++) {
784 if (inst
->src
[i
].file
== GRF
) {
785 if (post_reg_alloc
) {
786 for (int r
= 0; r
< reg_width
* inst
->regs_read(v
, i
); r
++)
787 add_dep(last_grf_write
[inst
->src
[i
].reg
+ r
], n
);
789 add_dep(last_grf_write
[inst
->src
[i
].reg
], n
);
791 } else if (inst
->src
[i
].file
== HW_REG
&&
792 (inst
->src
[i
].fixed_hw_reg
.file
==
793 BRW_GENERAL_REGISTER_FILE
)) {
794 if (post_reg_alloc
) {
795 int size
= reg_width
;
796 if (inst
->src
[i
].fixed_hw_reg
.vstride
== BRW_VERTICAL_STRIDE_0
)
798 for (int r
= 0; r
< size
; r
++)
799 add_dep(last_grf_write
[inst
->src
[i
].fixed_hw_reg
.nr
+ r
], n
);
801 add_dep(last_fixed_grf_write
, n
);
803 } else if (inst
->src
[i
].file
!= BAD_FILE
&&
804 inst
->src
[i
].file
!= IMM
&&
805 inst
->src
[i
].file
!= UNIFORM
) {
806 assert(inst
->src
[i
].file
!= MRF
);
811 if (inst
->base_mrf
!= -1) {
812 for (int i
= 0; i
< inst
->mlen
; i
++) {
813 /* It looks like the MRF regs are released in the send
814 * instruction once it's sent, not when the result comes
817 add_dep(last_mrf_write
[inst
->base_mrf
+ i
], n
);
821 if (inst
->reads_flag()) {
822 add_dep(last_conditional_mod
[inst
->flag_subreg
], n
);
825 /* write-after-write deps. */
826 if (inst
->dst
.file
== GRF
) {
827 if (post_reg_alloc
) {
828 for (int r
= 0; r
< inst
->regs_written
* reg_width
; r
++) {
829 add_dep(last_grf_write
[inst
->dst
.reg
+ r
], n
);
830 last_grf_write
[inst
->dst
.reg
+ r
] = n
;
833 add_dep(last_grf_write
[inst
->dst
.reg
], n
);
834 last_grf_write
[inst
->dst
.reg
] = n
;
836 } else if (inst
->dst
.file
== MRF
) {
837 int reg
= inst
->dst
.reg
& ~BRW_MRF_COMPR4
;
839 add_dep(last_mrf_write
[reg
], n
);
840 last_mrf_write
[reg
] = n
;
841 if (is_compressed(inst
)) {
842 if (inst
->dst
.reg
& BRW_MRF_COMPR4
)
846 add_dep(last_mrf_write
[reg
], n
);
847 last_mrf_write
[reg
] = n
;
849 } else if (inst
->dst
.file
== HW_REG
&&
850 inst
->dst
.fixed_hw_reg
.file
== BRW_GENERAL_REGISTER_FILE
) {
851 if (post_reg_alloc
) {
852 for (int r
= 0; r
< reg_width
; r
++)
853 last_grf_write
[inst
->dst
.fixed_hw_reg
.nr
+ r
] = n
;
855 last_fixed_grf_write
= n
;
857 } else if (inst
->dst
.file
!= BAD_FILE
) {
861 if (inst
->mlen
> 0 && inst
->base_mrf
!= -1) {
862 for (int i
= 0; i
< v
->implied_mrf_writes(inst
); i
++) {
863 add_dep(last_mrf_write
[inst
->base_mrf
+ i
], n
);
864 last_mrf_write
[inst
->base_mrf
+ i
] = n
;
868 if (inst
->writes_flag()) {
869 add_dep(last_conditional_mod
[inst
->flag_subreg
], n
, 0);
870 last_conditional_mod
[inst
->flag_subreg
] = n
;
874 /* bottom-to-top dependencies: WAR */
875 memset(last_grf_write
, 0, sizeof(last_grf_write
));
876 memset(last_mrf_write
, 0, sizeof(last_mrf_write
));
877 memset(last_conditional_mod
, 0, sizeof(last_conditional_mod
));
878 last_fixed_grf_write
= NULL
;
882 for (node
= instructions
.get_tail(), prev
= node
->prev
;
883 !node
->is_head_sentinel();
884 node
= prev
, prev
= node
->prev
) {
885 schedule_node
*n
= (schedule_node
*)node
;
886 fs_inst
*inst
= (fs_inst
*)n
->inst
;
888 /* write-after-read deps. */
889 for (int i
= 0; i
< 3; i
++) {
890 if (inst
->src
[i
].file
== GRF
) {
891 if (post_reg_alloc
) {
892 for (int r
= 0; r
< reg_width
* inst
->regs_read(v
, i
); r
++)
893 add_dep(n
, last_grf_write
[inst
->src
[i
].reg
+ r
]);
895 add_dep(n
, last_grf_write
[inst
->src
[i
].reg
]);
897 } else if (inst
->src
[i
].file
== HW_REG
&&
898 (inst
->src
[i
].fixed_hw_reg
.file
==
899 BRW_GENERAL_REGISTER_FILE
)) {
900 if (post_reg_alloc
) {
901 int size
= reg_width
;
902 if (inst
->src
[i
].fixed_hw_reg
.vstride
== BRW_VERTICAL_STRIDE_0
)
904 for (int r
= 0; r
< size
; r
++)
905 add_dep(n
, last_grf_write
[inst
->src
[i
].fixed_hw_reg
.nr
+ r
]);
907 add_dep(n
, last_fixed_grf_write
);
909 } else if (inst
->src
[i
].file
!= BAD_FILE
&&
910 inst
->src
[i
].file
!= IMM
&&
911 inst
->src
[i
].file
!= UNIFORM
) {
912 assert(inst
->src
[i
].file
!= MRF
);
917 if (inst
->base_mrf
!= -1) {
918 for (int i
= 0; i
< inst
->mlen
; i
++) {
919 /* It looks like the MRF regs are released in the send
920 * instruction once it's sent, not when the result comes
923 add_dep(n
, last_mrf_write
[inst
->base_mrf
+ i
], 2);
927 if (inst
->reads_flag()) {
928 add_dep(n
, last_conditional_mod
[inst
->flag_subreg
]);
931 /* Update the things this instruction wrote, so earlier reads
932 * can mark this as WAR dependency.
934 if (inst
->dst
.file
== GRF
) {
935 if (post_reg_alloc
) {
936 for (int r
= 0; r
< inst
->regs_written
* reg_width
; r
++)
937 last_grf_write
[inst
->dst
.reg
+ r
] = n
;
939 last_grf_write
[inst
->dst
.reg
] = n
;
941 } else if (inst
->dst
.file
== MRF
) {
942 int reg
= inst
->dst
.reg
& ~BRW_MRF_COMPR4
;
944 last_mrf_write
[reg
] = n
;
946 if (is_compressed(inst
)) {
947 if (inst
->dst
.reg
& BRW_MRF_COMPR4
)
952 last_mrf_write
[reg
] = n
;
954 } else if (inst
->dst
.file
== HW_REG
&&
955 inst
->dst
.fixed_hw_reg
.file
== BRW_GENERAL_REGISTER_FILE
) {
956 if (post_reg_alloc
) {
957 for (int r
= 0; r
< reg_width
; r
++)
958 last_grf_write
[inst
->dst
.fixed_hw_reg
.nr
+ r
] = n
;
960 last_fixed_grf_write
= n
;
962 } else if (inst
->dst
.file
!= BAD_FILE
) {
966 if (inst
->mlen
> 0 && inst
->base_mrf
!= -1) {
967 for (int i
= 0; i
< v
->implied_mrf_writes(inst
); i
++) {
968 last_mrf_write
[inst
->base_mrf
+ i
] = n
;
972 if (inst
->writes_flag()) {
973 last_conditional_mod
[inst
->flag_subreg
] = n
;
979 vec4_instruction_scheduler::calculate_deps()
981 schedule_node
*last_grf_write
[grf_count
];
982 schedule_node
*last_mrf_write
[BRW_MAX_MRF
];
983 schedule_node
*last_conditional_mod
= NULL
;
984 /* Fixed HW registers are assumed to be separate from the virtual
985 * GRFs, so they can be tracked separately. We don't really write
986 * to fixed GRFs much, so don't bother tracking them on a more
989 schedule_node
*last_fixed_grf_write
= NULL
;
991 /* The last instruction always needs to still be the last instruction.
992 * Either it's flow control (IF, ELSE, ENDIF, DO, WHILE) and scheduling
993 * other things after it would disturb the basic block, or it's the EOT
994 * URB_WRITE and we should do a better job at dead code eliminating
995 * anything that could have been scheduled after it.
997 schedule_node
*last
= (schedule_node
*)instructions
.get_tail();
998 add_barrier_deps(last
);
1000 memset(last_grf_write
, 0, sizeof(last_grf_write
));
1001 memset(last_mrf_write
, 0, sizeof(last_mrf_write
));
1003 /* top-to-bottom dependencies: RAW and WAW. */
1004 foreach_list(node
, &instructions
) {
1005 schedule_node
*n
= (schedule_node
*)node
;
1006 vec4_instruction
*inst
= (vec4_instruction
*)n
->inst
;
1008 if (inst
->has_side_effects())
1009 add_barrier_deps(n
);
1011 /* read-after-write deps. */
1012 for (int i
= 0; i
< 3; i
++) {
1013 if (inst
->src
[i
].file
== GRF
) {
1014 add_dep(last_grf_write
[inst
->src
[i
].reg
], n
);
1015 } else if (inst
->src
[i
].file
== HW_REG
&&
1016 (inst
->src
[i
].fixed_hw_reg
.file
==
1017 BRW_GENERAL_REGISTER_FILE
)) {
1018 add_dep(last_fixed_grf_write
, n
);
1019 } else if (inst
->src
[i
].file
!= BAD_FILE
&&
1020 inst
->src
[i
].file
!= IMM
&&
1021 inst
->src
[i
].file
!= UNIFORM
) {
1022 /* No reads from MRF, and ATTR is already translated away */
1023 assert(inst
->src
[i
].file
!= MRF
&&
1024 inst
->src
[i
].file
!= ATTR
);
1025 add_barrier_deps(n
);
1029 for (int i
= 0; i
< inst
->mlen
; i
++) {
1030 /* It looks like the MRF regs are released in the send
1031 * instruction once it's sent, not when the result comes
1034 add_dep(last_mrf_write
[inst
->base_mrf
+ i
], n
);
1037 if (inst
->depends_on_flags()) {
1038 assert(last_conditional_mod
);
1039 add_dep(last_conditional_mod
, n
);
1042 /* write-after-write deps. */
1043 if (inst
->dst
.file
== GRF
) {
1044 add_dep(last_grf_write
[inst
->dst
.reg
], n
);
1045 last_grf_write
[inst
->dst
.reg
] = n
;
1046 } else if (inst
->dst
.file
== MRF
) {
1047 add_dep(last_mrf_write
[inst
->dst
.reg
], n
);
1048 last_mrf_write
[inst
->dst
.reg
] = n
;
1049 } else if (inst
->dst
.file
== HW_REG
&&
1050 inst
->dst
.fixed_hw_reg
.file
== BRW_GENERAL_REGISTER_FILE
) {
1051 last_fixed_grf_write
= n
;
1052 } else if (inst
->dst
.file
!= BAD_FILE
) {
1053 add_barrier_deps(n
);
1056 if (inst
->mlen
> 0) {
1057 for (int i
= 0; i
< v
->implied_mrf_writes(inst
); i
++) {
1058 add_dep(last_mrf_write
[inst
->base_mrf
+ i
], n
);
1059 last_mrf_write
[inst
->base_mrf
+ i
] = n
;
1063 if (inst
->conditional_mod
) {
1064 add_dep(last_conditional_mod
, n
, 0);
1065 last_conditional_mod
= n
;
1069 /* bottom-to-top dependencies: WAR */
1070 memset(last_grf_write
, 0, sizeof(last_grf_write
));
1071 memset(last_mrf_write
, 0, sizeof(last_mrf_write
));
1072 last_conditional_mod
= NULL
;
1073 last_fixed_grf_write
= NULL
;
1077 for (node
= instructions
.get_tail(), prev
= node
->prev
;
1078 !node
->is_head_sentinel();
1079 node
= prev
, prev
= node
->prev
) {
1080 schedule_node
*n
= (schedule_node
*)node
;
1081 vec4_instruction
*inst
= (vec4_instruction
*)n
->inst
;
1083 /* write-after-read deps. */
1084 for (int i
= 0; i
< 3; i
++) {
1085 if (inst
->src
[i
].file
== GRF
) {
1086 add_dep(n
, last_grf_write
[inst
->src
[i
].reg
]);
1087 } else if (inst
->src
[i
].file
== HW_REG
&&
1088 (inst
->src
[i
].fixed_hw_reg
.file
==
1089 BRW_GENERAL_REGISTER_FILE
)) {
1090 add_dep(n
, last_fixed_grf_write
);
1091 } else if (inst
->src
[i
].file
!= BAD_FILE
&&
1092 inst
->src
[i
].file
!= IMM
&&
1093 inst
->src
[i
].file
!= UNIFORM
) {
1094 assert(inst
->src
[i
].file
!= MRF
&&
1095 inst
->src
[i
].file
!= ATTR
);
1096 add_barrier_deps(n
);
1100 for (int i
= 0; i
< inst
->mlen
; i
++) {
1101 /* It looks like the MRF regs are released in the send
1102 * instruction once it's sent, not when the result comes
1105 add_dep(n
, last_mrf_write
[inst
->base_mrf
+ i
], 2);
1108 if (inst
->depends_on_flags()) {
1109 add_dep(n
, last_conditional_mod
);
1112 /* Update the things this instruction wrote, so earlier reads
1113 * can mark this as WAR dependency.
1115 if (inst
->dst
.file
== GRF
) {
1116 last_grf_write
[inst
->dst
.reg
] = n
;
1117 } else if (inst
->dst
.file
== MRF
) {
1118 last_mrf_write
[inst
->dst
.reg
] = n
;
1119 } else if (inst
->dst
.file
== HW_REG
&&
1120 inst
->dst
.fixed_hw_reg
.file
== BRW_GENERAL_REGISTER_FILE
) {
1121 last_fixed_grf_write
= n
;
1122 } else if (inst
->dst
.file
!= BAD_FILE
) {
1123 add_barrier_deps(n
);
1126 if (inst
->mlen
> 0) {
1127 for (int i
= 0; i
< v
->implied_mrf_writes(inst
); i
++) {
1128 last_mrf_write
[inst
->base_mrf
+ i
] = n
;
1132 if (inst
->conditional_mod
) {
1133 last_conditional_mod
= n
;
1139 fs_instruction_scheduler::choose_instruction_to_schedule()
1141 schedule_node
*chosen
= NULL
;
1143 if (mode
== SCHEDULE_PRE
|| mode
== SCHEDULE_POST
) {
1144 int chosen_time
= 0;
1146 /* Of the instructions ready to execute or the closest to
1147 * being ready, choose the oldest one.
1149 foreach_list(node
, &instructions
) {
1150 schedule_node
*n
= (schedule_node
*)node
;
1152 if (!chosen
|| n
->unblocked_time
< chosen_time
) {
1154 chosen_time
= n
->unblocked_time
;
1158 /* Before register allocation, we don't care about the latencies of
1159 * instructions. All we care about is reducing live intervals of
1160 * variables so that we can avoid register spilling, or get SIMD16
1161 * shaders which naturally do a better job of hiding instruction
1164 foreach_list(node
, &instructions
) {
1165 schedule_node
*n
= (schedule_node
*)node
;
1166 fs_inst
*inst
= (fs_inst
*)n
->inst
;
1173 /* Most important: If we can definitely reduce register pressure, do
1176 int register_pressure_benefit
= get_register_pressure_benefit(n
->inst
);
1177 int chosen_register_pressure_benefit
=
1178 get_register_pressure_benefit(chosen
->inst
);
1180 if (register_pressure_benefit
> 0 &&
1181 register_pressure_benefit
> chosen_register_pressure_benefit
) {
1184 } else if (chosen_register_pressure_benefit
> 0 &&
1185 (register_pressure_benefit
<
1186 chosen_register_pressure_benefit
)) {
1190 if (mode
== SCHEDULE_PRE_LIFO
) {
1191 /* Prefer instructions that recently became available for
1192 * scheduling. These are the things that are most likely to
1193 * (eventually) make a variable dead and reduce register pressure.
1194 * Typical register pressure estimates don't work for us because
1195 * most of our pressure comes from texturing, where no single
1196 * instruction to schedule will make a vec4 value dead.
1198 if (n
->cand_generation
> chosen
->cand_generation
) {
1201 } else if (n
->cand_generation
< chosen
->cand_generation
) {
1205 /* On MRF-using chips, prefer non-SEND instructions. If we don't
1206 * do this, then because we prefer instructions that just became
1207 * candidates, we'll end up in a pattern of scheduling a SEND,
1208 * then the MRFs for the next SEND, then the next SEND, then the
1209 * MRFs, etc., without ever consuming the results of a send.
1211 if (v
->brw
->gen
< 7) {
1212 fs_inst
*chosen_inst
= (fs_inst
*)chosen
->inst
;
1214 /* We use regs_written > 1 as our test for the kind of send
1215 * instruction to avoid -- only sends generate many regs, and a
1216 * single-result send is probably actually reducing register
1219 if (inst
->regs_written
<= 1 && chosen_inst
->regs_written
> 1) {
1222 } else if (inst
->regs_written
> chosen_inst
->regs_written
) {
1228 /* For instructions pushed on the cands list at the same time, prefer
1229 * the one with the highest delay to the end of the program. This is
1230 * most likely to have its values able to be consumed first (such as
1231 * for a large tree of lowered ubo loads, which appear reversed in
1232 * the instruction stream with respect to when they can be consumed).
1234 if (n
->delay
> chosen
->delay
) {
1237 } else if (n
->delay
< chosen
->delay
) {
1241 /* If all other metrics are equal, we prefer the first instruction in
1242 * the list (program execution).
1251 vec4_instruction_scheduler::choose_instruction_to_schedule()
1253 schedule_node
*chosen
= NULL
;
1254 int chosen_time
= 0;
1256 /* Of the instructions ready to execute or the closest to being ready,
1257 * choose the oldest one.
1259 foreach_list(node
, &instructions
) {
1260 schedule_node
*n
= (schedule_node
*)node
;
1262 if (!chosen
|| n
->unblocked_time
< chosen_time
) {
1264 chosen_time
= n
->unblocked_time
;
1272 fs_instruction_scheduler::issue_time(backend_instruction
*inst
)
1274 if (is_compressed((fs_inst
*)inst
))
1281 vec4_instruction_scheduler::issue_time(backend_instruction
*inst
)
1283 /* We always execute as two vec4s in parallel. */
1288 instruction_scheduler::schedule_instructions(backend_instruction
*next_block_header
)
1292 /* Remove non-DAG heads from the list. */
1293 foreach_list_safe(node
, &instructions
) {
1294 schedule_node
*n
= (schedule_node
*)node
;
1295 if (n
->parent_count
!= 0)
1299 unsigned cand_generation
= 1;
1300 while (!instructions
.is_empty()) {
1301 schedule_node
*chosen
= choose_instruction_to_schedule();
1303 /* Schedule this instruction. */
1306 next_block_header
->insert_before(chosen
->inst
);
1307 instructions_to_schedule
--;
1308 update_register_pressure(chosen
->inst
);
1310 /* Update the clock for how soon an instruction could start after the
1313 time
+= issue_time(chosen
->inst
);
1315 /* If we expected a delay for scheduling, then bump the clock to reflect
1316 * that as well. In reality, the hardware will switch to another
1317 * hyperthread and may not return to dispatching our thread for a while
1318 * even after we're unblocked.
1320 time
= MAX2(time
, chosen
->unblocked_time
);
1323 fprintf(stderr
, "clock %4d, scheduled: ", time
);
1324 bv
->dump_instruction(chosen
->inst
);
1327 /* Now that we've scheduled a new instruction, some of its
1328 * children can be promoted to the list of instructions ready to
1329 * be scheduled. Update the children's unblocked time for this
1330 * DAG edge as we do so.
1332 for (int i
= chosen
->child_count
- 1; i
>= 0; i
--) {
1333 schedule_node
*child
= chosen
->children
[i
];
1335 child
->unblocked_time
= MAX2(child
->unblocked_time
,
1336 time
+ chosen
->child_latency
[i
]);
1339 fprintf(stderr
, "\tchild %d, %d parents: ", i
, child
->parent_count
);
1340 bv
->dump_instruction(child
->inst
);
1343 child
->cand_generation
= cand_generation
;
1344 child
->parent_count
--;
1345 if (child
->parent_count
== 0) {
1347 fprintf(stderr
, "\t\tnow available\n");
1349 instructions
.push_head(child
);
1354 /* Shared resource: the mathbox. There's one mathbox per EU on Gen6+
1355 * but it's more limited pre-gen6, so if we send something off to it then
1356 * the next math instruction isn't going to make progress until the first
1359 if (chosen
->inst
->is_math()) {
1360 foreach_list(node
, &instructions
) {
1361 schedule_node
*n
= (schedule_node
*)node
;
1363 if (n
->inst
->is_math())
1364 n
->unblocked_time
= MAX2(n
->unblocked_time
,
1365 time
+ chosen
->latency
);
1370 assert(instructions_to_schedule
== 0);
1374 instruction_scheduler::run(exec_list
*all_instructions
)
1376 backend_instruction
*next_block_header
=
1377 (backend_instruction
*)all_instructions
->head
;
1380 fprintf(stderr
, "\nInstructions before scheduling (reg_alloc %d)\n",
1382 bv
->dump_instructions();
1385 /* Populate the remaining GRF uses array to improve the pre-regalloc
1388 if (remaining_grf_uses
) {
1389 foreach_list(node
, all_instructions
) {
1390 count_remaining_grf_uses((backend_instruction
*)node
);
1394 while (!next_block_header
->is_tail_sentinel()) {
1395 /* Add things to be scheduled until we get to a new BB. */
1396 while (!next_block_header
->is_tail_sentinel()) {
1397 backend_instruction
*inst
= next_block_header
;
1398 next_block_header
= (backend_instruction
*)next_block_header
->next
;
1401 if (inst
->is_control_flow())
1406 foreach_list(node
, &instructions
) {
1407 schedule_node
*n
= (schedule_node
*)node
;
1411 schedule_instructions(next_block_header
);
1415 fprintf(stderr
, "\nInstructions after scheduling (reg_alloc %d)\n",
1417 bv
->dump_instructions();
1422 fs_visitor::schedule_instructions(instruction_scheduler_mode mode
)
1425 if (mode
== SCHEDULE_POST
)
1426 grf_count
= grf_used
;
1428 grf_count
= virtual_grf_count
;
1430 fs_instruction_scheduler
sched(this, grf_count
, mode
);
1431 sched
.run(&instructions
);
1433 if (unlikely(INTEL_DEBUG
& DEBUG_WM
) && mode
== SCHEDULE_POST
) {
1434 fprintf(stderr
, "fs%d estimated execution time: %d cycles\n",
1435 dispatch_width
, sched
.time
);
1438 invalidate_live_intervals();
1442 vec4_visitor::opt_schedule_instructions()
1444 vec4_instruction_scheduler
sched(this, prog_data
->total_grf
);
1445 sched
.run(&instructions
);
1447 if (unlikely(debug_flag
)) {
1448 fprintf(stderr
, "vec4 estimated execution time: %d cycles\n", sched
.time
);
1451 invalidate_live_intervals();