src/mesa/drivers/dri/i965/brw_state_upload.c

   1 /*
   2  Copyright (C) Intel Corp.  2006.  All Rights Reserved.
   3  Intel funded Tungsten Graphics (http://www.tungstengraphics.com) to
   4  develop this 3D driver.
   5
   6  Permission is hereby granted, free of charge, to any person obtaining
   7  a copy of this software and associated documentation files (the
   8  "Software"), to deal in the Software without restriction, including
   9  without limitation the rights to use, copy, modify, merge, publish,
  10  distribute, sublicense, and/or sell copies of the Software, and to
  11  permit persons to whom the Software is furnished to do so, subject to
  12  the following conditions:
  13
  14  The above copyright notice and this permission notice (including the
  15  next paragraph) shall be included in all copies or substantial
  16  portions of the Software.
  17
  18  THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  19  EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  20  MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
  21  IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
  22  LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
  23  OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
  24  WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  25
  26  **********************************************************************/
  27  /*
  28   * Authors:
  29   *   Keith Whitwell <keith@tungstengraphics.com>
  30   */
  31
  32
  33
  34 #include "brw_context.h"
  35 #include "brw_state.h"
  36 #include "intel_batchbuffer.h"
  37 #include "intel_buffers.h"
  38
  39 /* This is used to initialize brw->state.atoms[].  We could use this
  40  * list directly except for a single atom, brw_constant_buffer, which
  41  * has a .dirty value which changes according to the parameters of the
  42  * current fragment and vertex programs, and so cannot be a static
  43  * value.
  44  */
  45 static const struct brw_tracked_state *gen4_atoms[] =
  46 {
  47    &brw_check_fallback,
  48
  49    &brw_wm_input_sizes,
  50    &brw_vs_prog,
  51    &brw_gs_prog,
  52    &brw_clip_prog,
  53    &brw_sf_prog,
  54    &brw_wm_prog,
  55
  56    /* Once all the programs are done, we know how large urb entry
  57     * sizes need to be and can decide if we need to change the urb
  58     * layout.
  59     */
  60    &brw_curbe_offsets,
  61    &brw_recalculate_urb_fence,
  62
  63    &brw_cc_vp,
  64    &brw_cc_unit,
  65
  66    &brw_vs_constants, /* Before vs_surfaces and constant_buffer */
  67    &brw_wm_constants, /* Before wm_surfaces and constant_buffer */
  68
  69    &brw_vs_surfaces,            /* must do before unit */
  70    &brw_wm_constant_surface,    /* must do before wm surfaces/bind bo */
  71    &brw_wm_surfaces,            /* must do before samplers and unit */
  72    &brw_wm_binding_table,
  73    &brw_wm_samplers,
  74
  75    &brw_wm_unit,
  76    &brw_sf_vp,
  77    &brw_sf_unit,
  78    &brw_vs_unit,                /* always required, enabled or not */
  79    &brw_clip_unit,
  80    &brw_gs_unit,
  81
  82    /* Command packets:
  83     */
  84    &brw_invarient_state,
  85    &brw_state_base_address,
  86
  87    &brw_binding_table_pointers,
  88    &brw_blend_constant_color,
  89
  90    &brw_depthbuffer,
  91
  92    &brw_polygon_stipple,
  93    &brw_polygon_stipple_offset,
  94
  95    &brw_line_stipple,
  96    &brw_aa_line_parameters,
  97
  98    &brw_psp_urb_cbs,
  99
 100    &brw_drawing_rect,
 101    &brw_indices,
 102    &brw_index_buffer,
 103    &brw_vertices,
 104
 105    &brw_constant_buffer
 106 };
 107
 108 static const struct brw_tracked_state *gen6_atoms[] =
 109 {
 110    &brw_check_fallback,
 111
 112    &brw_wm_input_sizes,
 113    &brw_vs_prog,
 114    &brw_gs_prog,
 115    &brw_wm_prog,
 116
 117    &gen6_clip_vp,
 118    &gen6_sf_vp,
 119
 120    /* Command packets: */
 121    &brw_invarient_state,
 122
 123    /* must do before binding table pointers, cc state ptrs */
 124    &brw_state_base_address,
 125
 126    &brw_cc_vp,
 127    &gen6_viewport_state,        /* must do after *_vp stages */
 128
 129    &gen6_urb,
 130    &gen6_blend_state,           /* must do before cc unit */
 131    &gen6_color_calc_state,      /* must do before cc unit */
 132    &gen6_depth_stencil_state,   /* must do before cc unit */
 133    &gen6_cc_state_pointers,
 134
 135    &brw_vs_constants, /* Before vs_surfaces and constant_buffer */
 136    &brw_wm_constants, /* Before wm_surfaces and constant_buffer */
 137    &gen6_vs_constants, /* Before vs_state */
 138    &gen6_wm_constants, /* Before wm_state */
 139
 140    &brw_vs_surfaces,            /* must do before unit */
 141    &brw_wm_constant_surface,    /* must do before wm surfaces/bind bo */
 142    &brw_wm_surfaces,            /* must do before samplers and unit */
 143    &brw_wm_binding_table,
 144
 145    &brw_wm_samplers,
 146    &gen6_sampler_state,
 147
 148    &gen6_vs_state,
 149    &gen6_gs_state,
 150    &gen6_clip_state,
 151    &gen6_sf_state,
 152    &gen6_wm_state,
 153
 154    &gen6_scissor_state,
 155
 156    &gen6_binding_table_pointers,
 157
 158    &brw_depthbuffer,
 159
 160    &brw_polygon_stipple,
 161    &brw_polygon_stipple_offset,
 162
 163    &brw_line_stipple,
 164    &brw_aa_line_parameters,
 165
 166    &brw_drawing_rect,
 167
 168    &brw_indices,
 169    &brw_index_buffer,
 170    &brw_vertices,
 171 };
 172
 173 const struct brw_tracked_state *gen7_atoms[] =
 174 {
 175    &brw_check_fallback,
 176
 177    &brw_wm_input_sizes,
 178    &brw_vs_prog,
 179    &brw_gs_prog,
 180    &brw_wm_prog,
 181
 182    /* Command packets: */
 183    &brw_invarient_state,
 184
 185    /* must do before binding table pointers, cc state ptrs */
 186    &brw_state_base_address,
 187
 188    &brw_cc_vp,
 189    &gen7_cc_viewport_state_pointer, /* must do after brw_cc_vp */
 190    &gen7_sf_clip_viewport,
 191
 192    &gen7_urb,
 193    &gen6_blend_state,           /* must do before cc unit */
 194    &gen6_color_calc_state,      /* must do before cc unit */
 195    &gen6_depth_stencil_state,   /* must do before cc unit */
 196    &gen7_blend_state_pointer,
 197    &gen7_cc_state_pointer,
 198    &gen7_depth_stencil_state_pointer,
 199
 200    &brw_vs_constants, /* Before vs_surfaces and constant_buffer */
 201    &brw_wm_constants, /* Before wm_surfaces and constant_buffer */
 202    &gen6_vs_constants, /* Before vs_state */
 203    &gen7_wm_constants, /* Before wm_state */
 204
 205    &brw_vs_surfaces,            /* must do before unit */
 206    &brw_wm_constant_surface,    /* must do before wm surfaces/bind bo */
 207    &brw_wm_surfaces,            /* must do before samplers and unit */
 208    &brw_wm_binding_table,
 209
 210    &brw_wm_samplers,
 211    &gen6_sampler_state,
 212
 213    &gen7_disable_stages,
 214    &gen7_vs_state,
 215    &gen7_clip_state,
 216    &gen7_sbe_state,
 217    &gen7_sf_state,
 218    &gen7_wm_state,
 219    &gen7_ps_state,
 220
 221    &gen6_scissor_state,
 222
 223    &brw_depthbuffer,
 224
 225    &brw_polygon_stipple,
 226    &brw_polygon_stipple_offset,
 227
 228    &brw_line_stipple,
 229    &brw_aa_line_parameters,
 230
 231    &brw_drawing_rect,
 232
 233    &brw_indices,
 234    &brw_index_buffer,
 235    &brw_vertices,
 236 };
 237
 238
 239 void brw_init_state( struct brw_context *brw )
 240 {
 241    const struct brw_tracked_state **atoms;
 242    int num_atoms;
 243
 244    brw_init_caches(brw);
 245
 246    if (brw->intel.gen >= 7) {
 247       atoms = gen7_atoms;
 248       num_atoms = ARRAY_SIZE(gen7_atoms);
 249    } else if (brw->intel.gen == 6) {
 250       atoms = gen6_atoms;
 251       num_atoms = ARRAY_SIZE(gen6_atoms);
 252    } else {
 253       atoms = gen4_atoms;
 254       num_atoms = ARRAY_SIZE(gen4_atoms);
 255    }
 256
 257    while (num_atoms--) {
 258       assert((*atoms)->dirty.mesa |
 259              (*atoms)->dirty.brw |
 260              (*atoms)->dirty.cache);
 261
 262       if ((*atoms)->prepare)
 263          brw->prepare_atoms[brw->num_prepare_atoms++] = **atoms;
 264       if ((*atoms)->emit)
 265          brw->emit_atoms[brw->num_emit_atoms++] = **atoms;
 266       atoms++;
 267    }
 268    assert(brw->num_emit_atoms <= ARRAY_SIZE(brw->emit_atoms));
 269    assert(brw->num_prepare_atoms <= ARRAY_SIZE(brw->prepare_atoms));
 270 }
 271
 272
 273 void brw_destroy_state( struct brw_context *brw )
 274 {
 275    brw_destroy_caches(brw);
 276 }
 277
 278 /***********************************************************************
 279  */
 280
 281 static GLuint check_state( const struct brw_state_flags *a,
 282                            const struct brw_state_flags *b )
 283 {
 284    return ((a->mesa & b->mesa) |
 285            (a->brw & b->brw) |
 286            (a->cache & b->cache)) != 0;
 287 }
 288
 289 static void accumulate_state( struct brw_state_flags *a,
 290                               const struct brw_state_flags *b )
 291 {
 292    a->mesa |= b->mesa;
 293    a->brw |= b->brw;
 294    a->cache |= b->cache;
 295 }
 296
 297
 298 static void xor_states( struct brw_state_flags *result,
 299                              const struct brw_state_flags *a,
 300                               const struct brw_state_flags *b )
 301 {
 302    result->mesa = a->mesa ^ b->mesa;
 303    result->brw = a->brw ^ b->brw;
 304    result->cache = a->cache ^ b->cache;
 305 }
 306
 307 void
 308 brw_clear_validated_bos(struct brw_context *brw)
 309 {
 310    int i;
 311
 312    /* Clear the last round of validated bos */
 313    for (i = 0; i < brw->state.validated_bo_count; i++) {
 314       drm_intel_bo_unreference(brw->state.validated_bos[i]);
 315       brw->state.validated_bos[i] = NULL;
 316    }
 317    brw->state.validated_bo_count = 0;
 318 }
 319
 320 struct dirty_bit_map {
 321    uint32_t bit;
 322    char *name;
 323    uint32_t count;
 324 };
 325
 326 #define DEFINE_BIT(name) {name, #name, 0}
 327
 328 static struct dirty_bit_map mesa_bits[] = {
 329    DEFINE_BIT(_NEW_MODELVIEW),
 330    DEFINE_BIT(_NEW_PROJECTION),
 331    DEFINE_BIT(_NEW_TEXTURE_MATRIX),
 332    DEFINE_BIT(_NEW_COLOR),
 333    DEFINE_BIT(_NEW_DEPTH),
 334    DEFINE_BIT(_NEW_EVAL),
 335    DEFINE_BIT(_NEW_FOG),
 336    DEFINE_BIT(_NEW_HINT),
 337    DEFINE_BIT(_NEW_LIGHT),
 338    DEFINE_BIT(_NEW_LINE),
 339    DEFINE_BIT(_NEW_PIXEL),
 340    DEFINE_BIT(_NEW_POINT),
 341    DEFINE_BIT(_NEW_POLYGON),
 342    DEFINE_BIT(_NEW_POLYGONSTIPPLE),
 343    DEFINE_BIT(_NEW_SCISSOR),
 344    DEFINE_BIT(_NEW_STENCIL),
 345    DEFINE_BIT(_NEW_TEXTURE),
 346    DEFINE_BIT(_NEW_TRANSFORM),
 347    DEFINE_BIT(_NEW_VIEWPORT),
 348    DEFINE_BIT(_NEW_PACKUNPACK),
 349    DEFINE_BIT(_NEW_ARRAY),
 350    DEFINE_BIT(_NEW_RENDERMODE),
 351    DEFINE_BIT(_NEW_BUFFERS),
 352    DEFINE_BIT(_NEW_MULTISAMPLE),
 353    DEFINE_BIT(_NEW_TRACK_MATRIX),
 354    DEFINE_BIT(_NEW_PROGRAM),
 355    DEFINE_BIT(_NEW_PROGRAM_CONSTANTS),
 356    {0, 0, 0}
 357 };
 358
 359 static struct dirty_bit_map brw_bits[] = {
 360    DEFINE_BIT(BRW_NEW_URB_FENCE),
 361    DEFINE_BIT(BRW_NEW_FRAGMENT_PROGRAM),
 362    DEFINE_BIT(BRW_NEW_VERTEX_PROGRAM),
 363    DEFINE_BIT(BRW_NEW_INPUT_DIMENSIONS),
 364    DEFINE_BIT(BRW_NEW_CURBE_OFFSETS),
 365    DEFINE_BIT(BRW_NEW_REDUCED_PRIMITIVE),
 366    DEFINE_BIT(BRW_NEW_PRIMITIVE),
 367    DEFINE_BIT(BRW_NEW_CONTEXT),
 368    DEFINE_BIT(BRW_NEW_WM_INPUT_DIMENSIONS),
 369    DEFINE_BIT(BRW_NEW_PSP),
 370    DEFINE_BIT(BRW_NEW_WM_SURFACES),
 371    DEFINE_BIT(BRW_NEW_INDICES),
 372    DEFINE_BIT(BRW_NEW_INDEX_BUFFER),
 373    DEFINE_BIT(BRW_NEW_VERTICES),
 374    DEFINE_BIT(BRW_NEW_BATCH),
 375    DEFINE_BIT(BRW_NEW_DEPTH_BUFFER),
 376    DEFINE_BIT(BRW_NEW_NR_WM_SURFACES),
 377    DEFINE_BIT(BRW_NEW_NR_VS_SURFACES),
 378    DEFINE_BIT(BRW_NEW_VS_CONSTBUF),
 379    DEFINE_BIT(BRW_NEW_WM_CONSTBUF),
 380    DEFINE_BIT(BRW_NEW_VS_BINDING_TABLE),
 381    DEFINE_BIT(BRW_NEW_GS_BINDING_TABLE),
 382    DEFINE_BIT(BRW_NEW_PS_BINDING_TABLE),
 383    {0, 0, 0}
 384 };
 385
 386 static struct dirty_bit_map cache_bits[] = {
 387    DEFINE_BIT(CACHE_NEW_BLEND_STATE),
 388    DEFINE_BIT(CACHE_NEW_CC_VP),
 389    DEFINE_BIT(CACHE_NEW_CC_UNIT),
 390    DEFINE_BIT(CACHE_NEW_WM_PROG),
 391    DEFINE_BIT(CACHE_NEW_SAMPLER),
 392    DEFINE_BIT(CACHE_NEW_WM_UNIT),
 393    DEFINE_BIT(CACHE_NEW_SF_PROG),
 394    DEFINE_BIT(CACHE_NEW_SF_VP),
 395    DEFINE_BIT(CACHE_NEW_SF_UNIT),
 396    DEFINE_BIT(CACHE_NEW_VS_UNIT),
 397    DEFINE_BIT(CACHE_NEW_VS_PROG),
 398    DEFINE_BIT(CACHE_NEW_GS_UNIT),
 399    DEFINE_BIT(CACHE_NEW_GS_PROG),
 400    DEFINE_BIT(CACHE_NEW_CLIP_VP),
 401    DEFINE_BIT(CACHE_NEW_CLIP_UNIT),
 402    DEFINE_BIT(CACHE_NEW_CLIP_PROG),
 403    {0, 0, 0}
 404 };
 405
 406
 407 static void
 408 brw_update_dirty_count(struct dirty_bit_map *bit_map, int32_t bits)
 409 {
 410    int i;
 411
 412    for (i = 0; i < 32; i++) {
 413       if (bit_map[i].bit == 0)
 414          return;
 415
 416       if (bit_map[i].bit & bits)
 417          bit_map[i].count++;
 418    }
 419 }
 420
 421 static void
 422 brw_print_dirty_count(struct dirty_bit_map *bit_map, int32_t bits)
 423 {
 424    int i;
 425
 426    for (i = 0; i < 32; i++) {
 427       if (bit_map[i].bit == 0)
 428          return;
 429
 430       fprintf(stderr, "0x%08x: %12d (%s)\n",
 431               bit_map[i].bit, bit_map[i].count, bit_map[i].name);
 432    }
 433 }
 434
 435 /***********************************************************************
 436  * Emit all state:
 437  */
 438 void brw_validate_state( struct brw_context *brw )
 439 {
 440    struct gl_context *ctx = &brw->intel.ctx;
 441    struct intel_context *intel = &brw->intel;
 442    struct brw_state_flags *state = &brw->state.dirty;
 443    const struct brw_tracked_state *atoms = brw->prepare_atoms;
 444    int num_atoms = brw->num_prepare_atoms;
 445    GLuint i;
 446
 447    brw_clear_validated_bos(brw);
 448
 449    state->mesa |= brw->intel.NewGLState;
 450    brw->intel.NewGLState = 0;
 451
 452    brw_add_validated_bo(brw, intel->batch.bo);
 453
 454    if (brw->emit_state_always) {
 455       state->mesa |= ~0;
 456       state->brw |= ~0;
 457       state->cache |= ~0;
 458    }
 459
 460    if (brw->fragment_program != ctx->FragmentProgram._Current) {
 461       brw->fragment_program = ctx->FragmentProgram._Current;
 462       brw->state.dirty.brw |= BRW_NEW_FRAGMENT_PROGRAM;
 463    }
 464
 465    if (brw->vertex_program != ctx->VertexProgram._Current) {
 466       brw->vertex_program = ctx->VertexProgram._Current;
 467       brw->state.dirty.brw |= BRW_NEW_VERTEX_PROGRAM;
 468    }
 469
 470    if ((state->mesa | state->cache | state->brw) == 0)
 471       return;
 472
 473    brw->intel.Fallback = GL_FALSE; /* boolean, not bitfield */
 474
 475    /* do prepare stage for all atoms */
 476    for (i = 0; i < num_atoms; i++) {
 477       const struct brw_tracked_state *atom = &atoms[i];
 478
 479       if (check_state(state, &atom->dirty)) {
 480          atom->prepare(brw);
 481
 482          if (brw->intel.Fallback)
 483             break;
 484       }
 485    }
 486
 487    intel_check_front_buffer_rendering(intel);
 488
 489    /* Make sure that the textures which are referenced by the current
 490     * brw fragment program are actually present/valid.
 491     * If this fails, we can experience GPU lock-ups.
 492     */
 493    {
 494       const struct brw_fragment_program *fp;
 495       fp = brw_fragment_program_const(brw->fragment_program);
 496       if (fp) {
 497          assert((fp->tex_units_used & ctx->Texture._EnabledUnits)
 498                 == fp->tex_units_used);
 499       }
 500    }
 501 }
 502
 503
 504 void brw_upload_state(struct brw_context *brw)
 505 {
 506    struct brw_state_flags *state = &brw->state.dirty;
 507    const struct brw_tracked_state *atoms = brw->emit_atoms;
 508    int num_atoms = brw->num_emit_atoms;
 509    int i;
 510    static int dirty_count = 0;
 511
 512    brw_clear_validated_bos(brw);
 513
 514    if (unlikely(INTEL_DEBUG)) {
 515       /* Debug version which enforces various sanity checks on the
 516        * state flags which are generated and checked to help ensure
 517        * state atoms are ordered correctly in the list.
 518        */
 519       struct brw_state_flags examined, prev;
 520       memset(&examined, 0, sizeof(examined));
 521       prev = *state;
 522
 523       for (i = 0; i < num_atoms; i++) {
 524          const struct brw_tracked_state *atom = &atoms[i];
 525          struct brw_state_flags generated;
 526
 527          if (brw->intel.Fallback)
 528             break;
 529
 530          if (check_state(state, &atom->dirty)) {
 531             atom->emit(brw);
 532          }
 533
 534          accumulate_state(&examined, &atom->dirty);
 535
 536          /* generated = (prev ^ state)
 537           * if (examined & generated)
 538           *     fail;
 539           */
 540          xor_states(&generated, &prev, state);
 541          assert(!check_state(&examined, &generated));
 542          prev = *state;
 543       }
 544    }
 545    else {
 546       for (i = 0; i < num_atoms; i++) {
 547          const struct brw_tracked_state *atom = &atoms[i];
 548
 549          if (brw->intel.Fallback)
 550             break;
 551
 552          if (check_state(state, &atom->dirty)) {
 553             atom->emit(brw);
 554          }
 555       }
 556    }
 557
 558    if (unlikely(INTEL_DEBUG & DEBUG_STATE)) {
 559       brw_update_dirty_count(mesa_bits, state->mesa);
 560       brw_update_dirty_count(brw_bits, state->brw);
 561       brw_update_dirty_count(cache_bits, state->cache);
 562       if (dirty_count++ % 1000 == 0) {
 563          brw_print_dirty_count(mesa_bits, state->mesa);
 564          brw_print_dirty_count(brw_bits, state->brw);
 565          brw_print_dirty_count(cache_bits, state->cache);
 566          fprintf(stderr, "\n");
 567       }
 568    }
 569
 570    if (!brw->intel.Fallback)
 571       memset(state, 0, sizeof(*state));
 572 }