2 Copyright (C) Intel Corp. 2006. All Rights Reserved.
3 Intel funded Tungsten Graphics to
4 develop this 3D driver.
6 Permission is hereby granted, free of charge, to any person obtaining
7 a copy of this software and associated documentation files (the
8 "Software"), to deal in the Software without restriction, including
9 without limitation the rights to use, copy, modify, merge, publish,
10 distribute, sublicense, and/or sell copies of the Software, and to
11 permit persons to whom the Software is furnished to do so, subject to
12 the following conditions:
14 The above copyright notice and this permission notice (including the
15 next paragraph) shall be included in all copies or substantial
16 portions of the Software.
18 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
19 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
20 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
21 IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
22 LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
23 OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
24 WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
26 **********************************************************************/
29 * Keith Whitwell <keithw@vmware.com>
34 #include "brw_context.h"
35 #include "brw_defines.h"
36 #include "brw_state.h"
37 #include "brw_program.h"
38 #include "drivers/common/meta.h"
39 #include "intel_batchbuffer.h"
40 #include "intel_buffers.h"
42 #include "brw_ff_gs.h"
46 #include "main/framebuffer.h"
49 brw_upload_initial_gpu_state(struct brw_context
*brw
)
51 const struct gen_device_info
*devinfo
= &brw
->screen
->devinfo
;
53 /* On platforms with hardware contexts, we can set our initial GPU state
54 * right away rather than doing it via state atoms. This saves a small
55 * amount of overhead on every draw call.
60 if (devinfo
->gen
== 6)
61 brw_emit_post_sync_nonzero_flush(brw
);
63 brw_upload_invariant_state(brw
);
65 if (devinfo
->gen
== 9) {
66 /* Recommended optimizations for Victim Cache eviction and floating
70 OUT_BATCH(MI_LOAD_REGISTER_IMM
| (3 - 2));
71 OUT_BATCH(GEN7_CACHE_MODE_1
);
72 OUT_BATCH(REG_MASK(GEN9_FLOAT_BLEND_OPTIMIZATION_ENABLE
) |
73 REG_MASK(GEN9_PARTIAL_RESOLVE_DISABLE_IN_VC
) |
74 GEN9_FLOAT_BLEND_OPTIMIZATION_ENABLE
|
75 GEN9_PARTIAL_RESOLVE_DISABLE_IN_VC
);
78 if (brw
->is_broxton
) {
80 OUT_BATCH(MI_LOAD_REGISTER_IMM
| (3 - 2));
81 OUT_BATCH(GEN7_GT_MODE
);
82 OUT_BATCH(GEN9_SUBSLICE_HASHING_MASK_BITS
|
83 GEN9_SUBSLICE_HASHING_16x16
);
88 if (devinfo
->gen
>= 8) {
89 gen8_emit_3dstate_sample_pattern(brw
);
92 OUT_BATCH(_3DSTATE_WM_HZ_OP
<< 16 | (5 - 2));
100 OUT_BATCH(_3DSTATE_WM_CHROMAKEY
<< 16 | (2 - 2));
105 /* Set the "CONSTANT_BUFFER Address Offset Disable" bit, so
106 * 3DSTATE_CONSTANT_XS buffer 0 is an absolute address.
108 * On Gen6-7.5, we use an execbuf parameter to do this for us.
109 * However, the kernel ignores that when execlists are in use.
110 * Fortunately, we can just write the registers from userspace
111 * on Gen8+, and they're context saved/restored.
113 if (devinfo
->gen
>= 9) {
115 OUT_BATCH(MI_LOAD_REGISTER_IMM
| (3 - 2));
116 OUT_BATCH(CS_DEBUG_MODE2
);
117 OUT_BATCH(REG_MASK(CSDBG2_CONSTANT_BUFFER_ADDRESS_OFFSET_DISABLE
) |
118 CSDBG2_CONSTANT_BUFFER_ADDRESS_OFFSET_DISABLE
);
120 } else if (devinfo
->gen
== 8) {
122 OUT_BATCH(MI_LOAD_REGISTER_IMM
| (3 - 2));
124 OUT_BATCH(REG_MASK(INSTPM_CONSTANT_BUFFER_ADDRESS_OFFSET_DISABLE
) |
125 INSTPM_CONSTANT_BUFFER_ADDRESS_OFFSET_DISABLE
);
130 static inline const struct brw_tracked_state
*
131 brw_get_pipeline_atoms(struct brw_context
*brw
,
132 enum brw_pipeline pipeline
)
135 case BRW_RENDER_PIPELINE
:
136 return brw
->render_atoms
;
137 case BRW_COMPUTE_PIPELINE
:
138 return brw
->compute_atoms
;
140 STATIC_ASSERT(BRW_NUM_PIPELINES
== 2);
141 unreachable("Unsupported pipeline");
147 brw_copy_pipeline_atoms(struct brw_context
*brw
,
148 enum brw_pipeline pipeline
,
149 const struct brw_tracked_state
**atoms
,
152 /* This is to work around brw_context::atoms being declared const. We want
153 * it to be const, but it needs to be initialized somehow!
155 struct brw_tracked_state
*context_atoms
=
156 (struct brw_tracked_state
*) brw_get_pipeline_atoms(brw
, pipeline
);
158 for (int i
= 0; i
< num_atoms
; i
++) {
159 context_atoms
[i
] = *atoms
[i
];
160 assert(context_atoms
[i
].dirty
.mesa
| context_atoms
[i
].dirty
.brw
);
161 assert(context_atoms
[i
].emit
);
164 brw
->num_atoms
[pipeline
] = num_atoms
;
167 void brw_init_state( struct brw_context
*brw
)
169 struct gl_context
*ctx
= &brw
->ctx
;
170 const struct gen_device_info
*devinfo
= &brw
->screen
->devinfo
;
172 /* Force the first brw_select_pipeline to emit pipeline select */
173 brw
->last_pipeline
= BRW_NUM_PIPELINES
;
175 brw_init_caches(brw
);
177 if (devinfo
->gen
>= 10)
178 gen10_init_atoms(brw
);
179 else if (devinfo
->gen
>= 9)
180 gen9_init_atoms(brw
);
181 else if (devinfo
->gen
>= 8)
182 gen8_init_atoms(brw
);
183 else if (devinfo
->is_haswell
)
184 gen75_init_atoms(brw
);
185 else if (devinfo
->gen
>= 7)
186 gen7_init_atoms(brw
);
187 else if (devinfo
->gen
>= 6)
188 gen6_init_atoms(brw
);
189 else if (devinfo
->gen
>= 5)
190 gen5_init_atoms(brw
);
191 else if (devinfo
->is_g4x
)
192 gen45_init_atoms(brw
);
194 gen4_init_atoms(brw
);
196 brw_upload_initial_gpu_state(brw
);
198 brw
->NewGLState
= ~0;
199 brw
->ctx
.NewDriverState
= ~0ull;
201 /* ~0 is a nonsensical value which won't match anything we program, so
202 * the programming will take effect on the first time around.
204 brw
->pma_stall_bits
= ~0;
206 /* Make sure that brw->ctx.NewDriverState has enough bits to hold all possible
209 STATIC_ASSERT(BRW_NUM_STATE_BITS
<= 8 * sizeof(brw
->ctx
.NewDriverState
));
211 ctx
->DriverFlags
.NewTransformFeedback
= BRW_NEW_TRANSFORM_FEEDBACK
;
212 ctx
->DriverFlags
.NewTransformFeedbackProg
= BRW_NEW_TRANSFORM_FEEDBACK
;
213 ctx
->DriverFlags
.NewRasterizerDiscard
= BRW_NEW_RASTERIZER_DISCARD
;
214 ctx
->DriverFlags
.NewUniformBuffer
= BRW_NEW_UNIFORM_BUFFER
;
215 ctx
->DriverFlags
.NewShaderStorageBuffer
= BRW_NEW_UNIFORM_BUFFER
;
216 ctx
->DriverFlags
.NewTextureBuffer
= BRW_NEW_TEXTURE_BUFFER
;
217 ctx
->DriverFlags
.NewAtomicBuffer
= BRW_NEW_ATOMIC_BUFFER
;
218 ctx
->DriverFlags
.NewImageUnits
= BRW_NEW_IMAGE_UNITS
;
219 ctx
->DriverFlags
.NewDefaultTessLevels
= BRW_NEW_DEFAULT_TESS_LEVELS
;
220 ctx
->DriverFlags
.NewIntelConservativeRasterization
= BRW_NEW_CONSERVATIVE_RASTERIZATION
;
224 void brw_destroy_state( struct brw_context
*brw
)
226 brw_destroy_caches(brw
);
229 /***********************************************************************
233 check_state(const struct brw_state_flags
*a
, const struct brw_state_flags
*b
)
235 return ((a
->mesa
& b
->mesa
) | (a
->brw
& b
->brw
)) != 0;
238 static void accumulate_state( struct brw_state_flags
*a
,
239 const struct brw_state_flags
*b
)
246 static void xor_states( struct brw_state_flags
*result
,
247 const struct brw_state_flags
*a
,
248 const struct brw_state_flags
*b
)
250 result
->mesa
= a
->mesa
^ b
->mesa
;
251 result
->brw
= a
->brw
^ b
->brw
;
254 struct dirty_bit_map
{
260 #define DEFINE_BIT(name) {name, #name, 0}
262 static struct dirty_bit_map mesa_bits
[] = {
263 DEFINE_BIT(_NEW_MODELVIEW
),
264 DEFINE_BIT(_NEW_PROJECTION
),
265 DEFINE_BIT(_NEW_TEXTURE_MATRIX
),
266 DEFINE_BIT(_NEW_COLOR
),
267 DEFINE_BIT(_NEW_DEPTH
),
268 DEFINE_BIT(_NEW_EVAL
),
269 DEFINE_BIT(_NEW_FOG
),
270 DEFINE_BIT(_NEW_HINT
),
271 DEFINE_BIT(_NEW_LIGHT
),
272 DEFINE_BIT(_NEW_LINE
),
273 DEFINE_BIT(_NEW_PIXEL
),
274 DEFINE_BIT(_NEW_POINT
),
275 DEFINE_BIT(_NEW_POLYGON
),
276 DEFINE_BIT(_NEW_POLYGONSTIPPLE
),
277 DEFINE_BIT(_NEW_SCISSOR
),
278 DEFINE_BIT(_NEW_STENCIL
),
279 DEFINE_BIT(_NEW_TEXTURE_OBJECT
),
280 DEFINE_BIT(_NEW_TRANSFORM
),
281 DEFINE_BIT(_NEW_VIEWPORT
),
282 DEFINE_BIT(_NEW_TEXTURE_STATE
),
283 DEFINE_BIT(_NEW_ARRAY
),
284 DEFINE_BIT(_NEW_RENDERMODE
),
285 DEFINE_BIT(_NEW_BUFFERS
),
286 DEFINE_BIT(_NEW_CURRENT_ATTRIB
),
287 DEFINE_BIT(_NEW_MULTISAMPLE
),
288 DEFINE_BIT(_NEW_TRACK_MATRIX
),
289 DEFINE_BIT(_NEW_PROGRAM
),
290 DEFINE_BIT(_NEW_PROGRAM_CONSTANTS
),
291 DEFINE_BIT(_NEW_FRAG_CLAMP
),
292 /* Avoid sign extension problems. */
293 {(unsigned) _NEW_VARYING_VP_INPUTS
, "_NEW_VARYING_VP_INPUTS", 0},
297 static struct dirty_bit_map brw_bits
[] = {
298 DEFINE_BIT(BRW_NEW_FS_PROG_DATA
),
299 DEFINE_BIT(BRW_NEW_BLORP_BLIT_PROG_DATA
),
300 DEFINE_BIT(BRW_NEW_SF_PROG_DATA
),
301 DEFINE_BIT(BRW_NEW_VS_PROG_DATA
),
302 DEFINE_BIT(BRW_NEW_FF_GS_PROG_DATA
),
303 DEFINE_BIT(BRW_NEW_GS_PROG_DATA
),
304 DEFINE_BIT(BRW_NEW_TCS_PROG_DATA
),
305 DEFINE_BIT(BRW_NEW_TES_PROG_DATA
),
306 DEFINE_BIT(BRW_NEW_CLIP_PROG_DATA
),
307 DEFINE_BIT(BRW_NEW_CS_PROG_DATA
),
308 DEFINE_BIT(BRW_NEW_URB_FENCE
),
309 DEFINE_BIT(BRW_NEW_FRAGMENT_PROGRAM
),
310 DEFINE_BIT(BRW_NEW_GEOMETRY_PROGRAM
),
311 DEFINE_BIT(BRW_NEW_TESS_PROGRAMS
),
312 DEFINE_BIT(BRW_NEW_VERTEX_PROGRAM
),
313 DEFINE_BIT(BRW_NEW_REDUCED_PRIMITIVE
),
314 DEFINE_BIT(BRW_NEW_PATCH_PRIMITIVE
),
315 DEFINE_BIT(BRW_NEW_PRIMITIVE
),
316 DEFINE_BIT(BRW_NEW_CONTEXT
),
317 DEFINE_BIT(BRW_NEW_PSP
),
318 DEFINE_BIT(BRW_NEW_SURFACES
),
319 DEFINE_BIT(BRW_NEW_BINDING_TABLE_POINTERS
),
320 DEFINE_BIT(BRW_NEW_INDICES
),
321 DEFINE_BIT(BRW_NEW_VERTICES
),
322 DEFINE_BIT(BRW_NEW_DEFAULT_TESS_LEVELS
),
323 DEFINE_BIT(BRW_NEW_BATCH
),
324 DEFINE_BIT(BRW_NEW_INDEX_BUFFER
),
325 DEFINE_BIT(BRW_NEW_VS_CONSTBUF
),
326 DEFINE_BIT(BRW_NEW_TCS_CONSTBUF
),
327 DEFINE_BIT(BRW_NEW_TES_CONSTBUF
),
328 DEFINE_BIT(BRW_NEW_GS_CONSTBUF
),
329 DEFINE_BIT(BRW_NEW_PROGRAM_CACHE
),
330 DEFINE_BIT(BRW_NEW_STATE_BASE_ADDRESS
),
331 DEFINE_BIT(BRW_NEW_VUE_MAP_GEOM_OUT
),
332 DEFINE_BIT(BRW_NEW_TRANSFORM_FEEDBACK
),
333 DEFINE_BIT(BRW_NEW_RASTERIZER_DISCARD
),
334 DEFINE_BIT(BRW_NEW_STATS_WM
),
335 DEFINE_BIT(BRW_NEW_UNIFORM_BUFFER
),
336 DEFINE_BIT(BRW_NEW_ATOMIC_BUFFER
),
337 DEFINE_BIT(BRW_NEW_IMAGE_UNITS
),
338 DEFINE_BIT(BRW_NEW_META_IN_PROGRESS
),
339 DEFINE_BIT(BRW_NEW_PUSH_CONSTANT_ALLOCATION
),
340 DEFINE_BIT(BRW_NEW_NUM_SAMPLES
),
341 DEFINE_BIT(BRW_NEW_TEXTURE_BUFFER
),
342 DEFINE_BIT(BRW_NEW_GEN4_UNIT_STATE
),
343 DEFINE_BIT(BRW_NEW_CC_VP
),
344 DEFINE_BIT(BRW_NEW_SF_VP
),
345 DEFINE_BIT(BRW_NEW_CLIP_VP
),
346 DEFINE_BIT(BRW_NEW_SAMPLER_STATE_TABLE
),
347 DEFINE_BIT(BRW_NEW_VS_ATTRIB_WORKAROUNDS
),
348 DEFINE_BIT(BRW_NEW_COMPUTE_PROGRAM
),
349 DEFINE_BIT(BRW_NEW_CS_WORK_GROUPS
),
350 DEFINE_BIT(BRW_NEW_URB_SIZE
),
351 DEFINE_BIT(BRW_NEW_CC_STATE
),
352 DEFINE_BIT(BRW_NEW_BLORP
),
353 DEFINE_BIT(BRW_NEW_VIEWPORT_COUNT
),
354 DEFINE_BIT(BRW_NEW_CONSERVATIVE_RASTERIZATION
),
355 DEFINE_BIT(BRW_NEW_DRAW_CALL
),
356 DEFINE_BIT(BRW_NEW_FAST_CLEAR_COLOR
),
361 brw_update_dirty_count(struct dirty_bit_map
*bit_map
, uint64_t bits
)
363 for (int i
= 0; bit_map
[i
].bit
!= 0; i
++) {
364 if (bit_map
[i
].bit
& bits
)
370 brw_print_dirty_count(struct dirty_bit_map
*bit_map
)
372 for (int i
= 0; bit_map
[i
].bit
!= 0; i
++) {
373 if (bit_map
[i
].count
> 1) {
374 fprintf(stderr
, "0x%016"PRIx64
": %12d (%s)\n",
375 bit_map
[i
].bit
, bit_map
[i
].count
, bit_map
[i
].name
);
381 brw_upload_tess_programs(struct brw_context
*brw
)
383 if (brw
->tess_eval_program
) {
384 brw_upload_tcs_prog(brw
);
385 brw_upload_tes_prog(brw
);
387 brw
->tcs
.base
.prog_data
= NULL
;
388 brw
->tes
.base
.prog_data
= NULL
;
393 brw_upload_programs(struct brw_context
*brw
,
394 enum brw_pipeline pipeline
)
396 struct gl_context
*ctx
= &brw
->ctx
;
397 const struct gen_device_info
*devinfo
= &brw
->screen
->devinfo
;
399 if (pipeline
== BRW_RENDER_PIPELINE
) {
400 brw_upload_vs_prog(brw
);
401 brw_upload_tess_programs(brw
);
403 if (devinfo
->gen
< 6)
404 brw_upload_ff_gs_prog(brw
);
406 brw_upload_gs_prog(brw
);
408 /* Update the VUE map for data exiting the GS stage of the pipeline.
409 * This comes from the last enabled shader stage.
411 GLbitfield64 old_slots
= brw
->vue_map_geom_out
.slots_valid
;
412 bool old_separate
= brw
->vue_map_geom_out
.separate
;
413 struct brw_vue_prog_data
*vue_prog_data
;
414 if (brw
->geometry_program
)
415 vue_prog_data
= brw_vue_prog_data(brw
->gs
.base
.prog_data
);
416 else if (brw
->tess_eval_program
)
417 vue_prog_data
= brw_vue_prog_data(brw
->tes
.base
.prog_data
);
419 vue_prog_data
= brw_vue_prog_data(brw
->vs
.base
.prog_data
);
421 brw
->vue_map_geom_out
= vue_prog_data
->vue_map
;
423 /* If the layout has changed, signal BRW_NEW_VUE_MAP_GEOM_OUT. */
424 if (old_slots
!= brw
->vue_map_geom_out
.slots_valid
||
425 old_separate
!= brw
->vue_map_geom_out
.separate
)
426 brw
->ctx
.NewDriverState
|= BRW_NEW_VUE_MAP_GEOM_OUT
;
428 if ((old_slots
^ brw
->vue_map_geom_out
.slots_valid
) &
429 VARYING_BIT_VIEWPORT
) {
430 ctx
->NewDriverState
|= BRW_NEW_VIEWPORT_COUNT
;
431 brw
->clip
.viewport_count
=
432 (brw
->vue_map_geom_out
.slots_valid
& VARYING_BIT_VIEWPORT
) ?
433 ctx
->Const
.MaxViewports
: 1;
436 brw_upload_wm_prog(brw
);
438 if (devinfo
->gen
< 6) {
439 brw_upload_clip_prog(brw
);
440 brw_upload_sf_prog(brw
);
442 } else if (pipeline
== BRW_COMPUTE_PIPELINE
) {
443 brw_upload_cs_prog(brw
);
448 merge_ctx_state(struct brw_context
*brw
,
449 struct brw_state_flags
*state
)
451 state
->mesa
|= brw
->NewGLState
;
452 state
->brw
|= brw
->ctx
.NewDriverState
;
455 static ALWAYS_INLINE
void
456 check_and_emit_atom(struct brw_context
*brw
,
457 struct brw_state_flags
*state
,
458 const struct brw_tracked_state
*atom
)
460 if (check_state(state
, &atom
->dirty
)) {
462 merge_ctx_state(brw
, state
);
467 brw_upload_pipeline_state(struct brw_context
*brw
,
468 enum brw_pipeline pipeline
)
470 const struct gen_device_info
*devinfo
= &brw
->screen
->devinfo
;
471 struct gl_context
*ctx
= &brw
->ctx
;
473 static int dirty_count
= 0;
474 struct brw_state_flags state
= brw
->state
.pipelines
[pipeline
];
475 const unsigned fb_samples
=
476 MAX2(_mesa_geometric_samples(ctx
->DrawBuffer
), 1);
478 brw_select_pipeline(brw
, pipeline
);
481 /* Always re-emit all state. */
482 brw
->NewGLState
= ~0;
483 ctx
->NewDriverState
= ~0ull;
486 if (pipeline
== BRW_RENDER_PIPELINE
) {
487 if (brw
->fragment_program
!= ctx
->FragmentProgram
._Current
) {
488 brw
->fragment_program
= ctx
->FragmentProgram
._Current
;
489 brw
->ctx
.NewDriverState
|= BRW_NEW_FRAGMENT_PROGRAM
;
492 if (brw
->tess_eval_program
!= ctx
->TessEvalProgram
._Current
) {
493 brw
->tess_eval_program
= ctx
->TessEvalProgram
._Current
;
494 brw
->ctx
.NewDriverState
|= BRW_NEW_TESS_PROGRAMS
;
497 if (brw
->tess_ctrl_program
!= ctx
->TessCtrlProgram
._Current
) {
498 brw
->tess_ctrl_program
= ctx
->TessCtrlProgram
._Current
;
499 brw
->ctx
.NewDriverState
|= BRW_NEW_TESS_PROGRAMS
;
502 if (brw
->geometry_program
!= ctx
->GeometryProgram
._Current
) {
503 brw
->geometry_program
= ctx
->GeometryProgram
._Current
;
504 brw
->ctx
.NewDriverState
|= BRW_NEW_GEOMETRY_PROGRAM
;
507 if (brw
->vertex_program
!= ctx
->VertexProgram
._Current
) {
508 brw
->vertex_program
= ctx
->VertexProgram
._Current
;
509 brw
->ctx
.NewDriverState
|= BRW_NEW_VERTEX_PROGRAM
;
513 if (brw
->compute_program
!= ctx
->ComputeProgram
._Current
) {
514 brw
->compute_program
= ctx
->ComputeProgram
._Current
;
515 brw
->ctx
.NewDriverState
|= BRW_NEW_COMPUTE_PROGRAM
;
518 if (brw
->meta_in_progress
!= _mesa_meta_in_progress(ctx
)) {
519 brw
->meta_in_progress
= _mesa_meta_in_progress(ctx
);
520 brw
->ctx
.NewDriverState
|= BRW_NEW_META_IN_PROGRESS
;
523 if (brw
->num_samples
!= fb_samples
) {
524 brw
->num_samples
= fb_samples
;
525 brw
->ctx
.NewDriverState
|= BRW_NEW_NUM_SAMPLES
;
528 /* Exit early if no state is flagged as dirty */
529 merge_ctx_state(brw
, &state
);
530 if ((state
.mesa
| state
.brw
) == 0)
533 /* Emit Sandybridge workaround flushes on every primitive, for safety. */
534 if (devinfo
->gen
== 6)
535 brw_emit_post_sync_nonzero_flush(brw
);
537 brw_upload_programs(brw
, pipeline
);
538 merge_ctx_state(brw
, &state
);
540 brw_upload_state_base_address(brw
);
542 const struct brw_tracked_state
*atoms
=
543 brw_get_pipeline_atoms(brw
, pipeline
);
544 const int num_atoms
= brw
->num_atoms
[pipeline
];
546 if (unlikely(INTEL_DEBUG
)) {
547 /* Debug version which enforces various sanity checks on the
548 * state flags which are generated and checked to help ensure
549 * state atoms are ordered correctly in the list.
551 struct brw_state_flags examined
, prev
;
552 memset(&examined
, 0, sizeof(examined
));
555 for (i
= 0; i
< num_atoms
; i
++) {
556 const struct brw_tracked_state
*atom
= &atoms
[i
];
557 struct brw_state_flags generated
;
559 check_and_emit_atom(brw
, &state
, atom
);
561 accumulate_state(&examined
, &atom
->dirty
);
563 /* generated = (prev ^ state)
564 * if (examined & generated)
567 xor_states(&generated
, &prev
, &state
);
568 assert(!check_state(&examined
, &generated
));
573 for (i
= 0; i
< num_atoms
; i
++) {
574 const struct brw_tracked_state
*atom
= &atoms
[i
];
576 check_and_emit_atom(brw
, &state
, atom
);
580 if (unlikely(INTEL_DEBUG
& DEBUG_STATE
)) {
581 STATIC_ASSERT(ARRAY_SIZE(brw_bits
) == BRW_NUM_STATE_BITS
+ 1);
583 brw_update_dirty_count(mesa_bits
, state
.mesa
);
584 brw_update_dirty_count(brw_bits
, state
.brw
);
585 if (dirty_count
++ % 1000 == 0) {
586 brw_print_dirty_count(mesa_bits
);
587 brw_print_dirty_count(brw_bits
);
588 fprintf(stderr
, "\n");
593 /***********************************************************************
596 void brw_upload_render_state(struct brw_context
*brw
)
598 brw_upload_pipeline_state(brw
, BRW_RENDER_PIPELINE
);
602 brw_pipeline_state_finished(struct brw_context
*brw
,
603 enum brw_pipeline pipeline
)
605 /* Save all dirty state into the other pipelines */
606 for (unsigned i
= 0; i
< BRW_NUM_PIPELINES
; i
++) {
608 brw
->state
.pipelines
[i
].mesa
|= brw
->NewGLState
;
609 brw
->state
.pipelines
[i
].brw
|= brw
->ctx
.NewDriverState
;
611 memset(&brw
->state
.pipelines
[i
], 0, sizeof(struct brw_state_flags
));
616 brw
->ctx
.NewDriverState
= 0ull;
620 * Clear dirty bits to account for the fact that the state emitted by
621 * brw_upload_render_state() has been committed to the hardware. This is a
622 * separate call from brw_upload_render_state() because it's possible that
623 * after the call to brw_upload_render_state(), we will discover that we've
624 * run out of aperture space, and need to rewind the batch buffer to the state
625 * it had before the brw_upload_render_state() call.
628 brw_render_state_finished(struct brw_context
*brw
)
630 brw_pipeline_state_finished(brw
, BRW_RENDER_PIPELINE
);
634 brw_upload_compute_state(struct brw_context
*brw
)
636 brw_upload_pipeline_state(brw
, BRW_COMPUTE_PIPELINE
);
640 brw_compute_state_finished(struct brw_context
*brw
)
642 brw_pipeline_state_finished(brw
, BRW_COMPUTE_PIPELINE
);