2 * Copyright © 2011 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
28 #include "brw_shader.h"
29 #include "main/compiler.h"
30 #include "program/hash_table.h"
34 #include "brw_context.h"
45 swizzle_for_size(int size
);
48 ARF
= BRW_ARCHITECTURE_REGISTER_FILE
,
49 GRF
= BRW_GENERAL_REGISTER_FILE
,
50 MRF
= BRW_MESSAGE_REGISTER_FILE
,
51 IMM
= BRW_IMMEDIATE_VALUE
,
52 HW_REG
, /* a struct brw_reg */
54 UNIFORM
, /* prog_data->params[hw_reg] */
61 /** Register file: ARF, GRF, MRF, IMM. */
62 enum register_file file
;
63 /** virtual register number. 0 = fixed hw reg */
65 /** Offset within the virtual register. */
67 /** Register type. BRW_REGISTER_TYPE_* */
69 struct brw_reg fixed_hw_reg
;
71 /** Value for file == BRW_IMMMEDIATE_FILE */
79 class src_reg
: public reg
82 /* Callers of this ralloc-based new need not call delete. It's
83 * easier to just ralloc_free 'ctx' (or any of its ancestors). */
84 static void* operator new(size_t size
, void *ctx
)
88 node
= ralloc_size(ctx
, size
);
96 src_reg(register_file file
, int reg
, const glsl_type
*type
);
102 bool equals(src_reg
*r
);
103 bool is_zero() const;
106 src_reg(class vec4_visitor
*v
, const struct glsl_type
*type
);
108 explicit src_reg(dst_reg reg
);
110 GLuint swizzle
; /**< SWIZZLE_XYZW swizzles from Mesa. */
117 class dst_reg
: public reg
120 /* Callers of this ralloc-based new need not call delete. It's
121 * easier to just ralloc_free 'ctx' (or any of its ancestors). */
122 static void* operator new(size_t size
, void *ctx
)
126 node
= ralloc_size(ctx
, size
);
127 assert(node
!= NULL
);
135 dst_reg(register_file file
, int reg
);
136 dst_reg(register_file file
, int reg
, const glsl_type
*type
, int writemask
);
137 dst_reg(struct brw_reg reg
);
138 dst_reg(class vec4_visitor
*v
, const struct glsl_type
*type
);
140 explicit dst_reg(src_reg reg
);
142 int writemask
; /**< Bitfield of WRITEMASK_[XYZW] */
147 class vec4_instruction
: public backend_instruction
{
149 /* Callers of this ralloc-based new need not call delete. It's
150 * easier to just ralloc_free 'ctx' (or any of its ancestors). */
151 static void* operator new(size_t size
, void *ctx
)
155 node
= rzalloc_size(ctx
, size
);
156 assert(node
!= NULL
);
161 vec4_instruction(vec4_visitor
*v
, enum opcode opcode
,
162 dst_reg dst
= dst_reg(),
163 src_reg src0
= src_reg(),
164 src_reg src1
= src_reg(),
165 src_reg src2
= src_reg());
167 struct brw_reg
get_dst(void);
168 struct brw_reg
get_src(int i
);
175 int conditional_mod
; /**< BRW_CONDITIONAL_* */
178 uint32_t texture_offset
; /**< Texture Offset bitfield */
179 int target
; /**< MRT target. */
184 int mlen
; /**< SEND message length */
185 int base_mrf
; /**< First MRF in the SEND message, if mlen is nonzero. */
187 uint32_t offset
; /* spill/unspill offset */
189 * Annotation for the generated IR. One of the two can be set.
192 const char *annotation
;
198 class vec4_visitor
: public backend_visitor
201 vec4_visitor(struct brw_context
*brw
,
202 struct brw_vs_compile
*c
,
203 struct gl_shader_program
*prog
, struct brw_shader
*shader
);
208 return dst_reg(brw_null_reg());
213 return dst_reg(retype(brw_null_reg(), BRW_REGISTER_TYPE_D
));
216 const struct gl_vertex_program
*vp
;
217 struct brw_vs_compile
*c
;
218 struct brw_vs_prog_data
*prog_data
;
219 struct brw_compile
*p
;
225 * GLSL IR currently being processed, which is associated with our
226 * driver IR instructions for debugging purposes.
229 const char *current_annotation
;
231 int *virtual_grf_sizes
;
232 int virtual_grf_count
;
233 int virtual_grf_array_size
;
234 int first_non_payload_grf
;
235 unsigned int max_grf
;
236 int *virtual_grf_def
;
237 int *virtual_grf_use
;
238 dst_reg userplane
[MAX_CLIP_PLANES
];
240 src_reg
*vp_temp_regs
;
244 * This is the size to be used for an array with an element per
247 int virtual_grf_reg_count
;
248 /** Per-virtual-grf indices into an array of size virtual_grf_reg_count */
249 int *virtual_grf_reg_map
;
251 bool live_intervals_valid
;
253 dst_reg
*variable_storage(ir_variable
*var
);
255 void reladdr_to_temp(ir_instruction
*ir
, src_reg
*reg
, int *num_reladdr
);
257 bool need_all_constants_in_pull_buffer
;
260 * \name Visit methods
262 * As typical for the visitor pattern, there must be one \c visit method for
263 * each concrete subclass of \c ir_instruction. Virtual base classes within
264 * the hierarchy should not have \c visit methods.
267 virtual void visit(ir_variable
*);
268 virtual void visit(ir_loop
*);
269 virtual void visit(ir_loop_jump
*);
270 virtual void visit(ir_function_signature
*);
271 virtual void visit(ir_function
*);
272 virtual void visit(ir_expression
*);
273 virtual void visit(ir_swizzle
*);
274 virtual void visit(ir_dereference_variable
*);
275 virtual void visit(ir_dereference_array
*);
276 virtual void visit(ir_dereference_record
*);
277 virtual void visit(ir_assignment
*);
278 virtual void visit(ir_constant
*);
279 virtual void visit(ir_call
*);
280 virtual void visit(ir_return
*);
281 virtual void visit(ir_discard
*);
282 virtual void visit(ir_texture
*);
283 virtual void visit(ir_if
*);
288 /* Regs for vertex results. Generated at ir_variable visiting time
289 * for the ir->location's used.
291 dst_reg output_reg
[BRW_VERT_RESULT_MAX
];
292 const char *output_reg_annotation
[BRW_VERT_RESULT_MAX
];
293 int uniform_size
[MAX_UNIFORMS
];
294 int uniform_vector_size
[MAX_UNIFORMS
];
297 struct hash_table
*variable_ht
;
300 void fail(const char *msg
, ...);
302 int virtual_grf_alloc(int size
);
303 void setup_uniform_clipplane_values();
304 int setup_uniform_values(int loc
, const glsl_type
*type
);
305 void setup_builtin_uniform_values(ir_variable
*ir
);
306 int setup_attributes(int payload_reg
);
307 int setup_uniforms(int payload_reg
);
308 void setup_payload();
309 bool reg_allocate_trivial();
311 void evaluate_spill_costs(float *spill_costs
, bool *no_spill
);
312 int choose_spill_reg(struct ra_graph
*g
);
313 void spill_reg(int spill_reg
);
314 void move_grf_array_access_to_scratch();
315 void move_uniform_array_access_to_pull_constants();
316 void move_push_constants_to_pull_constants();
317 void split_uniform_registers();
318 void pack_uniform_registers();
319 void calculate_live_intervals();
320 void split_virtual_grfs();
321 bool dead_code_eliminate();
322 bool virtual_grf_interferes(int a
, int b
);
323 bool opt_copy_propagation();
324 bool opt_algebraic();
325 bool opt_compute_to_mrf();
327 vec4_instruction
*emit(vec4_instruction
*inst
);
329 vec4_instruction
*emit(enum opcode opcode
);
331 vec4_instruction
*emit(enum opcode opcode
, dst_reg dst
, src_reg src0
);
333 vec4_instruction
*emit(enum opcode opcode
, dst_reg dst
,
334 src_reg src0
, src_reg src1
);
336 vec4_instruction
*emit(enum opcode opcode
, dst_reg dst
,
337 src_reg src0
, src_reg src1
, src_reg src2
);
339 vec4_instruction
*emit_before(vec4_instruction
*inst
,
340 vec4_instruction
*new_inst
);
342 vec4_instruction
*MOV(dst_reg dst
, src_reg src0
);
343 vec4_instruction
*NOT(dst_reg dst
, src_reg src0
);
344 vec4_instruction
*RNDD(dst_reg dst
, src_reg src0
);
345 vec4_instruction
*RNDE(dst_reg dst
, src_reg src0
);
346 vec4_instruction
*RNDZ(dst_reg dst
, src_reg src0
);
347 vec4_instruction
*FRC(dst_reg dst
, src_reg src0
);
348 vec4_instruction
*ADD(dst_reg dst
, src_reg src0
, src_reg src1
);
349 vec4_instruction
*MUL(dst_reg dst
, src_reg src0
, src_reg src1
);
350 vec4_instruction
*MACH(dst_reg dst
, src_reg src0
, src_reg src1
);
351 vec4_instruction
*MAC(dst_reg dst
, src_reg src0
, src_reg src1
);
352 vec4_instruction
*AND(dst_reg dst
, src_reg src0
, src_reg src1
);
353 vec4_instruction
*OR(dst_reg dst
, src_reg src0
, src_reg src1
);
354 vec4_instruction
*XOR(dst_reg dst
, src_reg src0
, src_reg src1
);
355 vec4_instruction
*DP3(dst_reg dst
, src_reg src0
, src_reg src1
);
356 vec4_instruction
*DP4(dst_reg dst
, src_reg src0
, src_reg src1
);
357 vec4_instruction
*DPH(dst_reg dst
, src_reg src0
, src_reg src1
);
358 vec4_instruction
*SHL(dst_reg dst
, src_reg src0
, src_reg src1
);
359 vec4_instruction
*SHR(dst_reg dst
, src_reg src0
, src_reg src1
);
360 vec4_instruction
*ASR(dst_reg dst
, src_reg src0
, src_reg src1
);
361 vec4_instruction
*CMP(dst_reg dst
, src_reg src0
, src_reg src1
,
363 vec4_instruction
*IF(src_reg src0
, src_reg src1
, uint32_t condition
);
364 vec4_instruction
*IF(uint32_t predicate
);
365 vec4_instruction
*PULL_CONSTANT_LOAD(dst_reg dst
, src_reg index
);
366 vec4_instruction
*SCRATCH_READ(dst_reg dst
, src_reg index
);
367 vec4_instruction
*SCRATCH_WRITE(dst_reg dst
, src_reg src
, src_reg index
);
369 int implied_mrf_writes(vec4_instruction
*inst
);
371 bool try_rewrite_rhs_to_dst(ir_assignment
*ir
,
374 vec4_instruction
*pre_rhs_inst
,
375 vec4_instruction
*last_rhs_inst
);
377 /** Walks an exec_list of ir_instruction and sends it through this visitor. */
378 void visit_instructions(const exec_list
*list
);
380 void setup_vp_regs();
381 void emit_attribute_fixups();
382 void emit_vertex_program_code();
383 void emit_vp_sop(uint32_t condmod
, dst_reg dst
,
384 src_reg src0
, src_reg src1
, src_reg one
);
385 dst_reg
get_vp_dst_reg(const prog_dst_register
&dst
);
386 src_reg
get_vp_src_reg(const prog_src_register
&src
);
388 void emit_bool_to_cond_code(ir_rvalue
*ir
, uint32_t *predicate
);
389 void emit_bool_comparison(unsigned int op
, dst_reg dst
, src_reg src0
, src_reg src1
);
390 void emit_if_gen6(ir_if
*ir
);
392 void emit_minmax(uint32_t condmod
, dst_reg dst
, src_reg src0
, src_reg src1
);
394 void emit_block_move(dst_reg
*dst
, src_reg
*src
,
395 const struct glsl_type
*type
, uint32_t predicate
);
397 void emit_constant_values(dst_reg
*dst
, ir_constant
*value
);
400 * Emit the correct dot-product instruction for the type of arguments
402 void emit_dp(dst_reg dst
, src_reg src0
, src_reg src1
, unsigned elements
);
404 void emit_scalar(ir_instruction
*ir
, enum prog_opcode op
,
405 dst_reg dst
, src_reg src0
);
407 void emit_scalar(ir_instruction
*ir
, enum prog_opcode op
,
408 dst_reg dst
, src_reg src0
, src_reg src1
);
410 void emit_scs(ir_instruction
*ir
, enum prog_opcode op
,
411 dst_reg dst
, const src_reg
&src
);
413 void emit_math1_gen6(enum opcode opcode
, dst_reg dst
, src_reg src
);
414 void emit_math1_gen4(enum opcode opcode
, dst_reg dst
, src_reg src
);
415 void emit_math(enum opcode opcode
, dst_reg dst
, src_reg src
);
416 void emit_math2_gen6(enum opcode opcode
, dst_reg dst
, src_reg src0
, src_reg src1
);
417 void emit_math2_gen4(enum opcode opcode
, dst_reg dst
, src_reg src0
, src_reg src1
);
418 void emit_math(enum opcode opcode
, dst_reg dst
, src_reg src0
, src_reg src1
);
420 void swizzle_result(ir_texture
*ir
, src_reg orig_val
, int sampler
);
422 void emit_ndc_computation();
423 void emit_psiz_and_flags(struct brw_reg reg
);
424 void emit_clip_distances(struct brw_reg reg
, int offset
);
425 void emit_generic_urb_slot(dst_reg reg
, int vert_result
);
426 void emit_urb_slot(int mrf
, int vert_result
);
427 void emit_urb_writes(void);
429 src_reg
get_scratch_offset(vec4_instruction
*inst
,
430 src_reg
*reladdr
, int reg_offset
);
431 src_reg
get_pull_constant_offset(vec4_instruction
*inst
,
432 src_reg
*reladdr
, int reg_offset
);
433 void emit_scratch_read(vec4_instruction
*inst
,
437 void emit_scratch_write(vec4_instruction
*inst
,
439 void emit_pull_constant_load(vec4_instruction
*inst
,
444 bool try_emit_sat(ir_expression
*ir
);
445 void resolve_ud_negate(src_reg
*reg
);
447 bool process_move_condition(ir_rvalue
*ir
);
449 void generate_code();
450 void generate_vs_instruction(vec4_instruction
*inst
,
452 struct brw_reg
*src
);
454 void generate_math1_gen4(vec4_instruction
*inst
,
457 void generate_math1_gen6(vec4_instruction
*inst
,
460 void generate_math2_gen4(vec4_instruction
*inst
,
463 struct brw_reg src1
);
464 void generate_math2_gen6(vec4_instruction
*inst
,
467 struct brw_reg src1
);
468 void generate_math2_gen7(vec4_instruction
*inst
,
471 struct brw_reg src1
);
473 void generate_tex(vec4_instruction
*inst
,
477 void generate_urb_write(vec4_instruction
*inst
);
478 void generate_oword_dual_block_offsets(struct brw_reg m1
,
479 struct brw_reg index
);
480 void generate_scratch_write(vec4_instruction
*inst
,
483 struct brw_reg index
);
484 void generate_scratch_read(vec4_instruction
*inst
,
486 struct brw_reg index
);
487 void generate_pull_constant_load(vec4_instruction
*inst
,
489 struct brw_reg index
,
490 struct brw_reg offset
);
492 void dump_instruction(vec4_instruction
*inst
);
493 void dump_instructions();
496 } /* namespace brw */
498 #endif /* BRW_VEC4_H */