2 * Copyright © 2011 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
28 #include "brw_shader.h"
29 #include "main/compiler.h"
30 #include "program/hash_table.h"
31 #include "brw_program.h"
37 #include "brw_context.h"
42 #include "gen8_generator.h"
48 struct brw_vec4_compile
{
49 GLuint last_scratch
; /**< measured in 32-byte (register size) units */
53 struct brw_vec4_prog_key
{
54 GLuint program_string_id
;
57 * True if at least one clip flag is enabled, regardless of whether the
58 * shader uses clip planes or gl_ClipDistance.
60 GLuint userclip_active
:1;
63 * How many user clipping planes are being uploaded to the vertex shader as
66 GLuint nr_userclip_plane_consts
:4;
68 GLuint clamp_vertex_color
:1;
70 struct brw_sampler_prog_key_data tex
;
79 brw_vec4_setup_prog_key_for_precompile(struct gl_context
*ctx
,
80 struct brw_vec4_prog_key
*key
,
81 GLuint id
, struct gl_program
*prog
);
91 swizzle_for_size(int size
);
96 /** Register file: GRF, MRF, IMM. */
97 enum register_file file
;
98 /** virtual register number. 0 = fixed hw reg */
100 /** Offset within the virtual register. */
102 /** Register type. BRW_REGISTER_TYPE_* */
104 struct brw_reg fixed_hw_reg
;
106 /** Value for file == BRW_IMMMEDIATE_FILE */
114 class src_reg
: public reg
117 DECLARE_RALLOC_CXX_OPERATORS(src_reg
)
121 src_reg(register_file file
, int reg
, const glsl_type
*type
);
126 src_reg(struct brw_reg reg
);
128 bool equals(src_reg
*r
);
129 bool is_zero() const;
132 src_reg(class vec4_visitor
*v
, const struct glsl_type
*type
);
134 explicit src_reg(dst_reg reg
);
136 GLuint swizzle
; /**< BRW_SWIZZLE_XYZW macros from brw_reg.h. */
143 static inline src_reg
144 retype(src_reg reg
, unsigned type
)
146 reg
.fixed_hw_reg
.type
= reg
.type
= type
;
150 static inline src_reg
151 offset(src_reg reg
, unsigned delta
)
153 assert(delta
== 0 || (reg
.file
!= HW_REG
&& reg
.file
!= IMM
));
154 reg
.reg_offset
+= delta
;
159 * Reswizzle a given source register.
162 static inline src_reg
163 swizzle(src_reg reg
, unsigned swizzle
)
165 assert(reg
.file
!= HW_REG
);
166 reg
.swizzle
= BRW_SWIZZLE4(
167 BRW_GET_SWZ(reg
.swizzle
, BRW_GET_SWZ(swizzle
, 0)),
168 BRW_GET_SWZ(reg
.swizzle
, BRW_GET_SWZ(swizzle
, 1)),
169 BRW_GET_SWZ(reg
.swizzle
, BRW_GET_SWZ(swizzle
, 2)),
170 BRW_GET_SWZ(reg
.swizzle
, BRW_GET_SWZ(swizzle
, 3)));
174 static inline src_reg
177 assert(reg
.file
!= HW_REG
&& reg
.file
!= IMM
);
178 reg
.negate
= !reg
.negate
;
182 class dst_reg
: public reg
185 DECLARE_RALLOC_CXX_OPERATORS(dst_reg
)
190 dst_reg(register_file file
, int reg
);
191 dst_reg(register_file file
, int reg
, const glsl_type
*type
, int writemask
);
192 dst_reg(struct brw_reg reg
);
193 dst_reg(class vec4_visitor
*v
, const struct glsl_type
*type
);
195 explicit dst_reg(src_reg reg
);
197 int writemask
; /**< Bitfield of WRITEMASK_[XYZW] */
202 static inline dst_reg
203 retype(dst_reg reg
, unsigned type
)
205 reg
.fixed_hw_reg
.type
= reg
.type
= type
;
209 static inline dst_reg
210 offset(dst_reg reg
, unsigned delta
)
212 assert(delta
== 0 || (reg
.file
!= HW_REG
&& reg
.file
!= IMM
));
213 reg
.reg_offset
+= delta
;
217 static inline dst_reg
218 writemask(dst_reg reg
, unsigned mask
)
220 assert(reg
.file
!= HW_REG
&& reg
.file
!= IMM
);
221 assert((reg
.writemask
& mask
) != 0);
222 reg
.writemask
&= mask
;
226 class vec4_instruction
: public backend_instruction
{
228 DECLARE_RALLOC_CXX_OPERATORS(vec4_instruction
)
230 vec4_instruction(vec4_visitor
*v
, enum opcode opcode
,
231 dst_reg dst
= dst_reg(),
232 src_reg src0
= src_reg(),
233 src_reg src1
= src_reg(),
234 src_reg src2
= src_reg());
236 struct brw_reg
get_dst(void);
237 struct brw_reg
get_src(const struct brw_vec4_prog_data
*prog_data
, int i
);
243 bool force_writemask_all
;
244 bool no_dd_clear
, no_dd_check
;
246 int conditional_mod
; /**< BRW_CONDITIONAL_* */
249 uint32_t texture_offset
; /**< Texture Offset bitfield */
250 int target
; /**< MRT target. */
253 enum brw_urb_write_flags urb_write_flags
;
255 int mlen
; /**< SEND message length */
256 int base_mrf
; /**< First MRF in the SEND message, if mlen is nonzero. */
258 uint32_t offset
; /* spill/unspill offset */
260 * Annotation for the generated IR. One of the two can be set.
263 const char *annotation
;
265 bool is_send_from_grf();
266 bool can_reswizzle_dst(int dst_writemask
, int swizzle
, int swizzle_mask
);
267 void reswizzle_dst(int dst_writemask
, int swizzle
);
269 bool depends_on_flags()
271 return predicate
|| opcode
== VS_OPCODE_UNPACK_FLAGS_SIMD4X2
;
276 * The vertex shader front-end.
278 * Translates either GLSL IR or Mesa IR (for ARB_vertex_program and
279 * fixed-function) into VS IR.
281 class vec4_visitor
: public backend_visitor
284 vec4_visitor(struct brw_context
*brw
,
285 struct brw_vec4_compile
*c
,
286 struct gl_program
*prog
,
287 const struct brw_vec4_prog_key
*key
,
288 struct brw_vec4_prog_data
*prog_data
,
289 struct gl_shader_program
*shader_prog
,
290 struct brw_shader
*shader
,
294 shader_time_shader_type st_base
,
295 shader_time_shader_type st_written
,
296 shader_time_shader_type st_reset
);
301 return dst_reg(brw_null_reg());
306 return dst_reg(retype(brw_null_reg(), BRW_REGISTER_TYPE_D
));
309 dst_reg
dst_null_ud()
311 return dst_reg(retype(brw_null_reg(), BRW_REGISTER_TYPE_UD
));
314 struct brw_vec4_compile
*c
;
315 const struct brw_vec4_prog_key
*key
;
316 struct brw_vec4_prog_data
*prog_data
;
317 unsigned int sanity_param_count
;
323 * GLSL IR currently being processed, which is associated with our
324 * driver IR instructions for debugging purposes.
327 const char *current_annotation
;
329 int *virtual_grf_sizes
;
330 int virtual_grf_count
;
331 int virtual_grf_array_size
;
332 int first_non_payload_grf
;
333 unsigned int max_grf
;
334 int *virtual_grf_start
;
335 int *virtual_grf_end
;
336 dst_reg userplane
[MAX_CLIP_PLANES
];
339 * This is the size to be used for an array with an element per
342 int virtual_grf_reg_count
;
343 /** Per-virtual-grf indices into an array of size virtual_grf_reg_count */
344 int *virtual_grf_reg_map
;
346 bool live_intervals_valid
;
348 dst_reg
*variable_storage(ir_variable
*var
);
350 void reladdr_to_temp(ir_instruction
*ir
, src_reg
*reg
, int *num_reladdr
);
352 bool need_all_constants_in_pull_buffer
;
355 * \name Visit methods
357 * As typical for the visitor pattern, there must be one \c visit method for
358 * each concrete subclass of \c ir_instruction. Virtual base classes within
359 * the hierarchy should not have \c visit methods.
362 virtual void visit(ir_variable
*);
363 virtual void visit(ir_loop
*);
364 virtual void visit(ir_loop_jump
*);
365 virtual void visit(ir_function_signature
*);
366 virtual void visit(ir_function
*);
367 virtual void visit(ir_expression
*);
368 virtual void visit(ir_swizzle
*);
369 virtual void visit(ir_dereference_variable
*);
370 virtual void visit(ir_dereference_array
*);
371 virtual void visit(ir_dereference_record
*);
372 virtual void visit(ir_assignment
*);
373 virtual void visit(ir_constant
*);
374 virtual void visit(ir_call
*);
375 virtual void visit(ir_return
*);
376 virtual void visit(ir_discard
*);
377 virtual void visit(ir_texture
*);
378 virtual void visit(ir_if
*);
379 virtual void visit(ir_emit_vertex
*);
380 virtual void visit(ir_end_primitive
*);
385 /* Regs for vertex results. Generated at ir_variable visiting time
386 * for the ir->location's used.
388 dst_reg output_reg
[BRW_VARYING_SLOT_COUNT
];
389 const char *output_reg_annotation
[BRW_VARYING_SLOT_COUNT
];
390 int uniform_size
[MAX_UNIFORMS
];
391 int uniform_vector_size
[MAX_UNIFORMS
];
394 src_reg shader_start_time
;
396 struct hash_table
*variable_ht
;
399 void fail(const char *msg
, ...);
401 int virtual_grf_alloc(int size
);
402 void setup_uniform_clipplane_values();
403 void setup_uniform_values(ir_variable
*ir
);
404 void setup_builtin_uniform_values(ir_variable
*ir
);
405 int setup_uniforms(int payload_reg
);
406 bool reg_allocate_trivial();
408 void evaluate_spill_costs(float *spill_costs
, bool *no_spill
);
409 int choose_spill_reg(struct ra_graph
*g
);
410 void spill_reg(int spill_reg
);
411 void move_grf_array_access_to_scratch();
412 void move_uniform_array_access_to_pull_constants();
413 void move_push_constants_to_pull_constants();
414 void split_uniform_registers();
415 void pack_uniform_registers();
416 void calculate_live_intervals();
417 void invalidate_live_intervals();
418 void split_virtual_grfs();
419 bool dead_code_eliminate();
420 bool virtual_grf_interferes(int a
, int b
);
421 bool opt_copy_propagation();
422 bool opt_algebraic();
423 bool opt_register_coalesce();
424 void opt_set_dependency_control();
425 void opt_schedule_instructions();
427 bool can_do_source_mods(vec4_instruction
*inst
);
429 vec4_instruction
*emit(vec4_instruction
*inst
);
431 vec4_instruction
*emit(enum opcode opcode
);
433 vec4_instruction
*emit(enum opcode opcode
, dst_reg dst
);
435 vec4_instruction
*emit(enum opcode opcode
, dst_reg dst
, src_reg src0
);
437 vec4_instruction
*emit(enum opcode opcode
, dst_reg dst
,
438 src_reg src0
, src_reg src1
);
440 vec4_instruction
*emit(enum opcode opcode
, dst_reg dst
,
441 src_reg src0
, src_reg src1
, src_reg src2
);
443 vec4_instruction
*emit_before(vec4_instruction
*inst
,
444 vec4_instruction
*new_inst
);
446 vec4_instruction
*MOV(dst_reg dst
, src_reg src0
);
447 vec4_instruction
*NOT(dst_reg dst
, src_reg src0
);
448 vec4_instruction
*RNDD(dst_reg dst
, src_reg src0
);
449 vec4_instruction
*RNDE(dst_reg dst
, src_reg src0
);
450 vec4_instruction
*RNDZ(dst_reg dst
, src_reg src0
);
451 vec4_instruction
*FRC(dst_reg dst
, src_reg src0
);
452 vec4_instruction
*F32TO16(dst_reg dst
, src_reg src0
);
453 vec4_instruction
*F16TO32(dst_reg dst
, src_reg src0
);
454 vec4_instruction
*ADD(dst_reg dst
, src_reg src0
, src_reg src1
);
455 vec4_instruction
*MUL(dst_reg dst
, src_reg src0
, src_reg src1
);
456 vec4_instruction
*MACH(dst_reg dst
, src_reg src0
, src_reg src1
);
457 vec4_instruction
*MAC(dst_reg dst
, src_reg src0
, src_reg src1
);
458 vec4_instruction
*AND(dst_reg dst
, src_reg src0
, src_reg src1
);
459 vec4_instruction
*OR(dst_reg dst
, src_reg src0
, src_reg src1
);
460 vec4_instruction
*XOR(dst_reg dst
, src_reg src0
, src_reg src1
);
461 vec4_instruction
*DP3(dst_reg dst
, src_reg src0
, src_reg src1
);
462 vec4_instruction
*DP4(dst_reg dst
, src_reg src0
, src_reg src1
);
463 vec4_instruction
*DPH(dst_reg dst
, src_reg src0
, src_reg src1
);
464 vec4_instruction
*SHL(dst_reg dst
, src_reg src0
, src_reg src1
);
465 vec4_instruction
*SHR(dst_reg dst
, src_reg src0
, src_reg src1
);
466 vec4_instruction
*ASR(dst_reg dst
, src_reg src0
, src_reg src1
);
467 vec4_instruction
*CMP(dst_reg dst
, src_reg src0
, src_reg src1
,
469 vec4_instruction
*IF(src_reg src0
, src_reg src1
, uint32_t condition
);
470 vec4_instruction
*IF(uint32_t predicate
);
471 vec4_instruction
*PULL_CONSTANT_LOAD(dst_reg dst
, src_reg index
);
472 vec4_instruction
*SCRATCH_READ(dst_reg dst
, src_reg index
);
473 vec4_instruction
*SCRATCH_WRITE(dst_reg dst
, src_reg src
, src_reg index
);
474 vec4_instruction
*LRP(dst_reg dst
, src_reg a
, src_reg y
, src_reg x
);
475 vec4_instruction
*BFREV(dst_reg dst
, src_reg value
);
476 vec4_instruction
*BFE(dst_reg dst
, src_reg bits
, src_reg offset
, src_reg value
);
477 vec4_instruction
*BFI1(dst_reg dst
, src_reg bits
, src_reg offset
);
478 vec4_instruction
*BFI2(dst_reg dst
, src_reg bfi1_dst
, src_reg insert
, src_reg base
);
479 vec4_instruction
*FBH(dst_reg dst
, src_reg value
);
480 vec4_instruction
*FBL(dst_reg dst
, src_reg value
);
481 vec4_instruction
*CBIT(dst_reg dst
, src_reg value
);
482 vec4_instruction
*MAD(dst_reg dst
, src_reg c
, src_reg b
, src_reg a
);
483 vec4_instruction
*ADDC(dst_reg dst
, src_reg src0
, src_reg src1
);
484 vec4_instruction
*SUBB(dst_reg dst
, src_reg src0
, src_reg src1
);
486 int implied_mrf_writes(vec4_instruction
*inst
);
488 bool try_rewrite_rhs_to_dst(ir_assignment
*ir
,
491 vec4_instruction
*pre_rhs_inst
,
492 vec4_instruction
*last_rhs_inst
);
494 bool try_copy_propagation(vec4_instruction
*inst
, int arg
,
497 /** Walks an exec_list of ir_instruction and sends it through this visitor. */
498 void visit_instructions(const exec_list
*list
);
500 void emit_vp_sop(uint32_t condmod
, dst_reg dst
,
501 src_reg src0
, src_reg src1
, src_reg one
);
503 void emit_bool_to_cond_code(ir_rvalue
*ir
, uint32_t *predicate
);
504 void emit_bool_comparison(unsigned int op
, dst_reg dst
, src_reg src0
, src_reg src1
);
505 void emit_if_gen6(ir_if
*ir
);
507 void emit_minmax(uint32_t condmod
, dst_reg dst
, src_reg src0
, src_reg src1
);
509 void emit_lrp(const dst_reg
&dst
,
510 const src_reg
&x
, const src_reg
&y
, const src_reg
&a
);
512 void emit_block_move(dst_reg
*dst
, src_reg
*src
,
513 const struct glsl_type
*type
, uint32_t predicate
);
515 void emit_constant_values(dst_reg
*dst
, ir_constant
*value
);
518 * Emit the correct dot-product instruction for the type of arguments
520 void emit_dp(dst_reg dst
, src_reg src0
, src_reg src1
, unsigned elements
);
522 void emit_scalar(ir_instruction
*ir
, enum prog_opcode op
,
523 dst_reg dst
, src_reg src0
);
525 void emit_scalar(ir_instruction
*ir
, enum prog_opcode op
,
526 dst_reg dst
, src_reg src0
, src_reg src1
);
528 void emit_scs(ir_instruction
*ir
, enum prog_opcode op
,
529 dst_reg dst
, const src_reg
&src
);
531 src_reg
fix_3src_operand(src_reg src
);
533 void emit_math1_gen6(enum opcode opcode
, dst_reg dst
, src_reg src
);
534 void emit_math1_gen4(enum opcode opcode
, dst_reg dst
, src_reg src
);
535 void emit_math(enum opcode opcode
, dst_reg dst
, src_reg src
);
536 void emit_math2_gen6(enum opcode opcode
, dst_reg dst
, src_reg src0
, src_reg src1
);
537 void emit_math2_gen4(enum opcode opcode
, dst_reg dst
, src_reg src0
, src_reg src1
);
538 void emit_math(enum opcode opcode
, dst_reg dst
, src_reg src0
, src_reg src1
);
539 src_reg
fix_math_operand(src_reg src
);
541 void emit_pack_half_2x16(dst_reg dst
, src_reg src0
);
542 void emit_unpack_half_2x16(dst_reg dst
, src_reg src0
);
544 uint32_t gather_channel(ir_texture
*ir
, int sampler
);
545 src_reg
emit_mcs_fetch(ir_texture
*ir
, src_reg coordinate
, int sampler
);
546 void emit_gen6_gather_wa(uint8_t wa
, dst_reg dst
);
547 void swizzle_result(ir_texture
*ir
, src_reg orig_val
, int sampler
);
549 void emit_ndc_computation();
550 void emit_psiz_and_flags(struct brw_reg reg
);
551 void emit_clip_distances(dst_reg reg
, int offset
);
552 void emit_generic_urb_slot(dst_reg reg
, int varying
);
553 void emit_urb_slot(int mrf
, int varying
);
555 void emit_shader_time_begin();
556 void emit_shader_time_end();
557 void emit_shader_time_write(enum shader_time_shader_type type
,
560 void emit_untyped_atomic(unsigned atomic_op
, unsigned surf_index
,
561 dst_reg dst
, src_reg offset
, src_reg src0
,
564 void emit_untyped_surface_read(unsigned surf_index
, dst_reg dst
,
567 src_reg
get_scratch_offset(vec4_instruction
*inst
,
568 src_reg
*reladdr
, int reg_offset
);
569 src_reg
get_pull_constant_offset(vec4_instruction
*inst
,
570 src_reg
*reladdr
, int reg_offset
);
571 void emit_scratch_read(vec4_instruction
*inst
,
575 void emit_scratch_write(vec4_instruction
*inst
,
577 void emit_pull_constant_load(vec4_instruction
*inst
,
582 bool try_emit_sat(ir_expression
*ir
);
583 bool try_emit_mad(ir_expression
*ir
, int mul_arg
);
584 void resolve_ud_negate(src_reg
*reg
);
586 src_reg
get_timestamp();
588 bool process_move_condition(ir_rvalue
*ir
);
590 void dump_instruction(backend_instruction
*inst
);
592 void visit_atomic_counter_intrinsic(ir_call
*ir
);
596 void lower_attributes_to_hw_regs(const int *attribute_map
,
598 void setup_payload_interference(struct ra_graph
*g
, int first_payload_node
,
600 virtual dst_reg
*make_reg_for_system_value(ir_variable
*ir
) = 0;
601 virtual void setup_payload() = 0;
602 virtual void emit_prolog() = 0;
603 virtual void emit_program_code() = 0;
604 virtual void emit_thread_end() = 0;
605 virtual void emit_urb_write_header(int mrf
) = 0;
606 virtual vec4_instruction
*emit_urb_write_opcode(bool complete
) = 0;
607 virtual int compute_array_stride(ir_dereference_array
*ir
);
609 const bool debug_flag
;
613 * If true, then register allocation should fail instead of spilling.
615 const bool no_spills
;
617 const shader_time_shader_type st_base
;
618 const shader_time_shader_type st_written
;
619 const shader_time_shader_type st_reset
;
624 * The vertex shader code generator.
626 * Translates VS IR to actual i965 assembly code.
631 vec4_generator(struct brw_context
*brw
,
632 struct gl_shader_program
*shader_prog
,
633 struct gl_program
*prog
,
634 struct brw_vec4_prog_data
*prog_data
,
639 const unsigned *generate_assembly(exec_list
*insts
, unsigned *asm_size
);
642 void generate_code(exec_list
*instructions
);
643 void generate_vec4_instruction(vec4_instruction
*inst
,
645 struct brw_reg
*src
);
647 void generate_math1_gen4(vec4_instruction
*inst
,
650 void generate_math1_gen6(vec4_instruction
*inst
,
653 void generate_math2_gen4(vec4_instruction
*inst
,
656 struct brw_reg src1
);
657 void generate_math2_gen6(vec4_instruction
*inst
,
660 struct brw_reg src1
);
661 void generate_math2_gen7(vec4_instruction
*inst
,
664 struct brw_reg src1
);
666 void generate_tex(vec4_instruction
*inst
,
670 void generate_vs_urb_write(vec4_instruction
*inst
);
671 void generate_gs_urb_write(vec4_instruction
*inst
);
672 void generate_gs_thread_end(vec4_instruction
*inst
);
673 void generate_gs_set_write_offset(struct brw_reg dst
,
675 struct brw_reg src1
);
676 void generate_gs_set_vertex_count(struct brw_reg dst
,
678 void generate_gs_set_dword_2_immed(struct brw_reg dst
, struct brw_reg src
);
679 void generate_gs_prepare_channel_masks(struct brw_reg dst
);
680 void generate_gs_set_channel_masks(struct brw_reg dst
, struct brw_reg src
);
681 void generate_gs_get_instance_id(struct brw_reg dst
);
682 void generate_oword_dual_block_offsets(struct brw_reg m1
,
683 struct brw_reg index
);
684 void generate_scratch_write(vec4_instruction
*inst
,
687 struct brw_reg index
);
688 void generate_scratch_read(vec4_instruction
*inst
,
690 struct brw_reg index
);
691 void generate_pull_constant_load(vec4_instruction
*inst
,
693 struct brw_reg index
,
694 struct brw_reg offset
);
695 void generate_pull_constant_load_gen7(vec4_instruction
*inst
,
697 struct brw_reg surf_index
,
698 struct brw_reg offset
);
699 void generate_unpack_flags(vec4_instruction
*inst
,
702 void generate_untyped_atomic(vec4_instruction
*inst
,
704 struct brw_reg atomic_op
,
705 struct brw_reg surf_index
);
707 void generate_untyped_surface_read(vec4_instruction
*inst
,
709 struct brw_reg surf_index
);
711 struct brw_context
*brw
;
713 struct brw_compile
*p
;
715 struct gl_shader_program
*shader_prog
;
716 const struct gl_program
*prog
;
718 struct brw_vec4_prog_data
*prog_data
;
721 const bool debug_flag
;
725 * The vertex shader code generator.
727 * Translates VS IR to actual i965 assembly code.
729 class gen8_vec4_generator
: public gen8_generator
732 gen8_vec4_generator(struct brw_context
*brw
,
733 struct gl_shader_program
*shader_prog
,
734 struct gl_program
*prog
,
735 struct brw_vec4_prog_data
*prog_data
,
738 ~gen8_vec4_generator();
740 const unsigned *generate_assembly(exec_list
*insts
, unsigned *asm_size
);
743 void generate_code(exec_list
*instructions
);
744 void generate_vec4_instruction(vec4_instruction
*inst
,
746 struct brw_reg
*src
);
748 void generate_tex(vec4_instruction
*inst
,
751 void generate_urb_write(vec4_instruction
*ir
, bool copy_g0
);
752 void generate_gs_thread_end(vec4_instruction
*ir
);
753 void generate_gs_set_write_offset(struct brw_reg dst
,
755 struct brw_reg src1
);
756 void generate_gs_set_vertex_count(struct brw_reg dst
,
758 void generate_gs_set_dword_2_immed(struct brw_reg dst
, struct brw_reg src
);
759 void generate_gs_prepare_channel_masks(struct brw_reg dst
);
760 void generate_gs_set_channel_masks(struct brw_reg dst
, struct brw_reg src
);
762 void generate_oword_dual_block_offsets(struct brw_reg m1
,
763 struct brw_reg index
);
764 void generate_scratch_write(vec4_instruction
*inst
,
767 struct brw_reg index
);
768 void generate_scratch_read(vec4_instruction
*inst
,
770 struct brw_reg index
);
771 void generate_pull_constant_load(vec4_instruction
*inst
,
773 struct brw_reg index
,
774 struct brw_reg offset
);
776 void mark_surface_used(unsigned surf_index
);
778 struct brw_vec4_prog_data
*prog_data
;
780 const bool debug_flag
;
784 } /* namespace brw */
785 #endif /* __cplusplus */
787 #endif /* BRW_VEC4_H */