src/mesa/drivers/dri/i965/brw_vec4_live_variables.cpp

   1 /*
   2  * Copyright © 2012 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *    Eric Anholt <eric@anholt.net>
  25  *
  26  */
  27
  28 #include "brw_cfg.h"
  29 #include "brw_vec4_live_variables.h"
  30
  31 using namespace brw;
  32
  33 /** @file brw_vec4_live_variables.cpp
  34  *
  35  * Support for computing at the basic block level which variables
  36  * (virtual GRFs in our case) are live at entry and exit.
  37  *
  38  * See Muchnick's Advanced Compiler Design and Implementation, section
  39  * 14.1 (p444).
  40  */
  41
  42 /**
  43  * Sets up the use[] and def[] arrays.
  44  *
  45  * The basic-block-level live variable analysis needs to know which
  46  * variables get used before they're completely defined, and which
  47  * variables are completely defined before they're used.
  48  *
  49  * We independently track each channel of a vec4.  This is because we need to
  50  * be able to recognize a sequence like:
  51  *
  52  * ...
  53  * DP4 tmp.x a b;
  54  * DP4 tmp.y c d;
  55  * MUL result.xy tmp.xy e.xy
  56  * ...
  57  *
  58  * as having tmp live only across that sequence (assuming it's used nowhere
  59  * else), because it's a common pattern.  A more conservative approach that
  60  * doesn't get tmp marked a deffed in this block will tend to result in
  61  * spilling.
  62  */
  63 void
  64 vec4_live_variables::setup_def_use()
  65 {
  66    int ip = 0;
  67
  68    foreach_block (block, cfg) {
  69       assert(ip == block->start_ip);
  70       if (block->num > 0)
  71          assert(cfg->blocks[block->num - 1]->end_ip == ip - 1);
  72
  73       foreach_inst_in_block(vec4_instruction, inst, block) {
  74          struct block_data *bd = &block_data[block->num];
  75
  76          /* Set use[] for this instruction */
  77          for (unsigned int i = 0; i < 3; i++) {
  78             if (inst->src[i].file == GRF) {
  79                for (unsigned j = 0; j < inst->regs_read(i); j++) {
  80                   for (int c = 0; c < 4; c++) {
  81                      const unsigned v =
  82                         var_from_reg(alloc, offset(inst->src[i], j), c);
  83                      if (!BITSET_TEST(bd->def, v))
  84                         BITSET_SET(bd->use, v);
  85                   }
  86                }
  87             }
  88          }
  89          if (inst->reads_flag()) {
  90             if (!BITSET_TEST(bd->flag_def, 0)) {
  91                BITSET_SET(bd->flag_use, 0);
  92             }
  93          }
  94
  95          /* Check for unconditional writes to whole registers. These
  96           * are the things that screen off preceding definitions of a
  97           * variable, and thus qualify for being in def[].
  98           */
  99          if (inst->dst.file == GRF &&
 100              (!inst->predicate || inst->opcode == BRW_OPCODE_SEL)) {
 101             for (unsigned i = 0; i < inst->regs_written; i++) {
 102                for (int c = 0; c < 4; c++) {
 103                   if (inst->dst.writemask & (1 << c)) {
 104                      const unsigned v =
 105                         var_from_reg(alloc, offset(inst->dst, i), c);
 106                      if (!BITSET_TEST(bd->use, v))
 107                         BITSET_SET(bd->def, v);
 108                   }
 109                }
 110             }
 111          }
 112          if (inst->writes_flag()) {
 113             if (!BITSET_TEST(bd->flag_use, 0)) {
 114                BITSET_SET(bd->flag_def, 0);
 115             }
 116          }
 117
 118          ip++;
 119       }
 120    }
 121 }
 122
 123 /**
 124  * The algorithm incrementally sets bits in liveout and livein,
 125  * propagating it through control flow.  It will eventually terminate
 126  * because it only ever adds bits, and stops when no bits are added in
 127  * a pass.
 128  */
 129 void
 130 vec4_live_variables::compute_live_variables()
 131 {
 132    bool cont = true;
 133
 134    while (cont) {
 135       cont = false;
 136
 137       foreach_block_reverse (block, cfg) {
 138          struct block_data *bd = &block_data[block->num];
 139
 140          /* Update liveout */
 141          foreach_list_typed(bblock_link, child_link, link, &block->children) {
 142             struct block_data *child_bd = &block_data[child_link->block->num];
 143
 144             for (int i = 0; i < bitset_words; i++) {
 145                BITSET_WORD new_liveout = (child_bd->livein[i] &
 146                                           ~bd->liveout[i]);
 147                if (new_liveout) {
 148                   bd->liveout[i] |= new_liveout;
 149                   cont = true;
 150                }
 151             }
 152             BITSET_WORD new_liveout = (child_bd->flag_livein[0] &
 153                                        ~bd->flag_liveout[0]);
 154             if (new_liveout) {
 155                bd->flag_liveout[0] |= new_liveout;
 156                cont = true;
 157             }
 158          }
 159
 160          /* Update livein */
 161          for (int i = 0; i < bitset_words; i++) {
 162             BITSET_WORD new_livein = (bd->use[i] |
 163                                       (bd->liveout[i] &
 164                                        ~bd->def[i]));
 165             if (new_livein & ~bd->livein[i]) {
 166                bd->livein[i] |= new_livein;
 167                cont = true;
 168             }
 169          }
 170          BITSET_WORD new_livein = (bd->flag_use[0] |
 171                                    (bd->flag_liveout[0] &
 172                                     ~bd->flag_def[0]));
 173          if (new_livein & ~bd->flag_livein[0]) {
 174             bd->flag_livein[0] |= new_livein;
 175             cont = true;
 176          }
 177       }
 178    }
 179 }
 180
 181 vec4_live_variables::vec4_live_variables(const simple_allocator &alloc,
 182                                          cfg_t *cfg)
 183    : alloc(alloc), cfg(cfg)
 184 {
 185    mem_ctx = ralloc_context(NULL);
 186
 187    num_vars = alloc.total_size * 4;
 188    block_data = rzalloc_array(mem_ctx, struct block_data, cfg->num_blocks);
 189
 190    bitset_words = BITSET_WORDS(num_vars);
 191    for (int i = 0; i < cfg->num_blocks; i++) {
 192       block_data[i].def = rzalloc_array(mem_ctx, BITSET_WORD, bitset_words);
 193       block_data[i].use = rzalloc_array(mem_ctx, BITSET_WORD, bitset_words);
 194       block_data[i].livein = rzalloc_array(mem_ctx, BITSET_WORD, bitset_words);
 195       block_data[i].liveout = rzalloc_array(mem_ctx, BITSET_WORD, bitset_words);
 196
 197       block_data[i].flag_def[0] = 0;
 198       block_data[i].flag_use[0] = 0;
 199       block_data[i].flag_livein[0] = 0;
 200       block_data[i].flag_liveout[0] = 0;
 201    }
 202
 203    setup_def_use();
 204    compute_live_variables();
 205 }
 206
 207 vec4_live_variables::~vec4_live_variables()
 208 {
 209    ralloc_free(mem_ctx);
 210 }
 211
 212 #define MAX_INSTRUCTION (1 << 30)
 213
 214 /**
 215  * Computes a conservative start/end of the live intervals for each virtual GRF.
 216  *
 217  * We could expose per-channel live intervals to the consumer based on the
 218  * information we computed in vec4_live_variables, except that our only
 219  * current user is virtual_grf_interferes().  So we instead union the
 220  * per-channel ranges into a per-vgrf range for virtual_grf_start[] and
 221  * virtual_grf_end[].
 222  *
 223  * We could potentially have virtual_grf_interferes() do the test per-channel,
 224  * which would let some interesting register allocation occur (particularly on
 225  * code-generated GLSL sequences from the Cg compiler which does register
 226  * allocation at the GLSL level and thus reuses components of the variable
 227  * with distinct lifetimes).  But right now the complexity of doing so doesn't
 228  * seem worth it, since having virtual_grf_interferes() be cheap is important
 229  * for register allocation performance.
 230  */
 231 void
 232 vec4_visitor::calculate_live_intervals()
 233 {
 234    if (this->live_intervals)
 235       return;
 236
 237    int *start = ralloc_array(mem_ctx, int, this->alloc.total_size * 4);
 238    int *end = ralloc_array(mem_ctx, int, this->alloc.total_size * 4);
 239    ralloc_free(this->virtual_grf_start);
 240    ralloc_free(this->virtual_grf_end);
 241    this->virtual_grf_start = start;
 242    this->virtual_grf_end = end;
 243
 244    for (unsigned i = 0; i < this->alloc.total_size * 4; i++) {
 245       start[i] = MAX_INSTRUCTION;
 246       end[i] = -1;
 247    }
 248
 249    /* Start by setting up the intervals with no knowledge of control
 250     * flow.
 251     */
 252    int ip = 0;
 253    foreach_block_and_inst(block, vec4_instruction, inst, cfg) {
 254       for (unsigned int i = 0; i < 3; i++) {
 255          if (inst->src[i].file == GRF) {
 256             for (unsigned j = 0; j < inst->regs_read(i); j++) {
 257                for (int c = 0; c < 4; c++) {
 258                   const unsigned v =
 259                      var_from_reg(alloc, offset(inst->src[i], j), c);
 260                   start[v] = MIN2(start[v], ip);
 261                   end[v] = ip;
 262                }
 263             }
 264          }
 265       }
 266
 267       if (inst->dst.file == GRF) {
 268          for (unsigned i = 0; i < inst->regs_written; i++) {
 269             for (int c = 0; c < 4; c++) {
 270                if (inst->dst.writemask & (1 << c)) {
 271                   const unsigned v =
 272                      var_from_reg(alloc, offset(inst->dst, i), c);
 273                   start[v] = MIN2(start[v], ip);
 274                   end[v] = ip;
 275                }
 276             }
 277          }
 278       }
 279
 280       ip++;
 281    }
 282
 283    /* Now, extend those intervals using our analysis of control flow.
 284     *
 285     * The control flow-aware analysis was done at a channel level, while at
 286     * this point we're distilling it down to vgrfs.
 287     */
 288    this->live_intervals = new(mem_ctx) vec4_live_variables(alloc, cfg);
 289
 290    foreach_block (block, cfg) {
 291       struct block_data *bd = &live_intervals->block_data[block->num];
 292
 293       for (int i = 0; i < live_intervals->num_vars; i++) {
 294          if (BITSET_TEST(bd->livein, i)) {
 295             start[i] = MIN2(start[i], block->start_ip);
 296             end[i] = MAX2(end[i], block->start_ip);
 297          }
 298
 299          if (BITSET_TEST(bd->liveout, i)) {
 300             start[i] = MIN2(start[i], block->end_ip);
 301             end[i] = MAX2(end[i], block->end_ip);
 302          }
 303       }
 304    }
 305 }
 306
 307 void
 308 vec4_visitor::invalidate_live_intervals()
 309 {
 310    ralloc_free(live_intervals);
 311    live_intervals = NULL;
 312 }
 313
 314 int
 315 vec4_visitor::var_range_start(unsigned v, unsigned n) const
 316 {
 317    int start = INT_MAX;
 318
 319    for (unsigned i = 0; i < n; i++)
 320       start = MIN2(start, virtual_grf_start[v + i]);
 321
 322    return start;
 323 }
 324
 325 int
 326 vec4_visitor::var_range_end(unsigned v, unsigned n) const
 327 {
 328    int end = INT_MIN;
 329
 330    for (unsigned i = 0; i < n; i++)
 331       end = MAX2(end, virtual_grf_end[v + i]);
 332
 333    return end;
 334 }
 335
 336 bool
 337 vec4_visitor::virtual_grf_interferes(int a, int b)
 338 {
 339    return !((var_range_end(4 * alloc.offsets[a], 4 * alloc.sizes[a]) <=
 340              var_range_start(4 * alloc.offsets[b], 4 * alloc.sizes[b])) ||
 341             (var_range_end(4 * alloc.offsets[b], 4 * alloc.sizes[b]) <=
 342              var_range_start(4 * alloc.offsets[a], 4 * alloc.sizes[a])));
 343 }