src/mesa/drivers/dri/i965/brw_wm_surface_state.c

   1 /*
   2  Copyright (C) Intel Corp.  2006.  All Rights Reserved.
   3  Intel funded Tungsten Graphics (http://www.tungstengraphics.com) to
   4  develop this 3D driver.
   5
   6  Permission is hereby granted, free of charge, to any person obtaining
   7  a copy of this software and associated documentation files (the
   8  "Software"), to deal in the Software without restriction, including
   9  without limitation the rights to use, copy, modify, merge, publish,
  10  distribute, sublicense, and/or sell copies of the Software, and to
  11  permit persons to whom the Software is furnished to do so, subject to
  12  the following conditions:
  13
  14  The above copyright notice and this permission notice (including the
  15  next paragraph) shall be included in all copies or substantial
  16  portions of the Software.
  17
  18  THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  19  EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  20  MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
  21  IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
  22  LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
  23  OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
  24  WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  25
  26  **********************************************************************/
  27  /*
  28   * Authors:
  29   *   Keith Whitwell <keith@tungstengraphics.com>
  30   */
  31
  32
  33 #include "main/mtypes.h"
  34 #include "main/texformat.h"
  35 #include "main/texstore.h"
  36 #include "shader/prog_parameter.h"
  37
  38 #include "intel_mipmap_tree.h"
  39 #include "intel_batchbuffer.h"
  40 #include "intel_tex.h"
  41 #include "intel_fbo.h"
  42
  43 #include "brw_context.h"
  44 #include "brw_state.h"
  45 #include "brw_defines.h"
  46
  47
  48 static GLuint translate_tex_target( GLenum target )
  49 {
  50    switch (target) {
  51    case GL_TEXTURE_1D:
  52       return BRW_SURFACE_1D;
  53
  54    case GL_TEXTURE_RECTANGLE_NV:
  55       return BRW_SURFACE_2D;
  56
  57    case GL_TEXTURE_2D:
  58       return BRW_SURFACE_2D;
  59
  60    case GL_TEXTURE_3D:
  61       return BRW_SURFACE_3D;
  62
  63    case GL_TEXTURE_CUBE_MAP:
  64       return BRW_SURFACE_CUBE;
  65
  66    default:
  67       assert(0);
  68       return 0;
  69    }
  70 }
  71
  72
  73 static GLuint translate_tex_format( GLuint mesa_format, GLenum internal_format,
  74                                     GLenum depth_mode )
  75 {
  76    switch( mesa_format ) {
  77    case MESA_FORMAT_L8:
  78       return BRW_SURFACEFORMAT_L8_UNORM;
  79
  80    case MESA_FORMAT_I8:
  81       return BRW_SURFACEFORMAT_I8_UNORM;
  82
  83    case MESA_FORMAT_A8:
  84       return BRW_SURFACEFORMAT_A8_UNORM;
  85
  86    case MESA_FORMAT_AL88:
  87       return BRW_SURFACEFORMAT_L8A8_UNORM;
  88
  89    case MESA_FORMAT_RGB888:
  90       assert(0);                /* not supported for sampling */
  91       return BRW_SURFACEFORMAT_R8G8B8_UNORM;
  92
  93    case MESA_FORMAT_ARGB8888:
  94       if (internal_format == GL_RGB)
  95          return BRW_SURFACEFORMAT_B8G8R8X8_UNORM;
  96       else
  97          return BRW_SURFACEFORMAT_B8G8R8A8_UNORM;
  98
  99    case MESA_FORMAT_RGBA8888_REV:
 100       if (internal_format == GL_RGB)
 101          return BRW_SURFACEFORMAT_R8G8B8X8_UNORM;
 102       else
 103          return BRW_SURFACEFORMAT_R8G8B8A8_UNORM;
 104
 105    case MESA_FORMAT_RGB565:
 106       return BRW_SURFACEFORMAT_B5G6R5_UNORM;
 107
 108    case MESA_FORMAT_ARGB1555:
 109       return BRW_SURFACEFORMAT_B5G5R5A1_UNORM;
 110
 111    case MESA_FORMAT_ARGB4444:
 112       return BRW_SURFACEFORMAT_B4G4R4A4_UNORM;
 113
 114    case MESA_FORMAT_YCBCR_REV:
 115       return BRW_SURFACEFORMAT_YCRCB_NORMAL;
 116
 117    case MESA_FORMAT_YCBCR:
 118       return BRW_SURFACEFORMAT_YCRCB_SWAPUVY;
 119
 120    case MESA_FORMAT_RGB_FXT1:
 121    case MESA_FORMAT_RGBA_FXT1:
 122       return BRW_SURFACEFORMAT_FXT1;
 123
 124    case MESA_FORMAT_Z16:
 125       if (depth_mode == GL_INTENSITY)
 126           return BRW_SURFACEFORMAT_I16_UNORM;
 127       else if (depth_mode == GL_ALPHA)
 128           return BRW_SURFACEFORMAT_A16_UNORM;
 129       else
 130           return BRW_SURFACEFORMAT_L16_UNORM;
 131
 132    case MESA_FORMAT_RGB_DXT1:
 133        return BRW_SURFACEFORMAT_DXT1_RGB;
 134
 135    case MESA_FORMAT_RGBA_DXT1:
 136        return BRW_SURFACEFORMAT_BC1_UNORM;
 137
 138    case MESA_FORMAT_RGBA_DXT3:
 139        return BRW_SURFACEFORMAT_BC2_UNORM;
 140
 141    case MESA_FORMAT_RGBA_DXT5:
 142        return BRW_SURFACEFORMAT_BC3_UNORM;
 143
 144    case MESA_FORMAT_SARGB8:
 145       return BRW_SURFACEFORMAT_B8G8R8A8_UNORM_SRGB;
 146
 147    case MESA_FORMAT_SLA8:
 148       return BRW_SURFACEFORMAT_L8A8_UNORM_SRGB;
 149
 150    case MESA_FORMAT_SL8:
 151       return BRW_SURFACEFORMAT_L8_UNORM_SRGB;
 152
 153    case MESA_FORMAT_SRGB_DXT1:
 154       return BRW_SURFACEFORMAT_BC1_UNORM_SRGB;
 155
 156    case MESA_FORMAT_S8_Z24:
 157       /* XXX: these different surface formats don't seem to
 158        * make any difference for shadow sampler/compares.
 159        */
 160       if (depth_mode == GL_INTENSITY)
 161          return BRW_SURFACEFORMAT_I24X8_UNORM;
 162       else if (depth_mode == GL_ALPHA)
 163          return BRW_SURFACEFORMAT_A24X8_UNORM;
 164       else
 165          return BRW_SURFACEFORMAT_L24X8_UNORM;
 166
 167    case MESA_FORMAT_DUDV8:
 168       return BRW_SURFACEFORMAT_R8G8_SNORM;
 169
 170    case MESA_FORMAT_SIGNED_RGBA8888_REV:
 171       return BRW_SURFACEFORMAT_R8G8B8A8_SNORM;
 172
 173    default:
 174       assert(0);
 175       return 0;
 176    }
 177 }
 178
 179 static void
 180 brw_set_surface_tiling(struct brw_surface_state *surf, uint32_t tiling)
 181 {
 182    switch (tiling) {
 183    case I915_TILING_NONE:
 184       surf->ss3.tiled_surface = 0;
 185       surf->ss3.tile_walk = 0;
 186       break;
 187    case I915_TILING_X:
 188       surf->ss3.tiled_surface = 1;
 189       surf->ss3.tile_walk = BRW_TILEWALK_XMAJOR;
 190       break;
 191    case I915_TILING_Y:
 192       surf->ss3.tiled_surface = 1;
 193       surf->ss3.tile_walk = BRW_TILEWALK_YMAJOR;
 194       break;
 195    }
 196 }
 197
 198 static dri_bo *
 199 brw_create_texture_surface( struct brw_context *brw,
 200                             struct brw_surface_key *key )
 201 {
 202    struct brw_surface_state surf;
 203    dri_bo *bo;
 204
 205    memset(&surf, 0, sizeof(surf));
 206
 207    surf.ss0.mipmap_layout_mode = BRW_SURFACE_MIPMAPLAYOUT_BELOW;
 208    surf.ss0.surface_type = translate_tex_target(key->target);
 209    if (key->bo) {
 210       surf.ss0.surface_format = translate_tex_format(key->format,
 211                                                      key->internal_format,
 212                                                      key->depthmode);
 213    }
 214    else {
 215       switch (key->depth) {
 216       case 32:
 217          surf.ss0.surface_format = BRW_SURFACEFORMAT_B8G8R8A8_UNORM;
 218          break;
 219       default:
 220       case 24:
 221          surf.ss0.surface_format = BRW_SURFACEFORMAT_B8G8R8X8_UNORM;
 222          break;
 223       case 16:
 224          surf.ss0.surface_format = BRW_SURFACEFORMAT_B5G6R5_UNORM;
 225          break;
 226       }
 227    }
 228
 229    /* This is ok for all textures with channel width 8bit or less:
 230     */
 231 /*    surf.ss0.data_return_format = BRW_SURFACERETURNFORMAT_S1; */
 232    if (key->bo)
 233       surf.ss1.base_addr = key->bo->offset; /* reloc */
 234    else
 235       surf.ss1.base_addr = key->offset;
 236
 237    surf.ss2.mip_count = key->last_level - key->first_level;
 238    surf.ss2.width = key->width - 1;
 239    surf.ss2.height = key->height - 1;
 240    brw_set_surface_tiling(&surf, key->tiling);
 241    surf.ss3.pitch = (key->pitch * key->cpp) - 1;
 242    surf.ss3.depth = key->depth - 1;
 243
 244    surf.ss4.min_lod = 0;
 245
 246    if (key->target == GL_TEXTURE_CUBE_MAP) {
 247       surf.ss0.cube_pos_x = 1;
 248       surf.ss0.cube_pos_y = 1;
 249       surf.ss0.cube_pos_z = 1;
 250       surf.ss0.cube_neg_x = 1;
 251       surf.ss0.cube_neg_y = 1;
 252       surf.ss0.cube_neg_z = 1;
 253    }
 254
 255    bo = brw_upload_cache(&brw->surface_cache, BRW_SS_SURFACE,
 256                          key, sizeof(*key),
 257                          &key->bo, key->bo ? 1 : 0,
 258                          &surf, sizeof(surf),
 259                          NULL, NULL);
 260
 261    if (key->bo) {
 262       /* Emit relocation to surface contents */
 263       dri_bo_emit_reloc(bo,
 264                         I915_GEM_DOMAIN_SAMPLER, 0,
 265                         0,
 266                         offsetof(struct brw_surface_state, ss1),
 267                         key->bo);
 268    }
 269    return bo;
 270 }
 271
 272 static void
 273 brw_update_texture_surface( GLcontext *ctx, GLuint unit )
 274 {
 275    struct brw_context *brw = brw_context(ctx);
 276    struct gl_texture_object *tObj = ctx->Texture.Unit[unit]._Current;
 277    struct intel_texture_object *intelObj = intel_texture_object(tObj);
 278    struct gl_texture_image *firstImage = tObj->Image[0][intelObj->firstLevel];
 279    struct brw_surface_key key;
 280    const GLuint surf = SURF_INDEX_TEXTURE(unit);
 281
 282    memset(&key, 0, sizeof(key));
 283
 284    if (intelObj->imageOverride) {
 285       key.pitch = intelObj->pitchOverride / intelObj->mt->cpp;
 286       key.depth = intelObj->depthOverride;
 287       key.bo = NULL;
 288       key.offset = intelObj->textureOffset;
 289    } else {
 290       key.format = firstImage->TexFormat;
 291       key.internal_format = firstImage->InternalFormat;
 292       key.pitch = intelObj->mt->pitch;
 293       key.depth = firstImage->Depth;
 294       key.bo = intelObj->mt->region->buffer;
 295       key.offset = 0;
 296    }
 297
 298    key.target = tObj->Target;
 299    key.depthmode = tObj->DepthMode;
 300    key.first_level = intelObj->firstLevel;
 301    key.last_level = intelObj->lastLevel;
 302    key.width = firstImage->Width;
 303    key.height = firstImage->Height;
 304    key.cpp = intelObj->mt->cpp;
 305    key.tiling = intelObj->mt->region->tiling;
 306
 307    dri_bo_unreference(brw->wm.surf_bo[surf]);
 308    brw->wm.surf_bo[surf] = brw_search_cache(&brw->surface_cache,
 309                                             BRW_SS_SURFACE,
 310                                             &key, sizeof(key),
 311                                             &key.bo, key.bo ? 1 : 0,
 312                                             NULL);
 313    if (brw->wm.surf_bo[surf] == NULL) {
 314       brw->wm.surf_bo[surf] = brw_create_texture_surface(brw, &key);
 315    }
 316 }
 317
 318
 319
 320 /**
 321  * Create the constant buffer surface.  Vertex/fragment shader constants will be
 322  * read from this buffer with Data Port Read instructions/messages.
 323  */
 324 dri_bo *
 325 brw_create_constant_surface( struct brw_context *brw,
 326                              struct brw_surface_key *key )
 327 {
 328    const GLint w = key->width - 1;
 329    struct brw_surface_state surf;
 330    dri_bo *bo;
 331
 332    memset(&surf, 0, sizeof(surf));
 333
 334    surf.ss0.mipmap_layout_mode = BRW_SURFACE_MIPMAPLAYOUT_BELOW;
 335    surf.ss0.surface_type = BRW_SURFACE_BUFFER;
 336    surf.ss0.surface_format = BRW_SURFACEFORMAT_R32G32B32A32_FLOAT;
 337
 338    assert(key->bo);
 339    if (key->bo)
 340       surf.ss1.base_addr = key->bo->offset; /* reloc */
 341    else
 342       surf.ss1.base_addr = key->offset;
 343
 344    surf.ss2.width = w & 0x7f;            /* bits 6:0 of size or width */
 345    surf.ss2.height = (w >> 7) & 0x1fff;  /* bits 19:7 of size or width */
 346    surf.ss3.depth = (w >> 20) & 0x7f;    /* bits 26:20 of size or width */
 347    surf.ss3.pitch = (key->pitch * key->cpp) - 1; /* ignored?? */
 348    brw_set_surface_tiling(&surf, key->tiling); /* tiling now allowed */
 349
 350    bo = brw_upload_cache(&brw->surface_cache, BRW_SS_SURFACE,
 351                          key, sizeof(*key),
 352                          &key->bo, key->bo ? 1 : 0,
 353                          &surf, sizeof(surf),
 354                          NULL, NULL);
 355
 356    if (key->bo) {
 357       /* Emit relocation to surface contents */
 358       dri_bo_emit_reloc(bo,
 359                         I915_GEM_DOMAIN_SAMPLER, 0,
 360                         0,
 361                         offsetof(struct brw_surface_state, ss1),
 362                         key->bo);
 363    }
 364
 365    return bo;
 366 }
 367
 368 /* Creates a new WM constant buffer reflecting the current fragment program's
 369  * constants, if needed by the fragment program.
 370  *
 371  * Otherwise, constants go through the CURBEs using the brw_constant_buffer
 372  * state atom.
 373  */
 374 static drm_intel_bo *
 375 brw_wm_update_constant_buffer(struct brw_context *brw)
 376 {
 377    struct intel_context *intel = &brw->intel;
 378    struct brw_fragment_program *fp =
 379       (struct brw_fragment_program *) brw->fragment_program;
 380    const struct gl_program_parameter_list *params = fp->program.Base.Parameters;
 381    const int size = params->NumParameters * 4 * sizeof(GLfloat);
 382    drm_intel_bo *const_buffer;
 383
 384    /* BRW_NEW_FRAGMENT_PROGRAM */
 385    if (!fp->use_const_buffer)
 386       return NULL;
 387
 388    const_buffer = drm_intel_bo_alloc(intel->bufmgr, "fp_const_buffer",
 389                                      size, 64);
 390
 391    /* _NEW_PROGRAM_CONSTANTS */
 392    dri_bo_subdata(const_buffer, 0, size, params->ParameterValues);
 393
 394    return const_buffer;
 395 }
 396
 397 /**
 398  * Update the surface state for a WM constant buffer.
 399  * The constant buffer will be (re)allocated here if needed.
 400  */
 401 static void
 402 brw_update_wm_constant_surface( GLcontext *ctx,
 403                                 GLuint surf)
 404 {
 405    struct brw_context *brw = brw_context(ctx);
 406    struct brw_surface_key key;
 407    struct brw_fragment_program *fp =
 408       (struct brw_fragment_program *) brw->fragment_program;
 409    const struct gl_program_parameter_list *params =
 410       fp->program.Base.Parameters;
 411
 412    /* If we're in this state update atom, we need to update WM constants, so
 413     * free the old buffer and create a new one for the new contents.
 414     */
 415    dri_bo_unreference(fp->const_buffer);
 416    fp->const_buffer = brw_wm_update_constant_buffer(brw);
 417
 418    /* If there's no constant buffer, then no surface BO is needed to point at
 419     * it.
 420     */
 421    if (fp->const_buffer == 0) {
 422       drm_intel_bo_unreference(brw->wm.surf_bo[surf]);
 423       brw->wm.surf_bo[surf] = NULL;
 424       return;
 425    }
 426
 427    memset(&key, 0, sizeof(key));
 428
 429    key.format = MESA_FORMAT_RGBA_FLOAT32;
 430    key.internal_format = GL_RGBA;
 431    key.bo = fp->const_buffer;
 432    key.depthmode = GL_NONE;
 433    key.pitch = params->NumParameters;
 434    key.width = params->NumParameters;
 435    key.height = 1;
 436    key.depth = 1;
 437    key.cpp = 16;
 438
 439    /*
 440    printf("%s:\n", __FUNCTION__);
 441    printf("  width %d  height %d  depth %d  cpp %d  pitch %d\n",
 442           key.width, key.height, key.depth, key.cpp, key.pitch);
 443    */
 444
 445    dri_bo_unreference(brw->wm.surf_bo[surf]);
 446    brw->wm.surf_bo[surf] = brw_search_cache(&brw->surface_cache,
 447                                             BRW_SS_SURFACE,
 448                                             &key, sizeof(key),
 449                                             &key.bo, key.bo ? 1 : 0,
 450                                             NULL);
 451    if (brw->wm.surf_bo[surf] == NULL) {
 452       brw->wm.surf_bo[surf] = brw_create_constant_surface(brw, &key);
 453    }
 454    brw->state.dirty.brw |= BRW_NEW_WM_SURFACES;
 455 }
 456
 457 /**
 458  * Updates surface / buffer for fragment shader constant buffer, if
 459  * one is required.
 460  *
 461  * This consumes the state updates for the constant buffer, and produces
 462  * BRW_NEW_WM_SURFACES to get picked up by brw_prepare_wm_surfaces for
 463  * inclusion in the binding table.
 464  */
 465 static void prepare_wm_constant_surface(struct brw_context *brw )
 466 {
 467    GLcontext *ctx = &brw->intel.ctx;
 468    struct brw_fragment_program *fp =
 469       (struct brw_fragment_program *) brw->fragment_program;
 470    GLuint surf = SURF_INDEX_FRAG_CONST_BUFFER;
 471
 472    drm_intel_bo_unreference(fp->const_buffer);
 473    fp->const_buffer = brw_wm_update_constant_buffer(brw);
 474
 475    /* If there's no constant buffer, then no surface BO is needed to point at
 476     * it.
 477     */
 478    if (fp->const_buffer == 0) {
 479       if (brw->wm.surf_bo[surf] != NULL) {
 480          drm_intel_bo_unreference(brw->wm.surf_bo[surf]);
 481          brw->wm.surf_bo[surf] = NULL;
 482          brw->state.dirty.brw |= BRW_NEW_WM_SURFACES;
 483       }
 484       return;
 485    }
 486
 487    brw_update_wm_constant_surface(ctx, surf);
 488 }
 489
 490 const struct brw_tracked_state brw_wm_constant_surface = {
 491    .dirty = {
 492       .mesa = (_NEW_PROGRAM_CONSTANTS),
 493       .brw = (BRW_NEW_FRAGMENT_PROGRAM),
 494       .cache = 0
 495    },
 496    .prepare = prepare_wm_constant_surface,
 497 };
 498
 499
 500 /**
 501  * Sets up a surface state structure to point at the given region.
 502  * While it is only used for the front/back buffer currently, it should be
 503  * usable for further buffers when doing ARB_draw_buffer support.
 504  */
 505 static void
 506 brw_update_renderbuffer_surface(struct brw_context *brw,
 507                                 struct gl_renderbuffer *rb,
 508                                 unsigned int unit)
 509 {
 510    GLcontext *ctx = &brw->intel.ctx;
 511    dri_bo *region_bo = NULL;
 512    struct intel_renderbuffer *irb = intel_renderbuffer(rb);
 513    struct intel_region *region = irb ? irb->region : NULL;
 514    struct {
 515       unsigned int surface_type;
 516       unsigned int surface_format;
 517       unsigned int width, height, pitch, cpp;
 518       GLubyte color_mask[4];
 519       GLboolean color_blend;
 520       uint32_t tiling;
 521       uint32_t draw_offset;
 522    } key;
 523
 524    memset(&key, 0, sizeof(key));
 525
 526    if (region != NULL) {
 527       region_bo = region->buffer;
 528
 529       key.surface_type = BRW_SURFACE_2D;
 530       switch (irb->texformat) {
 531       case MESA_FORMAT_ARGB8888:
 532          key.surface_format = BRW_SURFACEFORMAT_B8G8R8A8_UNORM;
 533          break;
 534       case MESA_FORMAT_RGB565:
 535          key.surface_format = BRW_SURFACEFORMAT_B5G6R5_UNORM;
 536          break;
 537       case MESA_FORMAT_ARGB1555:
 538          key.surface_format = BRW_SURFACEFORMAT_B5G5R5A1_UNORM;
 539          break;
 540       case MESA_FORMAT_ARGB4444:
 541          key.surface_format = BRW_SURFACEFORMAT_B4G4R4A4_UNORM;
 542          break;
 543       default:
 544          _mesa_problem(ctx, "Bad renderbuffer format: %d\n", irb->texformat);
 545       }
 546       key.tiling = region->tiling;
 547       if (brw->intel.intelScreen->driScrnPriv->dri2.enabled) {
 548          key.width = rb->Width;
 549          key.height = rb->Height;
 550       } else {
 551          key.width = region->width;
 552          key.height = region->height;
 553       }
 554       key.pitch = region->pitch;
 555       key.cpp = region->cpp;
 556       key.draw_offset = region->draw_offset; /* cur 3d or cube face offset */
 557    } else {
 558       key.surface_type = BRW_SURFACE_NULL;
 559       key.surface_format = BRW_SURFACEFORMAT_B8G8R8A8_UNORM;
 560       key.tiling = I915_TILING_X;
 561       key.width = 1;
 562       key.height = 1;
 563       key.cpp = 4;
 564       key.draw_offset = 0;
 565    }
 566    memcpy(key.color_mask, ctx->Color.ColorMask,
 567           sizeof(key.color_mask));
 568    key.color_blend = (!ctx->Color._LogicOpEnabled &&
 569                       ctx->Color.BlendEnabled);
 570
 571    dri_bo_unreference(brw->wm.surf_bo[unit]);
 572    brw->wm.surf_bo[unit] = brw_search_cache(&brw->surface_cache,
 573                                             BRW_SS_SURFACE,
 574                                             &key, sizeof(key),
 575                                             &region_bo, 1,
 576                                             NULL);
 577
 578    if (brw->wm.surf_bo[unit] == NULL) {
 579       struct brw_surface_state surf;
 580
 581       memset(&surf, 0, sizeof(surf));
 582
 583       surf.ss0.surface_format = key.surface_format;
 584       surf.ss0.surface_type = key.surface_type;
 585       if (key.tiling == I915_TILING_NONE) {
 586          surf.ss1.base_addr = key.draw_offset;
 587       } else {
 588          uint32_t tile_offset = key.draw_offset % 4096;
 589
 590          surf.ss1.base_addr = key.draw_offset - tile_offset;
 591
 592          assert(BRW_IS_G4X(brw) || tile_offset == 0);
 593          if (BRW_IS_G4X(brw)) {
 594             if (key.tiling == I915_TILING_X) {
 595                /* Note that the low bits of these fields are missing, so
 596                 * there's the possibility of getting in trouble.
 597                 */
 598                surf.ss5.x_offset = (tile_offset % 512) / key.cpp / 4;
 599                surf.ss5.y_offset = tile_offset / 512 / 2;
 600             } else {
 601                surf.ss5.x_offset = (tile_offset % 128) / key.cpp / 4;
 602                surf.ss5.y_offset = tile_offset / 128 / 2;
 603             }
 604          }
 605       }
 606       if (region_bo != NULL)
 607          surf.ss1.base_addr += region_bo->offset; /* reloc */
 608
 609       surf.ss2.width = key.width - 1;
 610       surf.ss2.height = key.height - 1;
 611       brw_set_surface_tiling(&surf, key.tiling);
 612       surf.ss3.pitch = (key.pitch * key.cpp) - 1;
 613
 614       /* _NEW_COLOR */
 615       surf.ss0.color_blend = key.color_blend;
 616       surf.ss0.writedisable_red =   !key.color_mask[0];
 617       surf.ss0.writedisable_green = !key.color_mask[1];
 618       surf.ss0.writedisable_blue =  !key.color_mask[2];
 619       surf.ss0.writedisable_alpha = !key.color_mask[3];
 620
 621       /* Key size will never match key size for textures, so we're safe. */
 622       brw->wm.surf_bo[unit] = brw_upload_cache(&brw->surface_cache,
 623                                                BRW_SS_SURFACE,
 624                                                &key, sizeof(key),
 625                                                &region_bo, 1,
 626                                                &surf, sizeof(surf),
 627                                                NULL, NULL);
 628       if (region_bo != NULL) {
 629          /* We might sample from it, and we might render to it, so flag
 630           * them both.  We might be able to figure out from other state
 631           * a more restrictive relocation to emit.
 632           */
 633          drm_intel_bo_emit_reloc(brw->wm.surf_bo[unit],
 634                                  offsetof(struct brw_surface_state, ss1),
 635                                  region_bo,
 636                                  surf.ss1.base_addr - region_bo->offset,
 637                                  I915_GEM_DOMAIN_RENDER,
 638                                  I915_GEM_DOMAIN_RENDER);
 639       }
 640    }
 641 }
 642
 643
 644 /**
 645  * Constructs the binding table for the WM surface state, which maps unit
 646  * numbers to surface state objects.
 647  */
 648 static dri_bo *
 649 brw_wm_get_binding_table(struct brw_context *brw)
 650 {
 651    dri_bo *bind_bo;
 652
 653    assert(brw->wm.nr_surfaces <= BRW_WM_MAX_SURF);
 654
 655    bind_bo = brw_search_cache(&brw->surface_cache, BRW_SS_SURF_BIND,
 656                               NULL, 0,
 657                               brw->wm.surf_bo, brw->wm.nr_surfaces,
 658                               NULL);
 659
 660    if (bind_bo == NULL) {
 661       GLuint data_size = brw->wm.nr_surfaces * sizeof(GLuint);
 662       uint32_t *data = malloc(data_size);
 663       int i;
 664
 665       for (i = 0; i < brw->wm.nr_surfaces; i++)
 666          if (brw->wm.surf_bo[i])
 667             data[i] = brw->wm.surf_bo[i]->offset;
 668          else
 669             data[i] = 0;
 670
 671       bind_bo = brw_upload_cache( &brw->surface_cache, BRW_SS_SURF_BIND,
 672                                   NULL, 0,
 673                                   brw->wm.surf_bo, brw->wm.nr_surfaces,
 674                                   data, data_size,
 675                                   NULL, NULL);
 676
 677       /* Emit binding table relocations to surface state */
 678       for (i = 0; i < BRW_WM_MAX_SURF; i++) {
 679          if (brw->wm.surf_bo[i] != NULL) {
 680             dri_bo_emit_reloc(bind_bo,
 681                               I915_GEM_DOMAIN_INSTRUCTION, 0,
 682                               0,
 683                               i * sizeof(GLuint),
 684                               brw->wm.surf_bo[i]);
 685          }
 686       }
 687
 688       free(data);
 689    }
 690
 691    return bind_bo;
 692 }
 693
 694 static void prepare_wm_surfaces(struct brw_context *brw )
 695 {
 696    GLcontext *ctx = &brw->intel.ctx;
 697    struct intel_context *intel = &brw->intel;
 698    GLuint i;
 699    int old_nr_surfaces;
 700
 701    /* _NEW_BUFFERS */
 702    /* Update surfaces for drawing buffers */
 703    if (ctx->DrawBuffer->_NumColorDrawBuffers >= 1) {
 704       for (i = 0; i < ctx->DrawBuffer->_NumColorDrawBuffers; i++) {
 705          brw_update_renderbuffer_surface(brw,
 706                                          ctx->DrawBuffer->_ColorDrawBuffers[i],
 707                                          i);
 708       }
 709    } else {
 710       brw_update_renderbuffer_surface(brw, NULL, 0);
 711    }
 712
 713    old_nr_surfaces = brw->wm.nr_surfaces;
 714    brw->wm.nr_surfaces = MAX_DRAW_BUFFERS;
 715
 716    if (brw->wm.surf_bo[SURF_INDEX_FRAG_CONST_BUFFER] != NULL)
 717        brw->wm.nr_surfaces = SURF_INDEX_FRAG_CONST_BUFFER + 1;
 718
 719    /* Update surfaces for textures */
 720    for (i = 0; i < BRW_MAX_TEX_UNIT; i++) {
 721       const struct gl_texture_unit *texUnit = &ctx->Texture.Unit[i];
 722       const GLuint surf = SURF_INDEX_TEXTURE(i);
 723
 724       /* _NEW_TEXTURE, BRW_NEW_TEXDATA */
 725       if (texUnit->_ReallyEnabled) {
 726          if (texUnit->_Current == intel->frame_buffer_texobj) {
 727             /* render to texture */
 728             dri_bo_unreference(brw->wm.surf_bo[surf]);
 729             brw->wm.surf_bo[surf] = brw->wm.surf_bo[0];
 730             dri_bo_reference(brw->wm.surf_bo[surf]);
 731             brw->wm.nr_surfaces = surf + 1;
 732          } else {
 733             /* regular texture */
 734             brw_update_texture_surface(ctx, i);
 735             brw->wm.nr_surfaces = surf + 1;
 736          }
 737       } else {
 738          dri_bo_unreference(brw->wm.surf_bo[surf]);
 739          brw->wm.surf_bo[surf] = NULL;
 740       }
 741    }
 742
 743    dri_bo_unreference(brw->wm.bind_bo);
 744    brw->wm.bind_bo = brw_wm_get_binding_table(brw);
 745
 746    if (brw->wm.nr_surfaces != old_nr_surfaces)
 747       brw->state.dirty.brw |= BRW_NEW_NR_WM_SURFACES;
 748 }
 749
 750 const struct brw_tracked_state brw_wm_surfaces = {
 751    .dirty = {
 752       .mesa = (_NEW_COLOR |
 753                _NEW_TEXTURE |
 754                _NEW_BUFFERS),
 755       .brw = (BRW_NEW_CONTEXT |
 756               BRW_NEW_WM_SURFACES),
 757       .cache = 0
 758    },
 759    .prepare = prepare_wm_surfaces,
 760 };
 761
 762
 763