2 * Copyright © 2009 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * Eric Anholt <eric@anholt.net>
28 #include "brw_context.h"
29 #include "brw_state.h"
30 #include "brw_defines.h"
32 #include "program/prog_parameter.h"
33 #include "program/prog_statevars.h"
34 #include "intel_batchbuffer.h"
37 gen6_upload_vec4_push_constants(struct brw_context
*brw
,
38 const struct gl_program
*prog
,
39 const struct brw_vec4_prog_data
*prog_data
,
40 struct brw_stage_state
*stage_state
,
41 enum state_struct_type type
)
43 struct gl_context
*ctx
= &brw
->ctx
;
45 /* Updates the ParamaterValues[i] pointers for all parameters of the
46 * basic type of PROGRAM_STATE_VAR.
48 /* XXX: Should this happen somewhere before to get our state flag set? */
49 _mesa_load_state_parameters(ctx
, prog
->Parameters
);
51 if (prog_data
->base
.nr_params
== 0) {
52 stage_state
->push_const_size
= 0;
58 param
= brw_state_batch(brw
, type
,
59 prog_data
->base
.nr_params
* sizeof(float),
60 32, &stage_state
->push_const_offset
);
62 /* _NEW_PROGRAM_CONSTANTS
64 * Also _NEW_TRANSFORM -- we may reference clip planes other than as a
65 * side effect of dereferencing uniforms, so _NEW_PROGRAM_CONSTANTS
66 * wouldn't be set for them.
68 for (i
= 0; i
< prog_data
->base
.nr_params
; i
++) {
69 param
[i
] = *prog_data
->base
.param
[i
];
71 params_uploaded
= prog_data
->base
.nr_params
/ 4;
74 fprintf(stderr
, "Constant buffer:\n");
75 for (i
= 0; i
< params_uploaded
; i
++) {
76 float *buf
= param
+ i
* 4;
77 fprintf(stderr
, "%d: %f %f %f %f\n",
78 i
, buf
[0], buf
[1], buf
[2], buf
[3]);
82 stage_state
->push_const_size
= (params_uploaded
+ 1) / 2;
83 /* We can only push 32 registers of constants at a time. */
84 assert(stage_state
->push_const_size
<= 32);
89 gen6_upload_vs_push_constants(struct brw_context
*brw
)
91 struct brw_stage_state
*stage_state
= &brw
->vs
.base
;
93 /* _BRW_NEW_VERTEX_PROGRAM */
94 const struct brw_vertex_program
*vp
=
95 brw_vertex_program_const(brw
->vertex_program
);
96 /* CACHE_NEW_VS_PROG */
97 const struct brw_vec4_prog_data
*prog_data
= &brw
->vs
.prog_data
->base
;
99 gen6_upload_vec4_push_constants(brw
, &vp
->program
.Base
, prog_data
,
100 stage_state
, AUB_TRACE_VS_CONSTANTS
);
103 const struct brw_tracked_state gen6_vs_push_constants
= {
105 .mesa
= _NEW_TRANSFORM
| _NEW_PROGRAM_CONSTANTS
,
106 .brw
= (BRW_NEW_BATCH
|
107 BRW_NEW_VERTEX_PROGRAM
),
108 .cache
= CACHE_NEW_VS_PROG
,
110 .emit
= gen6_upload_vs_push_constants
,
114 upload_vs_state(struct brw_context
*brw
)
116 struct gl_context
*ctx
= &brw
->ctx
;
117 const struct brw_stage_state
*stage_state
= &brw
->vs
.base
;
118 uint32_t floating_point_mode
= 0;
120 /* From the BSpec, 3D Pipeline > Geometry > Vertex Shader > State,
121 * 3DSTATE_VS, Dword 5.0 "VS Function Enable":
123 * [DevSNB] A pipeline flush must be programmed prior to a 3DSTATE_VS
124 * command that causes the VS Function Enable to toggle. Pipeline
125 * flush can be executed by sending a PIPE_CONTROL command with CS
126 * stall bit set and a post sync operation.
128 * Although we don't disable the VS during normal drawing, BLORP sometimes
129 * disables it. To be safe, do the flush here just in case.
131 intel_emit_post_sync_nonzero_flush(brw
);
133 if (stage_state
->push_const_size
== 0) {
134 /* Disable the push constant buffers. */
136 OUT_BATCH(_3DSTATE_CONSTANT_VS
<< 16 | (5 - 2));
144 OUT_BATCH(_3DSTATE_CONSTANT_VS
<< 16 |
145 GEN6_CONSTANT_BUFFER_0_ENABLE
|
147 /* Pointer to the VS constant buffer. Covered by the set of
148 * state flags from gen6_upload_vs_constants
150 OUT_BATCH(stage_state
->push_const_offset
+
151 stage_state
->push_const_size
- 1);
158 /* Use ALT floating point mode for ARB vertex programs, because they
161 if (ctx
->Shader
.CurrentProgram
[MESA_SHADER_VERTEX
] == NULL
)
162 floating_point_mode
= GEN6_VS_FLOATING_POINT_MODE_ALT
;
165 OUT_BATCH(_3DSTATE_VS
<< 16 | (6 - 2));
166 OUT_BATCH(stage_state
->prog_offset
);
167 OUT_BATCH(floating_point_mode
|
168 ((ALIGN(stage_state
->sampler_count
, 4)/4) << GEN6_VS_SAMPLER_COUNT_SHIFT
) |
169 ((brw
->vs
.prog_data
->base
.base
.binding_table
.size_bytes
/ 4) <<
170 GEN6_VS_BINDING_TABLE_ENTRY_COUNT_SHIFT
));
172 if (brw
->vs
.prog_data
->base
.total_scratch
) {
173 OUT_RELOC(stage_state
->scratch_bo
,
174 I915_GEM_DOMAIN_RENDER
, I915_GEM_DOMAIN_RENDER
,
175 ffs(brw
->vs
.prog_data
->base
.total_scratch
) - 11);
180 OUT_BATCH((brw
->vs
.prog_data
->base
.dispatch_grf_start_reg
<<
181 GEN6_VS_DISPATCH_START_GRF_SHIFT
) |
182 (brw
->vs
.prog_data
->base
.urb_read_length
<< GEN6_VS_URB_READ_LENGTH_SHIFT
) |
183 (0 << GEN6_VS_URB_ENTRY_READ_OFFSET_SHIFT
));
185 OUT_BATCH(((brw
->max_vs_threads
- 1) << GEN6_VS_MAX_THREADS_SHIFT
) |
186 GEN6_VS_STATISTICS_ENABLE
|
190 /* Based on my reading of the simulator, the VS constants don't get
191 * pulled into the VS FF unit until an appropriate pipeline flush
192 * happens, and instead the 3DSTATE_CONSTANT_VS packet just adds
193 * references to them into a little FIFO. The flushes are common,
194 * but don't reliably happen between this and a 3DPRIMITIVE, causing
195 * the primitive to use the wrong constants. Then the FIFO
196 * containing the constant setup gets added to again on the next
197 * constants change, and eventually when a flush does happen the
198 * unit is overwhelmed by constant changes and dies.
200 * To avoid this, send a PIPE_CONTROL down the line that will
201 * update the unit immediately loading the constants. The flush
202 * type bits here were those set by the STATE_BASE_ADDRESS whose
203 * move in a82a43e8d99e1715dd11c9c091b5ab734079b6a6 triggered the
204 * bug reports that led to this workaround, and may be more than
205 * what is strictly required to avoid the issue.
207 intel_emit_post_sync_nonzero_flush(brw
);
208 brw_emit_pipe_control_flush(brw
,
209 PIPE_CONTROL_DEPTH_STALL
|
210 PIPE_CONTROL_INSTRUCTION_FLUSH
|
211 PIPE_CONTROL_STATE_CACHE_INVALIDATE
);
214 const struct brw_tracked_state gen6_vs_state
= {
216 .mesa
= _NEW_TRANSFORM
| _NEW_PROGRAM_CONSTANTS
,
217 .brw
= (BRW_NEW_CONTEXT
|
218 BRW_NEW_VERTEX_PROGRAM
|
220 BRW_NEW_PUSH_CONSTANT_ALLOCATION
),
221 .cache
= CACHE_NEW_VS_PROG
| CACHE_NEW_SAMPLER
223 .emit
= upload_vs_state
,