2 * Copyright © 2011 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
23 #include "main/mtypes.h"
24 #include "main/blend.h"
25 #include "main/samplerobj.h"
26 #include "main/texformat.h"
27 #include "program/prog_parameter.h"
29 #include "intel_mipmap_tree.h"
30 #include "intel_batchbuffer.h"
31 #include "intel_tex.h"
32 #include "intel_fbo.h"
33 #include "intel_buffer_objects.h"
35 #include "brw_context.h"
36 #include "brw_state.h"
37 #include "brw_defines.h"
41 * Convert an swizzle enumeration (i.e. SWIZZLE_X) to one of the Gen7.5+
42 * "Shader Channel Select" enumerations (i.e. HSW_SCS_RED)
45 brw_swizzle_to_scs(GLenum swizzle
, bool need_green_to_blue
)
51 return need_green_to_blue
? HSW_SCS_BLUE
: HSW_SCS_GREEN
;
62 assert(!"Should not get here: invalid swizzle mode");
67 gen7_surface_tiling_mode(uint32_t tiling
)
71 return GEN7_SURFACE_TILING_X
;
73 return GEN7_SURFACE_TILING_Y
;
75 return GEN7_SURFACE_TILING_NONE
;
81 gen7_surface_msaa_bits(unsigned num_samples
, enum intel_msaa_layout layout
)
85 assert(num_samples
<= 8);
87 /* The SURFACE_MULTISAMPLECOUNT_X enums are simply log2(num_samples) << 3. */
88 ss4
|= (ffs(MAX2(num_samples
, 1)) - 1) << 3;
90 if (layout
== INTEL_MSAA_LAYOUT_IMS
)
91 ss4
|= GEN7_SURFACE_MSFMT_DEPTH_STENCIL
;
93 ss4
|= GEN7_SURFACE_MSFMT_MSS
;
100 gen7_set_surface_mcs_info(struct brw_context
*brw
,
102 uint32_t surf_offset
,
103 const struct intel_mipmap_tree
*mcs_mt
,
104 bool is_render_target
)
106 /* From the Ivy Bridge PRM, Vol4 Part1 p76, "MCS Base Address":
108 * "The MCS surface must be stored as Tile Y."
110 assert(mcs_mt
->region
->tiling
== I915_TILING_Y
);
112 /* Compute the pitch in units of tiles. To do this we need to divide the
113 * pitch in bytes by 128, since a single Y-tile is 128 bytes wide.
115 unsigned pitch_tiles
= mcs_mt
->region
->pitch
/ 128;
117 /* The upper 20 bits of surface state DWORD 6 are the upper 20 bits of the
118 * GPU address of the MCS buffer; the lower 12 bits contain other control
119 * information. Since buffer addresses are always on 4k boundaries (and
120 * thus have their lower 12 bits zero), we can use an ordinary reloc to do
121 * the necessary address translation.
123 assert ((mcs_mt
->region
->bo
->offset64
& 0xfff) == 0);
125 surf
[6] = GEN7_SURFACE_MCS_ENABLE
|
126 SET_FIELD(pitch_tiles
- 1, GEN7_SURFACE_MCS_PITCH
) |
127 mcs_mt
->region
->bo
->offset64
;
129 drm_intel_bo_emit_reloc(brw
->batch
.bo
,
133 is_render_target
? I915_GEM_DOMAIN_RENDER
134 : I915_GEM_DOMAIN_SAMPLER
,
135 is_render_target
? I915_GEM_DOMAIN_RENDER
: 0);
140 gen7_check_surface_setup(uint32_t *surf
, bool is_render_target
)
142 unsigned num_multisamples
= surf
[4] & INTEL_MASK(5, 3);
143 unsigned multisampled_surface_storage_format
= surf
[4] & (1 << 6);
144 unsigned surface_array_spacing
= surf
[0] & (1 << 10);
145 bool is_multisampled
= num_multisamples
!= GEN7_SURFACE_MULTISAMPLECOUNT_1
;
147 (void) surface_array_spacing
;
149 /* From the Ivybridge PRM, Volume 4 Part 1, page 66 (RENDER_SURFACE_STATE
150 * dword 0 bit 10 "Surface Array Spacing" Programming Notes):
152 * If Multisampled Surface Storage Format is MSFMT_MSS and Number of
153 * Multisamples is not MULTISAMPLECOUNT_1, this field must be set to
156 if (multisampled_surface_storage_format
== GEN7_SURFACE_MSFMT_MSS
158 assert(surface_array_spacing
== GEN7_SURFACE_ARYSPC_LOD0
);
160 /* From the Ivybridge PRM, Volume 4 Part 1, page 72 (RENDER_SURFACE_STATE
161 * dword 4 bit 6 "Multisampled Surface Storage" Programming Notes):
163 * All multisampled render target surfaces must have this field set to
168 * This field is ignored if Number of Multisamples is MULTISAMPLECOUNT_1.
170 if (is_render_target
&& is_multisampled
) {
171 assert(multisampled_surface_storage_format
== GEN7_SURFACE_MSFMT_MSS
);
174 /* From the Ivybridge PRM, Volume 4 Part 1, page 72 (RENDER_SURFACE_STATE
175 * dword 4 bit 6 "Multisampled Surface Storage Format" Errata):
177 * If the surface’s Number of Multisamples is MULTISAMPLECOUNT_8, Width
178 * is >= 8192 (meaning the actual surface width is >= 8193 pixels), this
179 * field must be set to MSFMT_MSS.
181 uint32_t width
= GET_FIELD(surf
[2], GEN7_SURFACE_WIDTH
) + 1;
182 if (num_multisamples
== GEN7_SURFACE_MULTISAMPLECOUNT_8
&& width
>= 8193) {
183 assert(multisampled_surface_storage_format
== GEN7_SURFACE_MSFMT_MSS
);
186 /* From the Ivybridge PRM, Volume 4 Part 1, page 72 (RENDER_SURFACE_STATE
187 * dword 4 bit 6 "Multisampled Surface Storage Format" Errata):
189 * If the surface’s Number of Multisamples is MULTISAMPLECOUNT_8,
190 * ((Depth+1) * (Height+1)) is > 4,194,304, OR if the surface’s Number of
191 * Multisamples is MULTISAMPLECOUNT_4, ((Depth+1) * (Height+1)) is >
192 * 8,388,608, this field must be set to MSFMT_DEPTH_STENCIL.This field
193 * must be set to MSFMT_DEPTH_STENCIL if Surface Format is one of the
194 * following: I24X8_UNORM, L24X8_UNORM, A24X8_UNORM, or
195 * R24_UNORM_X8_TYPELESS.
197 * But also (from the Programming Notes):
199 * This field is ignored if Number of Multisamples is MULTISAMPLECOUNT_1.
201 uint32_t depth
= GET_FIELD(surf
[3], BRW_SURFACE_DEPTH
) + 1;
202 uint32_t height
= GET_FIELD(surf
[2], GEN7_SURFACE_HEIGHT
) + 1;
203 if (num_multisamples
== GEN7_SURFACE_MULTISAMPLECOUNT_8
&&
204 depth
* height
> 4194304) {
205 assert(multisampled_surface_storage_format
==
206 GEN7_SURFACE_MSFMT_DEPTH_STENCIL
);
208 if (num_multisamples
== GEN7_SURFACE_MULTISAMPLECOUNT_4
&&
209 depth
* height
> 8388608) {
210 assert(multisampled_surface_storage_format
==
211 GEN7_SURFACE_MSFMT_DEPTH_STENCIL
);
213 if (is_multisampled
) {
214 switch (GET_FIELD(surf
[0], BRW_SURFACE_FORMAT
)) {
215 case BRW_SURFACEFORMAT_I24X8_UNORM
:
216 case BRW_SURFACEFORMAT_L24X8_UNORM
:
217 case BRW_SURFACEFORMAT_A24X8_UNORM
:
218 case BRW_SURFACEFORMAT_R24_UNORM_X8_TYPELESS
:
219 assert(multisampled_surface_storage_format
==
220 GEN7_SURFACE_MSFMT_DEPTH_STENCIL
);
226 gen7_emit_buffer_surface_state(struct brw_context
*brw
,
227 uint32_t *out_offset
,
229 unsigned buffer_offset
,
230 unsigned surface_format
,
231 unsigned buffer_size
,
236 uint32_t *surf
= brw_state_batch(brw
, AUB_TRACE_SURFACE_STATE
,
237 8 * 4, 32, out_offset
);
238 memset(surf
, 0, 8 * 4);
240 surf
[0] = BRW_SURFACE_BUFFER
<< BRW_SURFACE_TYPE_SHIFT
|
241 surface_format
<< BRW_SURFACE_FORMAT_SHIFT
|
242 BRW_SURFACE_RC_READ_WRITE
;
243 surf
[1] = (bo
? bo
->offset64
: 0) + buffer_offset
; /* reloc */
244 surf
[2] = SET_FIELD((buffer_size
- 1) & 0x7f, GEN7_SURFACE_WIDTH
) |
245 SET_FIELD(((buffer_size
- 1) >> 7) & 0x3fff, GEN7_SURFACE_HEIGHT
);
246 surf
[3] = SET_FIELD(((buffer_size
- 1) >> 21) & 0x3f, BRW_SURFACE_DEPTH
) |
249 surf
[5] = SET_FIELD(mocs
, GEN7_SURFACE_MOCS
);
251 if (brw
->is_haswell
) {
252 surf
[7] |= (SET_FIELD(HSW_SCS_RED
, GEN7_SURFACE_SCS_R
) |
253 SET_FIELD(HSW_SCS_GREEN
, GEN7_SURFACE_SCS_G
) |
254 SET_FIELD(HSW_SCS_BLUE
, GEN7_SURFACE_SCS_B
) |
255 SET_FIELD(HSW_SCS_ALPHA
, GEN7_SURFACE_SCS_A
));
258 /* Emit relocation to surface contents */
260 drm_intel_bo_emit_reloc(brw
->batch
.bo
, *out_offset
+ 4,
261 bo
, buffer_offset
, I915_GEM_DOMAIN_SAMPLER
,
262 (rw
? I915_GEM_DOMAIN_SAMPLER
: 0));
265 gen7_check_surface_setup(surf
, false /* is_render_target */);
269 gen7_update_texture_surface(struct gl_context
*ctx
,
271 uint32_t *surf_offset
,
274 struct brw_context
*brw
= brw_context(ctx
);
275 struct gl_texture_object
*tObj
= ctx
->Texture
.Unit
[unit
]._Current
;
276 struct intel_texture_object
*intelObj
= intel_texture_object(tObj
);
277 struct intel_mipmap_tree
*mt
= intelObj
->mt
;
278 struct gl_texture_image
*firstImage
= tObj
->Image
[0][tObj
->BaseLevel
];
279 struct gl_sampler_object
*sampler
= _mesa_get_samplerobj(ctx
, unit
);
281 if (tObj
->Target
== GL_TEXTURE_BUFFER
) {
282 brw_update_buffer_texture_surface(ctx
, unit
, surf_offset
);
286 uint32_t *surf
= brw_state_batch(brw
, AUB_TRACE_SURFACE_STATE
,
287 8 * 4, 32, surf_offset
);
288 memset(surf
, 0, 8 * 4);
290 uint32_t tex_format
= translate_tex_format(brw
,
292 sampler
->sRGBDecode
);
294 if (for_gather
&& tex_format
== BRW_SURFACEFORMAT_R32G32_FLOAT
)
295 tex_format
= BRW_SURFACEFORMAT_R32G32_FLOAT_LD
;
297 surf
[0] = translate_tex_target(tObj
->Target
) << BRW_SURFACE_TYPE_SHIFT
|
298 tex_format
<< BRW_SURFACE_FORMAT_SHIFT
|
299 gen7_surface_tiling_mode(mt
->region
->tiling
);
301 /* mask of faces present in cube map; for other surfaces MBZ. */
302 if (tObj
->Target
== GL_TEXTURE_CUBE_MAP
|| tObj
->Target
== GL_TEXTURE_CUBE_MAP_ARRAY
)
303 surf
[0] |= BRW_SURFACE_CUBEFACE_ENABLES
;
305 if (mt
->align_h
== 4)
306 surf
[0] |= GEN7_SURFACE_VALIGN_4
;
307 if (mt
->align_w
== 8)
308 surf
[0] |= GEN7_SURFACE_HALIGN_8
;
310 if (mt
->logical_depth0
> 1 && tObj
->Target
!= GL_TEXTURE_3D
)
311 surf
[0] |= GEN7_SURFACE_IS_ARRAY
;
313 if (mt
->array_spacing_lod0
)
314 surf
[0] |= GEN7_SURFACE_ARYSPC_LOD0
;
316 surf
[1] = mt
->region
->bo
->offset64
+ mt
->offset
; /* reloc */
318 surf
[2] = SET_FIELD(mt
->logical_width0
- 1, GEN7_SURFACE_WIDTH
) |
319 SET_FIELD(mt
->logical_height0
- 1, GEN7_SURFACE_HEIGHT
);
320 surf
[3] = SET_FIELD(mt
->logical_depth0
- 1, BRW_SURFACE_DEPTH
) |
321 ((intelObj
->mt
->region
->pitch
) - 1);
323 surf
[4] = gen7_surface_msaa_bits(mt
->num_samples
, mt
->msaa_layout
);
325 surf
[5] = (SET_FIELD(GEN7_MOCS_L3
, GEN7_SURFACE_MOCS
) |
326 SET_FIELD(tObj
->BaseLevel
- mt
->first_level
,
327 GEN7_SURFACE_MIN_LOD
) |
329 (intelObj
->_MaxLevel
- tObj
->BaseLevel
));
331 if (brw
->is_haswell
) {
332 /* Handling GL_ALPHA as a surface format override breaks 1.30+ style
333 * texturing functions that return a float, as our code generation always
334 * selects the .x channel (which would always be 0).
336 const bool alpha_depth
= tObj
->DepthMode
== GL_ALPHA
&&
337 (firstImage
->_BaseFormat
== GL_DEPTH_COMPONENT
||
338 firstImage
->_BaseFormat
== GL_DEPTH_STENCIL
);
340 const int swizzle
= unlikely(alpha_depth
)
341 ? SWIZZLE_XYZW
: brw_get_texture_swizzle(ctx
, tObj
);
343 const bool need_scs_green_to_blue
= for_gather
&& tex_format
== BRW_SURFACEFORMAT_R32G32_FLOAT_LD
;
346 SET_FIELD(brw_swizzle_to_scs(GET_SWZ(swizzle
, 0), need_scs_green_to_blue
), GEN7_SURFACE_SCS_R
) |
347 SET_FIELD(brw_swizzle_to_scs(GET_SWZ(swizzle
, 1), need_scs_green_to_blue
), GEN7_SURFACE_SCS_G
) |
348 SET_FIELD(brw_swizzle_to_scs(GET_SWZ(swizzle
, 2), need_scs_green_to_blue
), GEN7_SURFACE_SCS_B
) |
349 SET_FIELD(brw_swizzle_to_scs(GET_SWZ(swizzle
, 3), need_scs_green_to_blue
), GEN7_SURFACE_SCS_A
);
353 gen7_set_surface_mcs_info(brw
, surf
, *surf_offset
,
354 mt
->mcs_mt
, false /* is RT */);
357 /* Emit relocation to surface contents */
358 drm_intel_bo_emit_reloc(brw
->batch
.bo
,
360 intelObj
->mt
->region
->bo
,
361 surf
[1] - intelObj
->mt
->region
->bo
->offset64
,
362 I915_GEM_DOMAIN_SAMPLER
, 0);
364 gen7_check_surface_setup(surf
, false /* is_render_target */);
368 * Create a raw surface for untyped R/W access.
371 gen7_create_raw_surface(struct brw_context
*brw
, drm_intel_bo
*bo
,
372 uint32_t offset
, uint32_t size
,
373 uint32_t *out_offset
, bool rw
)
375 gen7_emit_buffer_surface_state(brw
,
379 BRW_SURFACEFORMAT_RAW
,
387 gen7_update_null_renderbuffer_surface(struct brw_context
*brw
, unsigned unit
)
389 /* From the Ivy bridge PRM, Vol4 Part1 p62 (Surface Type: Programming
392 * A null surface is used in instances where an actual surface is not
393 * bound. When a write message is generated to a null surface, no
394 * actual surface is written to. When a read message (including any
395 * sampling engine message) is generated to a null surface, the result
396 * is all zeros. Note that a null surface type is allowed to be used
397 * with all messages, even if it is not specificially indicated as
398 * supported. All of the remaining fields in surface state are ignored
399 * for null surfaces, with the following exceptions: Width, Height,
400 * Depth, LOD, and Render Target View Extent fields must match the
401 * depth buffer’s corresponding state for all render target surfaces,
404 struct gl_context
*ctx
= &brw
->ctx
;
407 const struct gl_framebuffer
*fb
= ctx
->DrawBuffer
;
408 uint32_t surf_index
=
409 brw
->wm
.prog_data
->binding_table
.render_target_start
+ unit
;
411 uint32_t *surf
= brw_state_batch(brw
, AUB_TRACE_SURFACE_STATE
, 8 * 4, 32,
412 &brw
->wm
.base
.surf_offset
[surf_index
]);
413 memset(surf
, 0, 8 * 4);
415 /* From the Ivybridge PRM, Volume 4, Part 1, page 65,
416 * Tiled Surface: Programming Notes:
417 * "If Surface Type is SURFTYPE_NULL, this field must be TRUE."
419 surf
[0] = BRW_SURFACE_NULL
<< BRW_SURFACE_TYPE_SHIFT
|
420 BRW_SURFACEFORMAT_B8G8R8A8_UNORM
<< BRW_SURFACE_FORMAT_SHIFT
|
421 GEN7_SURFACE_TILING_Y
;
423 surf
[2] = SET_FIELD(fb
->Width
- 1, GEN7_SURFACE_WIDTH
) |
424 SET_FIELD(fb
->Height
- 1, GEN7_SURFACE_HEIGHT
);
426 gen7_check_surface_setup(surf
, true /* is_render_target */);
430 * Sets up a surface state structure to point at the given region.
431 * While it is only used for the front/back buffer currently, it should be
432 * usable for further buffers when doing ARB_draw_buffer support.
435 gen7_update_renderbuffer_surface(struct brw_context
*brw
,
436 struct gl_renderbuffer
*rb
,
440 struct gl_context
*ctx
= &brw
->ctx
;
441 struct intel_renderbuffer
*irb
= intel_renderbuffer(rb
);
442 struct intel_region
*region
= irb
->mt
->region
;
445 mesa_format rb_format
= _mesa_get_render_format(ctx
, intel_rb_format(irb
));
447 bool is_array
= false;
448 int depth
= MAX2(rb
->Depth
, 1);
449 int min_array_element
;
450 const uint8_t mocs
= GEN7_MOCS_L3
;
451 GLenum gl_target
= rb
->TexImage
?
452 rb
->TexImage
->TexObject
->Target
: GL_TEXTURE_2D
;
454 uint32_t surf_index
=
455 brw
->wm
.prog_data
->binding_table
.render_target_start
+ unit
;
457 uint32_t *surf
= brw_state_batch(brw
, AUB_TRACE_SURFACE_STATE
, 8 * 4, 32,
458 &brw
->wm
.base
.surf_offset
[surf_index
]);
459 memset(surf
, 0, 8 * 4);
461 intel_miptree_used_for_rendering(irb
->mt
);
463 /* Render targets can't use IMS layout */
464 assert(irb
->mt
->msaa_layout
!= INTEL_MSAA_LAYOUT_IMS
);
466 assert(brw_render_target_supported(brw
, rb
));
467 format
= brw
->render_target_format
[rb_format
];
468 if (unlikely(!brw
->format_supported_as_render_target
[rb_format
])) {
469 _mesa_problem(ctx
, "%s: renderbuffer format %s unsupported\n",
470 __FUNCTION__
, _mesa_get_format_name(rb_format
));
474 case GL_TEXTURE_CUBE_MAP_ARRAY
:
475 case GL_TEXTURE_CUBE_MAP
:
476 surftype
= BRW_SURFACE_2D
;
481 surftype
= translate_tex_target(gl_target
);
482 is_array
= _mesa_tex_target_is_array(gl_target
);
487 min_array_element
= 0;
488 } else if (irb
->mt
->num_samples
> 1) {
489 min_array_element
= irb
->mt_layer
/ irb
->mt
->num_samples
;
491 min_array_element
= irb
->mt_layer
;
494 surf
[0] = surftype
<< BRW_SURFACE_TYPE_SHIFT
|
495 format
<< BRW_SURFACE_FORMAT_SHIFT
|
496 (irb
->mt
->array_spacing_lod0
? GEN7_SURFACE_ARYSPC_LOD0
497 : GEN7_SURFACE_ARYSPC_FULL
) |
498 gen7_surface_tiling_mode(region
->tiling
);
500 if (irb
->mt
->align_h
== 4)
501 surf
[0] |= GEN7_SURFACE_VALIGN_4
;
502 if (irb
->mt
->align_w
== 8)
503 surf
[0] |= GEN7_SURFACE_HALIGN_8
;
506 surf
[0] |= GEN7_SURFACE_IS_ARRAY
;
509 surf
[1] = region
->bo
->offset64
;
511 assert(brw
->has_surface_tile_offset
);
513 surf
[5] = SET_FIELD(mocs
, GEN7_SURFACE_MOCS
) |
514 (irb
->mt_level
- irb
->mt
->first_level
);
516 surf
[2] = SET_FIELD(irb
->mt
->logical_width0
- 1, GEN7_SURFACE_WIDTH
) |
517 SET_FIELD(irb
->mt
->logical_height0
- 1, GEN7_SURFACE_HEIGHT
);
519 surf
[3] = ((depth
- 1) << BRW_SURFACE_DEPTH_SHIFT
) |
522 surf
[4] = gen7_surface_msaa_bits(irb
->mt
->num_samples
, irb
->mt
->msaa_layout
) |
523 min_array_element
<< GEN7_SURFACE_MIN_ARRAY_ELEMENT_SHIFT
|
524 (depth
- 1) << GEN7_SURFACE_RENDER_TARGET_VIEW_EXTENT_SHIFT
;
526 if (irb
->mt
->mcs_mt
) {
527 gen7_set_surface_mcs_info(brw
, surf
, brw
->wm
.base
.surf_offset
[surf_index
],
528 irb
->mt
->mcs_mt
, true /* is RT */);
531 surf
[7] = irb
->mt
->fast_clear_color_value
;
533 if (brw
->is_haswell
) {
534 surf
[7] |= (SET_FIELD(HSW_SCS_RED
, GEN7_SURFACE_SCS_R
) |
535 SET_FIELD(HSW_SCS_GREEN
, GEN7_SURFACE_SCS_G
) |
536 SET_FIELD(HSW_SCS_BLUE
, GEN7_SURFACE_SCS_B
) |
537 SET_FIELD(HSW_SCS_ALPHA
, GEN7_SURFACE_SCS_A
));
540 drm_intel_bo_emit_reloc(brw
->batch
.bo
,
541 brw
->wm
.base
.surf_offset
[surf_index
] + 4,
543 surf
[1] - region
->bo
->offset64
,
544 I915_GEM_DOMAIN_RENDER
,
545 I915_GEM_DOMAIN_RENDER
);
547 gen7_check_surface_setup(surf
, true /* is_render_target */);
551 gen7_init_vtable_surface_functions(struct brw_context
*brw
)
553 brw
->vtbl
.update_texture_surface
= gen7_update_texture_surface
;
554 brw
->vtbl
.update_renderbuffer_surface
= gen7_update_renderbuffer_surface
;
555 brw
->vtbl
.update_null_renderbuffer_surface
=
556 gen7_update_null_renderbuffer_surface
;
557 brw
->vtbl
.create_raw_surface
= gen7_create_raw_surface
;
558 brw
->vtbl
.emit_buffer_surface_state
= gen7_emit_buffer_surface_state
;