1 /**************************************************************************
3 * Copyright 2006 VMware, Inc.
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the
8 * "Software"), to deal in the Software without restriction, including
9 * without limitation the rights to use, copy, modify, merge, publish,
10 * distribute, sub license, and/or sell copies of the Software, and to
11 * permit persons to whom the Software is furnished to do so, subject to
12 * the following conditions:
14 * The above copyright notice and this permission notice (including the
15 * next paragraph) shall be included in all copies or substantial portions
18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
19 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
20 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
21 * IN NO EVENT SHALL VMWARE AND/OR ITS SUPPLIERS BE LIABLE FOR
22 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
23 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
24 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
26 **************************************************************************/
28 #include "intel_batchbuffer.h"
29 #include "intel_buffer_objects.h"
30 #include "intel_reg.h"
31 #include "intel_bufmgr.h"
32 #include "intel_buffers.h"
33 #include "brw_context.h"
36 intel_batchbuffer_reset(struct brw_context
*brw
);
38 struct cached_batch_item
{
39 struct cached_batch_item
*next
;
45 intel_batchbuffer_clear_cache(struct brw_context
*brw
)
47 struct cached_batch_item
*item
= brw
->batch
.cached_items
;
50 struct cached_batch_item
*next
= item
->next
;
55 brw
->batch
.cached_items
= NULL
;
59 intel_batchbuffer_init(struct brw_context
*brw
)
61 intel_batchbuffer_reset(brw
);
64 /* We can't just use brw_state_batch to get a chunk of space for
65 * the gen6 workaround because it involves actually writing to
66 * the buffer, and the kernel doesn't let us write to the batch.
68 brw
->batch
.workaround_bo
= drm_intel_bo_alloc(brw
->bufmgr
,
69 "pipe_control workaround",
73 brw
->batch
.need_workaround_flush
= true;
76 brw
->batch
.cpu_map
= malloc(BATCH_SZ
);
77 brw
->batch
.map
= brw
->batch
.cpu_map
;
82 intel_batchbuffer_reset(struct brw_context
*brw
)
84 if (brw
->batch
.last_bo
!= NULL
) {
85 drm_intel_bo_unreference(brw
->batch
.last_bo
);
86 brw
->batch
.last_bo
= NULL
;
88 brw
->batch
.last_bo
= brw
->batch
.bo
;
90 intel_batchbuffer_clear_cache(brw
);
92 brw
->batch
.bo
= drm_intel_bo_alloc(brw
->bufmgr
, "batchbuffer",
95 drm_intel_bo_map(brw
->batch
.bo
, true);
96 brw
->batch
.map
= brw
->batch
.bo
->virtual;
99 brw
->batch
.reserved_space
= BATCH_RESERVED
;
100 brw
->batch
.state_batch_offset
= brw
->batch
.bo
->size
;
102 brw
->batch
.needs_sol_reset
= false;
104 /* We don't know what ring the new batch will be sent to until we see the
105 * first BEGIN_BATCH or BEGIN_BATCH_BLT. Mark it as unknown.
107 brw
->batch
.ring
= UNKNOWN_RING
;
111 intel_batchbuffer_save_state(struct brw_context
*brw
)
113 brw
->batch
.saved
.used
= brw
->batch
.used
;
114 brw
->batch
.saved
.reloc_count
=
115 drm_intel_gem_bo_get_reloc_count(brw
->batch
.bo
);
119 intel_batchbuffer_reset_to_saved(struct brw_context
*brw
)
121 drm_intel_gem_bo_clear_relocs(brw
->batch
.bo
, brw
->batch
.saved
.reloc_count
);
123 brw
->batch
.used
= brw
->batch
.saved
.used
;
124 if (brw
->batch
.used
== 0)
125 brw
->batch
.ring
= UNKNOWN_RING
;
127 /* Cached batch state is dead, since we just cleared some unknown part of the
128 * batchbuffer. Assume that the caller resets any other state necessary.
130 intel_batchbuffer_clear_cache(brw
);
134 intel_batchbuffer_free(struct brw_context
*brw
)
136 free(brw
->batch
.cpu_map
);
137 drm_intel_bo_unreference(brw
->batch
.last_bo
);
138 drm_intel_bo_unreference(brw
->batch
.bo
);
139 drm_intel_bo_unreference(brw
->batch
.workaround_bo
);
140 intel_batchbuffer_clear_cache(brw
);
144 do_batch_dump(struct brw_context
*brw
)
146 struct drm_intel_decode
*decode
;
147 struct intel_batchbuffer
*batch
= &brw
->batch
;
150 decode
= drm_intel_decode_context_alloc(brw
->intelScreen
->deviceID
);
154 ret
= drm_intel_bo_map(batch
->bo
, false);
156 drm_intel_decode_set_batch_pointer(decode
,
162 "WARNING: failed to map batchbuffer (%s), "
163 "dumping uploaded data instead.\n", strerror(ret
));
165 drm_intel_decode_set_batch_pointer(decode
,
171 drm_intel_decode(decode
);
173 drm_intel_decode_context_free(decode
);
176 drm_intel_bo_unmap(batch
->bo
);
178 brw_debug_batch(brw
);
183 intel_batchbuffer_emit_render_ring_prelude(struct brw_context
*brw
)
185 /* We may need to enable and snapshot OA counters. */
186 brw_perf_monitor_new_batch(brw
);
190 * Called when starting a new batch buffer.
193 brw_new_batch(struct brw_context
*brw
)
195 /* Create a new batchbuffer and reset the associated state: */
196 intel_batchbuffer_reset(brw
);
198 /* If the kernel supports hardware contexts, then most hardware state is
199 * preserved between batches; we only need to re-emit state that is required
200 * to be in every batch. Otherwise we need to re-emit all the state that
201 * would otherwise be stored in the context (which for all intents and
202 * purposes means everything).
204 if (brw
->hw_ctx
== NULL
)
205 brw
->state
.dirty
.brw
|= BRW_NEW_CONTEXT
;
207 brw
->state
.dirty
.brw
|= BRW_NEW_BATCH
;
209 /* Assume that the last command before the start of our batch was a
210 * primitive, for safety.
212 brw
->batch
.need_workaround_flush
= true;
214 brw
->state_batch_count
= 0;
218 /* We need to periodically reap the shader time results, because rollover
219 * happens every few seconds. We also want to see results every once in a
220 * while, because many programs won't cleanly destroy our context, so the
221 * end-of-run printout may not happen.
223 if (INTEL_DEBUG
& DEBUG_SHADER_TIME
)
224 brw_collect_and_report_shader_time(brw
);
226 if (INTEL_DEBUG
& DEBUG_PERFMON
)
227 brw_dump_perf_monitors(brw
);
231 * Called from intel_batchbuffer_flush before emitting MI_BATCHBUFFER_END and
234 * This function can emit state (say, to preserve registers that aren't saved
235 * between batches). All of this state MUST fit in the reserved space at the
236 * end of the batchbuffer. If you add more GPU state, increase the reserved
237 * space by updating the BATCH_RESERVED macro.
240 brw_finish_batch(struct brw_context
*brw
)
242 /* Capture the closing pipeline statistics register values necessary to
243 * support query objects (in the non-hardware context world).
245 brw_emit_query_end(brw
);
247 /* We may also need to snapshot and disable OA counters. */
248 if (brw
->batch
.ring
== RENDER_RING
)
249 brw_perf_monitor_finish_batch(brw
);
251 if (brw
->curbe
.curbe_bo
) {
252 drm_intel_gem_bo_unmap_gtt(brw
->curbe
.curbe_bo
);
253 drm_intel_bo_unreference(brw
->curbe
.curbe_bo
);
254 brw
->curbe
.curbe_bo
= NULL
;
257 /* Mark that the current program cache BO has been used by the GPU.
258 * It will be reallocated if we need to put new programs in for the
261 brw
->cache
.bo_used_by_gpu
= true;
264 /* TODO: Push this whole function into bufmgr.
267 do_flush_locked(struct brw_context
*brw
)
269 struct intel_batchbuffer
*batch
= &brw
->batch
;
273 drm_intel_bo_unmap(batch
->bo
);
275 ret
= drm_intel_bo_subdata(batch
->bo
, 0, 4*batch
->used
, batch
->map
);
276 if (ret
== 0 && batch
->state_batch_offset
!= batch
->bo
->size
) {
277 ret
= drm_intel_bo_subdata(batch
->bo
,
278 batch
->state_batch_offset
,
279 batch
->bo
->size
- batch
->state_batch_offset
,
280 (char *)batch
->map
+ batch
->state_batch_offset
);
284 if (!brw
->intelScreen
->no_hw
) {
287 if (brw
->gen
>= 6 && batch
->ring
== BLT_RING
) {
288 flags
= I915_EXEC_BLT
;
290 flags
= I915_EXEC_RENDER
;
292 if (batch
->needs_sol_reset
)
293 flags
|= I915_EXEC_GEN7_SOL_RESET
;
296 if (unlikely(INTEL_DEBUG
& DEBUG_AUB
))
297 brw_annotate_aub(brw
);
298 if (brw
->hw_ctx
== NULL
|| batch
->ring
!= RENDER_RING
) {
299 ret
= drm_intel_bo_mrb_exec(batch
->bo
, 4 * batch
->used
, NULL
, 0, 0,
302 ret
= drm_intel_gem_bo_context_exec(batch
->bo
, brw
->hw_ctx
,
303 4 * batch
->used
, flags
);
308 if (unlikely(INTEL_DEBUG
& DEBUG_BATCH
))
312 fprintf(stderr
, "intel_do_flush_locked failed: %s\n", strerror(-ret
));
320 _intel_batchbuffer_flush(struct brw_context
*brw
,
321 const char *file
, int line
)
325 if (brw
->batch
.used
== 0)
328 if (brw
->first_post_swapbuffers_batch
== NULL
) {
329 brw
->first_post_swapbuffers_batch
= brw
->batch
.bo
;
330 drm_intel_bo_reference(brw
->first_post_swapbuffers_batch
);
333 if (unlikely(INTEL_DEBUG
& DEBUG_BATCH
)) {
334 int bytes_for_commands
= 4 * brw
->batch
.used
;
335 int bytes_for_state
= brw
->batch
.bo
->size
- brw
->batch
.state_batch_offset
;
336 int total_bytes
= bytes_for_commands
+ bytes_for_state
;
337 fprintf(stderr
, "%s:%d: Batchbuffer flush with %4db (pkt) + "
338 "%4db (state) = %4db (%0.1f%%)\n", file
, line
,
339 bytes_for_commands
, bytes_for_state
,
341 100.0f
* total_bytes
/ BATCH_SZ
);
344 brw
->batch
.reserved_space
= 0;
346 brw_finish_batch(brw
);
348 /* Mark the end of the buffer. */
349 intel_batchbuffer_emit_dword(brw
, MI_BATCH_BUFFER_END
);
350 if (brw
->batch
.used
& 1) {
351 /* Round batchbuffer usage to 2 DWORDs. */
352 intel_batchbuffer_emit_dword(brw
, MI_NOOP
);
355 intel_upload_finish(brw
);
357 /* Check that we didn't just wrap our batchbuffer at a bad time. */
358 assert(!brw
->no_batch_wrap
);
360 ret
= do_flush_locked(brw
);
362 if (unlikely(INTEL_DEBUG
& DEBUG_SYNC
)) {
363 fprintf(stderr
, "waiting for idle\n");
364 drm_intel_bo_wait_rendering(brw
->batch
.bo
);
367 /* Start a new batch buffer. */
374 /* This is the only way buffers get added to the validate list.
377 intel_batchbuffer_emit_reloc(struct brw_context
*brw
,
378 drm_intel_bo
*buffer
,
379 uint32_t read_domains
, uint32_t write_domain
,
384 ret
= drm_intel_bo_emit_reloc(brw
->batch
.bo
, 4*brw
->batch
.used
,
386 read_domains
, write_domain
);
391 * Using the old buffer offset, write in what the right data would be, in case
392 * the buffer doesn't move and we can short-circuit the relocation processing
395 intel_batchbuffer_emit_dword(brw
, buffer
->offset64
+ delta
);
401 intel_batchbuffer_emit_reloc64(struct brw_context
*brw
,
402 drm_intel_bo
*buffer
,
403 uint32_t read_domains
, uint32_t write_domain
,
406 int ret
= drm_intel_bo_emit_reloc(brw
->batch
.bo
, 4*brw
->batch
.used
,
408 read_domains
, write_domain
);
412 /* Using the old buffer offset, write in what the right data would be, in
413 * case the buffer doesn't move and we can short-circuit the relocation
414 * processing in the kernel
416 uint64_t offset
= buffer
->offset64
+ delta
;
417 intel_batchbuffer_emit_dword(brw
, offset
);
418 intel_batchbuffer_emit_dword(brw
, offset
>> 32);
425 intel_batchbuffer_data(struct brw_context
*brw
,
426 const void *data
, GLuint bytes
, enum brw_gpu_ring ring
)
428 assert((bytes
& 3) == 0);
429 intel_batchbuffer_require_space(brw
, bytes
, ring
);
430 __memcpy(brw
->batch
.map
+ brw
->batch
.used
, data
, bytes
);
431 brw
->batch
.used
+= bytes
>> 2;
435 * According to the latest documentation, any PIPE_CONTROL with the
436 * "Command Streamer Stall" bit set must also have another bit set,
437 * with five different options:
439 * - Render Target Cache Flush
440 * - Depth Cache Flush
441 * - Stall at Pixel Scoreboard
442 * - Post-Sync Operation
445 * I chose "Stall at Pixel Scoreboard" since we've used it effectively
446 * in the past, but the choice is fairly arbitrary.
449 gen8_add_cs_stall_workaround_bits(uint32_t *flags
)
451 uint32_t wa_bits
= PIPE_CONTROL_WRITE_FLUSH
|
452 PIPE_CONTROL_DEPTH_CACHE_FLUSH
|
453 PIPE_CONTROL_WRITE_IMMEDIATE
|
454 PIPE_CONTROL_WRITE_DEPTH_COUNT
|
455 PIPE_CONTROL_WRITE_TIMESTAMP
|
456 PIPE_CONTROL_STALL_AT_SCOREBOARD
|
457 PIPE_CONTROL_DEPTH_STALL
;
459 /* If we're doing a CS stall, and don't already have one of the
460 * workaround bits set, add "Stall at Pixel Scoreboard."
462 if ((*flags
& PIPE_CONTROL_CS_STALL
) != 0 && (*flags
& wa_bits
) == 0)
463 *flags
|= PIPE_CONTROL_STALL_AT_SCOREBOARD
;
467 * Emit a PIPE_CONTROL with various flushing flags.
469 * The caller is responsible for deciding what flags are appropriate for the
473 brw_emit_pipe_control_flush(struct brw_context
*brw
, uint32_t flags
)
476 gen8_add_cs_stall_workaround_bits(&flags
);
479 OUT_BATCH(_3DSTATE_PIPE_CONTROL
| (6 - 2));
486 } else if (brw
->gen
>= 6) {
488 OUT_BATCH(_3DSTATE_PIPE_CONTROL
| (5 - 2));
496 OUT_BATCH(_3DSTATE_PIPE_CONTROL
| flags
| (4 - 2));
505 * Emit a PIPE_CONTROL that writes to a buffer object.
507 * \p flags should contain one of the following items:
508 * - PIPE_CONTROL_WRITE_IMMEDIATE
509 * - PIPE_CONTROL_WRITE_TIMESTAMP
510 * - PIPE_CONTROL_WRITE_DEPTH_COUNT
513 brw_emit_pipe_control_write(struct brw_context
*brw
, uint32_t flags
,
514 drm_intel_bo
*bo
, uint32_t offset
,
515 uint32_t imm_lower
, uint32_t imm_upper
)
518 gen8_add_cs_stall_workaround_bits(&flags
);
521 OUT_BATCH(_3DSTATE_PIPE_CONTROL
| (6 - 2));
523 OUT_RELOC64(bo
, I915_GEM_DOMAIN_INSTRUCTION
, I915_GEM_DOMAIN_INSTRUCTION
,
525 OUT_BATCH(imm_lower
);
526 OUT_BATCH(imm_upper
);
528 } else if (brw
->gen
>= 6) {
529 /* PPGTT/GGTT is selected by DW2 bit 2 on Sandybridge, but DW1 bit 24
530 * on later platforms. We always use PPGTT on Gen7+.
532 unsigned gen6_gtt
= brw
->gen
== 6 ? PIPE_CONTROL_GLOBAL_GTT_WRITE
: 0;
535 OUT_BATCH(_3DSTATE_PIPE_CONTROL
| (5 - 2));
537 OUT_RELOC(bo
, I915_GEM_DOMAIN_INSTRUCTION
, I915_GEM_DOMAIN_INSTRUCTION
,
539 OUT_BATCH(imm_lower
);
540 OUT_BATCH(imm_upper
);
544 OUT_BATCH(_3DSTATE_PIPE_CONTROL
| flags
| (4 - 2));
545 OUT_RELOC(bo
, I915_GEM_DOMAIN_INSTRUCTION
, I915_GEM_DOMAIN_INSTRUCTION
,
546 PIPE_CONTROL_GLOBAL_GTT_WRITE
| offset
);
547 OUT_BATCH(imm_lower
);
548 OUT_BATCH(imm_upper
);
554 * Restriction [DevSNB, DevIVB]:
556 * Prior to changing Depth/Stencil Buffer state (i.e. any combination of
557 * 3DSTATE_DEPTH_BUFFER, 3DSTATE_CLEAR_PARAMS, 3DSTATE_STENCIL_BUFFER,
558 * 3DSTATE_HIER_DEPTH_BUFFER) SW must first issue a pipelined depth stall
559 * (PIPE_CONTROL with Depth Stall bit set), followed by a pipelined depth
560 * cache flush (PIPE_CONTROL with Depth Flush Bit set), followed by
561 * another pipelined depth stall (PIPE_CONTROL with Depth Stall bit set),
562 * unless SW can otherwise guarantee that the pipeline from WM onwards is
563 * already flushed (e.g., via a preceding MI_FLUSH).
566 intel_emit_depth_stall_flushes(struct brw_context
*brw
)
568 assert(brw
->gen
>= 6 && brw
->gen
<= 8);
570 brw_emit_pipe_control_flush(brw
, PIPE_CONTROL_DEPTH_STALL
);
571 brw_emit_pipe_control_flush(brw
, PIPE_CONTROL_DEPTH_CACHE_FLUSH
);
572 brw_emit_pipe_control_flush(brw
, PIPE_CONTROL_DEPTH_STALL
);
576 * From the Ivybridge PRM, Volume 2 Part 1, Section 3.2 (VS Stage Input):
577 * "A PIPE_CONTROL with Post-Sync Operation set to 1h and a depth
578 * stall needs to be sent just prior to any 3DSTATE_VS, 3DSTATE_URB_VS,
579 * 3DSTATE_CONSTANT_VS, 3DSTATE_BINDING_TABLE_POINTER_VS,
580 * 3DSTATE_SAMPLER_STATE_POINTER_VS command. Only one PIPE_CONTROL needs
581 * to be sent before any combination of VS associated 3DSTATE."
584 gen7_emit_vs_workaround_flush(struct brw_context
*brw
)
586 assert(brw
->gen
>= 7 && brw
->gen
<= 8);
587 brw_emit_pipe_control_write(brw
,
588 PIPE_CONTROL_WRITE_IMMEDIATE
589 | PIPE_CONTROL_DEPTH_STALL
,
590 brw
->batch
.workaround_bo
, 0,
596 * Emit a PIPE_CONTROL command for gen7 with the CS Stall bit set.
599 gen7_emit_cs_stall_flush(struct brw_context
*brw
)
601 brw_emit_pipe_control_write(brw
,
602 PIPE_CONTROL_CS_STALL
603 | PIPE_CONTROL_WRITE_IMMEDIATE
,
604 brw
->batch
.workaround_bo
, 0,
610 * Emits a PIPE_CONTROL with a non-zero post-sync operation, for
611 * implementing two workarounds on gen6. From section 1.4.7.1
612 * "PIPE_CONTROL" of the Sandy Bridge PRM volume 2 part 1:
614 * [DevSNB-C+{W/A}] Before any depth stall flush (including those
615 * produced by non-pipelined state commands), software needs to first
616 * send a PIPE_CONTROL with no bits set except Post-Sync Operation !=
619 * [Dev-SNB{W/A}]: Before a PIPE_CONTROL with Write Cache Flush Enable
620 * =1, a PIPE_CONTROL with any non-zero post-sync-op is required.
622 * And the workaround for these two requires this workaround first:
624 * [Dev-SNB{W/A}]: Pipe-control with CS-stall bit set must be sent
625 * BEFORE the pipe-control with a post-sync op and no write-cache
628 * And this last workaround is tricky because of the requirements on
629 * that bit. From section 1.4.7.2.3 "Stall" of the Sandy Bridge PRM
632 * "1 of the following must also be set:
633 * - Render Target Cache Flush Enable ([12] of DW1)
634 * - Depth Cache Flush Enable ([0] of DW1)
635 * - Stall at Pixel Scoreboard ([1] of DW1)
636 * - Depth Stall ([13] of DW1)
637 * - Post-Sync Operation ([13] of DW1)
638 * - Notify Enable ([8] of DW1)"
640 * The cache flushes require the workaround flush that triggered this
641 * one, so we can't use it. Depth stall would trigger the same.
642 * Post-sync nonzero is what triggered this second workaround, so we
643 * can't use that one either. Notify enable is IRQs, which aren't
644 * really our business. That leaves only stall at scoreboard.
647 intel_emit_post_sync_nonzero_flush(struct brw_context
*brw
)
649 if (!brw
->batch
.need_workaround_flush
)
652 brw_emit_pipe_control_flush(brw
,
653 PIPE_CONTROL_CS_STALL
|
654 PIPE_CONTROL_STALL_AT_SCOREBOARD
);
656 brw_emit_pipe_control_write(brw
, PIPE_CONTROL_WRITE_IMMEDIATE
,
657 brw
->batch
.workaround_bo
, 0, 0, 0);
659 brw
->batch
.need_workaround_flush
= false;
662 /* Emit a pipelined flush to either flush render and texture cache for
663 * reading from a FBO-drawn texture, or flush so that frontbuffer
664 * render appears on the screen in DRI1.
666 * This is also used for the always_flush_cache driconf debug option.
669 intel_batchbuffer_emit_mi_flush(struct brw_context
*brw
)
671 if (brw
->batch
.ring
== BLT_RING
&& brw
->gen
>= 6) {
673 OUT_BATCH(MI_FLUSH_DW
);
679 int flags
= PIPE_CONTROL_NO_WRITE
| PIPE_CONTROL_WRITE_FLUSH
;
681 flags
|= PIPE_CONTROL_INSTRUCTION_FLUSH
|
682 PIPE_CONTROL_DEPTH_CACHE_FLUSH
|
683 PIPE_CONTROL_VF_CACHE_INVALIDATE
|
684 PIPE_CONTROL_TC_FLUSH
|
685 PIPE_CONTROL_CS_STALL
;
688 /* Hardware workaround: SNB B-Spec says:
690 * [Dev-SNB{W/A}]: Before a PIPE_CONTROL with Write Cache
691 * Flush Enable =1, a PIPE_CONTROL with any non-zero
692 * post-sync-op is required.
694 intel_emit_post_sync_nonzero_flush(brw
);
697 brw_emit_pipe_control_flush(brw
, flags
);
702 brw_load_register_mem(struct brw_context
*brw
,
705 uint32_t read_domains
, uint32_t write_domain
,
708 /* MI_LOAD_REGISTER_MEM only exists on Gen7+. */
709 assert(brw
->gen
>= 7);
713 OUT_BATCH(GEN7_MI_LOAD_REGISTER_MEM
| (4 - 2));
715 OUT_RELOC64(bo
, read_domains
, write_domain
, offset
);
719 OUT_BATCH(GEN7_MI_LOAD_REGISTER_MEM
| (3 - 2));
721 OUT_RELOC(bo
, read_domains
, write_domain
, offset
);