2 * Copyright 2006 VMware, Inc.
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the
7 * "Software"), to deal in the Software without restriction, including
8 * without limitation the rights to use, copy, modify, merge, publish,
9 * distribute, sublicense, and/or sell copies of the Software, and to
10 * permit persons to whom the Software is furnished to do so, subject to
11 * the following conditions:
13 * The above copyright notice and this permission notice (including the
14 * next paragraph) shall be included in all copies or substantial portions
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
18 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
19 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
20 * IN NO EVENT SHALL VMWARE AND/OR ITS SUPPLIERS BE LIABLE FOR
21 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
22 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
23 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
26 #include "intel_batchbuffer.h"
27 #include "intel_buffer_objects.h"
28 #include "brw_bufmgr.h"
29 #include "intel_buffers.h"
30 #include "intel_fbo.h"
31 #include "brw_context.h"
32 #include "brw_defines.h"
33 #include "brw_state.h"
34 #include "common/gen_decoder.h"
35 #include "common/gen_gem.h"
37 #include "util/hash_table.h"
42 #define FILE_DEBUG_FLAG DEBUG_BUFMGR
45 * Target sizes of the batch and state buffers. We create the initial
46 * buffers at these sizes, and flush when they're nearly full. If we
47 * underestimate how close we are to the end, and suddenly need more space
48 * in the middle of a draw, we can grow the buffers, and finish the draw.
49 * At that point, we'll be over our target size, so the next operation
50 * should flush. Each time we flush the batch, we recreate both buffers
51 * at the original target size, so it doesn't grow without bound.
53 #define BATCH_SZ (20 * 1024)
54 #define STATE_SZ (16 * 1024)
57 intel_batchbuffer_reset(struct brw_context
*brw
);
60 dump_validation_list(struct intel_batchbuffer
*batch
)
62 fprintf(stderr
, "Validation list (length %d):\n", batch
->exec_count
);
64 for (int i
= 0; i
< batch
->exec_count
; i
++) {
65 uint64_t flags
= batch
->validation_list
[i
].flags
;
66 assert(batch
->validation_list
[i
].handle
==
67 batch
->exec_bos
[i
]->gem_handle
);
68 fprintf(stderr
, "[%2d]: %2d %-14s %p %s%-7s @ 0x%016llx%s (%"PRIu64
"B)\n",
70 batch
->validation_list
[i
].handle
,
71 batch
->exec_bos
[i
]->name
,
73 (flags
& EXEC_OBJECT_SUPPORTS_48B_ADDRESS
) ? "(48b" : "(32b",
74 (flags
& EXEC_OBJECT_WRITE
) ? " write)" : ")",
75 batch
->validation_list
[i
].offset
,
76 (flags
& EXEC_OBJECT_PINNED
) ? " (pinned)" : "",
77 batch
->exec_bos
[i
]->size
);
81 static struct gen_batch_decode_bo
82 decode_get_bo(void *v_brw
, uint64_t address
)
84 struct brw_context
*brw
= v_brw
;
85 struct intel_batchbuffer
*batch
= &brw
->batch
;
87 for (int i
= 0; i
< batch
->exec_count
; i
++) {
88 struct brw_bo
*bo
= batch
->exec_bos
[i
];
89 /* The decoder zeroes out the top 16 bits, so we need to as well */
90 uint64_t bo_address
= bo
->gtt_offset
& (~0ull >> 16);
92 if (address
>= bo_address
&& address
< bo_address
+ bo
->size
) {
93 return (struct gen_batch_decode_bo
) {
96 .map
= brw_bo_map(brw
, bo
, MAP_READ
) + (address
- bo_address
),
101 return (struct gen_batch_decode_bo
) { };
105 decode_get_state_size(void *v_brw
, uint32_t offset_from_dsba
)
107 struct brw_context
*brw
= v_brw
;
108 struct intel_batchbuffer
*batch
= &brw
->batch
;
109 struct hash_entry
*entry
=
110 _mesa_hash_table_search(batch
->state_batch_sizes
,
111 (void *) (uintptr_t) offset_from_dsba
);
112 return entry
? (uintptr_t) entry
->data
: 0;
116 uint_key_compare(const void *a
, const void *b
)
122 uint_key_hash(const void *key
)
124 return (uintptr_t) key
;
128 init_reloc_list(struct brw_reloc_list
*rlist
, int count
)
130 rlist
->reloc_count
= 0;
131 rlist
->reloc_array_size
= count
;
132 rlist
->relocs
= malloc(rlist
->reloc_array_size
*
133 sizeof(struct drm_i915_gem_relocation_entry
));
137 intel_batchbuffer_init(struct brw_context
*brw
)
139 struct intel_screen
*screen
= brw
->screen
;
140 struct intel_batchbuffer
*batch
= &brw
->batch
;
141 const struct gen_device_info
*devinfo
= &screen
->devinfo
;
143 batch
->use_shadow_copy
= !devinfo
->has_llc
;
145 init_reloc_list(&batch
->batch_relocs
, 250);
146 init_reloc_list(&batch
->state_relocs
, 250);
148 batch
->batch
.map
= NULL
;
149 batch
->state
.map
= NULL
;
150 batch
->exec_count
= 0;
151 batch
->exec_array_size
= 100;
153 malloc(batch
->exec_array_size
* sizeof(batch
->exec_bos
[0]));
154 batch
->validation_list
=
155 malloc(batch
->exec_array_size
* sizeof(batch
->validation_list
[0]));
157 if (INTEL_DEBUG
& DEBUG_BATCH
) {
158 batch
->state_batch_sizes
=
159 _mesa_hash_table_create(NULL
, uint_key_hash
, uint_key_compare
);
161 const unsigned decode_flags
=
162 GEN_BATCH_DECODE_FULL
|
163 ((INTEL_DEBUG
& DEBUG_COLOR
) ? GEN_BATCH_DECODE_IN_COLOR
: 0) |
164 GEN_BATCH_DECODE_OFFSETS
|
165 GEN_BATCH_DECODE_FLOATS
;
167 gen_batch_decode_ctx_init(&batch
->decoder
, devinfo
, stderr
,
168 decode_flags
, NULL
, decode_get_bo
,
169 decode_get_state_size
, brw
);
170 batch
->decoder
.max_vbo_decoded_lines
= 100;
173 batch
->use_batch_first
=
174 screen
->kernel_features
& KERNEL_ALLOWS_EXEC_BATCH_FIRST
;
176 /* PIPE_CONTROL needs a w/a but only on gen6 */
177 batch
->valid_reloc_flags
= EXEC_OBJECT_WRITE
;
178 if (devinfo
->gen
== 6)
179 batch
->valid_reloc_flags
|= EXEC_OBJECT_NEEDS_GTT
;
181 intel_batchbuffer_reset(brw
);
184 #define READ_ONCE(x) (*(volatile __typeof__(x) *)&(x))
187 add_exec_bo(struct intel_batchbuffer
*batch
, struct brw_bo
*bo
)
189 unsigned index
= READ_ONCE(bo
->index
);
191 if (index
< batch
->exec_count
&& batch
->exec_bos
[index
] == bo
)
194 /* May have been shared between multiple active batches */
195 for (index
= 0; index
< batch
->exec_count
; index
++) {
196 if (batch
->exec_bos
[index
] == bo
)
200 brw_bo_reference(bo
);
202 if (batch
->exec_count
== batch
->exec_array_size
) {
203 batch
->exec_array_size
*= 2;
205 realloc(batch
->exec_bos
,
206 batch
->exec_array_size
* sizeof(batch
->exec_bos
[0]));
207 batch
->validation_list
=
208 realloc(batch
->validation_list
,
209 batch
->exec_array_size
* sizeof(batch
->validation_list
[0]));
212 batch
->validation_list
[batch
->exec_count
] =
213 (struct drm_i915_gem_exec_object2
) {
214 .handle
= bo
->gem_handle
,
215 .offset
= bo
->gtt_offset
,
219 bo
->index
= batch
->exec_count
;
220 batch
->exec_bos
[batch
->exec_count
] = bo
;
221 batch
->aperture_space
+= bo
->size
;
223 return batch
->exec_count
++;
227 recreate_growing_buffer(struct brw_context
*brw
,
228 struct brw_growing_bo
*grow
,
229 const char *name
, unsigned size
,
230 enum brw_memory_zone memzone
)
232 struct intel_screen
*screen
= brw
->screen
;
233 struct intel_batchbuffer
*batch
= &brw
->batch
;
234 struct brw_bufmgr
*bufmgr
= screen
->bufmgr
;
236 /* We can't grow buffers when using softpin, so just overallocate them. */
237 if (brw_using_softpin(bufmgr
))
240 grow
->bo
= brw_bo_alloc(bufmgr
, name
, size
, memzone
);
241 grow
->bo
->kflags
|= can_do_exec_capture(screen
) ? EXEC_OBJECT_CAPTURE
: 0;
242 grow
->partial_bo
= NULL
;
243 grow
->partial_bo_map
= NULL
;
244 grow
->partial_bytes
= 0;
245 grow
->memzone
= memzone
;
247 if (batch
->use_shadow_copy
)
248 grow
->map
= realloc(grow
->map
, grow
->bo
->size
);
250 grow
->map
= brw_bo_map(brw
, grow
->bo
, MAP_READ
| MAP_WRITE
);
254 intel_batchbuffer_reset(struct brw_context
*brw
)
256 struct intel_batchbuffer
*batch
= &brw
->batch
;
258 if (batch
->last_bo
!= NULL
) {
259 brw_bo_unreference(batch
->last_bo
);
260 batch
->last_bo
= NULL
;
262 batch
->last_bo
= batch
->batch
.bo
;
264 recreate_growing_buffer(brw
, &batch
->batch
, "batchbuffer", BATCH_SZ
,
266 batch
->map_next
= batch
->batch
.map
;
268 recreate_growing_buffer(brw
, &batch
->state
, "statebuffer", STATE_SZ
,
269 BRW_MEMZONE_DYNAMIC
);
271 /* Avoid making 0 a valid state offset - otherwise the decoder will try
272 * and decode data when we use offset 0 as a null pointer.
274 batch
->state_used
= 1;
276 add_exec_bo(batch
, batch
->batch
.bo
);
277 assert(batch
->batch
.bo
->index
== 0);
279 batch
->needs_sol_reset
= false;
280 batch
->state_base_address_emitted
= false;
282 if (batch
->state_batch_sizes
)
283 _mesa_hash_table_clear(batch
->state_batch_sizes
, NULL
);
287 intel_batchbuffer_reset_and_clear_render_cache(struct brw_context
*brw
)
289 intel_batchbuffer_reset(brw
);
290 brw_cache_sets_clear(brw
);
294 intel_batchbuffer_save_state(struct brw_context
*brw
)
296 brw
->batch
.saved
.map_next
= brw
->batch
.map_next
;
297 brw
->batch
.saved
.batch_reloc_count
= brw
->batch
.batch_relocs
.reloc_count
;
298 brw
->batch
.saved
.state_reloc_count
= brw
->batch
.state_relocs
.reloc_count
;
299 brw
->batch
.saved
.exec_count
= brw
->batch
.exec_count
;
303 intel_batchbuffer_reset_to_saved(struct brw_context
*brw
)
305 for (int i
= brw
->batch
.saved
.exec_count
;
306 i
< brw
->batch
.exec_count
; i
++) {
307 brw_bo_unreference(brw
->batch
.exec_bos
[i
]);
309 brw
->batch
.batch_relocs
.reloc_count
= brw
->batch
.saved
.batch_reloc_count
;
310 brw
->batch
.state_relocs
.reloc_count
= brw
->batch
.saved
.state_reloc_count
;
311 brw
->batch
.exec_count
= brw
->batch
.saved
.exec_count
;
313 brw
->batch
.map_next
= brw
->batch
.saved
.map_next
;
317 intel_batchbuffer_free(struct intel_batchbuffer
*batch
)
319 if (batch
->use_shadow_copy
) {
320 free(batch
->batch
.map
);
321 free(batch
->state
.map
);
324 for (int i
= 0; i
< batch
->exec_count
; i
++) {
325 brw_bo_unreference(batch
->exec_bos
[i
]);
327 free(batch
->batch_relocs
.relocs
);
328 free(batch
->state_relocs
.relocs
);
329 free(batch
->exec_bos
);
330 free(batch
->validation_list
);
332 brw_bo_unreference(batch
->last_bo
);
333 brw_bo_unreference(batch
->batch
.bo
);
334 brw_bo_unreference(batch
->state
.bo
);
335 if (batch
->state_batch_sizes
) {
336 _mesa_hash_table_destroy(batch
->state_batch_sizes
, NULL
);
337 gen_batch_decode_ctx_finish(&batch
->decoder
);
342 * Finish copying the old batch/state buffer's contents to the new one
343 * after we tried to "grow" the buffer in an earlier operation.
346 finish_growing_bos(struct brw_growing_bo
*grow
)
348 struct brw_bo
*old_bo
= grow
->partial_bo
;
352 memcpy(grow
->map
, grow
->partial_bo_map
, grow
->partial_bytes
);
354 grow
->partial_bo
= NULL
;
355 grow
->partial_bo_map
= NULL
;
356 grow
->partial_bytes
= 0;
358 brw_bo_unreference(old_bo
);
362 replace_bo_in_reloc_list(struct brw_reloc_list
*rlist
,
363 uint32_t old_handle
, uint32_t new_handle
)
365 for (int i
= 0; i
< rlist
->reloc_count
; i
++) {
366 if (rlist
->relocs
[i
].target_handle
== old_handle
)
367 rlist
->relocs
[i
].target_handle
= new_handle
;
372 * Grow either the batch or state buffer to a new larger size.
374 * We can't actually grow buffers, so we allocate a new one, copy over
375 * the existing contents, and update our lists to refer to the new one.
377 * Note that this is only temporary - each new batch recreates the buffers
378 * at their original target size (BATCH_SZ or STATE_SZ).
381 grow_buffer(struct brw_context
*brw
,
382 struct brw_growing_bo
*grow
,
383 unsigned existing_bytes
,
386 struct intel_batchbuffer
*batch
= &brw
->batch
;
387 struct brw_bufmgr
*bufmgr
= brw
->bufmgr
;
388 struct brw_bo
*bo
= grow
->bo
;
390 /* We can't grow buffers that are softpinned, as the growing mechanism
391 * involves putting a larger buffer at the same gtt_offset...and we've
392 * only allocated the smaller amount of VMA. Without relocations, this
393 * simply won't work. This should never happen, however.
395 assert(!(bo
->kflags
& EXEC_OBJECT_PINNED
));
397 perf_debug("Growing %s - ran out of space\n", bo
->name
);
399 if (grow
->partial_bo
) {
400 /* We've already grown once, and now we need to do it again.
401 * Finish our last grow operation so we can start a new one.
402 * This should basically never happen.
404 perf_debug("Had to grow multiple times");
405 finish_growing_bos(grow
);
408 struct brw_bo
*new_bo
=
409 brw_bo_alloc(bufmgr
, bo
->name
, new_size
, grow
->memzone
);
411 /* Copy existing data to the new larger buffer */
412 grow
->partial_bo_map
= grow
->map
;
414 if (batch
->use_shadow_copy
) {
415 /* We can't safely use realloc, as it may move the existing buffer,
416 * breaking existing pointers the caller may still be using. Just
417 * malloc a new copy and memcpy it like the normal BO path.
419 * Use bo->size rather than new_size because the bufmgr may have
420 * rounded up the size, and we want the shadow size to match.
422 grow
->map
= malloc(new_bo
->size
);
424 grow
->map
= brw_bo_map(brw
, new_bo
, MAP_READ
| MAP_WRITE
);
427 /* Try to put the new BO at the same GTT offset as the old BO (which
428 * we're throwing away, so it doesn't need to be there).
430 * This guarantees that our relocations continue to work: values we've
431 * already written into the buffer, values we're going to write into the
432 * buffer, and the validation/relocation lists all will match.
434 * Also preserve kflags for EXEC_OBJECT_CAPTURE.
436 new_bo
->gtt_offset
= bo
->gtt_offset
;
437 new_bo
->index
= bo
->index
;
438 new_bo
->kflags
= bo
->kflags
;
440 /* Batch/state buffers are per-context, and if we've run out of space,
441 * we must have actually used them before, so...they will be in the list.
443 assert(bo
->index
< batch
->exec_count
);
444 assert(batch
->exec_bos
[bo
->index
] == bo
);
446 /* Update the validation list to use the new BO. */
447 batch
->validation_list
[bo
->index
].handle
= new_bo
->gem_handle
;
449 if (!batch
->use_batch_first
) {
450 /* We're not using I915_EXEC_HANDLE_LUT, which means we need to go
451 * update the relocation list entries to point at the new BO as well.
452 * (With newer kernels, the "handle" is an offset into the validation
453 * list, which remains unchanged, so we can skip this.)
455 replace_bo_in_reloc_list(&batch
->batch_relocs
,
456 bo
->gem_handle
, new_bo
->gem_handle
);
457 replace_bo_in_reloc_list(&batch
->state_relocs
,
458 bo
->gem_handle
, new_bo
->gem_handle
);
461 /* Exchange the two BOs...without breaking pointers to the old BO.
463 * Consider this scenario:
465 * 1. Somebody calls brw_state_batch() to get a region of memory, and
466 * and then creates a brw_address pointing to brw->batch.state.bo.
467 * 2. They then call brw_state_batch() a second time, which happens to
468 * grow and replace the state buffer. They then try to emit a
469 * relocation to their first section of memory.
471 * If we replace the brw->batch.state.bo pointer at step 2, we would
472 * break the address created in step 1. They'd have a pointer to the
473 * old destroyed BO. Emitting a relocation would add this dead BO to
474 * the validation list...causing /both/ statebuffers to be in the list,
475 * and all kinds of disasters.
477 * This is not a contrived case - BLORP vertex data upload hits this.
479 * There are worse scenarios too. Fences for GL sync objects reference
480 * brw->batch.batch.bo. If we replaced the batch pointer when growing,
481 * we'd need to chase down every fence and update it to point to the
482 * new BO. Otherwise, it would refer to a "batch" that never actually
483 * gets submitted, and would fail to trigger.
485 * To work around both of these issues, we transmutate the buffers in
486 * place, making the existing struct brw_bo represent the new buffer,
487 * and "new_bo" represent the old BO. This is highly unusual, but it
488 * seems like a necessary evil.
490 * We also defer the memcpy of the existing batch's contents. Callers
491 * may make multiple brw_state_batch calls, and retain pointers to the
492 * old BO's map. We'll perform the memcpy in finish_growing_bo() when
493 * we finally submit the batch, at which point we've finished uploading
494 * state, and nobody should have any old references anymore.
496 * To do that, we keep a reference to the old BO in grow->partial_bo,
497 * and store the number of bytes to copy in grow->partial_bytes. We
498 * can monkey with the refcounts directly without atomics because these
499 * are per-context BOs and they can only be touched by this thread.
501 assert(new_bo
->refcount
== 1);
502 new_bo
->refcount
= bo
->refcount
;
506 memcpy(&tmp
, bo
, sizeof(struct brw_bo
));
507 memcpy(bo
, new_bo
, sizeof(struct brw_bo
));
508 memcpy(new_bo
, &tmp
, sizeof(struct brw_bo
));
510 grow
->partial_bo
= new_bo
; /* the one reference of the OLD bo */
511 grow
->partial_bytes
= existing_bytes
;
515 intel_batchbuffer_require_space(struct brw_context
*brw
, GLuint sz
)
517 struct intel_batchbuffer
*batch
= &brw
->batch
;
519 const unsigned batch_used
= USED_BATCH(*batch
) * 4;
520 if (batch_used
+ sz
>= BATCH_SZ
&& !batch
->no_wrap
) {
521 intel_batchbuffer_flush(brw
);
522 } else if (batch_used
+ sz
>= batch
->batch
.bo
->size
) {
523 const unsigned new_size
=
524 MIN2(batch
->batch
.bo
->size
+ batch
->batch
.bo
->size
/ 2,
526 grow_buffer(brw
, &batch
->batch
, batch_used
, new_size
);
527 batch
->map_next
= (void *) batch
->batch
.map
+ batch_used
;
528 assert(batch_used
+ sz
< batch
->batch
.bo
->size
);
533 * Called when starting a new batch buffer.
536 brw_new_batch(struct brw_context
*brw
)
538 /* Unreference any BOs held by the previous batch, and reset counts. */
539 for (int i
= 0; i
< brw
->batch
.exec_count
; i
++) {
540 brw_bo_unreference(brw
->batch
.exec_bos
[i
]);
541 brw
->batch
.exec_bos
[i
] = NULL
;
543 brw
->batch
.batch_relocs
.reloc_count
= 0;
544 brw
->batch
.state_relocs
.reloc_count
= 0;
545 brw
->batch
.exec_count
= 0;
546 brw
->batch
.aperture_space
= 0;
548 brw_bo_unreference(brw
->batch
.state
.bo
);
550 /* Create a new batchbuffer and reset the associated state: */
551 intel_batchbuffer_reset_and_clear_render_cache(brw
);
553 /* If the kernel supports hardware contexts, then most hardware state is
554 * preserved between batches; we only need to re-emit state that is required
555 * to be in every batch. Otherwise we need to re-emit all the state that
556 * would otherwise be stored in the context (which for all intents and
557 * purposes means everything).
559 if (brw
->hw_ctx
== 0) {
560 brw
->ctx
.NewDriverState
|= BRW_NEW_CONTEXT
;
561 brw_upload_invariant_state(brw
);
564 brw
->ctx
.NewDriverState
|= BRW_NEW_BATCH
;
566 brw
->ib
.index_size
= -1;
568 /* We need to periodically reap the shader time results, because rollover
569 * happens every few seconds. We also want to see results every once in a
570 * while, because many programs won't cleanly destroy our context, so the
571 * end-of-run printout may not happen.
573 if (INTEL_DEBUG
& DEBUG_SHADER_TIME
)
574 brw_collect_and_report_shader_time(brw
);
578 * Called from intel_batchbuffer_flush before emitting MI_BATCHBUFFER_END and
581 * This function can emit state (say, to preserve registers that aren't saved
585 brw_finish_batch(struct brw_context
*brw
)
587 const struct gen_device_info
*devinfo
= &brw
->screen
->devinfo
;
589 brw
->batch
.no_wrap
= true;
591 /* Capture the closing pipeline statistics register values necessary to
592 * support query objects (in the non-hardware context world).
594 brw_emit_query_end(brw
);
596 /* Work around L3 state leaks into contexts set MI_RESTORE_INHIBIT which
597 * assume that the L3 cache is configured according to the hardware
598 * defaults. On Kernel 4.16+, we no longer need to do this.
600 if (devinfo
->gen
>= 7 &&
601 !(brw
->screen
->kernel_features
& KERNEL_ALLOWS_CONTEXT_ISOLATION
))
602 gen7_restore_default_l3_config(brw
);
604 if (devinfo
->is_haswell
) {
605 /* From the Haswell PRM, Volume 2b, Command Reference: Instructions,
606 * 3DSTATE_CC_STATE_POINTERS > "Note":
608 * "SW must program 3DSTATE_CC_STATE_POINTERS command at the end of every
609 * 3D batch buffer followed by a PIPE_CONTROL with RC flush and CS stall."
611 * From the example in the docs, it seems to expect a regular pipe control
612 * flush here as well. We may have done it already, but meh.
614 * See also WaAvoidRCZCounterRollover.
616 brw_emit_mi_flush(brw
);
618 OUT_BATCH(_3DSTATE_CC_STATE_POINTERS
<< 16 | (2 - 2));
619 OUT_BATCH(brw
->cc
.state_offset
| 1);
621 brw_emit_pipe_control_flush(brw
, PIPE_CONTROL_RENDER_TARGET_FLUSH
|
622 PIPE_CONTROL_CS_STALL
);
625 /* Do not restore push constant packets during context restore. */
626 if (devinfo
->gen
>= 7)
627 gen10_emit_isp_disable(brw
);
629 /* Emit MI_BATCH_BUFFER_END to finish our batch. Note that execbuf2
630 * requires our batch size to be QWord aligned, so we pad it out if
631 * necessary by emitting an extra MI_NOOP after the end.
633 intel_batchbuffer_require_space(brw
, 8);
634 *brw
->batch
.map_next
++ = MI_BATCH_BUFFER_END
;
635 if (USED_BATCH(brw
->batch
) & 1) {
636 *brw
->batch
.map_next
++ = MI_NOOP
;
639 brw
->batch
.no_wrap
= false;
643 throttle(struct brw_context
*brw
)
645 /* Wait for the swapbuffers before the one we just emitted, so we
646 * don't get too many swaps outstanding for apps that are GPU-heavy
649 * We're using intelDRI2Flush (called from the loader before
650 * swapbuffer) and glFlush (for front buffer rendering) as the
651 * indicator that a frame is done and then throttle when we get
652 * here as we prepare to render the next frame. At this point for
653 * round trips for swap/copy and getting new buffers are done and
654 * we'll spend less time waiting on the GPU.
656 * Unfortunately, we don't have a handle to the batch containing
657 * the swap, and getting our hands on that doesn't seem worth it,
658 * so we just use the first batch we emitted after the last swap.
660 if (brw
->need_swap_throttle
&& brw
->throttle_batch
[0]) {
661 if (brw
->throttle_batch
[1]) {
662 if (!brw
->disable_throttling
) {
663 brw_bo_wait_rendering(brw
->throttle_batch
[1]);
665 brw_bo_unreference(brw
->throttle_batch
[1]);
667 brw
->throttle_batch
[1] = brw
->throttle_batch
[0];
668 brw
->throttle_batch
[0] = NULL
;
669 brw
->need_swap_throttle
= false;
670 /* Throttling here is more precise than the throttle ioctl, so skip it */
671 brw
->need_flush_throttle
= false;
674 if (brw
->need_flush_throttle
) {
675 __DRIscreen
*dri_screen
= brw
->screen
->driScrnPriv
;
676 drmCommandNone(dri_screen
->fd
, DRM_I915_GEM_THROTTLE
);
677 brw
->need_flush_throttle
= false;
683 struct intel_batchbuffer
*batch
,
690 struct drm_i915_gem_execbuffer2 execbuf
= {
691 .buffers_ptr
= (uintptr_t) batch
->validation_list
,
692 .buffer_count
= batch
->exec_count
,
693 .batch_start_offset
= 0,
696 .rsvd1
= ctx_id
, /* rsvd1 is actually the context ID */
699 unsigned long cmd
= DRM_IOCTL_I915_GEM_EXECBUFFER2
;
701 if (in_fence
!= -1) {
702 execbuf
.rsvd2
= in_fence
;
703 execbuf
.flags
|= I915_EXEC_FENCE_IN
;
706 if (out_fence
!= NULL
) {
707 cmd
= DRM_IOCTL_I915_GEM_EXECBUFFER2_WR
;
709 execbuf
.flags
|= I915_EXEC_FENCE_OUT
;
712 int ret
= drmIoctl(fd
, cmd
, &execbuf
);
716 for (int i
= 0; i
< batch
->exec_count
; i
++) {
717 struct brw_bo
*bo
= batch
->exec_bos
[i
];
722 /* Update brw_bo::gtt_offset */
723 if (batch
->validation_list
[i
].offset
!= bo
->gtt_offset
) {
724 assert(!(bo
->kflags
& EXEC_OBJECT_PINNED
));
725 DBG("BO %d migrated: 0x%" PRIx64
" -> 0x%llx\n",
726 bo
->gem_handle
, bo
->gtt_offset
,
727 batch
->validation_list
[i
].offset
);
728 bo
->gtt_offset
= batch
->validation_list
[i
].offset
;
732 if (ret
== 0 && out_fence
!= NULL
)
733 *out_fence
= execbuf
.rsvd2
>> 32;
739 submit_batch(struct brw_context
*brw
, int in_fence_fd
, int *out_fence_fd
)
741 __DRIscreen
*dri_screen
= brw
->screen
->driScrnPriv
;
742 struct intel_batchbuffer
*batch
= &brw
->batch
;
745 if (batch
->use_shadow_copy
) {
746 void *bo_map
= brw_bo_map(brw
, batch
->batch
.bo
, MAP_WRITE
);
747 memcpy(bo_map
, batch
->batch
.map
, 4 * USED_BATCH(*batch
));
749 bo_map
= brw_bo_map(brw
, batch
->state
.bo
, MAP_WRITE
);
750 memcpy(bo_map
, batch
->state
.map
, batch
->state_used
);
753 brw_bo_unmap(batch
->batch
.bo
);
754 brw_bo_unmap(batch
->state
.bo
);
756 if (!brw
->screen
->no_hw
) {
757 /* The requirement for using I915_EXEC_NO_RELOC are:
759 * The addresses written in the objects must match the corresponding
760 * reloc.gtt_offset which in turn must match the corresponding
763 * Any render targets written to in the batch must be flagged with
766 * To avoid stalling, execobject.offset should match the current
767 * address of that object within the active context.
769 int flags
= I915_EXEC_NO_RELOC
| I915_EXEC_RENDER
;
771 if (batch
->needs_sol_reset
)
772 flags
|= I915_EXEC_GEN7_SOL_RESET
;
774 /* Set statebuffer relocations */
775 const unsigned state_index
= batch
->state
.bo
->index
;
776 if (state_index
< batch
->exec_count
&&
777 batch
->exec_bos
[state_index
] == batch
->state
.bo
) {
778 struct drm_i915_gem_exec_object2
*entry
=
779 &batch
->validation_list
[state_index
];
780 assert(entry
->handle
== batch
->state
.bo
->gem_handle
);
781 entry
->relocation_count
= batch
->state_relocs
.reloc_count
;
782 entry
->relocs_ptr
= (uintptr_t) batch
->state_relocs
.relocs
;
785 /* Set batchbuffer relocations */
786 struct drm_i915_gem_exec_object2
*entry
= &batch
->validation_list
[0];
787 assert(entry
->handle
== batch
->batch
.bo
->gem_handle
);
788 entry
->relocation_count
= batch
->batch_relocs
.reloc_count
;
789 entry
->relocs_ptr
= (uintptr_t) batch
->batch_relocs
.relocs
;
791 if (batch
->use_batch_first
) {
792 flags
|= I915_EXEC_BATCH_FIRST
| I915_EXEC_HANDLE_LUT
;
794 /* Move the batch to the end of the validation list */
795 struct drm_i915_gem_exec_object2 tmp
;
796 struct brw_bo
*tmp_bo
;
797 const unsigned index
= batch
->exec_count
- 1;
800 *entry
= batch
->validation_list
[index
];
801 batch
->validation_list
[index
] = tmp
;
803 tmp_bo
= batch
->exec_bos
[0];
804 batch
->exec_bos
[0] = batch
->exec_bos
[index
];
805 batch
->exec_bos
[index
] = tmp_bo
;
808 ret
= execbuffer(dri_screen
->fd
, batch
, brw
->hw_ctx
,
809 4 * USED_BATCH(*batch
),
810 in_fence_fd
, out_fence_fd
, flags
);
815 if (unlikely(INTEL_DEBUG
& DEBUG_BATCH
)) {
816 gen_print_batch(&batch
->decoder
, batch
->batch
.map
,
817 4 * USED_BATCH(*batch
),
818 batch
->batch
.bo
->gtt_offset
);
821 if (brw
->ctx
.Const
.ResetStrategy
== GL_LOSE_CONTEXT_ON_RESET_ARB
)
822 brw_check_for_reset(brw
);
825 fprintf(stderr
, "i965: Failed to submit batchbuffer: %s\n",
834 * The in_fence_fd is ignored if -1. Otherwise this function takes ownership
837 * The out_fence_fd is ignored if NULL. Otherwise, the caller takes ownership
838 * of the returned fd.
841 _intel_batchbuffer_flush_fence(struct brw_context
*brw
,
842 int in_fence_fd
, int *out_fence_fd
,
843 const char *file
, int line
)
847 if (USED_BATCH(brw
->batch
) == 0)
850 /* Check that we didn't just wrap our batchbuffer at a bad time. */
851 assert(!brw
->batch
.no_wrap
);
853 brw_finish_batch(brw
);
854 brw_upload_finish(&brw
->upload
);
856 finish_growing_bos(&brw
->batch
.batch
);
857 finish_growing_bos(&brw
->batch
.state
);
859 if (brw
->throttle_batch
[0] == NULL
) {
860 brw
->throttle_batch
[0] = brw
->batch
.batch
.bo
;
861 brw_bo_reference(brw
->throttle_batch
[0]);
864 if (unlikely(INTEL_DEBUG
& (DEBUG_BATCH
| DEBUG_SUBMIT
))) {
865 int bytes_for_commands
= 4 * USED_BATCH(brw
->batch
);
866 int bytes_for_state
= brw
->batch
.state_used
;
867 fprintf(stderr
, "%19s:%-3d: Batchbuffer flush with %5db (%0.1f%%) (pkt),"
868 " %5db (%0.1f%%) (state), %4d BOs (%0.1fMb aperture),"
869 " %4d batch relocs, %4d state relocs\n", file
, line
,
870 bytes_for_commands
, 100.0f
* bytes_for_commands
/ BATCH_SZ
,
871 bytes_for_state
, 100.0f
* bytes_for_state
/ STATE_SZ
,
872 brw
->batch
.exec_count
,
873 (float) brw
->batch
.aperture_space
/ (1024 * 1024),
874 brw
->batch
.batch_relocs
.reloc_count
,
875 brw
->batch
.state_relocs
.reloc_count
);
877 dump_validation_list(&brw
->batch
);
880 ret
= submit_batch(brw
, in_fence_fd
, out_fence_fd
);
882 if (unlikely(INTEL_DEBUG
& DEBUG_SYNC
)) {
883 fprintf(stderr
, "waiting for idle\n");
884 brw_bo_wait_rendering(brw
->batch
.batch
.bo
);
887 /* Start a new batch buffer. */
894 brw_batch_has_aperture_space(struct brw_context
*brw
, unsigned extra_space
)
896 return brw
->batch
.aperture_space
+ extra_space
<=
897 brw
->screen
->aperture_threshold
;
901 brw_batch_references(struct intel_batchbuffer
*batch
, struct brw_bo
*bo
)
903 unsigned index
= READ_ONCE(bo
->index
);
904 if (index
< batch
->exec_count
&& batch
->exec_bos
[index
] == bo
)
907 for (int i
= 0; i
< batch
->exec_count
; i
++) {
908 if (batch
->exec_bos
[i
] == bo
)
914 /* This is the only way buffers get added to the validate list.
917 emit_reloc(struct intel_batchbuffer
*batch
,
918 struct brw_reloc_list
*rlist
, uint32_t offset
,
919 struct brw_bo
*target
, int32_t target_offset
,
920 unsigned int reloc_flags
)
922 assert(target
!= NULL
);
924 if (target
->kflags
& EXEC_OBJECT_PINNED
) {
925 brw_use_pinned_bo(batch
, target
, reloc_flags
& RELOC_WRITE
);
926 return gen_canonical_address(target
->gtt_offset
+ target_offset
);
929 unsigned int index
= add_exec_bo(batch
, target
);
930 struct drm_i915_gem_exec_object2
*entry
= &batch
->validation_list
[index
];
932 if (rlist
->reloc_count
== rlist
->reloc_array_size
) {
933 rlist
->reloc_array_size
*= 2;
934 rlist
->relocs
= realloc(rlist
->relocs
,
935 rlist
->reloc_array_size
*
936 sizeof(struct drm_i915_gem_relocation_entry
));
939 if (reloc_flags
& RELOC_32BIT
) {
940 /* Restrict this buffer to the low 32 bits of the address space.
942 * Altering the validation list flags restricts it for this batch,
943 * but we also alter the BO's kflags to restrict it permanently
944 * (until the BO is destroyed and put back in the cache). Buffers
945 * may stay bound across batches, and we want keep it constrained.
947 target
->kflags
&= ~EXEC_OBJECT_SUPPORTS_48B_ADDRESS
;
948 entry
->flags
&= ~EXEC_OBJECT_SUPPORTS_48B_ADDRESS
;
950 /* RELOC_32BIT is not an EXEC_OBJECT_* flag, so get rid of it. */
951 reloc_flags
&= ~RELOC_32BIT
;
955 entry
->flags
|= reloc_flags
& batch
->valid_reloc_flags
;
957 rlist
->relocs
[rlist
->reloc_count
++] =
958 (struct drm_i915_gem_relocation_entry
) {
960 .delta
= target_offset
,
961 .target_handle
= batch
->use_batch_first
? index
: target
->gem_handle
,
962 .presumed_offset
= entry
->offset
,
965 /* Using the old buffer offset, write in what the right data would be, in
966 * case the buffer doesn't move and we can short-circuit the relocation
967 * processing in the kernel
969 return entry
->offset
+ target_offset
;
973 brw_use_pinned_bo(struct intel_batchbuffer
*batch
, struct brw_bo
*bo
,
974 unsigned writable_flag
)
976 assert(bo
->kflags
& EXEC_OBJECT_PINNED
);
977 assert((writable_flag
& ~EXEC_OBJECT_WRITE
) == 0);
979 unsigned int index
= add_exec_bo(batch
, bo
);
980 struct drm_i915_gem_exec_object2
*entry
= &batch
->validation_list
[index
];
981 assert(entry
->offset
== bo
->gtt_offset
);
984 entry
->flags
|= EXEC_OBJECT_WRITE
;
988 brw_batch_reloc(struct intel_batchbuffer
*batch
, uint32_t batch_offset
,
989 struct brw_bo
*target
, uint32_t target_offset
,
990 unsigned int reloc_flags
)
992 assert(batch_offset
<= batch
->batch
.bo
->size
- sizeof(uint32_t));
994 return emit_reloc(batch
, &batch
->batch_relocs
, batch_offset
,
995 target
, target_offset
, reloc_flags
);
999 brw_state_reloc(struct intel_batchbuffer
*batch
, uint32_t state_offset
,
1000 struct brw_bo
*target
, uint32_t target_offset
,
1001 unsigned int reloc_flags
)
1003 assert(state_offset
<= batch
->state
.bo
->size
- sizeof(uint32_t));
1005 return emit_reloc(batch
, &batch
->state_relocs
, state_offset
,
1006 target
, target_offset
, reloc_flags
);
1010 * Reserve some space in the statebuffer, or flush.
1012 * This is used to estimate when we're near the end of the batch,
1013 * so we can flush early.
1016 brw_require_statebuffer_space(struct brw_context
*brw
, int size
)
1018 if (brw
->batch
.state_used
+ size
>= STATE_SZ
)
1019 intel_batchbuffer_flush(brw
);
1023 * Allocates a block of space in the batchbuffer for indirect state.
1026 brw_state_batch(struct brw_context
*brw
,
1029 uint32_t *out_offset
)
1031 struct intel_batchbuffer
*batch
= &brw
->batch
;
1033 assert(size
< batch
->state
.bo
->size
);
1035 uint32_t offset
= ALIGN(batch
->state_used
, alignment
);
1037 if (offset
+ size
>= STATE_SZ
&& !batch
->no_wrap
) {
1038 intel_batchbuffer_flush(brw
);
1039 offset
= ALIGN(batch
->state_used
, alignment
);
1040 } else if (offset
+ size
>= batch
->state
.bo
->size
) {
1041 const unsigned new_size
=
1042 MIN2(batch
->state
.bo
->size
+ batch
->state
.bo
->size
/ 2,
1044 grow_buffer(brw
, &batch
->state
, batch
->state_used
, new_size
);
1045 assert(offset
+ size
< batch
->state
.bo
->size
);
1048 if (unlikely(INTEL_DEBUG
& DEBUG_BATCH
)) {
1049 _mesa_hash_table_insert(batch
->state_batch_sizes
,
1050 (void *) (uintptr_t) offset
,
1051 (void *) (uintptr_t) size
);
1054 batch
->state_used
= offset
+ size
;
1056 *out_offset
= offset
;
1057 return batch
->state
.map
+ (offset
>> 2);
1061 intel_batchbuffer_data(struct brw_context
*brw
,
1062 const void *data
, GLuint bytes
)
1064 assert((bytes
& 3) == 0);
1065 intel_batchbuffer_require_space(brw
, bytes
);
1066 memcpy(brw
->batch
.map_next
, data
, bytes
);
1067 brw
->batch
.map_next
+= bytes
>> 2;
1071 load_sized_register_mem(struct brw_context
*brw
,
1077 const struct gen_device_info
*devinfo
= &brw
->screen
->devinfo
;
1080 /* MI_LOAD_REGISTER_MEM only exists on Gen7+. */
1081 assert(devinfo
->gen
>= 7);
1083 if (devinfo
->gen
>= 8) {
1084 BEGIN_BATCH(4 * size
);
1085 for (i
= 0; i
< size
; i
++) {
1086 OUT_BATCH(GEN7_MI_LOAD_REGISTER_MEM
| (4 - 2));
1087 OUT_BATCH(reg
+ i
* 4);
1088 OUT_RELOC64(bo
, 0, offset
+ i
* 4);
1092 BEGIN_BATCH(3 * size
);
1093 for (i
= 0; i
< size
; i
++) {
1094 OUT_BATCH(GEN7_MI_LOAD_REGISTER_MEM
| (3 - 2));
1095 OUT_BATCH(reg
+ i
* 4);
1096 OUT_RELOC(bo
, 0, offset
+ i
* 4);
1103 brw_load_register_mem(struct brw_context
*brw
,
1108 load_sized_register_mem(brw
, reg
, bo
, offset
, 1);
1112 brw_load_register_mem64(struct brw_context
*brw
,
1117 load_sized_register_mem(brw
, reg
, bo
, offset
, 2);
1121 * Write an arbitrary 32-bit register to a buffer via MI_STORE_REGISTER_MEM.
1124 brw_store_register_mem32(struct brw_context
*brw
,
1125 struct brw_bo
*bo
, uint32_t reg
, uint32_t offset
)
1127 const struct gen_device_info
*devinfo
= &brw
->screen
->devinfo
;
1129 assert(devinfo
->gen
>= 6);
1131 if (devinfo
->gen
>= 8) {
1133 OUT_BATCH(MI_STORE_REGISTER_MEM
| (4 - 2));
1135 OUT_RELOC64(bo
, RELOC_WRITE
, offset
);
1139 OUT_BATCH(MI_STORE_REGISTER_MEM
| (3 - 2));
1141 OUT_RELOC(bo
, RELOC_WRITE
| RELOC_NEEDS_GGTT
, offset
);
1147 * Write an arbitrary 64-bit register to a buffer via MI_STORE_REGISTER_MEM.
1150 brw_store_register_mem64(struct brw_context
*brw
,
1151 struct brw_bo
*bo
, uint32_t reg
, uint32_t offset
)
1153 const struct gen_device_info
*devinfo
= &brw
->screen
->devinfo
;
1155 assert(devinfo
->gen
>= 6);
1157 /* MI_STORE_REGISTER_MEM only stores a single 32-bit value, so to
1158 * read a full 64-bit register, we need to do two of them.
1160 if (devinfo
->gen
>= 8) {
1162 OUT_BATCH(MI_STORE_REGISTER_MEM
| (4 - 2));
1164 OUT_RELOC64(bo
, RELOC_WRITE
, offset
);
1165 OUT_BATCH(MI_STORE_REGISTER_MEM
| (4 - 2));
1166 OUT_BATCH(reg
+ sizeof(uint32_t));
1167 OUT_RELOC64(bo
, RELOC_WRITE
, offset
+ sizeof(uint32_t));
1171 OUT_BATCH(MI_STORE_REGISTER_MEM
| (3 - 2));
1173 OUT_RELOC(bo
, RELOC_WRITE
| RELOC_NEEDS_GGTT
, offset
);
1174 OUT_BATCH(MI_STORE_REGISTER_MEM
| (3 - 2));
1175 OUT_BATCH(reg
+ sizeof(uint32_t));
1176 OUT_RELOC(bo
, RELOC_WRITE
| RELOC_NEEDS_GGTT
, offset
+ sizeof(uint32_t));
1182 * Write a 32-bit register using immediate data.
1185 brw_load_register_imm32(struct brw_context
*brw
, uint32_t reg
, uint32_t imm
)
1187 assert(brw
->screen
->devinfo
.gen
>= 6);
1190 OUT_BATCH(MI_LOAD_REGISTER_IMM
| (3 - 2));
1197 * Write a 64-bit register using immediate data.
1200 brw_load_register_imm64(struct brw_context
*brw
, uint32_t reg
, uint64_t imm
)
1202 assert(brw
->screen
->devinfo
.gen
>= 6);
1205 OUT_BATCH(MI_LOAD_REGISTER_IMM
| (5 - 2));
1207 OUT_BATCH(imm
& 0xffffffff);
1209 OUT_BATCH(imm
>> 32);
1214 * Copies a 32-bit register.
1217 brw_load_register_reg(struct brw_context
*brw
, uint32_t src
, uint32_t dest
)
1219 assert(brw
->screen
->devinfo
.gen
>= 8 || brw
->screen
->devinfo
.is_haswell
);
1222 OUT_BATCH(MI_LOAD_REGISTER_REG
| (3 - 2));
1229 * Copies a 64-bit register.
1232 brw_load_register_reg64(struct brw_context
*brw
, uint32_t src
, uint32_t dest
)
1234 assert(brw
->screen
->devinfo
.gen
>= 8 || brw
->screen
->devinfo
.is_haswell
);
1237 OUT_BATCH(MI_LOAD_REGISTER_REG
| (3 - 2));
1240 OUT_BATCH(MI_LOAD_REGISTER_REG
| (3 - 2));
1241 OUT_BATCH(src
+ sizeof(uint32_t));
1242 OUT_BATCH(dest
+ sizeof(uint32_t));
1247 * Write 32-bits of immediate data to a GPU memory buffer.
1250 brw_store_data_imm32(struct brw_context
*brw
, struct brw_bo
*bo
,
1251 uint32_t offset
, uint32_t imm
)
1253 const struct gen_device_info
*devinfo
= &brw
->screen
->devinfo
;
1255 assert(devinfo
->gen
>= 6);
1258 OUT_BATCH(MI_STORE_DATA_IMM
| (4 - 2));
1259 if (devinfo
->gen
>= 8)
1260 OUT_RELOC64(bo
, RELOC_WRITE
, offset
);
1262 OUT_BATCH(0); /* MBZ */
1263 OUT_RELOC(bo
, RELOC_WRITE
, offset
);
1270 * Write 64-bits of immediate data to a GPU memory buffer.
1273 brw_store_data_imm64(struct brw_context
*brw
, struct brw_bo
*bo
,
1274 uint32_t offset
, uint64_t imm
)
1276 const struct gen_device_info
*devinfo
= &brw
->screen
->devinfo
;
1278 assert(devinfo
->gen
>= 6);
1281 OUT_BATCH(MI_STORE_DATA_IMM
| (5 - 2));
1282 if (devinfo
->gen
>= 8)
1283 OUT_RELOC64(bo
, RELOC_WRITE
, offset
);
1285 OUT_BATCH(0); /* MBZ */
1286 OUT_RELOC(bo
, RELOC_WRITE
, offset
);
1288 OUT_BATCH(imm
& 0xffffffffu
);
1289 OUT_BATCH(imm
>> 32);