1 /**************************************************************************
3 * Copyright 2006 VMware, Inc.
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the
8 * "Software"), to deal in the Software without restriction, including
9 * without limitation the rights to use, copy, modify, merge, publish,
10 * distribute, sub license, and/or sell copies of the Software, and to
11 * permit persons to whom the Software is furnished to do so, subject to
12 * the following conditions:
14 * The above copyright notice and this permission notice (including the
15 * next paragraph) shall be included in all copies or substantial portions
18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
19 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
20 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
21 * IN NO EVENT SHALL VMWARE AND/OR ITS SUPPLIERS BE LIABLE FOR
22 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
23 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
24 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
26 **************************************************************************/
29 #include <GL/internal/dri_interface.h>
31 #include "intel_batchbuffer.h"
32 #include "intel_chipset.h"
33 #include "intel_mipmap_tree.h"
34 #include "intel_regions.h"
35 #include "intel_resolve_map.h"
36 #include "intel_tex.h"
37 #include "intel_blit.h"
38 #include "intel_fbo.h"
40 #include "brw_blorp.h"
41 #include "brw_context.h"
43 #include "main/enums.h"
44 #include "main/formats.h"
45 #include "main/glformats.h"
46 #include "main/texcompress_etc.h"
47 #include "main/teximage.h"
48 #include "main/streaming-load-memcpy.h"
50 #define FILE_DEBUG_FLAG DEBUG_MIPTREE
53 * Determine which MSAA layout should be used by the MSAA surface being
54 * created, based on the chip generation and the surface type.
56 static enum intel_msaa_layout
57 compute_msaa_layout(struct brw_context
*brw
, mesa_format format
, GLenum target
)
59 /* Prior to Gen7, all MSAA surfaces used IMS layout. */
61 return INTEL_MSAA_LAYOUT_IMS
;
63 /* In Gen7, IMS layout is only used for depth and stencil buffers. */
64 switch (_mesa_get_format_base_format(format
)) {
65 case GL_DEPTH_COMPONENT
:
66 case GL_STENCIL_INDEX
:
67 case GL_DEPTH_STENCIL
:
68 return INTEL_MSAA_LAYOUT_IMS
;
70 /* Disable MCS on Broadwell for now. We can enable it once things
71 * are working without it.
74 perf_debug("Missing CMS support on Broadwell.\n");
75 return INTEL_MSAA_LAYOUT_UMS
;
78 /* From the Ivy Bridge PRM, Vol4 Part1 p77 ("MCS Enable"):
80 * This field must be set to 0 for all SINT MSRTs when all RT channels
83 * In practice this means that we have to disable MCS for all signed
84 * integer MSAA buffers. The alternative, to disable MCS only when one
85 * of the render target channels is disabled, is impractical because it
86 * would require converting between CMS and UMS MSAA layouts on the fly,
89 if (_mesa_get_format_datatype(format
) == GL_INT
) {
90 /* TODO: is this workaround needed for future chipsets? */
91 assert(brw
->gen
== 7);
92 return INTEL_MSAA_LAYOUT_UMS
;
94 return INTEL_MSAA_LAYOUT_CMS
;
101 * For single-sampled render targets ("non-MSRT"), the MCS buffer is a
102 * scaled-down bitfield representation of the color buffer which is capable of
103 * recording when blocks of the color buffer are equal to the clear value.
104 * This function returns the block size that will be used by the MCS buffer
105 * corresponding to a certain color miptree.
107 * From the Ivy Bridge PRM, Vol2 Part1 11.7 "MCS Buffer for Render Target(s)",
108 * beneath the "Fast Color Clear" bullet (p327):
110 * The following table describes the RT alignment
124 * This alignment has the following uses:
126 * - For figuring out the size of the MCS buffer. Each 4k tile in the MCS
127 * buffer contains 128 blocks horizontally and 256 blocks vertically.
129 * - For figuring out alignment restrictions for a fast clear operation. Fast
130 * clear operations must always clear aligned multiples of 16 blocks
131 * horizontally and 32 blocks vertically.
133 * - For scaling down the coordinates sent through the render pipeline during
134 * a fast clear. X coordinates must be scaled down by 8 times the block
135 * width, and Y coordinates by 16 times the block height.
137 * - For scaling down the coordinates sent through the render pipeline during
138 * a "Render Target Resolve" operation. X coordinates must be scaled down
139 * by half the block width, and Y coordinates by half the block height.
142 intel_get_non_msrt_mcs_alignment(struct brw_context
*brw
,
143 struct intel_mipmap_tree
*mt
,
144 unsigned *width_px
, unsigned *height
)
146 switch (mt
->region
->tiling
) {
148 assert(!"Non-MSRT MCS requires X or Y tiling");
149 /* In release builds, fall through */
151 *width_px
= 32 / mt
->cpp
;
155 *width_px
= 64 / mt
->cpp
;
162 * For a single-sampled render target ("non-MSRT"), determine if an MCS buffer
165 * From the Ivy Bridge PRM, Vol2 Part1 11.7 "MCS Buffer for Render Target(s)",
166 * beneath the "Fast Color Clear" bullet (p326):
168 * - Support is limited to tiled render targets.
169 * - Support is for non-mip-mapped and non-array surface types only.
171 * And then later, on p327:
173 * - MCS buffer for non-MSRT is supported only for RT formats 32bpp,
177 intel_is_non_msrt_mcs_buffer_supported(struct brw_context
*brw
,
178 struct intel_mipmap_tree
*mt
)
180 /* MCS support does not exist prior to Gen7 */
181 if (brw
->gen
< 7 || brw
->gen
>= 8)
184 /* MCS is only supported for color buffers */
185 switch (_mesa_get_format_base_format(mt
->format
)) {
186 case GL_DEPTH_COMPONENT
:
187 case GL_DEPTH_STENCIL
:
188 case GL_STENCIL_INDEX
:
192 if (mt
->region
->tiling
!= I915_TILING_X
&&
193 mt
->region
->tiling
!= I915_TILING_Y
)
195 if (mt
->cpp
!= 4 && mt
->cpp
!= 8 && mt
->cpp
!= 16)
197 if (mt
->first_level
!= 0 || mt
->last_level
!= 0)
199 if (mt
->physical_depth0
!= 1)
202 /* There's no point in using an MCS buffer if the surface isn't in a
205 if (!brw
->format_supported_as_render_target
[mt
->format
])
213 * @param for_bo Indicates that the caller is
214 * intel_miptree_create_for_bo(). If true, then do not create
217 struct intel_mipmap_tree
*
218 intel_miptree_create_layout(struct brw_context
*brw
,
229 struct intel_mipmap_tree
*mt
= calloc(sizeof(*mt
), 1);
233 DBG("%s target %s format %s level %d..%d <-- %p\n", __FUNCTION__
,
234 _mesa_lookup_enum_by_nr(target
),
235 _mesa_get_format_name(format
),
236 first_level
, last_level
, mt
);
240 mt
->first_level
= first_level
;
241 mt
->last_level
= last_level
;
242 mt
->logical_width0
= width0
;
243 mt
->logical_height0
= height0
;
244 mt
->logical_depth0
= depth0
;
245 mt
->fast_clear_state
= INTEL_FAST_CLEAR_STATE_NO_MCS
;
247 /* The cpp is bytes per (1, blockheight)-sized block for compressed
248 * textures. This is why you'll see divides by blockheight all over
251 _mesa_get_format_block_size(format
, &bw
, &bh
);
252 assert(_mesa_get_format_bytes(mt
->format
) % bw
== 0);
253 mt
->cpp
= _mesa_get_format_bytes(mt
->format
) / bw
;
255 mt
->num_samples
= num_samples
;
256 mt
->compressed
= _mesa_is_format_compressed(format
);
257 mt
->msaa_layout
= INTEL_MSAA_LAYOUT_NONE
;
260 if (num_samples
> 1) {
261 /* Adjust width/height/depth for MSAA */
262 mt
->msaa_layout
= compute_msaa_layout(brw
, format
, mt
->target
);
263 if (mt
->msaa_layout
== INTEL_MSAA_LAYOUT_IMS
) {
264 /* In the Sandy Bridge PRM, volume 4, part 1, page 31, it says:
266 * "Any of the other messages (sample*, LOD, load4) used with a
267 * (4x) multisampled surface will in-effect sample a surface with
268 * double the height and width as that indicated in the surface
269 * state. Each pixel position on the original-sized surface is
270 * replaced with a 2x2 of samples with the following arrangement:
275 * Thus, when sampling from a multisampled texture, it behaves as
276 * though the layout in memory for (x,y,sample) is:
278 * (0,0,0) (0,0,2) (1,0,0) (1,0,2)
279 * (0,0,1) (0,0,3) (1,0,1) (1,0,3)
281 * (0,1,0) (0,1,2) (1,1,0) (1,1,2)
282 * (0,1,1) (0,1,3) (1,1,1) (1,1,3)
284 * However, the actual layout of multisampled data in memory is:
286 * (0,0,0) (1,0,0) (0,0,1) (1,0,1)
287 * (0,1,0) (1,1,0) (0,1,1) (1,1,1)
289 * (0,0,2) (1,0,2) (0,0,3) (1,0,3)
290 * (0,1,2) (1,1,2) (0,1,3) (1,1,3)
292 * This pattern repeats for each 2x2 pixel block.
294 * As a result, when calculating the size of our 4-sample buffer for
295 * an odd width or height, we have to align before scaling up because
296 * sample 3 is in that bottom right 2x2 block.
298 switch (num_samples
) {
300 assert(brw
->gen
>= 8);
301 width0
= ALIGN(width0
, 2) * 2;
302 height0
= ALIGN(height0
, 2);
305 width0
= ALIGN(width0
, 2) * 2;
306 height0
= ALIGN(height0
, 2) * 2;
309 width0
= ALIGN(width0
, 2) * 4;
310 height0
= ALIGN(height0
, 2) * 2;
313 /* num_samples should already have been quantized to 0, 1, 2, 4, or
319 /* Non-interleaved */
320 depth0
*= num_samples
;
324 /* array_spacing_lod0 is only used for non-IMS MSAA surfaces. TODO: can we
327 switch (mt
->msaa_layout
) {
328 case INTEL_MSAA_LAYOUT_NONE
:
329 case INTEL_MSAA_LAYOUT_IMS
:
330 mt
->array_spacing_lod0
= false;
332 case INTEL_MSAA_LAYOUT_UMS
:
333 case INTEL_MSAA_LAYOUT_CMS
:
334 mt
->array_spacing_lod0
= true;
338 if (target
== GL_TEXTURE_CUBE_MAP
) {
343 mt
->physical_width0
= width0
;
344 mt
->physical_height0
= height0
;
345 mt
->physical_depth0
= depth0
;
348 _mesa_get_format_base_format(format
) == GL_DEPTH_STENCIL
&&
349 (brw
->must_use_separate_stencil
||
350 (brw
->has_separate_stencil
&& brw_is_hiz_depth_format(brw
, format
)))) {
351 mt
->stencil_mt
= intel_miptree_create(brw
,
361 INTEL_MIPTREE_TILING_ANY
);
362 if (!mt
->stencil_mt
) {
363 intel_miptree_release(&mt
);
367 /* Fix up the Z miptree format for how we're splitting out separate
368 * stencil. Gen7 expects there to be no stencil bits in its depth buffer.
370 if (mt
->format
== MESA_FORMAT_Z24_UNORM_S8_UINT
) {
371 mt
->format
= MESA_FORMAT_Z24_UNORM_X8_UINT
;
372 } else if (mt
->format
== MESA_FORMAT_Z32_FLOAT_S8X24_UINT
) {
373 mt
->format
= MESA_FORMAT_Z_FLOAT32
;
376 _mesa_problem(NULL
, "Unknown format %s in separate stencil mt\n",
377 _mesa_get_format_name(mt
->format
));
381 brw_miptree_layout(brw
, mt
);
387 * \brief Helper function for intel_miptree_create().
390 intel_miptree_choose_tiling(struct brw_context
*brw
,
393 uint32_t num_samples
,
394 enum intel_miptree_tiling_mode requested
,
395 struct intel_mipmap_tree
*mt
)
397 if (format
== MESA_FORMAT_S_UINT8
) {
398 /* The stencil buffer is W tiled. However, we request from the kernel a
399 * non-tiled buffer because the GTT is incapable of W fencing.
401 return I915_TILING_NONE
;
404 /* Some usages may want only one type of tiling, like depth miptrees (Y
405 * tiled), or temporary BOs for uploading data once (linear).
408 case INTEL_MIPTREE_TILING_ANY
:
410 case INTEL_MIPTREE_TILING_Y
:
411 return I915_TILING_Y
;
412 case INTEL_MIPTREE_TILING_NONE
:
413 return I915_TILING_NONE
;
416 if (num_samples
> 1) {
417 /* From p82 of the Sandy Bridge PRM, dw3[1] of SURFACE_STATE ("Tiled
420 * [DevSNB+]: For multi-sample render targets, this field must be
421 * 1. MSRTs can only be tiled.
423 * Our usual reason for preferring X tiling (fast blits using the
424 * blitting engine) doesn't apply to MSAA, since we'll generally be
425 * downsampling or upsampling when blitting between the MSAA buffer
426 * and another buffer, and the blitting engine doesn't support that.
427 * So use Y tiling, since it makes better use of the cache.
429 return I915_TILING_Y
;
432 GLenum base_format
= _mesa_get_format_base_format(format
);
433 if (base_format
== GL_DEPTH_COMPONENT
||
434 base_format
== GL_DEPTH_STENCIL_EXT
)
435 return I915_TILING_Y
;
437 int minimum_pitch
= mt
->total_width
* mt
->cpp
;
439 /* If the width is much smaller than a tile, don't bother tiling. */
440 if (minimum_pitch
< 64)
441 return I915_TILING_NONE
;
443 if (ALIGN(minimum_pitch
, 512) >= 32768 ||
444 mt
->total_width
>= 32768 || mt
->total_height
>= 32768) {
445 perf_debug("%dx%d miptree too large to blit, falling back to untiled",
446 mt
->total_width
, mt
->total_height
);
447 return I915_TILING_NONE
;
450 /* Pre-gen6 doesn't have BLORP to handle Y-tiling, so use X-tiling. */
452 return I915_TILING_X
;
454 /* From the Sandybridge PRM, Volume 1, Part 2, page 32:
455 * "NOTE: 128BPE Format Color Buffer ( render target ) MUST be either TileX
457 * 128 bits per pixel translates to 16 bytes per pixel. This is necessary
458 * all the way back to 965, but is explicitly permitted on Gen7.
460 if (brw
->gen
!= 7 && mt
->cpp
>= 16)
461 return I915_TILING_X
;
463 /* From the Ivy Bridge PRM, Vol4 Part1 2.12.2.1 (SURFACE_STATE for most
464 * messages), on p64, under the heading "Surface Vertical Alignment":
466 * This field must be set to VALIGN_4 for all tiled Y Render Target
469 * So if the surface is renderable and uses a vertical alignment of 2,
470 * force it to be X tiled. This is somewhat conservative (it's possible
471 * that the client won't ever render to this surface), but it's difficult
472 * to know that ahead of time. And besides, since we use a vertical
473 * alignment of 4 as often as we can, this shouldn't happen very often.
475 if (brw
->gen
== 7 && mt
->align_h
== 2 &&
476 brw
->format_supported_as_render_target
[format
]) {
477 return I915_TILING_X
;
480 return I915_TILING_Y
| I915_TILING_X
;
483 struct intel_mipmap_tree
*
484 intel_miptree_create(struct brw_context
*brw
,
492 bool expect_accelerated_upload
,
494 enum intel_miptree_tiling_mode requested_tiling
)
496 struct intel_mipmap_tree
*mt
;
497 mesa_format tex_format
= format
;
498 mesa_format etc_format
= MESA_FORMAT_NONE
;
499 GLuint total_width
, total_height
;
501 if (brw
->gen
< 8 && !brw
->is_baytrail
) {
503 case MESA_FORMAT_ETC1_RGB8
:
504 format
= MESA_FORMAT_R8G8B8X8_UNORM
;
506 case MESA_FORMAT_ETC2_RGB8
:
507 format
= MESA_FORMAT_R8G8B8X8_UNORM
;
509 case MESA_FORMAT_ETC2_SRGB8
:
510 case MESA_FORMAT_ETC2_SRGB8_ALPHA8_EAC
:
511 case MESA_FORMAT_ETC2_SRGB8_PUNCHTHROUGH_ALPHA1
:
512 format
= MESA_FORMAT_B8G8R8A8_SRGB
;
514 case MESA_FORMAT_ETC2_RGBA8_EAC
:
515 case MESA_FORMAT_ETC2_RGB8_PUNCHTHROUGH_ALPHA1
:
516 format
= MESA_FORMAT_R8G8B8A8_UNORM
;
518 case MESA_FORMAT_ETC2_R11_EAC
:
519 format
= MESA_FORMAT_R_UNORM16
;
521 case MESA_FORMAT_ETC2_SIGNED_R11_EAC
:
522 format
= MESA_FORMAT_R_SNORM16
;
524 case MESA_FORMAT_ETC2_RG11_EAC
:
525 format
= MESA_FORMAT_R16G16_UNORM
;
527 case MESA_FORMAT_ETC2_SIGNED_RG11_EAC
:
528 format
= MESA_FORMAT_R16G16_SNORM
;
531 /* Non ETC1 / ETC2 format */
536 etc_format
= (format
!= tex_format
) ? tex_format
: MESA_FORMAT_NONE
;
538 mt
= intel_miptree_create_layout(brw
, target
, format
,
539 first_level
, last_level
, width0
,
543 * pitch == 0 || height == 0 indicates the null texture
545 if (!mt
|| !mt
->total_width
|| !mt
->total_height
) {
546 intel_miptree_release(&mt
);
550 total_width
= mt
->total_width
;
551 total_height
= mt
->total_height
;
553 if (format
== MESA_FORMAT_S_UINT8
) {
554 /* Align to size of W tile, 64x64. */
555 total_width
= ALIGN(total_width
, 64);
556 total_height
= ALIGN(total_height
, 64);
559 uint32_t tiling
= intel_miptree_choose_tiling(brw
, format
, width0
,
560 num_samples
, requested_tiling
,
562 bool y_or_x
= tiling
== (I915_TILING_Y
| I915_TILING_X
);
564 mt
->etc_format
= etc_format
;
565 mt
->region
= intel_region_alloc(brw
->intelScreen
,
566 y_or_x
? I915_TILING_Y
: tiling
,
570 expect_accelerated_upload
);
572 /* If the region is too large to fit in the aperture, we need to use the
573 * BLT engine to support it. The BLT paths can't currently handle Y-tiling,
574 * so we need to fall back to X.
576 if (y_or_x
&& mt
->region
->bo
->size
>= brw
->max_gtt_map_object_size
) {
577 perf_debug("%dx%d miptree larger than aperture; falling back to X-tiled\n",
578 mt
->total_width
, mt
->total_height
);
579 intel_region_release(&mt
->region
);
581 mt
->region
= intel_region_alloc(brw
->intelScreen
,
586 expect_accelerated_upload
);
592 intel_miptree_release(&mt
);
597 if (mt
->msaa_layout
== INTEL_MSAA_LAYOUT_CMS
) {
598 if (!intel_miptree_alloc_mcs(brw
, mt
, num_samples
)) {
599 intel_miptree_release(&mt
);
604 /* If this miptree is capable of supporting fast color clears, set
605 * fast_clear_state appropriately to ensure that fast clears will occur.
606 * Allocation of the MCS miptree will be deferred until the first fast
607 * clear actually occurs.
609 if (intel_is_non_msrt_mcs_buffer_supported(brw
, mt
))
610 mt
->fast_clear_state
= INTEL_FAST_CLEAR_STATE_RESOLVED
;
615 struct intel_mipmap_tree
*
616 intel_miptree_create_for_bo(struct brw_context
*brw
,
625 struct intel_mipmap_tree
*mt
;
627 struct intel_region
*region
= calloc(1, sizeof(*region
));
631 /* Nothing will be able to use this miptree with the BO if the offset isn't
634 if (tiling
!= I915_TILING_NONE
)
635 assert(offset
% 4096 == 0);
637 /* miptrees can't handle negative pitch. If you need flipping of images,
638 * that's outside of the scope of the mt.
642 mt
= intel_miptree_create_layout(brw
, GL_TEXTURE_2D
, format
,
645 true, 0 /* num_samples */);
651 region
->cpp
= mt
->cpp
;
652 region
->width
= width
;
653 region
->height
= height
;
654 region
->pitch
= pitch
;
655 region
->refcount
= 1;
656 drm_intel_bo_reference(bo
);
658 region
->tiling
= tiling
;
667 * For a singlesample image buffer, this simply wraps the given region with a miptree.
669 * For a multisample image buffer, this wraps the given region with
670 * a singlesample miptree, then creates a multisample miptree into which the
671 * singlesample miptree is embedded as a child.
674 intel_update_winsys_renderbuffer_miptree(struct brw_context
*intel
,
675 struct intel_renderbuffer
*irb
,
676 struct intel_region
*region
)
678 struct intel_mipmap_tree
*singlesample_mt
= NULL
;
679 struct intel_mipmap_tree
*multisample_mt
= NULL
;
680 struct gl_renderbuffer
*rb
= &irb
->Base
.Base
;
681 mesa_format format
= rb
->Format
;
682 int num_samples
= rb
->NumSamples
;
684 intel_miptree_release(&irb
->mt
);
686 /* Only the front and back buffers, which are color buffers, are allocated
687 * through the image loader.
689 assert(_mesa_get_format_base_format(format
) == GL_RGB
||
690 _mesa_get_format_base_format(format
) == GL_RGBA
);
692 singlesample_mt
= intel_miptree_create_for_bo(intel
,
700 if (!singlesample_mt
)
702 singlesample_mt
->region
->name
= region
->name
;
704 /* If this miptree is capable of supporting fast color clears, set
705 * mcs_state appropriately to ensure that fast clears will occur.
706 * Allocation of the MCS miptree will be deferred until the first fast
707 * clear actually occurs.
709 if (intel_is_non_msrt_mcs_buffer_supported(intel
, singlesample_mt
))
710 singlesample_mt
->fast_clear_state
= INTEL_FAST_CLEAR_STATE_RESOLVED
;
712 if (num_samples
== 0) {
713 irb
->mt
= singlesample_mt
;
717 multisample_mt
= intel_miptree_create_for_renderbuffer(intel
,
722 if (!multisample_mt
) {
723 intel_miptree_release(&singlesample_mt
);
727 irb
->need_downsample
= false;
728 irb
->mt
= multisample_mt
;
729 irb
->singlesample_mt
= singlesample_mt
;
732 struct intel_mipmap_tree
*
733 intel_miptree_create_for_renderbuffer(struct brw_context
*brw
,
737 uint32_t num_samples
)
739 struct intel_mipmap_tree
*mt
;
742 GLenum target
= num_samples
> 1 ? GL_TEXTURE_2D_MULTISAMPLE
: GL_TEXTURE_2D
;
744 mt
= intel_miptree_create(brw
, target
, format
, 0, 0,
745 width
, height
, depth
, true, num_samples
,
746 INTEL_MIPTREE_TILING_ANY
);
750 if (brw_is_hiz_depth_format(brw
, format
)) {
751 ok
= intel_miptree_alloc_hiz(brw
, mt
);
759 intel_miptree_release(&mt
);
764 intel_miptree_reference(struct intel_mipmap_tree
**dst
,
765 struct intel_mipmap_tree
*src
)
770 intel_miptree_release(dst
);
774 DBG("%s %p refcount now %d\n", __FUNCTION__
, src
, src
->refcount
);
782 intel_miptree_release(struct intel_mipmap_tree
**mt
)
787 DBG("%s %p refcount will be %d\n", __FUNCTION__
, *mt
, (*mt
)->refcount
- 1);
788 if (--(*mt
)->refcount
<= 0) {
791 DBG("%s deleting %p\n", __FUNCTION__
, *mt
);
793 intel_region_release(&((*mt
)->region
));
794 intel_miptree_release(&(*mt
)->stencil_mt
);
795 intel_miptree_release(&(*mt
)->hiz_mt
);
796 intel_miptree_release(&(*mt
)->mcs_mt
);
797 intel_resolve_map_clear(&(*mt
)->hiz_map
);
799 for (i
= 0; i
< MAX_TEXTURE_LEVELS
; i
++) {
800 free((*mt
)->level
[i
].slice
);
809 intel_miptree_get_dimensions_for_image(struct gl_texture_image
*image
,
810 int *width
, int *height
, int *depth
)
812 switch (image
->TexObject
->Target
) {
813 case GL_TEXTURE_1D_ARRAY
:
814 *width
= image
->Width
;
816 *depth
= image
->Height
;
819 *width
= image
->Width
;
820 *height
= image
->Height
;
821 *depth
= image
->Depth
;
827 * Can the image be pulled into a unified mipmap tree? This mirrors
828 * the completeness test in a lot of ways.
830 * Not sure whether I want to pass gl_texture_image here.
833 intel_miptree_match_image(struct intel_mipmap_tree
*mt
,
834 struct gl_texture_image
*image
)
836 struct intel_texture_image
*intelImage
= intel_texture_image(image
);
837 GLuint level
= intelImage
->base
.Base
.Level
;
838 int width
, height
, depth
;
840 /* glTexImage* choose the texture object based on the target passed in, and
841 * objects can't change targets over their lifetimes, so this should be
844 assert(image
->TexObject
->Target
== mt
->target
);
846 mesa_format mt_format
= mt
->format
;
847 if (mt
->format
== MESA_FORMAT_Z24_UNORM_X8_UINT
&& mt
->stencil_mt
)
848 mt_format
= MESA_FORMAT_Z24_UNORM_S8_UINT
;
849 if (mt
->format
== MESA_FORMAT_Z_FLOAT32
&& mt
->stencil_mt
)
850 mt_format
= MESA_FORMAT_Z32_FLOAT_S8X24_UINT
;
851 if (mt
->etc_format
!= MESA_FORMAT_NONE
)
852 mt_format
= mt
->etc_format
;
854 if (image
->TexFormat
!= mt_format
)
857 intel_miptree_get_dimensions_for_image(image
, &width
, &height
, &depth
);
859 if (mt
->target
== GL_TEXTURE_CUBE_MAP
)
862 int level_depth
= mt
->level
[level
].depth
;
863 if (mt
->num_samples
> 1) {
864 switch (mt
->msaa_layout
) {
865 case INTEL_MSAA_LAYOUT_NONE
:
866 case INTEL_MSAA_LAYOUT_IMS
:
868 case INTEL_MSAA_LAYOUT_UMS
:
869 case INTEL_MSAA_LAYOUT_CMS
:
870 level_depth
/= mt
->num_samples
;
875 /* Test image dimensions against the base level image adjusted for
876 * minification. This will also catch images not present in the
877 * tree, changed targets, etc.
879 if (width
!= minify(mt
->logical_width0
, level
) ||
880 height
!= minify(mt
->logical_height0
, level
) ||
881 depth
!= level_depth
) {
885 if (image
->NumSamples
!= mt
->num_samples
)
893 intel_miptree_set_level_info(struct intel_mipmap_tree
*mt
,
895 GLuint x
, GLuint y
, GLuint d
)
897 mt
->level
[level
].depth
= d
;
898 mt
->level
[level
].level_x
= x
;
899 mt
->level
[level
].level_y
= y
;
901 DBG("%s level %d, depth %d, offset %d,%d\n", __FUNCTION__
,
904 assert(mt
->level
[level
].slice
== NULL
);
906 mt
->level
[level
].slice
= calloc(d
, sizeof(*mt
->level
[0].slice
));
907 mt
->level
[level
].slice
[0].x_offset
= mt
->level
[level
].level_x
;
908 mt
->level
[level
].slice
[0].y_offset
= mt
->level
[level
].level_y
;
913 intel_miptree_set_image_offset(struct intel_mipmap_tree
*mt
,
914 GLuint level
, GLuint img
,
917 if (img
== 0 && level
== 0)
918 assert(x
== 0 && y
== 0);
920 assert(img
< mt
->level
[level
].depth
);
922 mt
->level
[level
].slice
[img
].x_offset
= mt
->level
[level
].level_x
+ x
;
923 mt
->level
[level
].slice
[img
].y_offset
= mt
->level
[level
].level_y
+ y
;
925 DBG("%s level %d img %d pos %d,%d\n",
926 __FUNCTION__
, level
, img
,
927 mt
->level
[level
].slice
[img
].x_offset
,
928 mt
->level
[level
].slice
[img
].y_offset
);
932 intel_miptree_get_image_offset(struct intel_mipmap_tree
*mt
,
933 GLuint level
, GLuint slice
,
934 GLuint
*x
, GLuint
*y
)
936 assert(slice
< mt
->level
[level
].depth
);
938 *x
= mt
->level
[level
].slice
[slice
].x_offset
;
939 *y
= mt
->level
[level
].slice
[slice
].y_offset
;
943 * Rendering with tiled buffers requires that the base address of the buffer
944 * be aligned to a page boundary. For renderbuffers, and sometimes with
945 * textures, we may want the surface to point at a texture image level that
946 * isn't at a page boundary.
948 * This function returns an appropriately-aligned base offset
949 * according to the tiling restrictions, plus any required x/y offset
953 intel_miptree_get_tile_offsets(struct intel_mipmap_tree
*mt
,
954 GLuint level
, GLuint slice
,
958 struct intel_region
*region
= mt
->region
;
960 uint32_t mask_x
, mask_y
;
962 intel_region_get_tile_masks(region
, &mask_x
, &mask_y
, false);
963 intel_miptree_get_image_offset(mt
, level
, slice
, &x
, &y
);
965 *tile_x
= x
& mask_x
;
966 *tile_y
= y
& mask_y
;
968 return intel_region_get_aligned_offset(region
, x
& ~mask_x
, y
& ~mask_y
,
973 intel_miptree_copy_slice_sw(struct brw_context
*brw
,
974 struct intel_mipmap_tree
*dst_mt
,
975 struct intel_mipmap_tree
*src_mt
,
982 int src_stride
, dst_stride
;
983 int cpp
= dst_mt
->cpp
;
985 intel_miptree_map(brw
, src_mt
,
989 GL_MAP_READ_BIT
| BRW_MAP_DIRECT_BIT
,
992 intel_miptree_map(brw
, dst_mt
,
996 GL_MAP_WRITE_BIT
| GL_MAP_INVALIDATE_RANGE_BIT
|
1000 DBG("sw blit %s mt %p %p/%d -> %s mt %p %p/%d (%dx%d)\n",
1001 _mesa_get_format_name(src_mt
->format
),
1002 src_mt
, src
, src_stride
,
1003 _mesa_get_format_name(dst_mt
->format
),
1004 dst_mt
, dst
, dst_stride
,
1007 int row_size
= cpp
* width
;
1008 if (src_stride
== row_size
&&
1009 dst_stride
== row_size
) {
1010 memcpy(dst
, src
, row_size
* height
);
1012 for (int i
= 0; i
< height
; i
++) {
1013 memcpy(dst
, src
, row_size
);
1019 intel_miptree_unmap(brw
, dst_mt
, level
, slice
);
1020 intel_miptree_unmap(brw
, src_mt
, level
, slice
);
1022 /* Don't forget to copy the stencil data over, too. We could have skipped
1023 * passing BRW_MAP_DIRECT_BIT, but that would have meant intel_miptree_map
1024 * shuffling the two data sources in/out of temporary storage instead of
1025 * the direct mapping we get this way.
1027 if (dst_mt
->stencil_mt
) {
1028 assert(src_mt
->stencil_mt
);
1029 intel_miptree_copy_slice_sw(brw
, dst_mt
->stencil_mt
, src_mt
->stencil_mt
,
1030 level
, slice
, width
, height
);
1035 intel_miptree_copy_slice(struct brw_context
*brw
,
1036 struct intel_mipmap_tree
*dst_mt
,
1037 struct intel_mipmap_tree
*src_mt
,
1043 mesa_format format
= src_mt
->format
;
1044 uint32_t width
= minify(src_mt
->physical_width0
, level
);
1045 uint32_t height
= minify(src_mt
->physical_height0
, level
);
1053 assert(depth
< src_mt
->level
[level
].depth
);
1054 assert(src_mt
->format
== dst_mt
->format
);
1056 if (dst_mt
->compressed
) {
1057 height
= ALIGN(height
, dst_mt
->align_h
) / dst_mt
->align_h
;
1058 width
= ALIGN(width
, dst_mt
->align_w
);
1061 /* If it's a packed depth/stencil buffer with separate stencil, the blit
1062 * below won't apply since we can't do the depth's Y tiling or the
1063 * stencil's W tiling in the blitter.
1065 if (src_mt
->stencil_mt
) {
1066 intel_miptree_copy_slice_sw(brw
,
1073 uint32_t dst_x
, dst_y
, src_x
, src_y
;
1074 intel_miptree_get_image_offset(dst_mt
, level
, slice
, &dst_x
, &dst_y
);
1075 intel_miptree_get_image_offset(src_mt
, level
, slice
, &src_x
, &src_y
);
1077 DBG("validate blit mt %s %p %d,%d/%d -> mt %s %p %d,%d/%d (%dx%d)\n",
1078 _mesa_get_format_name(src_mt
->format
),
1079 src_mt
, src_x
, src_y
, src_mt
->region
->pitch
,
1080 _mesa_get_format_name(dst_mt
->format
),
1081 dst_mt
, dst_x
, dst_y
, dst_mt
->region
->pitch
,
1084 if (!intel_miptree_blit(brw
,
1085 src_mt
, level
, slice
, 0, 0, false,
1086 dst_mt
, level
, slice
, 0, 0, false,
1087 width
, height
, GL_COPY
)) {
1088 perf_debug("miptree validate blit for %s failed\n",
1089 _mesa_get_format_name(format
));
1091 intel_miptree_copy_slice_sw(brw
, dst_mt
, src_mt
, level
, slice
,
1097 * Copies the image's current data to the given miptree, and associates that
1098 * miptree with the image.
1100 * If \c invalidate is true, then the actual image data does not need to be
1101 * copied, but the image still needs to be associated to the new miptree (this
1102 * is set to true if we're about to clear the image).
1105 intel_miptree_copy_teximage(struct brw_context
*brw
,
1106 struct intel_texture_image
*intelImage
,
1107 struct intel_mipmap_tree
*dst_mt
,
1110 struct intel_mipmap_tree
*src_mt
= intelImage
->mt
;
1111 struct intel_texture_object
*intel_obj
=
1112 intel_texture_object(intelImage
->base
.Base
.TexObject
);
1113 int level
= intelImage
->base
.Base
.Level
;
1114 int face
= intelImage
->base
.Base
.Face
;
1115 GLuint depth
= intelImage
->base
.Base
.Depth
;
1118 for (int slice
= 0; slice
< depth
; slice
++) {
1119 intel_miptree_copy_slice(brw
, dst_mt
, src_mt
, level
, face
, slice
);
1123 intel_miptree_reference(&intelImage
->mt
, dst_mt
);
1124 intel_obj
->needs_validate
= true;
1128 intel_miptree_alloc_mcs(struct brw_context
*brw
,
1129 struct intel_mipmap_tree
*mt
,
1132 assert(brw
->gen
>= 7); /* MCS only used on Gen7+ */
1133 assert(mt
->mcs_mt
== NULL
);
1135 /* Choose the correct format for the MCS buffer. All that really matters
1136 * is that we allocate the right buffer size, since we'll always be
1137 * accessing this miptree using MCS-specific hardware mechanisms, which
1138 * infer the correct format based on num_samples.
1141 switch (num_samples
) {
1143 /* 8 bits/pixel are required for MCS data when using 4x MSAA (2 bits for
1146 format
= MESA_FORMAT_R_UNORM8
;
1149 /* 32 bits/pixel are required for MCS data when using 8x MSAA (3 bits
1150 * for each sample, plus 8 padding bits).
1152 format
= MESA_FORMAT_R_UINT32
;
1155 assert(!"Unrecognized sample count in intel_miptree_alloc_mcs");
1159 /* From the Ivy Bridge PRM, Vol4 Part1 p76, "MCS Base Address":
1161 * "The MCS surface must be stored as Tile Y."
1163 mt
->mcs_mt
= intel_miptree_create(brw
,
1169 mt
->logical_height0
,
1172 0 /* num_samples */,
1173 INTEL_MIPTREE_TILING_Y
);
1175 /* From the Ivy Bridge PRM, Vol 2 Part 1 p326:
1177 * When MCS buffer is enabled and bound to MSRT, it is required that it
1178 * is cleared prior to any rendering.
1180 * Since we don't use the MCS buffer for any purpose other than rendering,
1181 * it makes sense to just clear it immediately upon allocation.
1183 * Note: the clear value for MCS buffers is all 1's, so we memset to 0xff.
1185 void *data
= intel_miptree_map_raw(brw
, mt
->mcs_mt
);
1186 memset(data
, 0xff, mt
->mcs_mt
->region
->bo
->size
);
1187 intel_miptree_unmap_raw(brw
, mt
->mcs_mt
);
1188 mt
->fast_clear_state
= INTEL_FAST_CLEAR_STATE_CLEAR
;
1195 intel_miptree_alloc_non_msrt_mcs(struct brw_context
*brw
,
1196 struct intel_mipmap_tree
*mt
)
1198 assert(mt
->mcs_mt
== NULL
);
1200 /* The format of the MCS buffer is opaque to the driver; all that matters
1201 * is that we get its size and pitch right. We'll pretend that the format
1202 * is R32. Since an MCS tile covers 128 blocks horizontally, and a Y-tiled
1203 * R32 buffer is 32 pixels across, we'll need to scale the width down by
1204 * the block width and then a further factor of 4. Since an MCS tile
1205 * covers 256 blocks vertically, and a Y-tiled R32 buffer is 32 rows high,
1206 * we'll need to scale the height down by the block height and then a
1207 * further factor of 8.
1209 const mesa_format format
= MESA_FORMAT_R_UINT32
;
1210 unsigned block_width_px
;
1211 unsigned block_height
;
1212 intel_get_non_msrt_mcs_alignment(brw
, mt
, &block_width_px
, &block_height
);
1213 unsigned width_divisor
= block_width_px
* 4;
1214 unsigned height_divisor
= block_height
* 8;
1215 unsigned mcs_width
=
1216 ALIGN(mt
->logical_width0
, width_divisor
) / width_divisor
;
1217 unsigned mcs_height
=
1218 ALIGN(mt
->logical_height0
, height_divisor
) / height_divisor
;
1219 assert(mt
->logical_depth0
== 1);
1220 mt
->mcs_mt
= intel_miptree_create(brw
,
1229 0 /* num_samples */,
1230 INTEL_MIPTREE_TILING_Y
);
1237 * Helper for intel_miptree_alloc_hiz() that sets
1238 * \c mt->level[level].slice[layer].has_hiz. Return true if and only if
1239 * \c has_hiz was set.
1242 intel_miptree_slice_enable_hiz(struct brw_context
*brw
,
1243 struct intel_mipmap_tree
*mt
,
1249 if (brw
->gen
>= 8 || brw
->is_haswell
) {
1250 uint32_t width
= minify(mt
->physical_width0
, level
);
1251 uint32_t height
= minify(mt
->physical_height0
, level
);
1253 /* Disable HiZ for LOD > 0 unless the width is 8 aligned
1254 * and the height is 4 aligned. This allows our HiZ support
1255 * to fulfill Haswell restrictions for HiZ ops. For LOD == 0,
1256 * we can grow the width & height to allow the HiZ op to
1257 * force the proper size alignments.
1259 if (level
> 0 && ((width
& 7) || (height
& 3))) {
1264 mt
->level
[level
].slice
[layer
].has_hiz
= true;
1271 intel_miptree_alloc_hiz(struct brw_context
*brw
,
1272 struct intel_mipmap_tree
*mt
)
1274 assert(mt
->hiz_mt
== NULL
);
1275 mt
->hiz_mt
= intel_miptree_create(brw
,
1281 mt
->logical_height0
,
1285 INTEL_MIPTREE_TILING_ANY
);
1290 /* Mark that all slices need a HiZ resolve. */
1291 struct intel_resolve_map
*head
= &mt
->hiz_map
;
1292 for (int level
= mt
->first_level
; level
<= mt
->last_level
; ++level
) {
1293 for (int layer
= 0; layer
< mt
->level
[level
].depth
; ++layer
) {
1294 if (!intel_miptree_slice_enable_hiz(brw
, mt
, level
, layer
))
1297 head
->next
= malloc(sizeof(*head
->next
));
1298 head
->next
->prev
= head
;
1299 head
->next
->next
= NULL
;
1302 head
->level
= level
;
1303 head
->layer
= layer
;
1304 head
->need
= GEN6_HIZ_OP_HIZ_RESOLVE
;
1312 * Does the miptree slice have hiz enabled?
1315 intel_miptree_slice_has_hiz(struct intel_mipmap_tree
*mt
,
1319 intel_miptree_check_level_layer(mt
, level
, layer
);
1320 return mt
->level
[level
].slice
[layer
].has_hiz
;
1324 intel_miptree_slice_set_needs_hiz_resolve(struct intel_mipmap_tree
*mt
,
1328 if (!intel_miptree_slice_has_hiz(mt
, level
, layer
))
1331 intel_resolve_map_set(&mt
->hiz_map
,
1332 level
, layer
, GEN6_HIZ_OP_HIZ_RESOLVE
);
1337 intel_miptree_slice_set_needs_depth_resolve(struct intel_mipmap_tree
*mt
,
1341 if (!intel_miptree_slice_has_hiz(mt
, level
, layer
))
1344 intel_resolve_map_set(&mt
->hiz_map
,
1345 level
, layer
, GEN6_HIZ_OP_DEPTH_RESOLVE
);
1349 intel_miptree_set_all_slices_need_depth_resolve(struct intel_mipmap_tree
*mt
,
1353 uint32_t end_layer
= mt
->level
[level
].depth
;
1355 for (layer
= 0; layer
< end_layer
; layer
++) {
1356 intel_miptree_slice_set_needs_depth_resolve(mt
, level
, layer
);
1361 intel_miptree_slice_resolve(struct brw_context
*brw
,
1362 struct intel_mipmap_tree
*mt
,
1365 enum gen6_hiz_op need
)
1367 intel_miptree_check_level_layer(mt
, level
, layer
);
1369 struct intel_resolve_map
*item
=
1370 intel_resolve_map_get(&mt
->hiz_map
, level
, layer
);
1372 if (!item
|| item
->need
!= need
)
1375 intel_hiz_exec(brw
, mt
, level
, layer
, need
);
1376 intel_resolve_map_remove(item
);
1381 intel_miptree_slice_resolve_hiz(struct brw_context
*brw
,
1382 struct intel_mipmap_tree
*mt
,
1386 return intel_miptree_slice_resolve(brw
, mt
, level
, layer
,
1387 GEN6_HIZ_OP_HIZ_RESOLVE
);
1391 intel_miptree_slice_resolve_depth(struct brw_context
*brw
,
1392 struct intel_mipmap_tree
*mt
,
1396 return intel_miptree_slice_resolve(brw
, mt
, level
, layer
,
1397 GEN6_HIZ_OP_DEPTH_RESOLVE
);
1401 intel_miptree_all_slices_resolve(struct brw_context
*brw
,
1402 struct intel_mipmap_tree
*mt
,
1403 enum gen6_hiz_op need
)
1405 bool did_resolve
= false;
1406 struct intel_resolve_map
*i
, *next
;
1408 for (i
= mt
->hiz_map
.next
; i
; i
= next
) {
1410 if (i
->need
!= need
)
1413 intel_hiz_exec(brw
, mt
, i
->level
, i
->layer
, need
);
1414 intel_resolve_map_remove(i
);
1422 intel_miptree_all_slices_resolve_hiz(struct brw_context
*brw
,
1423 struct intel_mipmap_tree
*mt
)
1425 return intel_miptree_all_slices_resolve(brw
, mt
,
1426 GEN6_HIZ_OP_HIZ_RESOLVE
);
1430 intel_miptree_all_slices_resolve_depth(struct brw_context
*brw
,
1431 struct intel_mipmap_tree
*mt
)
1433 return intel_miptree_all_slices_resolve(brw
, mt
,
1434 GEN6_HIZ_OP_DEPTH_RESOLVE
);
1439 intel_miptree_resolve_color(struct brw_context
*brw
,
1440 struct intel_mipmap_tree
*mt
)
1442 switch (mt
->fast_clear_state
) {
1443 case INTEL_FAST_CLEAR_STATE_NO_MCS
:
1444 case INTEL_FAST_CLEAR_STATE_RESOLVED
:
1445 /* No resolve needed */
1447 case INTEL_FAST_CLEAR_STATE_UNRESOLVED
:
1448 case INTEL_FAST_CLEAR_STATE_CLEAR
:
1449 /* Fast color clear resolves only make sense for non-MSAA buffers. */
1450 if (mt
->msaa_layout
== INTEL_MSAA_LAYOUT_NONE
)
1451 brw_blorp_resolve_color(brw
, mt
);
1458 * Make it possible to share the region backing the given miptree with another
1459 * process or another miptree.
1461 * Fast color clears are unsafe with shared buffers, so we need to resolve and
1462 * then discard the MCS buffer, if present. We also set the fast_clear_state
1463 * to INTEL_FAST_CLEAR_STATE_NO_MCS to ensure that no MCS buffer gets
1464 * allocated in the future.
1467 intel_miptree_make_shareable(struct brw_context
*brw
,
1468 struct intel_mipmap_tree
*mt
)
1470 /* MCS buffers are also used for multisample buffers, but we can't resolve
1471 * away a multisample MCS buffer because it's an integral part of how the
1472 * pixel data is stored. Fortunately this code path should never be
1473 * reached for multisample buffers.
1475 assert(mt
->msaa_layout
== INTEL_MSAA_LAYOUT_NONE
);
1478 intel_miptree_resolve_color(brw
, mt
);
1479 intel_miptree_release(&mt
->mcs_mt
);
1480 mt
->fast_clear_state
= INTEL_FAST_CLEAR_STATE_NO_MCS
;
1486 * \brief Get pointer offset into stencil buffer.
1488 * The stencil buffer is W tiled. Since the GTT is incapable of W fencing, we
1489 * must decode the tile's layout in software.
1492 * - PRM, 2011 Sandy Bridge, Volume 1, Part 2, Section 4.5.2.1 W-Major Tile
1494 * - PRM, 2011 Sandy Bridge, Volume 1, Part 2, Section 4.5.3 Tiling Algorithm
1496 * Even though the returned offset is always positive, the return type is
1498 * commit e8b1c6d6f55f5be3bef25084fdd8b6127517e137
1499 * mesa: Fix return type of _mesa_get_format_bytes() (#37351)
1502 intel_offset_S8(uint32_t stride
, uint32_t x
, uint32_t y
, bool swizzled
)
1504 uint32_t tile_size
= 4096;
1505 uint32_t tile_width
= 64;
1506 uint32_t tile_height
= 64;
1507 uint32_t row_size
= 64 * stride
;
1509 uint32_t tile_x
= x
/ tile_width
;
1510 uint32_t tile_y
= y
/ tile_height
;
1512 /* The byte's address relative to the tile's base addres. */
1513 uint32_t byte_x
= x
% tile_width
;
1514 uint32_t byte_y
= y
% tile_height
;
1516 uintptr_t u
= tile_y
* row_size
1517 + tile_x
* tile_size
1518 + 512 * (byte_x
/ 8)
1520 + 32 * ((byte_y
/ 4) % 2)
1521 + 16 * ((byte_x
/ 4) % 2)
1522 + 8 * ((byte_y
/ 2) % 2)
1523 + 4 * ((byte_x
/ 2) % 2)
1528 /* adjust for bit6 swizzling */
1529 if (((byte_x
/ 8) % 2) == 1) {
1530 if (((byte_y
/ 8) % 2) == 0) {
1542 intel_miptree_updownsample(struct brw_context
*brw
,
1543 struct intel_mipmap_tree
*src
,
1544 struct intel_mipmap_tree
*dst
)
1546 brw_blorp_blit_miptrees(brw
,
1547 src
, 0 /* level */, 0 /* layer */,
1548 dst
, 0 /* level */, 0 /* layer */,
1550 src
->logical_width0
, src
->logical_height0
,
1552 dst
->logical_width0
, dst
->logical_height0
,
1553 GL_NEAREST
, false, false /*mirror x, y*/);
1555 if (src
->stencil_mt
) {
1556 brw_blorp_blit_miptrees(brw
,
1557 src
->stencil_mt
, 0 /* level */, 0 /* layer */,
1558 dst
->stencil_mt
, 0 /* level */, 0 /* layer */,
1560 src
->logical_width0
, src
->logical_height0
,
1562 dst
->logical_width0
, dst
->logical_height0
,
1563 GL_NEAREST
, false, false /*mirror x, y*/);
1568 intel_miptree_map_raw(struct brw_context
*brw
, struct intel_mipmap_tree
*mt
)
1570 /* CPU accesses to color buffers don't understand fast color clears, so
1571 * resolve any pending fast color clears before we map.
1573 intel_miptree_resolve_color(brw
, mt
);
1575 drm_intel_bo
*bo
= mt
->region
->bo
;
1577 intel_batchbuffer_flush(brw
);
1579 if (mt
->region
->tiling
!= I915_TILING_NONE
)
1580 brw_bo_map_gtt(brw
, bo
, "miptree");
1582 brw_bo_map(brw
, bo
, true, "miptree");
1588 intel_miptree_unmap_raw(struct brw_context
*brw
,
1589 struct intel_mipmap_tree
*mt
)
1591 drm_intel_bo_unmap(mt
->region
->bo
);
1595 intel_miptree_map_gtt(struct brw_context
*brw
,
1596 struct intel_mipmap_tree
*mt
,
1597 struct intel_miptree_map
*map
,
1598 unsigned int level
, unsigned int slice
)
1600 unsigned int bw
, bh
;
1602 unsigned int image_x
, image_y
;
1606 /* For compressed formats, the stride is the number of bytes per
1607 * row of blocks. intel_miptree_get_image_offset() already does
1610 _mesa_get_format_block_size(mt
->format
, &bw
, &bh
);
1611 assert(y
% bh
== 0);
1614 base
= intel_miptree_map_raw(brw
, mt
) + mt
->offset
;
1619 /* Note that in the case of cube maps, the caller must have passed the
1620 * slice number referencing the face.
1622 intel_miptree_get_image_offset(mt
, level
, slice
, &image_x
, &image_y
);
1626 map
->stride
= mt
->region
->pitch
;
1627 map
->ptr
= base
+ y
* map
->stride
+ x
* mt
->cpp
;
1630 DBG("%s: %d,%d %dx%d from mt %p (%s) %d,%d = %p/%d\n", __FUNCTION__
,
1631 map
->x
, map
->y
, map
->w
, map
->h
,
1632 mt
, _mesa_get_format_name(mt
->format
),
1633 x
, y
, map
->ptr
, map
->stride
);
1637 intel_miptree_unmap_gtt(struct brw_context
*brw
,
1638 struct intel_mipmap_tree
*mt
,
1639 struct intel_miptree_map
*map
,
1643 intel_miptree_unmap_raw(brw
, mt
);
1647 intel_miptree_map_blit(struct brw_context
*brw
,
1648 struct intel_mipmap_tree
*mt
,
1649 struct intel_miptree_map
*map
,
1650 unsigned int level
, unsigned int slice
)
1652 map
->mt
= intel_miptree_create(brw
, GL_TEXTURE_2D
, mt
->format
,
1656 INTEL_MIPTREE_TILING_NONE
);
1658 fprintf(stderr
, "Failed to allocate blit temporary\n");
1661 map
->stride
= map
->mt
->region
->pitch
;
1663 if (!intel_miptree_blit(brw
,
1665 map
->x
, map
->y
, false,
1668 map
->w
, map
->h
, GL_COPY
)) {
1669 fprintf(stderr
, "Failed to blit\n");
1673 map
->ptr
= intel_miptree_map_raw(brw
, map
->mt
);
1675 DBG("%s: %d,%d %dx%d from mt %p (%s) %d,%d = %p/%d\n", __FUNCTION__
,
1676 map
->x
, map
->y
, map
->w
, map
->h
,
1677 mt
, _mesa_get_format_name(mt
->format
),
1678 level
, slice
, map
->ptr
, map
->stride
);
1683 intel_miptree_release(&map
->mt
);
1689 intel_miptree_unmap_blit(struct brw_context
*brw
,
1690 struct intel_mipmap_tree
*mt
,
1691 struct intel_miptree_map
*map
,
1695 struct gl_context
*ctx
= &brw
->ctx
;
1697 intel_miptree_unmap_raw(brw
, map
->mt
);
1699 if (map
->mode
& GL_MAP_WRITE_BIT
) {
1700 bool ok
= intel_miptree_blit(brw
,
1704 map
->x
, map
->y
, false,
1705 map
->w
, map
->h
, GL_COPY
);
1706 WARN_ONCE(!ok
, "Failed to blit from linear temporary mapping");
1709 intel_miptree_release(&map
->mt
);
1714 * "Map" a buffer by copying it to an untiled temporary using MOVNTDQA.
1717 intel_miptree_map_movntdqa(struct brw_context
*brw
,
1718 struct intel_mipmap_tree
*mt
,
1719 struct intel_miptree_map
*map
,
1720 unsigned int level
, unsigned int slice
)
1722 assert(map
->mode
& GL_MAP_READ_BIT
);
1723 assert(!(map
->mode
& GL_MAP_WRITE_BIT
));
1725 DBG("%s: %d,%d %dx%d from mt %p (%s) %d,%d = %p/%d\n", __FUNCTION__
,
1726 map
->x
, map
->y
, map
->w
, map
->h
,
1727 mt
, _mesa_get_format_name(mt
->format
),
1728 level
, slice
, map
->ptr
, map
->stride
);
1730 /* Map the original image */
1733 intel_miptree_get_image_offset(mt
, level
, slice
, &image_x
, &image_y
);
1737 void *src
= intel_miptree_map_raw(brw
, mt
);
1740 src
+= image_y
* mt
->region
->pitch
;
1741 src
+= image_x
* mt
->region
->cpp
;
1743 /* Due to the pixel offsets for the particular image being mapped, our
1744 * src pointer may not be 16-byte aligned. However, if the pitch is
1745 * divisible by 16, then the amount by which it's misaligned will remain
1746 * consistent from row to row.
1748 assert((mt
->region
->pitch
% 16) == 0);
1749 const int misalignment
= ((uintptr_t) src
) & 15;
1751 /* Create an untiled temporary buffer for the mapping. */
1752 const unsigned width_bytes
= _mesa_format_row_stride(mt
->format
, map
->w
);
1754 map
->stride
= ALIGN(misalignment
+ width_bytes
, 16);
1756 map
->buffer
= malloc(map
->stride
* map
->h
);
1757 /* Offset the destination so it has the same misalignment as src. */
1758 map
->ptr
= map
->buffer
+ misalignment
;
1760 assert((((uintptr_t) map
->ptr
) & 15) == misalignment
);
1762 for (uint32_t y
= 0; y
< map
->h
; y
++) {
1763 void *dst_ptr
= map
->ptr
+ y
* map
->stride
;
1764 void *src_ptr
= src
+ y
* mt
->region
->pitch
;
1766 _mesa_streaming_load_memcpy(dst_ptr
, src_ptr
, width_bytes
);
1769 intel_miptree_unmap_raw(brw
, mt
);
1773 intel_miptree_unmap_movntdqa(struct brw_context
*brw
,
1774 struct intel_mipmap_tree
*mt
,
1775 struct intel_miptree_map
*map
,
1786 intel_miptree_map_s8(struct brw_context
*brw
,
1787 struct intel_mipmap_tree
*mt
,
1788 struct intel_miptree_map
*map
,
1789 unsigned int level
, unsigned int slice
)
1791 map
->stride
= map
->w
;
1792 map
->buffer
= map
->ptr
= malloc(map
->stride
* map
->h
);
1796 /* One of either READ_BIT or WRITE_BIT or both is set. READ_BIT implies no
1797 * INVALIDATE_RANGE_BIT. WRITE_BIT needs the original values read in unless
1798 * invalidate is set, since we'll be writing the whole rectangle from our
1799 * temporary buffer back out.
1801 if (!(map
->mode
& GL_MAP_INVALIDATE_RANGE_BIT
)) {
1802 uint8_t *untiled_s8_map
= map
->ptr
;
1803 uint8_t *tiled_s8_map
= intel_miptree_map_raw(brw
, mt
);
1804 unsigned int image_x
, image_y
;
1806 intel_miptree_get_image_offset(mt
, level
, slice
, &image_x
, &image_y
);
1808 for (uint32_t y
= 0; y
< map
->h
; y
++) {
1809 for (uint32_t x
= 0; x
< map
->w
; x
++) {
1810 ptrdiff_t offset
= intel_offset_S8(mt
->region
->pitch
,
1811 x
+ image_x
+ map
->x
,
1812 y
+ image_y
+ map
->y
,
1813 brw
->has_swizzling
);
1814 untiled_s8_map
[y
* map
->w
+ x
] = tiled_s8_map
[offset
];
1818 intel_miptree_unmap_raw(brw
, mt
);
1820 DBG("%s: %d,%d %dx%d from mt %p %d,%d = %p/%d\n", __FUNCTION__
,
1821 map
->x
, map
->y
, map
->w
, map
->h
,
1822 mt
, map
->x
+ image_x
, map
->y
+ image_y
, map
->ptr
, map
->stride
);
1824 DBG("%s: %d,%d %dx%d from mt %p = %p/%d\n", __FUNCTION__
,
1825 map
->x
, map
->y
, map
->w
, map
->h
,
1826 mt
, map
->ptr
, map
->stride
);
1831 intel_miptree_unmap_s8(struct brw_context
*brw
,
1832 struct intel_mipmap_tree
*mt
,
1833 struct intel_miptree_map
*map
,
1837 if (map
->mode
& GL_MAP_WRITE_BIT
) {
1838 unsigned int image_x
, image_y
;
1839 uint8_t *untiled_s8_map
= map
->ptr
;
1840 uint8_t *tiled_s8_map
= intel_miptree_map_raw(brw
, mt
);
1842 intel_miptree_get_image_offset(mt
, level
, slice
, &image_x
, &image_y
);
1844 for (uint32_t y
= 0; y
< map
->h
; y
++) {
1845 for (uint32_t x
= 0; x
< map
->w
; x
++) {
1846 ptrdiff_t offset
= intel_offset_S8(mt
->region
->pitch
,
1849 brw
->has_swizzling
);
1850 tiled_s8_map
[offset
] = untiled_s8_map
[y
* map
->w
+ x
];
1854 intel_miptree_unmap_raw(brw
, mt
);
1861 intel_miptree_map_etc(struct brw_context
*brw
,
1862 struct intel_mipmap_tree
*mt
,
1863 struct intel_miptree_map
*map
,
1867 assert(mt
->etc_format
!= MESA_FORMAT_NONE
);
1868 if (mt
->etc_format
== MESA_FORMAT_ETC1_RGB8
) {
1869 assert(mt
->format
== MESA_FORMAT_R8G8B8X8_UNORM
);
1872 assert(map
->mode
& GL_MAP_WRITE_BIT
);
1873 assert(map
->mode
& GL_MAP_INVALIDATE_RANGE_BIT
);
1875 map
->stride
= _mesa_format_row_stride(mt
->etc_format
, map
->w
);
1876 map
->buffer
= malloc(_mesa_format_image_size(mt
->etc_format
,
1877 map
->w
, map
->h
, 1));
1878 map
->ptr
= map
->buffer
;
1882 intel_miptree_unmap_etc(struct brw_context
*brw
,
1883 struct intel_mipmap_tree
*mt
,
1884 struct intel_miptree_map
*map
,
1890 intel_miptree_get_image_offset(mt
, level
, slice
, &image_x
, &image_y
);
1895 uint8_t *dst
= intel_miptree_map_raw(brw
, mt
)
1896 + image_y
* mt
->region
->pitch
1897 + image_x
* mt
->region
->cpp
;
1899 if (mt
->etc_format
== MESA_FORMAT_ETC1_RGB8
)
1900 _mesa_etc1_unpack_rgba8888(dst
, mt
->region
->pitch
,
1901 map
->ptr
, map
->stride
,
1904 _mesa_unpack_etc2_format(dst
, mt
->region
->pitch
,
1905 map
->ptr
, map
->stride
,
1906 map
->w
, map
->h
, mt
->etc_format
);
1908 intel_miptree_unmap_raw(brw
, mt
);
1913 * Mapping function for packed depth/stencil miptrees backed by real separate
1914 * miptrees for depth and stencil.
1916 * On gen7, and to support HiZ pre-gen7, we have to have the stencil buffer
1917 * separate from the depth buffer. Yet at the GL API level, we have to expose
1918 * packed depth/stencil textures and FBO attachments, and Mesa core expects to
1919 * be able to map that memory for texture storage and glReadPixels-type
1920 * operations. We give Mesa core that access by mallocing a temporary and
1921 * copying the data between the actual backing store and the temporary.
1924 intel_miptree_map_depthstencil(struct brw_context
*brw
,
1925 struct intel_mipmap_tree
*mt
,
1926 struct intel_miptree_map
*map
,
1927 unsigned int level
, unsigned int slice
)
1929 struct intel_mipmap_tree
*z_mt
= mt
;
1930 struct intel_mipmap_tree
*s_mt
= mt
->stencil_mt
;
1931 bool map_z32f_x24s8
= mt
->format
== MESA_FORMAT_Z_FLOAT32
;
1932 int packed_bpp
= map_z32f_x24s8
? 8 : 4;
1934 map
->stride
= map
->w
* packed_bpp
;
1935 map
->buffer
= map
->ptr
= malloc(map
->stride
* map
->h
);
1939 /* One of either READ_BIT or WRITE_BIT or both is set. READ_BIT implies no
1940 * INVALIDATE_RANGE_BIT. WRITE_BIT needs the original values read in unless
1941 * invalidate is set, since we'll be writing the whole rectangle from our
1942 * temporary buffer back out.
1944 if (!(map
->mode
& GL_MAP_INVALIDATE_RANGE_BIT
)) {
1945 uint32_t *packed_map
= map
->ptr
;
1946 uint8_t *s_map
= intel_miptree_map_raw(brw
, s_mt
);
1947 uint32_t *z_map
= intel_miptree_map_raw(brw
, z_mt
);
1948 unsigned int s_image_x
, s_image_y
;
1949 unsigned int z_image_x
, z_image_y
;
1951 intel_miptree_get_image_offset(s_mt
, level
, slice
,
1952 &s_image_x
, &s_image_y
);
1953 intel_miptree_get_image_offset(z_mt
, level
, slice
,
1954 &z_image_x
, &z_image_y
);
1956 for (uint32_t y
= 0; y
< map
->h
; y
++) {
1957 for (uint32_t x
= 0; x
< map
->w
; x
++) {
1958 int map_x
= map
->x
+ x
, map_y
= map
->y
+ y
;
1959 ptrdiff_t s_offset
= intel_offset_S8(s_mt
->region
->pitch
,
1962 brw
->has_swizzling
);
1963 ptrdiff_t z_offset
= ((map_y
+ z_image_y
) *
1964 (z_mt
->region
->pitch
/ 4) +
1965 (map_x
+ z_image_x
));
1966 uint8_t s
= s_map
[s_offset
];
1967 uint32_t z
= z_map
[z_offset
];
1969 if (map_z32f_x24s8
) {
1970 packed_map
[(y
* map
->w
+ x
) * 2 + 0] = z
;
1971 packed_map
[(y
* map
->w
+ x
) * 2 + 1] = s
;
1973 packed_map
[y
* map
->w
+ x
] = (s
<< 24) | (z
& 0x00ffffff);
1978 intel_miptree_unmap_raw(brw
, s_mt
);
1979 intel_miptree_unmap_raw(brw
, z_mt
);
1981 DBG("%s: %d,%d %dx%d from z mt %p %d,%d, s mt %p %d,%d = %p/%d\n",
1983 map
->x
, map
->y
, map
->w
, map
->h
,
1984 z_mt
, map
->x
+ z_image_x
, map
->y
+ z_image_y
,
1985 s_mt
, map
->x
+ s_image_x
, map
->y
+ s_image_y
,
1986 map
->ptr
, map
->stride
);
1988 DBG("%s: %d,%d %dx%d from mt %p = %p/%d\n", __FUNCTION__
,
1989 map
->x
, map
->y
, map
->w
, map
->h
,
1990 mt
, map
->ptr
, map
->stride
);
1995 intel_miptree_unmap_depthstencil(struct brw_context
*brw
,
1996 struct intel_mipmap_tree
*mt
,
1997 struct intel_miptree_map
*map
,
2001 struct intel_mipmap_tree
*z_mt
= mt
;
2002 struct intel_mipmap_tree
*s_mt
= mt
->stencil_mt
;
2003 bool map_z32f_x24s8
= mt
->format
== MESA_FORMAT_Z_FLOAT32
;
2005 if (map
->mode
& GL_MAP_WRITE_BIT
) {
2006 uint32_t *packed_map
= map
->ptr
;
2007 uint8_t *s_map
= intel_miptree_map_raw(brw
, s_mt
);
2008 uint32_t *z_map
= intel_miptree_map_raw(brw
, z_mt
);
2009 unsigned int s_image_x
, s_image_y
;
2010 unsigned int z_image_x
, z_image_y
;
2012 intel_miptree_get_image_offset(s_mt
, level
, slice
,
2013 &s_image_x
, &s_image_y
);
2014 intel_miptree_get_image_offset(z_mt
, level
, slice
,
2015 &z_image_x
, &z_image_y
);
2017 for (uint32_t y
= 0; y
< map
->h
; y
++) {
2018 for (uint32_t x
= 0; x
< map
->w
; x
++) {
2019 ptrdiff_t s_offset
= intel_offset_S8(s_mt
->region
->pitch
,
2020 x
+ s_image_x
+ map
->x
,
2021 y
+ s_image_y
+ map
->y
,
2022 brw
->has_swizzling
);
2023 ptrdiff_t z_offset
= ((y
+ z_image_y
) *
2024 (z_mt
->region
->pitch
/ 4) +
2027 if (map_z32f_x24s8
) {
2028 z_map
[z_offset
] = packed_map
[(y
* map
->w
+ x
) * 2 + 0];
2029 s_map
[s_offset
] = packed_map
[(y
* map
->w
+ x
) * 2 + 1];
2031 uint32_t packed
= packed_map
[y
* map
->w
+ x
];
2032 s_map
[s_offset
] = packed
>> 24;
2033 z_map
[z_offset
] = packed
;
2038 intel_miptree_unmap_raw(brw
, s_mt
);
2039 intel_miptree_unmap_raw(brw
, z_mt
);
2041 DBG("%s: %d,%d %dx%d from z mt %p (%s) %d,%d, s mt %p %d,%d = %p/%d\n",
2043 map
->x
, map
->y
, map
->w
, map
->h
,
2044 z_mt
, _mesa_get_format_name(z_mt
->format
),
2045 map
->x
+ z_image_x
, map
->y
+ z_image_y
,
2046 s_mt
, map
->x
+ s_image_x
, map
->y
+ s_image_y
,
2047 map
->ptr
, map
->stride
);
2054 * Create and attach a map to the miptree at (level, slice). Return the
2057 static struct intel_miptree_map
*
2058 intel_miptree_attach_map(struct intel_mipmap_tree
*mt
,
2067 struct intel_miptree_map
*map
= calloc(1, sizeof(*map
));
2072 assert(mt
->level
[level
].slice
[slice
].map
== NULL
);
2073 mt
->level
[level
].slice
[slice
].map
= map
;
2085 * Release the map at (level, slice).
2088 intel_miptree_release_map(struct intel_mipmap_tree
*mt
,
2092 struct intel_miptree_map
**map
;
2094 map
= &mt
->level
[level
].slice
[slice
].map
;
2100 can_blit_slice(struct intel_mipmap_tree
*mt
,
2101 unsigned int level
, unsigned int slice
)
2105 intel_miptree_get_image_offset(mt
, level
, slice
, &image_x
, &image_y
);
2106 if (image_x
>= 32768 || image_y
>= 32768)
2109 if (mt
->region
->pitch
>= 32768)
2116 intel_miptree_map(struct brw_context
*brw
,
2117 struct intel_mipmap_tree
*mt
,
2128 struct intel_miptree_map
*map
;
2130 assert(mt
->num_samples
<= 1);
2132 map
= intel_miptree_attach_map(mt
, level
, slice
, x
, y
, w
, h
, mode
);
2139 intel_miptree_slice_resolve_depth(brw
, mt
, level
, slice
);
2140 if (map
->mode
& GL_MAP_WRITE_BIT
) {
2141 intel_miptree_slice_set_needs_hiz_resolve(mt
, level
, slice
);
2144 if (mt
->format
== MESA_FORMAT_S_UINT8
) {
2145 intel_miptree_map_s8(brw
, mt
, map
, level
, slice
);
2146 } else if (mt
->etc_format
!= MESA_FORMAT_NONE
&&
2147 !(mode
& BRW_MAP_DIRECT_BIT
)) {
2148 intel_miptree_map_etc(brw
, mt
, map
, level
, slice
);
2149 } else if (mt
->stencil_mt
&& !(mode
& BRW_MAP_DIRECT_BIT
)) {
2150 intel_miptree_map_depthstencil(brw
, mt
, map
, level
, slice
);
2152 /* See intel_miptree_blit() for details on the 32k pitch limit. */
2153 else if (brw
->has_llc
&&
2154 !(mode
& GL_MAP_WRITE_BIT
) &&
2156 (mt
->region
->tiling
== I915_TILING_X
||
2157 (brw
->gen
>= 6 && mt
->region
->tiling
== I915_TILING_Y
)) &&
2158 can_blit_slice(mt
, level
, slice
)) {
2159 intel_miptree_map_blit(brw
, mt
, map
, level
, slice
);
2160 } else if (mt
->region
->tiling
!= I915_TILING_NONE
&&
2161 mt
->region
->bo
->size
>= brw
->max_gtt_map_object_size
) {
2162 assert(can_blit_slice(mt
, level
, slice
));
2163 intel_miptree_map_blit(brw
, mt
, map
, level
, slice
);
2165 } else if (!(mode
& GL_MAP_WRITE_BIT
) && !mt
->compressed
) {
2166 intel_miptree_map_movntdqa(brw
, mt
, map
, level
, slice
);
2169 intel_miptree_map_gtt(brw
, mt
, map
, level
, slice
);
2172 *out_ptr
= map
->ptr
;
2173 *out_stride
= map
->stride
;
2175 if (map
->ptr
== NULL
)
2176 intel_miptree_release_map(mt
, level
, slice
);
2180 intel_miptree_unmap(struct brw_context
*brw
,
2181 struct intel_mipmap_tree
*mt
,
2185 struct intel_miptree_map
*map
= mt
->level
[level
].slice
[slice
].map
;
2187 assert(mt
->num_samples
<= 1);
2192 DBG("%s: mt %p (%s) level %d slice %d\n", __FUNCTION__
,
2193 mt
, _mesa_get_format_name(mt
->format
), level
, slice
);
2195 if (mt
->format
== MESA_FORMAT_S_UINT8
) {
2196 intel_miptree_unmap_s8(brw
, mt
, map
, level
, slice
);
2197 } else if (mt
->etc_format
!= MESA_FORMAT_NONE
&&
2198 !(map
->mode
& BRW_MAP_DIRECT_BIT
)) {
2199 intel_miptree_unmap_etc(brw
, mt
, map
, level
, slice
);
2200 } else if (mt
->stencil_mt
&& !(map
->mode
& BRW_MAP_DIRECT_BIT
)) {
2201 intel_miptree_unmap_depthstencil(brw
, mt
, map
, level
, slice
);
2202 } else if (map
->mt
) {
2203 intel_miptree_unmap_blit(brw
, mt
, map
, level
, slice
);
2205 } else if (map
->buffer
) {
2206 intel_miptree_unmap_movntdqa(brw
, mt
, map
, level
, slice
);
2209 intel_miptree_unmap_gtt(brw
, mt
, map
, level
, slice
);
2212 intel_miptree_release_map(mt
, level
, slice
);