2 * Copyright 2003 VMware, Inc.
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the
7 * "Software"), to deal in the Software without restriction, including
8 * without limitation the rights to use, copy, modify, merge, publish,
9 * distribute, sublicense, and/or sell copies of the Software, and to
10 * permit persons to whom the Software is furnished to do so, subject to
11 * the following conditions:
13 * The above copyright notice and this permission notice (including the
14 * next paragraph) shall be included in all copies or substantial portions
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
18 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
19 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
20 * IN NO EVENT SHALL VMWARE AND/OR ITS SUPPLIERS BE LIABLE FOR
21 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
22 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
23 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
26 #include <drm_fourcc.h>
30 #include "main/context.h"
31 #include "main/framebuffer.h"
32 #include "main/renderbuffer.h"
33 #include "main/texobj.h"
34 #include "main/hash.h"
35 #include "main/fbobject.h"
36 #include "main/version.h"
37 #include "swrast/s_renderbuffer.h"
38 #include "util/ralloc.h"
39 #include "brw_defines.h"
40 #include "compiler/nir/nir.h"
45 #ifndef DRM_FORMAT_MOD_INVALID
46 #define DRM_FORMAT_MOD_INVALID ((1ULL<<56) - 1)
49 #ifndef DRM_FORMAT_MOD_LINEAR
50 #define DRM_FORMAT_MOD_LINEAR 0
53 static const __DRIconfigOptionsExtension brw_config_options
= {
54 .base
= { __DRI_CONFIG_OPTIONS
, 1 },
57 DRI_CONF_SECTION_PERFORMANCE
58 DRI_CONF_VBLANK_MODE(DRI_CONF_VBLANK_ALWAYS_SYNC
)
59 /* Options correspond to DRI_CONF_BO_REUSE_DISABLED,
60 * DRI_CONF_BO_REUSE_ALL
62 DRI_CONF_OPT_BEGIN_V(bo_reuse
, enum, 1, "0:1")
63 DRI_CONF_DESC_BEGIN(en
, "Buffer object reuse")
64 DRI_CONF_ENUM(0, "Disable buffer object reuse")
65 DRI_CONF_ENUM(1, "Enable reuse of all sizes of buffer objects")
70 DRI_CONF_SECTION_QUALITY
71 DRI_CONF_FORCE_S3TC_ENABLE("false")
73 DRI_CONF_PRECISE_TRIG("false")
75 DRI_CONF_OPT_BEGIN(clamp_max_samples
, int, -1)
76 DRI_CONF_DESC(en
, "Clamp the value of GL_MAX_SAMPLES to the "
77 "given integer. If negative, then do not clamp.")
81 DRI_CONF_SECTION_DEBUG
82 DRI_CONF_NO_RAST("false")
83 DRI_CONF_ALWAYS_FLUSH_BATCH("false")
84 DRI_CONF_ALWAYS_FLUSH_CACHE("false")
85 DRI_CONF_DISABLE_THROTTLING("false")
86 DRI_CONF_FORCE_GLSL_EXTENSIONS_WARN("false")
87 DRI_CONF_FORCE_GLSL_VERSION(0)
88 DRI_CONF_DISABLE_GLSL_LINE_CONTINUATIONS("false")
89 DRI_CONF_DISABLE_BLEND_FUNC_EXTENDED("false")
90 DRI_CONF_DUAL_COLOR_BLEND_BY_LOCATION("false")
91 DRI_CONF_ALLOW_GLSL_EXTENSION_DIRECTIVE_MIDSHADER("false")
92 DRI_CONF_ALLOW_HIGHER_COMPAT_VERSION("false")
93 DRI_CONF_FORCE_GLSL_ABS_SQRT("false")
95 DRI_CONF_OPT_BEGIN_B(shader_precompile
, "true")
96 DRI_CONF_DESC(en
, "Perform code generation at shader link time.")
100 DRI_CONF_SECTION_MISCELLANEOUS
101 DRI_CONF_GLSL_ZERO_INIT("false")
106 #include "intel_batchbuffer.h"
107 #include "intel_buffers.h"
108 #include "brw_bufmgr.h"
109 #include "intel_fbo.h"
110 #include "intel_mipmap_tree.h"
111 #include "intel_screen.h"
112 #include "intel_tex.h"
113 #include "intel_image.h"
115 #include "brw_context.h"
117 #include "i915_drm.h"
120 * For debugging purposes, this returns a time in seconds.
127 clock_gettime(CLOCK_MONOTONIC
, &tp
);
129 return tp
.tv_sec
+ tp
.tv_nsec
/ 1000000000.0;
132 static const __DRItexBufferExtension intelTexBufferExtension
= {
133 .base
= { __DRI_TEX_BUFFER
, 3 },
135 .setTexBuffer
= intelSetTexBuffer
,
136 .setTexBuffer2
= intelSetTexBuffer2
,
137 .releaseTexBuffer
= NULL
,
141 intel_dri2_flush_with_flags(__DRIcontext
*cPriv
,
142 __DRIdrawable
*dPriv
,
144 enum __DRI2throttleReason reason
)
146 struct brw_context
*brw
= cPriv
->driverPrivate
;
151 struct gl_context
*ctx
= &brw
->ctx
;
153 FLUSH_VERTICES(ctx
, 0);
155 if (flags
& __DRI2_FLUSH_DRAWABLE
)
156 intel_resolve_for_dri2_flush(brw
, dPriv
);
158 if (reason
== __DRI2_THROTTLE_SWAPBUFFER
)
159 brw
->need_swap_throttle
= true;
160 if (reason
== __DRI2_THROTTLE_FLUSHFRONT
)
161 brw
->need_flush_throttle
= true;
163 intel_batchbuffer_flush(brw
);
167 * Provides compatibility with loaders that only support the older (version
168 * 1-3) flush interface.
170 * That includes libGL up to Mesa 9.0, and the X Server at least up to 1.13.
173 intel_dri2_flush(__DRIdrawable
*drawable
)
175 intel_dri2_flush_with_flags(drawable
->driContextPriv
, drawable
,
176 __DRI2_FLUSH_DRAWABLE
,
177 __DRI2_THROTTLE_SWAPBUFFER
);
180 static const struct __DRI2flushExtensionRec intelFlushExtension
= {
181 .base
= { __DRI2_FLUSH
, 4 },
183 .flush
= intel_dri2_flush
,
184 .invalidate
= dri2InvalidateDrawable
,
185 .flush_with_flags
= intel_dri2_flush_with_flags
,
188 static struct intel_image_format intel_image_formats
[] = {
189 { __DRI_IMAGE_FOURCC_ARGB8888
, __DRI_IMAGE_COMPONENTS_RGBA
, 1,
190 { { 0, 0, 0, __DRI_IMAGE_FORMAT_ARGB8888
, 4 } } },
192 { __DRI_IMAGE_FOURCC_ABGR8888
, __DRI_IMAGE_COMPONENTS_RGBA
, 1,
193 { { 0, 0, 0, __DRI_IMAGE_FORMAT_ABGR8888
, 4 } } },
195 { __DRI_IMAGE_FOURCC_SARGB8888
, __DRI_IMAGE_COMPONENTS_RGBA
, 1,
196 { { 0, 0, 0, __DRI_IMAGE_FORMAT_SARGB8
, 4 } } },
198 { __DRI_IMAGE_FOURCC_XRGB8888
, __DRI_IMAGE_COMPONENTS_RGB
, 1,
199 { { 0, 0, 0, __DRI_IMAGE_FORMAT_XRGB8888
, 4 }, } },
201 { __DRI_IMAGE_FOURCC_XBGR8888
, __DRI_IMAGE_COMPONENTS_RGB
, 1,
202 { { 0, 0, 0, __DRI_IMAGE_FORMAT_XBGR8888
, 4 }, } },
204 { __DRI_IMAGE_FOURCC_ARGB1555
, __DRI_IMAGE_COMPONENTS_RGBA
, 1,
205 { { 0, 0, 0, __DRI_IMAGE_FORMAT_ARGB1555
, 2 } } },
207 { __DRI_IMAGE_FOURCC_RGB565
, __DRI_IMAGE_COMPONENTS_RGB
, 1,
208 { { 0, 0, 0, __DRI_IMAGE_FORMAT_RGB565
, 2 } } },
210 { __DRI_IMAGE_FOURCC_R8
, __DRI_IMAGE_COMPONENTS_R
, 1,
211 { { 0, 0, 0, __DRI_IMAGE_FORMAT_R8
, 1 }, } },
213 { __DRI_IMAGE_FOURCC_R16
, __DRI_IMAGE_COMPONENTS_R
, 1,
214 { { 0, 0, 0, __DRI_IMAGE_FORMAT_R16
, 1 }, } },
216 { __DRI_IMAGE_FOURCC_GR88
, __DRI_IMAGE_COMPONENTS_RG
, 1,
217 { { 0, 0, 0, __DRI_IMAGE_FORMAT_GR88
, 2 }, } },
219 { __DRI_IMAGE_FOURCC_GR1616
, __DRI_IMAGE_COMPONENTS_RG
, 1,
220 { { 0, 0, 0, __DRI_IMAGE_FORMAT_GR1616
, 2 }, } },
222 { __DRI_IMAGE_FOURCC_YUV410
, __DRI_IMAGE_COMPONENTS_Y_U_V
, 3,
223 { { 0, 0, 0, __DRI_IMAGE_FORMAT_R8
, 1 },
224 { 1, 2, 2, __DRI_IMAGE_FORMAT_R8
, 1 },
225 { 2, 2, 2, __DRI_IMAGE_FORMAT_R8
, 1 } } },
227 { __DRI_IMAGE_FOURCC_YUV411
, __DRI_IMAGE_COMPONENTS_Y_U_V
, 3,
228 { { 0, 0, 0, __DRI_IMAGE_FORMAT_R8
, 1 },
229 { 1, 2, 0, __DRI_IMAGE_FORMAT_R8
, 1 },
230 { 2, 2, 0, __DRI_IMAGE_FORMAT_R8
, 1 } } },
232 { __DRI_IMAGE_FOURCC_YUV420
, __DRI_IMAGE_COMPONENTS_Y_U_V
, 3,
233 { { 0, 0, 0, __DRI_IMAGE_FORMAT_R8
, 1 },
234 { 1, 1, 1, __DRI_IMAGE_FORMAT_R8
, 1 },
235 { 2, 1, 1, __DRI_IMAGE_FORMAT_R8
, 1 } } },
237 { __DRI_IMAGE_FOURCC_YUV422
, __DRI_IMAGE_COMPONENTS_Y_U_V
, 3,
238 { { 0, 0, 0, __DRI_IMAGE_FORMAT_R8
, 1 },
239 { 1, 1, 0, __DRI_IMAGE_FORMAT_R8
, 1 },
240 { 2, 1, 0, __DRI_IMAGE_FORMAT_R8
, 1 } } },
242 { __DRI_IMAGE_FOURCC_YUV444
, __DRI_IMAGE_COMPONENTS_Y_U_V
, 3,
243 { { 0, 0, 0, __DRI_IMAGE_FORMAT_R8
, 1 },
244 { 1, 0, 0, __DRI_IMAGE_FORMAT_R8
, 1 },
245 { 2, 0, 0, __DRI_IMAGE_FORMAT_R8
, 1 } } },
247 { __DRI_IMAGE_FOURCC_YVU410
, __DRI_IMAGE_COMPONENTS_Y_U_V
, 3,
248 { { 0, 0, 0, __DRI_IMAGE_FORMAT_R8
, 1 },
249 { 2, 2, 2, __DRI_IMAGE_FORMAT_R8
, 1 },
250 { 1, 2, 2, __DRI_IMAGE_FORMAT_R8
, 1 } } },
252 { __DRI_IMAGE_FOURCC_YVU411
, __DRI_IMAGE_COMPONENTS_Y_U_V
, 3,
253 { { 0, 0, 0, __DRI_IMAGE_FORMAT_R8
, 1 },
254 { 2, 2, 0, __DRI_IMAGE_FORMAT_R8
, 1 },
255 { 1, 2, 0, __DRI_IMAGE_FORMAT_R8
, 1 } } },
257 { __DRI_IMAGE_FOURCC_YVU420
, __DRI_IMAGE_COMPONENTS_Y_U_V
, 3,
258 { { 0, 0, 0, __DRI_IMAGE_FORMAT_R8
, 1 },
259 { 2, 1, 1, __DRI_IMAGE_FORMAT_R8
, 1 },
260 { 1, 1, 1, __DRI_IMAGE_FORMAT_R8
, 1 } } },
262 { __DRI_IMAGE_FOURCC_YVU422
, __DRI_IMAGE_COMPONENTS_Y_U_V
, 3,
263 { { 0, 0, 0, __DRI_IMAGE_FORMAT_R8
, 1 },
264 { 2, 1, 0, __DRI_IMAGE_FORMAT_R8
, 1 },
265 { 1, 1, 0, __DRI_IMAGE_FORMAT_R8
, 1 } } },
267 { __DRI_IMAGE_FOURCC_YVU444
, __DRI_IMAGE_COMPONENTS_Y_U_V
, 3,
268 { { 0, 0, 0, __DRI_IMAGE_FORMAT_R8
, 1 },
269 { 2, 0, 0, __DRI_IMAGE_FORMAT_R8
, 1 },
270 { 1, 0, 0, __DRI_IMAGE_FORMAT_R8
, 1 } } },
272 { __DRI_IMAGE_FOURCC_NV12
, __DRI_IMAGE_COMPONENTS_Y_UV
, 2,
273 { { 0, 0, 0, __DRI_IMAGE_FORMAT_R8
, 1 },
274 { 1, 1, 1, __DRI_IMAGE_FORMAT_GR88
, 2 } } },
276 { __DRI_IMAGE_FOURCC_NV16
, __DRI_IMAGE_COMPONENTS_Y_UV
, 2,
277 { { 0, 0, 0, __DRI_IMAGE_FORMAT_R8
, 1 },
278 { 1, 1, 0, __DRI_IMAGE_FORMAT_GR88
, 2 } } },
280 /* For YUYV buffers, we set up two overlapping DRI images and treat
281 * them as planar buffers in the compositors. Plane 0 is GR88 and
282 * samples YU or YV pairs and places Y into the R component, while
283 * plane 1 is ARGB and samples YUYV clusters and places pairs and
284 * places U into the G component and V into A. This lets the
285 * texture sampler interpolate the Y components correctly when
286 * sampling from plane 0, and interpolate U and V correctly when
287 * sampling from plane 1. */
288 { __DRI_IMAGE_FOURCC_YUYV
, __DRI_IMAGE_COMPONENTS_Y_XUXV
, 2,
289 { { 0, 0, 0, __DRI_IMAGE_FORMAT_GR88
, 2 },
290 { 0, 1, 0, __DRI_IMAGE_FORMAT_ARGB8888
, 4 } } }
294 intel_image_warn_if_unaligned(__DRIimage
*image
, const char *func
)
296 uint32_t tiling
, swizzle
;
297 brw_bo_get_tiling(image
->bo
, &tiling
, &swizzle
);
299 if (tiling
!= I915_TILING_NONE
&& (image
->offset
& 0xfff)) {
300 _mesa_warning(NULL
, "%s: offset 0x%08x not on tile boundary",
301 func
, image
->offset
);
305 static struct intel_image_format
*
306 intel_image_format_lookup(int fourcc
)
308 struct intel_image_format
*f
= NULL
;
310 for (unsigned i
= 0; i
< ARRAY_SIZE(intel_image_formats
); i
++) {
311 if (intel_image_formats
[i
].fourcc
== fourcc
) {
312 f
= &intel_image_formats
[i
];
320 static boolean
intel_lookup_fourcc(int dri_format
, int *fourcc
)
322 for (unsigned i
= 0; i
< ARRAY_SIZE(intel_image_formats
); i
++) {
323 if (intel_image_formats
[i
].planes
[0].dri_format
== dri_format
) {
324 *fourcc
= intel_image_formats
[i
].fourcc
;
332 intel_allocate_image(struct intel_screen
*screen
, int dri_format
,
337 image
= calloc(1, sizeof *image
);
341 image
->screen
= screen
;
342 image
->dri_format
= dri_format
;
345 image
->format
= driImageFormatToGLFormat(dri_format
);
346 if (dri_format
!= __DRI_IMAGE_FORMAT_NONE
&&
347 image
->format
== MESA_FORMAT_NONE
) {
352 image
->internal_format
= _mesa_get_format_base_format(image
->format
);
353 image
->data
= loaderPrivate
;
359 * Sets up a DRIImage structure to point to a slice out of a miptree.
362 intel_setup_image_from_mipmap_tree(struct brw_context
*brw
, __DRIimage
*image
,
363 struct intel_mipmap_tree
*mt
, GLuint level
,
366 intel_miptree_make_shareable(brw
, mt
);
368 intel_miptree_check_level_layer(mt
, level
, zoffset
);
370 image
->width
= minify(mt
->physical_width0
, level
- mt
->first_level
);
371 image
->height
= minify(mt
->physical_height0
, level
- mt
->first_level
);
372 image
->pitch
= mt
->pitch
;
374 image
->offset
= intel_miptree_get_tile_offsets(mt
, level
, zoffset
,
378 brw_bo_unreference(image
->bo
);
380 brw_bo_reference(mt
->bo
);
384 intel_create_image_from_name(__DRIscreen
*dri_screen
,
385 int width
, int height
, int format
,
386 int name
, int pitch
, void *loaderPrivate
)
388 struct intel_screen
*screen
= dri_screen
->driverPrivate
;
392 image
= intel_allocate_image(screen
, format
, loaderPrivate
);
396 if (image
->format
== MESA_FORMAT_NONE
)
399 cpp
= _mesa_get_format_bytes(image
->format
);
401 image
->width
= width
;
402 image
->height
= height
;
403 image
->pitch
= pitch
* cpp
;
404 image
->bo
= brw_bo_gem_create_from_name(screen
->bufmgr
, "image",
415 intel_create_image_from_renderbuffer(__DRIcontext
*context
,
416 int renderbuffer
, void *loaderPrivate
)
419 struct brw_context
*brw
= context
->driverPrivate
;
420 struct gl_context
*ctx
= &brw
->ctx
;
421 struct gl_renderbuffer
*rb
;
422 struct intel_renderbuffer
*irb
;
424 rb
= _mesa_lookup_renderbuffer(ctx
, renderbuffer
);
426 _mesa_error(ctx
, GL_INVALID_OPERATION
, "glRenderbufferExternalMESA");
430 irb
= intel_renderbuffer(rb
);
431 intel_miptree_make_shareable(brw
, irb
->mt
);
432 image
= calloc(1, sizeof *image
);
436 image
->internal_format
= rb
->InternalFormat
;
437 image
->format
= rb
->Format
;
439 image
->data
= loaderPrivate
;
440 brw_bo_unreference(image
->bo
);
441 image
->bo
= irb
->mt
->bo
;
442 brw_bo_reference(irb
->mt
->bo
);
443 image
->width
= rb
->Width
;
444 image
->height
= rb
->Height
;
445 image
->pitch
= irb
->mt
->pitch
;
446 image
->dri_format
= driGLFormatToImageFormat(image
->format
);
447 image
->has_depthstencil
= irb
->mt
->stencil_mt
? true : false;
449 rb
->NeedsFinishRenderTexture
= true;
454 intel_create_image_from_texture(__DRIcontext
*context
, int target
,
455 unsigned texture
, int zoffset
,
461 struct brw_context
*brw
= context
->driverPrivate
;
462 struct gl_texture_object
*obj
;
463 struct intel_texture_object
*iobj
;
466 obj
= _mesa_lookup_texture(&brw
->ctx
, texture
);
467 if (!obj
|| obj
->Target
!= target
) {
468 *error
= __DRI_IMAGE_ERROR_BAD_PARAMETER
;
472 if (target
== GL_TEXTURE_CUBE_MAP
)
475 _mesa_test_texobj_completeness(&brw
->ctx
, obj
);
476 iobj
= intel_texture_object(obj
);
477 if (!obj
->_BaseComplete
|| (level
> 0 && !obj
->_MipmapComplete
)) {
478 *error
= __DRI_IMAGE_ERROR_BAD_PARAMETER
;
482 if (level
< obj
->BaseLevel
|| level
> obj
->_MaxLevel
) {
483 *error
= __DRI_IMAGE_ERROR_BAD_MATCH
;
487 if (target
== GL_TEXTURE_3D
&& obj
->Image
[face
][level
]->Depth
< zoffset
) {
488 *error
= __DRI_IMAGE_ERROR_BAD_MATCH
;
491 image
= calloc(1, sizeof *image
);
493 *error
= __DRI_IMAGE_ERROR_BAD_ALLOC
;
497 image
->internal_format
= obj
->Image
[face
][level
]->InternalFormat
;
498 image
->format
= obj
->Image
[face
][level
]->TexFormat
;
499 image
->data
= loaderPrivate
;
500 intel_setup_image_from_mipmap_tree(brw
, image
, iobj
->mt
, level
, zoffset
);
501 image
->dri_format
= driGLFormatToImageFormat(image
->format
);
502 image
->has_depthstencil
= iobj
->mt
->stencil_mt
? true : false;
503 if (image
->dri_format
== MESA_FORMAT_NONE
) {
504 *error
= __DRI_IMAGE_ERROR_BAD_PARAMETER
;
509 *error
= __DRI_IMAGE_ERROR_SUCCESS
;
514 intel_destroy_image(__DRIimage
*image
)
516 brw_bo_unreference(image
->bo
);
520 enum modifier_priority
{
521 MODIFIER_PRIORITY_INVALID
= 0,
522 MODIFIER_PRIORITY_LINEAR
,
527 const uint64_t priority_to_modifier
[] = {
528 [MODIFIER_PRIORITY_INVALID
] = DRM_FORMAT_MOD_INVALID
,
529 [MODIFIER_PRIORITY_LINEAR
] = DRM_FORMAT_MOD_LINEAR
,
530 [MODIFIER_PRIORITY_X
] = I915_FORMAT_MOD_X_TILED
,
531 [MODIFIER_PRIORITY_Y
] = I915_FORMAT_MOD_Y_TILED
,
535 select_best_modifier(struct gen_device_info
*devinfo
,
536 const uint64_t *modifiers
,
537 const unsigned count
)
539 enum modifier_priority prio
= MODIFIER_PRIORITY_INVALID
;
541 for (int i
= 0; i
< count
; i
++) {
542 switch (modifiers
[i
]) {
543 case I915_FORMAT_MOD_Y_TILED
:
544 prio
= MAX2(prio
, MODIFIER_PRIORITY_Y
);
546 case I915_FORMAT_MOD_X_TILED
:
547 prio
= MAX2(prio
, MODIFIER_PRIORITY_X
);
549 case DRM_FORMAT_MOD_LINEAR
:
550 prio
= MAX2(prio
, MODIFIER_PRIORITY_LINEAR
);
552 case DRM_FORMAT_MOD_INVALID
:
558 return priority_to_modifier
[prio
];
562 intel_create_image_common(__DRIscreen
*dri_screen
,
563 int width
, int height
, int format
,
565 const uint64_t *modifiers
,
570 struct intel_screen
*screen
= dri_screen
->driverPrivate
;
571 /* Historically, X-tiled was the default, and so lack of modifier means
574 uint32_t tiling
= I915_TILING_X
;
577 /* Callers of this may specify a modifier, or a dri usage, but not both. The
578 * newer modifier interface deprecates the older usage flags newer modifier
579 * interface deprecates the older usage flags.
581 assert(!(use
&& count
));
583 uint64_t modifier
= select_best_modifier(&screen
->devinfo
, modifiers
, count
);
585 case I915_FORMAT_MOD_X_TILED
:
586 assert(tiling
== I915_TILING_X
);
588 case DRM_FORMAT_MOD_LINEAR
:
589 tiling
= I915_TILING_NONE
;
591 case I915_FORMAT_MOD_Y_TILED
:
592 tiling
= I915_TILING_Y
;
594 case DRM_FORMAT_MOD_INVALID
:
601 if (use
& __DRI_IMAGE_USE_CURSOR
) {
602 if (width
!= 64 || height
!= 64)
604 tiling
= I915_TILING_NONE
;
607 if (use
& __DRI_IMAGE_USE_LINEAR
)
608 tiling
= I915_TILING_NONE
;
610 image
= intel_allocate_image(screen
, format
, loaderPrivate
);
614 cpp
= _mesa_get_format_bytes(image
->format
);
615 image
->bo
= brw_bo_alloc_tiled(screen
->bufmgr
, "image",
616 width
, height
, cpp
, tiling
,
618 if (image
->bo
== NULL
) {
622 image
->width
= width
;
623 image
->height
= height
;
624 image
->modifier
= modifier
;
630 intel_create_image(__DRIscreen
*dri_screen
,
631 int width
, int height
, int format
,
635 return intel_create_image_common(dri_screen
, width
, height
, format
, use
, NULL
, 0,
640 intel_create_image_with_modifiers(__DRIscreen
*dri_screen
,
641 int width
, int height
, int format
,
642 const uint64_t *modifiers
,
643 const unsigned count
,
646 return intel_create_image_common(dri_screen
, width
, height
, format
, 0,
647 modifiers
, count
, loaderPrivate
);
651 intel_query_image(__DRIimage
*image
, int attrib
, int *value
)
654 case __DRI_IMAGE_ATTRIB_STRIDE
:
655 *value
= image
->pitch
;
657 case __DRI_IMAGE_ATTRIB_HANDLE
:
658 *value
= image
->bo
->gem_handle
;
660 case __DRI_IMAGE_ATTRIB_NAME
:
661 return !brw_bo_flink(image
->bo
, (uint32_t *) value
);
662 case __DRI_IMAGE_ATTRIB_FORMAT
:
663 *value
= image
->dri_format
;
665 case __DRI_IMAGE_ATTRIB_WIDTH
:
666 *value
= image
->width
;
668 case __DRI_IMAGE_ATTRIB_HEIGHT
:
669 *value
= image
->height
;
671 case __DRI_IMAGE_ATTRIB_COMPONENTS
:
672 if (image
->planar_format
== NULL
)
674 *value
= image
->planar_format
->components
;
676 case __DRI_IMAGE_ATTRIB_FD
:
677 return !brw_bo_gem_export_to_prime(image
->bo
, value
);
678 case __DRI_IMAGE_ATTRIB_FOURCC
:
679 return intel_lookup_fourcc(image
->dri_format
, value
);
680 case __DRI_IMAGE_ATTRIB_NUM_PLANES
:
683 case __DRI_IMAGE_ATTRIB_OFFSET
:
684 *value
= image
->offset
;
686 case __DRI_IMAGE_ATTRIB_MODIFIER_LOWER
:
687 *value
= (image
->modifier
& 0xffffffff);
689 case __DRI_IMAGE_ATTRIB_MODIFIER_UPPER
:
690 *value
= ((image
->modifier
>> 32) & 0xffffffff);
699 intel_dup_image(__DRIimage
*orig_image
, void *loaderPrivate
)
703 image
= calloc(1, sizeof *image
);
707 brw_bo_reference(orig_image
->bo
);
708 image
->bo
= orig_image
->bo
;
709 image
->internal_format
= orig_image
->internal_format
;
710 image
->planar_format
= orig_image
->planar_format
;
711 image
->dri_format
= orig_image
->dri_format
;
712 image
->format
= orig_image
->format
;
713 image
->offset
= orig_image
->offset
;
714 image
->width
= orig_image
->width
;
715 image
->height
= orig_image
->height
;
716 image
->pitch
= orig_image
->pitch
;
717 image
->tile_x
= orig_image
->tile_x
;
718 image
->tile_y
= orig_image
->tile_y
;
719 image
->has_depthstencil
= orig_image
->has_depthstencil
;
720 image
->data
= loaderPrivate
;
722 memcpy(image
->strides
, orig_image
->strides
, sizeof(image
->strides
));
723 memcpy(image
->offsets
, orig_image
->offsets
, sizeof(image
->offsets
));
729 intel_validate_usage(__DRIimage
*image
, unsigned int use
)
731 if (use
& __DRI_IMAGE_USE_CURSOR
) {
732 if (image
->width
!= 64 || image
->height
!= 64)
740 intel_create_image_from_names(__DRIscreen
*dri_screen
,
741 int width
, int height
, int fourcc
,
742 int *names
, int num_names
,
743 int *strides
, int *offsets
,
746 struct intel_image_format
*f
= NULL
;
750 if (dri_screen
== NULL
|| names
== NULL
|| num_names
!= 1)
753 f
= intel_image_format_lookup(fourcc
);
757 image
= intel_create_image_from_name(dri_screen
, width
, height
,
758 __DRI_IMAGE_FORMAT_NONE
,
759 names
[0], strides
[0],
765 image
->planar_format
= f
;
766 for (i
= 0; i
< f
->nplanes
; i
++) {
767 index
= f
->planes
[i
].buffer_index
;
768 image
->offsets
[index
] = offsets
[index
];
769 image
->strides
[index
] = strides
[index
];
776 intel_create_image_from_fds(__DRIscreen
*dri_screen
,
777 int width
, int height
, int fourcc
,
778 int *fds
, int num_fds
, int *strides
, int *offsets
,
781 struct intel_screen
*screen
= dri_screen
->driverPrivate
;
782 struct intel_image_format
*f
;
786 if (fds
== NULL
|| num_fds
< 1)
789 /* We only support all planes from the same bo */
790 for (i
= 0; i
< num_fds
; i
++)
791 if (fds
[0] != fds
[i
])
794 f
= intel_image_format_lookup(fourcc
);
799 image
= intel_allocate_image(screen
, f
->planes
[0].dri_format
,
802 image
= intel_allocate_image(screen
, __DRI_IMAGE_FORMAT_NONE
,
808 image
->width
= width
;
809 image
->height
= height
;
810 image
->pitch
= strides
[0];
812 image
->planar_format
= f
;
814 for (i
= 0; i
< f
->nplanes
; i
++) {
815 index
= f
->planes
[i
].buffer_index
;
816 image
->offsets
[index
] = offsets
[index
];
817 image
->strides
[index
] = strides
[index
];
819 const int plane_height
= height
>> f
->planes
[i
].height_shift
;
820 const int end
= offsets
[index
] + plane_height
* strides
[index
];
825 image
->bo
= brw_bo_gem_create_from_prime(screen
->bufmgr
,
827 if (image
->bo
== NULL
) {
832 if (f
->nplanes
== 1) {
833 image
->offset
= image
->offsets
[0];
834 intel_image_warn_if_unaligned(image
, __func__
);
841 intel_create_image_from_dma_bufs(__DRIscreen
*dri_screen
,
842 int width
, int height
, int fourcc
,
843 int *fds
, int num_fds
,
844 int *strides
, int *offsets
,
845 enum __DRIYUVColorSpace yuv_color_space
,
846 enum __DRISampleRange sample_range
,
847 enum __DRIChromaSiting horizontal_siting
,
848 enum __DRIChromaSiting vertical_siting
,
853 struct intel_image_format
*f
= intel_image_format_lookup(fourcc
);
856 *error
= __DRI_IMAGE_ERROR_BAD_MATCH
;
860 image
= intel_create_image_from_fds(dri_screen
, width
, height
, fourcc
, fds
,
861 num_fds
, strides
, offsets
,
865 * Invalid parameters and any inconsistencies between are assumed to be
866 * checked by the caller. Therefore besides unsupported formats one can fail
867 * only in allocation.
870 *error
= __DRI_IMAGE_ERROR_BAD_ALLOC
;
874 image
->dma_buf_imported
= true;
875 image
->yuv_color_space
= yuv_color_space
;
876 image
->sample_range
= sample_range
;
877 image
->horizontal_siting
= horizontal_siting
;
878 image
->vertical_siting
= vertical_siting
;
880 *error
= __DRI_IMAGE_ERROR_SUCCESS
;
885 intel_from_planar(__DRIimage
*parent
, int plane
, void *loaderPrivate
)
887 int width
, height
, offset
, stride
, dri_format
, index
;
888 struct intel_image_format
*f
;
891 if (parent
== NULL
|| parent
->planar_format
== NULL
)
894 f
= parent
->planar_format
;
896 if (plane
>= f
->nplanes
)
899 width
= parent
->width
>> f
->planes
[plane
].width_shift
;
900 height
= parent
->height
>> f
->planes
[plane
].height_shift
;
901 dri_format
= f
->planes
[plane
].dri_format
;
902 index
= f
->planes
[plane
].buffer_index
;
903 offset
= parent
->offsets
[index
];
904 stride
= parent
->strides
[index
];
906 image
= intel_allocate_image(parent
->screen
, dri_format
, loaderPrivate
);
910 if (offset
+ height
* stride
> parent
->bo
->size
) {
911 _mesa_warning(NULL
, "intel_create_sub_image: subimage out of bounds");
916 image
->bo
= parent
->bo
;
917 brw_bo_reference(parent
->bo
);
919 image
->width
= width
;
920 image
->height
= height
;
921 image
->pitch
= stride
;
922 image
->offset
= offset
;
924 intel_image_warn_if_unaligned(image
, __func__
);
929 static const __DRIimageExtension intelImageExtension
= {
930 .base
= { __DRI_IMAGE
, 14 },
932 .createImageFromName
= intel_create_image_from_name
,
933 .createImageFromRenderbuffer
= intel_create_image_from_renderbuffer
,
934 .destroyImage
= intel_destroy_image
,
935 .createImage
= intel_create_image
,
936 .queryImage
= intel_query_image
,
937 .dupImage
= intel_dup_image
,
938 .validateUsage
= intel_validate_usage
,
939 .createImageFromNames
= intel_create_image_from_names
,
940 .fromPlanar
= intel_from_planar
,
941 .createImageFromTexture
= intel_create_image_from_texture
,
942 .createImageFromFds
= intel_create_image_from_fds
,
943 .createImageFromDmaBufs
= intel_create_image_from_dma_bufs
,
945 .getCapabilities
= NULL
,
948 .createImageWithModifiers
= intel_create_image_with_modifiers
,
952 get_aperture_size(int fd
)
954 struct drm_i915_gem_get_aperture aperture
;
956 if (drmIoctl(fd
, DRM_IOCTL_I915_GEM_GET_APERTURE
, &aperture
) != 0)
959 return aperture
.aper_size
;
963 brw_query_renderer_integer(__DRIscreen
*dri_screen
,
964 int param
, unsigned int *value
)
966 const struct intel_screen
*const screen
=
967 (struct intel_screen
*) dri_screen
->driverPrivate
;
970 case __DRI2_RENDERER_VENDOR_ID
:
973 case __DRI2_RENDERER_DEVICE_ID
:
974 value
[0] = screen
->deviceID
;
976 case __DRI2_RENDERER_ACCELERATED
:
979 case __DRI2_RENDERER_VIDEO_MEMORY
: {
980 /* Once a batch uses more than 75% of the maximum mappable size, we
981 * assume that there's some fragmentation, and we start doing extra
982 * flushing, etc. That's the big cliff apps will care about.
984 const unsigned gpu_mappable_megabytes
=
985 screen
->aperture_threshold
/ (1024 * 1024);
987 const long system_memory_pages
= sysconf(_SC_PHYS_PAGES
);
988 const long system_page_size
= sysconf(_SC_PAGE_SIZE
);
990 if (system_memory_pages
<= 0 || system_page_size
<= 0)
993 const uint64_t system_memory_bytes
= (uint64_t) system_memory_pages
994 * (uint64_t) system_page_size
;
996 const unsigned system_memory_megabytes
=
997 (unsigned) (system_memory_bytes
/ (1024 * 1024));
999 value
[0] = MIN2(system_memory_megabytes
, gpu_mappable_megabytes
);
1002 case __DRI2_RENDERER_UNIFIED_MEMORY_ARCHITECTURE
:
1005 case __DRI2_RENDERER_HAS_TEXTURE_3D
:
1009 return driQueryRendererIntegerCommon(dri_screen
, param
, value
);
1016 brw_query_renderer_string(__DRIscreen
*dri_screen
,
1017 int param
, const char **value
)
1019 const struct intel_screen
*screen
=
1020 (struct intel_screen
*) dri_screen
->driverPrivate
;
1023 case __DRI2_RENDERER_VENDOR_ID
:
1024 value
[0] = brw_vendor_string
;
1026 case __DRI2_RENDERER_DEVICE_ID
:
1027 value
[0] = brw_get_renderer_string(screen
);
1036 static const __DRI2rendererQueryExtension intelRendererQueryExtension
= {
1037 .base
= { __DRI2_RENDERER_QUERY
, 1 },
1039 .queryInteger
= brw_query_renderer_integer
,
1040 .queryString
= brw_query_renderer_string
1043 static const __DRIrobustnessExtension dri2Robustness
= {
1044 .base
= { __DRI2_ROBUSTNESS
, 1 }
1047 static const __DRIextension
*screenExtensions
[] = {
1048 &intelTexBufferExtension
.base
,
1049 &intelFenceExtension
.base
,
1050 &intelFlushExtension
.base
,
1051 &intelImageExtension
.base
,
1052 &intelRendererQueryExtension
.base
,
1053 &dri2ConfigQueryExtension
.base
,
1057 static const __DRIextension
*intelRobustScreenExtensions
[] = {
1058 &intelTexBufferExtension
.base
,
1059 &intelFenceExtension
.base
,
1060 &intelFlushExtension
.base
,
1061 &intelImageExtension
.base
,
1062 &intelRendererQueryExtension
.base
,
1063 &dri2ConfigQueryExtension
.base
,
1064 &dri2Robustness
.base
,
1069 intel_get_param(struct intel_screen
*screen
, int param
, int *value
)
1072 struct drm_i915_getparam gp
;
1074 memset(&gp
, 0, sizeof(gp
));
1078 if (drmIoctl(screen
->driScrnPriv
->fd
, DRM_IOCTL_I915_GETPARAM
, &gp
) == -1) {
1081 _mesa_warning(NULL
, "drm_i915_getparam: %d", ret
);
1088 intel_get_boolean(struct intel_screen
*screen
, int param
)
1091 return (intel_get_param(screen
, param
, &value
) == 0) && value
;
1095 intel_get_integer(struct intel_screen
*screen
, int param
)
1099 if (intel_get_param(screen
, param
, &value
) == 0)
1106 intelDestroyScreen(__DRIscreen
* sPriv
)
1108 struct intel_screen
*screen
= sPriv
->driverPrivate
;
1110 brw_bufmgr_destroy(screen
->bufmgr
);
1111 driDestroyOptionInfo(&screen
->optionCache
);
1113 ralloc_free(screen
);
1114 sPriv
->driverPrivate
= NULL
;
1119 * This is called when we need to set up GL rendering to a new X window.
1122 intelCreateBuffer(__DRIscreen
*dri_screen
,
1123 __DRIdrawable
* driDrawPriv
,
1124 const struct gl_config
* mesaVis
, GLboolean isPixmap
)
1126 struct intel_renderbuffer
*rb
;
1127 struct intel_screen
*screen
= (struct intel_screen
*)
1128 dri_screen
->driverPrivate
;
1129 mesa_format rgbFormat
;
1130 unsigned num_samples
=
1131 intel_quantize_num_samples(screen
, mesaVis
->samples
);
1132 struct gl_framebuffer
*fb
;
1137 fb
= CALLOC_STRUCT(gl_framebuffer
);
1141 _mesa_initialize_window_framebuffer(fb
, mesaVis
);
1143 if (screen
->winsys_msaa_samples_override
!= -1) {
1144 num_samples
= screen
->winsys_msaa_samples_override
;
1145 fb
->Visual
.samples
= num_samples
;
1148 if (mesaVis
->redBits
== 5) {
1149 rgbFormat
= mesaVis
->redMask
== 0x1f ? MESA_FORMAT_R5G6B5_UNORM
1150 : MESA_FORMAT_B5G6R5_UNORM
;
1151 } else if (mesaVis
->sRGBCapable
) {
1152 rgbFormat
= mesaVis
->redMask
== 0xff ? MESA_FORMAT_R8G8B8A8_SRGB
1153 : MESA_FORMAT_B8G8R8A8_SRGB
;
1154 } else if (mesaVis
->alphaBits
== 0) {
1155 rgbFormat
= mesaVis
->redMask
== 0xff ? MESA_FORMAT_R8G8B8X8_UNORM
1156 : MESA_FORMAT_B8G8R8X8_UNORM
;
1158 rgbFormat
= mesaVis
->redMask
== 0xff ? MESA_FORMAT_R8G8B8A8_SRGB
1159 : MESA_FORMAT_B8G8R8A8_SRGB
;
1160 fb
->Visual
.sRGBCapable
= true;
1163 /* setup the hardware-based renderbuffers */
1164 rb
= intel_create_renderbuffer(rgbFormat
, num_samples
);
1165 _mesa_add_renderbuffer_without_ref(fb
, BUFFER_FRONT_LEFT
, &rb
->Base
.Base
);
1167 if (mesaVis
->doubleBufferMode
) {
1168 rb
= intel_create_renderbuffer(rgbFormat
, num_samples
);
1169 _mesa_add_renderbuffer_without_ref(fb
, BUFFER_BACK_LEFT
, &rb
->Base
.Base
);
1173 * Assert here that the gl_config has an expected depth/stencil bit
1174 * combination: one of d24/s8, d16/s0, d0/s0. (See intelInitScreen2(),
1175 * which constructs the advertised configs.)
1177 if (mesaVis
->depthBits
== 24) {
1178 assert(mesaVis
->stencilBits
== 8);
1180 if (screen
->devinfo
.has_hiz_and_separate_stencil
) {
1181 rb
= intel_create_private_renderbuffer(MESA_FORMAT_Z24_UNORM_X8_UINT
,
1183 _mesa_add_renderbuffer_without_ref(fb
, BUFFER_DEPTH
, &rb
->Base
.Base
);
1184 rb
= intel_create_private_renderbuffer(MESA_FORMAT_S_UINT8
,
1186 _mesa_add_renderbuffer_without_ref(fb
, BUFFER_STENCIL
,
1190 * Use combined depth/stencil. Note that the renderbuffer is
1191 * attached to two attachment points.
1193 rb
= intel_create_private_renderbuffer(MESA_FORMAT_Z24_UNORM_S8_UINT
,
1195 _mesa_add_renderbuffer_without_ref(fb
, BUFFER_DEPTH
, &rb
->Base
.Base
);
1196 _mesa_add_renderbuffer(fb
, BUFFER_STENCIL
, &rb
->Base
.Base
);
1199 else if (mesaVis
->depthBits
== 16) {
1200 assert(mesaVis
->stencilBits
== 0);
1201 rb
= intel_create_private_renderbuffer(MESA_FORMAT_Z_UNORM16
,
1203 _mesa_add_renderbuffer_without_ref(fb
, BUFFER_DEPTH
, &rb
->Base
.Base
);
1206 assert(mesaVis
->depthBits
== 0);
1207 assert(mesaVis
->stencilBits
== 0);
1210 /* now add any/all software-based renderbuffers we may need */
1211 _swrast_add_soft_renderbuffers(fb
,
1212 false, /* never sw color */
1213 false, /* never sw depth */
1214 false, /* never sw stencil */
1215 mesaVis
->accumRedBits
> 0,
1216 false, /* never sw alpha */
1217 false /* never sw aux */ );
1218 driDrawPriv
->driverPrivate
= fb
;
1224 intelDestroyBuffer(__DRIdrawable
* driDrawPriv
)
1226 struct gl_framebuffer
*fb
= driDrawPriv
->driverPrivate
;
1228 _mesa_reference_framebuffer(&fb
, NULL
);
1232 intel_detect_sseu(struct intel_screen
*screen
)
1234 assert(screen
->devinfo
.gen
>= 8);
1237 screen
->subslice_total
= -1;
1238 screen
->eu_total
= -1;
1240 ret
= intel_get_param(screen
, I915_PARAM_SUBSLICE_TOTAL
,
1241 &screen
->subslice_total
);
1242 if (ret
< 0 && ret
!= -EINVAL
)
1245 ret
= intel_get_param(screen
,
1246 I915_PARAM_EU_TOTAL
, &screen
->eu_total
);
1247 if (ret
< 0 && ret
!= -EINVAL
)
1250 /* Without this information, we cannot get the right Braswell brandstrings,
1251 * and we have to use conservative numbers for GPGPU on many platforms, but
1252 * otherwise, things will just work.
1254 if (screen
->subslice_total
< 1 || screen
->eu_total
< 1)
1256 "Kernel 4.1 required to properly query GPU properties.\n");
1261 screen
->subslice_total
= -1;
1262 screen
->eu_total
= -1;
1263 _mesa_warning(NULL
, "Failed to query GPU properties (%s).\n", strerror(-ret
));
1267 intel_init_bufmgr(struct intel_screen
*screen
)
1269 __DRIscreen
*dri_screen
= screen
->driScrnPriv
;
1271 if (getenv("INTEL_NO_HW") != NULL
)
1272 screen
->no_hw
= true;
1274 screen
->bufmgr
= brw_bufmgr_init(&screen
->devinfo
, dri_screen
->fd
, BATCH_SZ
);
1275 if (screen
->bufmgr
== NULL
) {
1276 fprintf(stderr
, "[%s:%u] Error initializing buffer manager.\n",
1277 __func__
, __LINE__
);
1281 if (!intel_get_boolean(screen
, I915_PARAM_HAS_WAIT_TIMEOUT
)) {
1282 fprintf(stderr
, "[%s: %u] Kernel 3.6 required.\n", __func__
, __LINE__
);
1290 intel_detect_swizzling(struct intel_screen
*screen
)
1292 struct brw_bo
*buffer
;
1294 uint32_t aligned_pitch
;
1295 uint32_t tiling
= I915_TILING_X
;
1296 uint32_t swizzle_mode
= 0;
1298 buffer
= brw_bo_alloc_tiled(screen
->bufmgr
, "swizzle test",
1299 64, 64, 4, tiling
, &aligned_pitch
, flags
);
1303 brw_bo_get_tiling(buffer
, &tiling
, &swizzle_mode
);
1304 brw_bo_unreference(buffer
);
1306 if (swizzle_mode
== I915_BIT_6_SWIZZLE_NONE
)
1313 intel_detect_timestamp(struct intel_screen
*screen
)
1315 uint64_t dummy
= 0, last
= 0;
1316 int upper
, lower
, loops
;
1318 /* On 64bit systems, some old kernels trigger a hw bug resulting in the
1319 * TIMESTAMP register being shifted and the low 32bits always zero.
1321 * More recent kernels offer an interface to read the full 36bits
1324 if (brw_reg_read(screen
->bufmgr
, TIMESTAMP
| 1, &dummy
) == 0)
1327 /* Determine if we have a 32bit or 64bit kernel by inspecting the
1328 * upper 32bits for a rapidly changing timestamp.
1330 if (brw_reg_read(screen
->bufmgr
, TIMESTAMP
, &last
))
1334 for (loops
= 0; loops
< 10; loops
++) {
1335 /* The TIMESTAMP should change every 80ns, so several round trips
1336 * through the kernel should be enough to advance it.
1338 if (brw_reg_read(screen
->bufmgr
, TIMESTAMP
, &dummy
))
1341 upper
+= (dummy
>> 32) != (last
>> 32);
1342 if (upper
> 1) /* beware 32bit counter overflow */
1343 return 2; /* upper dword holds the low 32bits of the timestamp */
1345 lower
+= (dummy
& 0xffffffff) != (last
& 0xffffffff);
1347 return 1; /* timestamp is unshifted */
1352 /* No advancement? No timestamp! */
1357 * Test if we can use MI_LOAD_REGISTER_MEM from an untrusted batchbuffer.
1359 * Some combinations of hardware and kernel versions allow this feature,
1360 * while others don't. Instead of trying to enumerate every case, just
1361 * try and write a register and see if works.
1364 intel_detect_pipelined_register(struct intel_screen
*screen
,
1365 int reg
, uint32_t expected_value
, bool reset
)
1370 struct brw_bo
*results
, *bo
;
1372 uint32_t offset
= 0;
1373 bool success
= false;
1375 /* Create a zero'ed temporary buffer for reading our results */
1376 results
= brw_bo_alloc(screen
->bufmgr
, "registers", 4096, 0);
1377 if (results
== NULL
)
1380 bo
= brw_bo_alloc(screen
->bufmgr
, "batchbuffer", 4096, 0);
1384 if (brw_bo_map(NULL
, bo
, 1))
1387 batch
= bo
->virtual;
1389 /* Write the register. */
1390 *batch
++ = MI_LOAD_REGISTER_IMM
| (3 - 2);
1392 *batch
++ = expected_value
;
1394 /* Save the register's value back to the buffer. */
1395 *batch
++ = MI_STORE_REGISTER_MEM
| (3 - 2);
1397 struct drm_i915_gem_relocation_entry reloc
= {
1398 .offset
= (char *) batch
- (char *) bo
->virtual,
1399 .delta
= offset
* sizeof(uint32_t),
1400 .target_handle
= results
->gem_handle
,
1401 .read_domains
= I915_GEM_DOMAIN_INSTRUCTION
,
1402 .write_domain
= I915_GEM_DOMAIN_INSTRUCTION
,
1404 *batch
++ = reloc
.presumed_offset
+ reloc
.delta
;
1406 /* And afterwards clear the register */
1408 *batch
++ = MI_LOAD_REGISTER_IMM
| (3 - 2);
1413 *batch
++ = MI_BATCH_BUFFER_END
;
1415 struct drm_i915_gem_exec_object2 exec_objects
[2] = {
1417 .handle
= results
->gem_handle
,
1420 .handle
= bo
->gem_handle
,
1421 .relocation_count
= 1,
1422 .relocs_ptr
= (uintptr_t) &reloc
,
1426 struct drm_i915_gem_execbuffer2 execbuf
= {
1427 .buffers_ptr
= (uintptr_t) exec_objects
,
1429 .batch_len
= ALIGN((char *) batch
- (char *) bo
->virtual, 8),
1430 .flags
= I915_EXEC_RENDER
,
1433 /* Don't bother with error checking - if the execbuf fails, the
1434 * value won't be written and we'll just report that there's no access.
1436 __DRIscreen
*dri_screen
= screen
->driScrnPriv
;
1437 drmIoctl(dri_screen
->fd
, DRM_IOCTL_I915_GEM_EXECBUFFER2
, &execbuf
);
1439 /* Check whether the value got written. */
1440 if (brw_bo_map(NULL
, results
, false) == 0) {
1441 success
= *((uint32_t *)results
->virtual + offset
) == expected_value
;
1442 brw_bo_unmap(results
);
1446 brw_bo_unreference(bo
);
1448 brw_bo_unreference(results
);
1454 intel_detect_pipelined_so(struct intel_screen
*screen
)
1456 const struct gen_device_info
*devinfo
= &screen
->devinfo
;
1458 /* Supposedly, Broadwell just works. */
1459 if (devinfo
->gen
>= 8)
1462 if (devinfo
->gen
<= 6)
1465 /* See the big explanation about command parser versions below */
1466 if (screen
->cmd_parser_version
>= (devinfo
->is_haswell
? 7 : 2))
1469 /* We use SO_WRITE_OFFSET0 since you're supposed to write it (unlike the
1470 * statistics registers), and we already reset it to zero before using it.
1472 return intel_detect_pipelined_register(screen
,
1473 GEN7_SO_WRITE_OFFSET(0),
1479 * Return array of MSAA modes supported by the hardware. The array is
1480 * zero-terminated and sorted in decreasing order.
1483 intel_supported_msaa_modes(const struct intel_screen
*screen
)
1485 static const int gen9_modes
[] = {16, 8, 4, 2, 0, -1};
1486 static const int gen8_modes
[] = {8, 4, 2, 0, -1};
1487 static const int gen7_modes
[] = {8, 4, 0, -1};
1488 static const int gen6_modes
[] = {4, 0, -1};
1489 static const int gen4_modes
[] = {0, -1};
1491 if (screen
->devinfo
.gen
>= 9) {
1493 } else if (screen
->devinfo
.gen
>= 8) {
1495 } else if (screen
->devinfo
.gen
>= 7) {
1497 } else if (screen
->devinfo
.gen
== 6) {
1504 static __DRIconfig
**
1505 intel_screen_make_configs(__DRIscreen
*dri_screen
)
1507 static const mesa_format formats
[] = {
1508 MESA_FORMAT_B5G6R5_UNORM
,
1509 MESA_FORMAT_B8G8R8A8_UNORM
,
1510 MESA_FORMAT_B8G8R8X8_UNORM
1513 /* GLX_SWAP_COPY_OML is not supported due to page flipping. */
1514 static const GLenum back_buffer_modes
[] = {
1515 GLX_SWAP_UNDEFINED_OML
, GLX_NONE
,
1518 static const uint8_t singlesample_samples
[1] = {0};
1519 static const uint8_t multisample_samples
[2] = {4, 8};
1521 struct intel_screen
*screen
= dri_screen
->driverPrivate
;
1522 const struct gen_device_info
*devinfo
= &screen
->devinfo
;
1523 uint8_t depth_bits
[4], stencil_bits
[4];
1524 __DRIconfig
**configs
= NULL
;
1526 /* Generate singlesample configs without accumulation buffer. */
1527 for (unsigned i
= 0; i
< ARRAY_SIZE(formats
); i
++) {
1528 __DRIconfig
**new_configs
;
1529 int num_depth_stencil_bits
= 2;
1531 /* Starting with DRI2 protocol version 1.1 we can request a depth/stencil
1532 * buffer that has a different number of bits per pixel than the color
1533 * buffer, gen >= 6 supports this.
1536 stencil_bits
[0] = 0;
1538 if (formats
[i
] == MESA_FORMAT_B5G6R5_UNORM
) {
1540 stencil_bits
[1] = 0;
1541 if (devinfo
->gen
>= 6) {
1543 stencil_bits
[2] = 8;
1544 num_depth_stencil_bits
= 3;
1548 stencil_bits
[1] = 8;
1551 new_configs
= driCreateConfigs(formats
[i
],
1554 num_depth_stencil_bits
,
1555 back_buffer_modes
, 2,
1556 singlesample_samples
, 1,
1558 configs
= driConcatConfigs(configs
, new_configs
);
1561 /* Generate the minimum possible set of configs that include an
1562 * accumulation buffer.
1564 for (unsigned i
= 0; i
< ARRAY_SIZE(formats
); i
++) {
1565 __DRIconfig
**new_configs
;
1567 if (formats
[i
] == MESA_FORMAT_B5G6R5_UNORM
) {
1569 stencil_bits
[0] = 0;
1572 stencil_bits
[0] = 8;
1575 new_configs
= driCreateConfigs(formats
[i
],
1576 depth_bits
, stencil_bits
, 1,
1577 back_buffer_modes
, 1,
1578 singlesample_samples
, 1,
1580 configs
= driConcatConfigs(configs
, new_configs
);
1583 /* Generate multisample configs.
1585 * This loop breaks early, and hence is a no-op, on gen < 6.
1587 * Multisample configs must follow the singlesample configs in order to
1588 * work around an X server bug present in 1.12. The X server chooses to
1589 * associate the first listed RGBA888-Z24S8 config, regardless of its
1590 * sample count, with the 32-bit depth visual used for compositing.
1592 * Only doublebuffer configs with GLX_SWAP_UNDEFINED_OML behavior are
1593 * supported. Singlebuffer configs are not supported because no one wants
1596 for (unsigned i
= 0; i
< ARRAY_SIZE(formats
); i
++) {
1597 if (devinfo
->gen
< 6)
1600 __DRIconfig
**new_configs
;
1601 const int num_depth_stencil_bits
= 2;
1602 int num_msaa_modes
= 0;
1605 stencil_bits
[0] = 0;
1607 if (formats
[i
] == MESA_FORMAT_B5G6R5_UNORM
) {
1609 stencil_bits
[1] = 0;
1612 stencil_bits
[1] = 8;
1615 if (devinfo
->gen
>= 7)
1617 else if (devinfo
->gen
== 6)
1620 new_configs
= driCreateConfigs(formats
[i
],
1623 num_depth_stencil_bits
,
1624 back_buffer_modes
, 1,
1625 multisample_samples
,
1628 configs
= driConcatConfigs(configs
, new_configs
);
1631 if (configs
== NULL
) {
1632 fprintf(stderr
, "[%s:%u] Error creating FBConfig!\n", __func__
,
1641 set_max_gl_versions(struct intel_screen
*screen
)
1643 __DRIscreen
*dri_screen
= screen
->driScrnPriv
;
1644 const bool has_astc
= screen
->devinfo
.gen
>= 9;
1646 switch (screen
->devinfo
.gen
) {
1649 dri_screen
->max_gl_core_version
= 45;
1650 dri_screen
->max_gl_compat_version
= 30;
1651 dri_screen
->max_gl_es1_version
= 11;
1652 dri_screen
->max_gl_es2_version
= has_astc
? 32 : 31;
1655 dri_screen
->max_gl_core_version
= 33;
1656 if (can_do_pipelined_register_writes(screen
)) {
1657 dri_screen
->max_gl_core_version
= 42;
1658 if (screen
->devinfo
.is_haswell
&& can_do_compute_dispatch(screen
))
1659 dri_screen
->max_gl_core_version
= 43;
1660 if (screen
->devinfo
.is_haswell
&& can_do_mi_math_and_lrr(screen
))
1661 dri_screen
->max_gl_core_version
= 45;
1663 dri_screen
->max_gl_compat_version
= 30;
1664 dri_screen
->max_gl_es1_version
= 11;
1665 dri_screen
->max_gl_es2_version
= screen
->devinfo
.is_haswell
? 31 : 30;
1668 dri_screen
->max_gl_core_version
= 33;
1669 dri_screen
->max_gl_compat_version
= 30;
1670 dri_screen
->max_gl_es1_version
= 11;
1671 dri_screen
->max_gl_es2_version
= 30;
1675 dri_screen
->max_gl_core_version
= 0;
1676 dri_screen
->max_gl_compat_version
= 21;
1677 dri_screen
->max_gl_es1_version
= 11;
1678 dri_screen
->max_gl_es2_version
= 20;
1681 unreachable("unrecognized intel_screen::gen");
1686 * Return the revision (generally the revid field of the PCI header) of the
1689 * XXX: This function is useful to keep around even if it is not currently in
1690 * use. It is necessary for new platforms and revision specific workarounds or
1691 * features. Please don't remove it so that we know it at least continues to
1694 static __attribute__((__unused__
)) int
1695 brw_get_revision(int fd
)
1697 struct drm_i915_getparam gp
;
1701 memset(&gp
, 0, sizeof(gp
));
1702 gp
.param
= I915_PARAM_REVISION
;
1703 gp
.value
= &revision
;
1705 ret
= drmCommandWriteRead(fd
, DRM_I915_GETPARAM
, &gp
, sizeof(gp
));
1713 shader_debug_log_mesa(void *data
, const char *fmt
, ...)
1715 struct brw_context
*brw
= (struct brw_context
*)data
;
1718 va_start(args
, fmt
);
1720 _mesa_gl_vdebug(&brw
->ctx
, &msg_id
,
1721 MESA_DEBUG_SOURCE_SHADER_COMPILER
,
1722 MESA_DEBUG_TYPE_OTHER
,
1723 MESA_DEBUG_SEVERITY_NOTIFICATION
, fmt
, args
);
1728 shader_perf_log_mesa(void *data
, const char *fmt
, ...)
1730 struct brw_context
*brw
= (struct brw_context
*)data
;
1733 va_start(args
, fmt
);
1735 if (unlikely(INTEL_DEBUG
& DEBUG_PERF
)) {
1737 va_copy(args_copy
, args
);
1738 vfprintf(stderr
, fmt
, args_copy
);
1742 if (brw
->perf_debug
) {
1744 _mesa_gl_vdebug(&brw
->ctx
, &msg_id
,
1745 MESA_DEBUG_SOURCE_SHADER_COMPILER
,
1746 MESA_DEBUG_TYPE_PERFORMANCE
,
1747 MESA_DEBUG_SEVERITY_MEDIUM
, fmt
, args
);
1753 parse_devid_override(const char *devid_override
)
1755 static const struct {
1771 for (unsigned i
= 0; i
< ARRAY_SIZE(name_map
); i
++) {
1772 if (!strcmp(name_map
[i
].name
, devid_override
))
1773 return name_map
[i
].pci_id
;
1776 return strtod(devid_override
, NULL
);
1780 * Get the PCI ID for the device. This can be overridden by setting the
1781 * INTEL_DEVID_OVERRIDE environment variable to the desired ID.
1783 * Returns -1 on ioctl failure.
1786 get_pci_device_id(struct intel_screen
*screen
)
1788 if (geteuid() == getuid()) {
1789 char *devid_override
= getenv("INTEL_DEVID_OVERRIDE");
1790 if (devid_override
) {
1791 screen
->no_hw
= true;
1792 return parse_devid_override(devid_override
);
1796 return intel_get_integer(screen
, I915_PARAM_CHIPSET_ID
);
1800 * This is the driver specific part of the createNewScreen entry point.
1801 * Called when using DRI2.
1803 * \return the struct gl_config supported by this driver
1806 __DRIconfig
**intelInitScreen2(__DRIscreen
*dri_screen
)
1808 struct intel_screen
*screen
;
1810 if (dri_screen
->image
.loader
) {
1811 } else if (dri_screen
->dri2
.loader
->base
.version
<= 2 ||
1812 dri_screen
->dri2
.loader
->getBuffersWithFormat
== NULL
) {
1814 "\nERROR! DRI2 loader with getBuffersWithFormat() "
1815 "support required\n");
1819 /* Allocate the private area */
1820 screen
= rzalloc(NULL
, struct intel_screen
);
1822 fprintf(stderr
, "\nERROR! Allocating private area failed\n");
1825 /* parse information in __driConfigOptions */
1826 driParseOptionInfo(&screen
->optionCache
, brw_config_options
.xml
);
1828 screen
->driScrnPriv
= dri_screen
;
1829 dri_screen
->driverPrivate
= (void *) screen
;
1831 screen
->deviceID
= get_pci_device_id(screen
);
1833 if (!gen_get_device_info(screen
->deviceID
, &screen
->devinfo
))
1836 if (!intel_init_bufmgr(screen
))
1839 const struct gen_device_info
*devinfo
= &screen
->devinfo
;
1841 brw_process_intel_debug_variable();
1843 if ((INTEL_DEBUG
& DEBUG_SHADER_TIME
) && devinfo
->gen
< 7) {
1845 "shader_time debugging requires gen7 (Ivybridge) or better.\n");
1846 INTEL_DEBUG
&= ~DEBUG_SHADER_TIME
;
1849 if (intel_get_integer(screen
, I915_PARAM_MMAP_GTT_VERSION
) >= 1) {
1850 /* Theorectically unlimited! At least for individual objects...
1852 * Currently the entire (global) address space for all GTT maps is
1853 * limited to 64bits. That is all objects on the system that are
1854 * setup for GTT mmapping must fit within 64bits. An attempt to use
1855 * one that exceeds the limit with fail in brw_bo_map_gtt().
1857 * Long before we hit that limit, we will be practically limited by
1858 * that any single object must fit in physical memory (RAM). The upper
1859 * limit on the CPU's address space is currently 48bits (Skylake), of
1860 * which only 39bits can be physical memory. (The GPU itself also has
1861 * a 48bit addressable virtual space.) We can fit over 32 million
1862 * objects of the current maximum allocable size before running out
1865 screen
->max_gtt_map_object_size
= UINT64_MAX
;
1867 /* Estimate the size of the mappable aperture into the GTT. There's an
1868 * ioctl to get the whole GTT size, but not one to get the mappable subset.
1869 * It turns out it's basically always 256MB, though some ancient hardware
1872 uint32_t gtt_size
= 256 * 1024 * 1024;
1874 /* We don't want to map two objects such that a memcpy between them would
1875 * just fault one mapping in and then the other over and over forever. So
1876 * we would need to divide the GTT size by 2. Additionally, some GTT is
1877 * taken up by things like the framebuffer and the ringbuffer and such, so
1878 * be more conservative.
1880 screen
->max_gtt_map_object_size
= gtt_size
/ 4;
1883 screen
->aperture_threshold
= get_aperture_size(dri_screen
->fd
) * 3 / 4;
1885 screen
->hw_has_swizzling
= intel_detect_swizzling(screen
);
1886 screen
->hw_has_timestamp
= intel_detect_timestamp(screen
);
1888 /* GENs prior to 8 do not support EU/Subslice info */
1889 if (devinfo
->gen
>= 8) {
1890 intel_detect_sseu(screen
);
1891 } else if (devinfo
->gen
== 7) {
1892 screen
->subslice_total
= 1 << (devinfo
->gt
- 1);
1895 /* Gen7-7.5 kernel requirements / command parser saga:
1898 * Haswell and Baytrail cannot use any privileged batchbuffer features.
1900 * Ivybridge has aliasing PPGTT on by default, which accidentally marks
1901 * all batches secure, allowing them to use any feature with no checking.
1902 * This is effectively equivalent to a command parser version of
1903 * \infinity - everything is possible.
1905 * The command parser does not exist, and querying the version will
1909 * The kernel enables the command parser by default, for systems with
1910 * aliasing PPGTT enabled (Ivybridge and Haswell). However, the
1911 * hardware checker is still enabled, so Haswell and Baytrail cannot
1914 * Ivybridge goes from "everything is possible" to "only what the
1915 * command parser allows" (if the user boots with i915.cmd_parser=0,
1916 * then everything is possible again). We can only safely use features
1917 * allowed by the supported command parser version.
1919 * Annoyingly, I915_PARAM_CMD_PARSER_VERSION reports the static version
1920 * implemented by the kernel, even if it's turned off. So, checking
1921 * for version > 0 does not mean that you can write registers. We have
1922 * to try it and see. The version does, however, indicate the age of
1925 * Instead of matching the hardware checker's behavior of converting
1926 * privileged commands to MI_NOOP, it makes execbuf2 start returning
1927 * -EINVAL, making it dangerous to try and use privileged features.
1929 * Effective command parser versions:
1930 * - Haswell: 0 (reporting 1, writes don't work)
1931 * - Baytrail: 0 (reporting 1, writes don't work)
1932 * - Ivybridge: 1 (enabled) or infinite (disabled)
1935 * Baytrail aliasing PPGTT is enabled, making it like Ivybridge:
1936 * effectively version 1 (enabled) or infinite (disabled).
1938 * - v3.19: f1f55cc0556031c8ee3fe99dae7251e78b9b653b
1939 * Command parser v2 supports predicate writes.
1941 * - Haswell: 0 (reporting 1, writes don't work)
1942 * - Baytrail: 2 (enabled) or infinite (disabled)
1943 * - Ivybridge: 2 (enabled) or infinite (disabled)
1945 * So version >= 2 is enough to know that Ivybridge and Baytrail
1946 * will work. Haswell still can't do anything.
1948 * - v4.0: Version 3 happened. Largely not relevant.
1950 * - v4.1: 6702cf16e0ba8b0129f5aa1b6609d4e9c70bc13b
1951 * L3 config registers are properly saved and restored as part
1952 * of the hardware context. We can approximately detect this point
1953 * in time by checking if I915_PARAM_REVISION is recognized - it
1954 * landed in a later commit, but in the same release cycle.
1956 * - v4.2: 245054a1fe33c06ad233e0d58a27ec7b64db9284
1957 * Command parser finally gains secure batch promotion. On Haswell,
1958 * the hardware checker gets disabled, which finally allows it to do
1959 * privileged commands.
1961 * I915_PARAM_CMD_PARSER_VERSION reports 3. Effective versions:
1962 * - Haswell: 3 (enabled) or 0 (disabled)
1963 * - Baytrail: 3 (enabled) or infinite (disabled)
1964 * - Ivybridge: 3 (enabled) or infinite (disabled)
1966 * Unfortunately, detecting this point in time is tricky, because
1967 * no version bump happened when this important change occurred.
1968 * On Haswell, if we can write any register, then the kernel is at
1969 * least this new, and we can start trusting the version number.
1971 * - v4.4: 2bbe6bbb0dc94fd4ce287bdac9e1bd184e23057b and
1972 * Command parser reaches version 4, allowing access to Haswell
1973 * atomic scratch and chicken3 registers. If version >= 4, we know
1974 * the kernel is new enough to support privileged features on all
1975 * hardware. However, the user might have disabled it...and the
1976 * kernel will still report version 4. So we still have to guess
1979 * - v4.4: 7b9748cb513a6bef4af87b79f0da3ff7e8b56cd8
1980 * Command parser v5 whitelists indirect compute shader dispatch
1981 * registers, needed for OpenGL 4.3 and later.
1984 * Command parser v7 lets us use MI_MATH on Haswell.
1986 * Additionally, the kernel begins reporting version 0 when
1987 * the command parser is disabled, allowing us to skip the
1988 * guess-and-check step on Haswell. Unfortunately, this also
1989 * means that we can no longer use it as an indicator of the
1990 * age of the kernel.
1992 if (intel_get_param(screen
, I915_PARAM_CMD_PARSER_VERSION
,
1993 &screen
->cmd_parser_version
) < 0) {
1994 /* Command parser does not exist - getparam is unrecognized */
1995 screen
->cmd_parser_version
= 0;
1998 if (!intel_detect_pipelined_so(screen
)) {
1999 /* We can't do anything, so the effective version is 0. */
2000 screen
->cmd_parser_version
= 0;
2002 screen
->kernel_features
|= KERNEL_ALLOWS_SOL_OFFSET_WRITES
;
2005 if (devinfo
->gen
>= 8 || screen
->cmd_parser_version
>= 2)
2006 screen
->kernel_features
|= KERNEL_ALLOWS_PREDICATE_WRITES
;
2008 /* Haswell requires command parser version 4 in order to have L3
2009 * atomic scratch1 and chicken3 bits
2011 if (devinfo
->is_haswell
&& screen
->cmd_parser_version
>= 4) {
2012 screen
->kernel_features
|=
2013 KERNEL_ALLOWS_HSW_SCRATCH1_AND_ROW_CHICKEN3
;
2016 /* Haswell requires command parser version 6 in order to write to the
2017 * MI_MATH GPR registers, and version 7 in order to use
2018 * MI_LOAD_REGISTER_REG (which all users of MI_MATH use).
2020 if (devinfo
->gen
>= 8 ||
2021 (devinfo
->is_haswell
&& screen
->cmd_parser_version
>= 7)) {
2022 screen
->kernel_features
|= KERNEL_ALLOWS_MI_MATH_AND_LRR
;
2025 /* Gen7 needs at least command parser version 5 to support compute */
2026 if (devinfo
->gen
>= 8 || screen
->cmd_parser_version
>= 5)
2027 screen
->kernel_features
|= KERNEL_ALLOWS_COMPUTE_DISPATCH
;
2029 const char *force_msaa
= getenv("INTEL_FORCE_MSAA");
2031 screen
->winsys_msaa_samples_override
=
2032 intel_quantize_num_samples(screen
, atoi(force_msaa
));
2033 printf("Forcing winsys sample count to %d\n",
2034 screen
->winsys_msaa_samples_override
);
2036 screen
->winsys_msaa_samples_override
= -1;
2039 set_max_gl_versions(screen
);
2041 /* Notification of GPU resets requires hardware contexts and a kernel new
2042 * enough to support DRM_IOCTL_I915_GET_RESET_STATS. If the ioctl is
2043 * supported, calling it with a context of 0 will either generate EPERM or
2044 * no error. If the ioctl is not supported, it always generate EINVAL.
2045 * Use this to determine whether to advertise the __DRI2_ROBUSTNESS
2046 * extension to the loader.
2048 * Don't even try on pre-Gen6, since we don't attempt to use contexts there.
2050 if (devinfo
->gen
>= 6) {
2051 struct drm_i915_reset_stats stats
;
2052 memset(&stats
, 0, sizeof(stats
));
2054 const int ret
= drmIoctl(dri_screen
->fd
, DRM_IOCTL_I915_GET_RESET_STATS
, &stats
);
2056 screen
->has_context_reset_notification
=
2057 (ret
!= -1 || errno
!= EINVAL
);
2060 dri_screen
->extensions
= !screen
->has_context_reset_notification
2061 ? screenExtensions
: intelRobustScreenExtensions
;
2063 screen
->compiler
= brw_compiler_create(screen
, devinfo
);
2064 screen
->compiler
->shader_debug_log
= shader_debug_log_mesa
;
2065 screen
->compiler
->shader_perf_log
= shader_perf_log_mesa
;
2066 screen
->program_id
= 1;
2068 screen
->has_exec_fence
=
2069 intel_get_boolean(screen
, I915_PARAM_HAS_EXEC_FENCE
);
2071 return (const __DRIconfig
**) intel_screen_make_configs(dri_screen
);
2074 struct intel_buffer
{
2079 static __DRIbuffer
*
2080 intelAllocateBuffer(__DRIscreen
*dri_screen
,
2081 unsigned attachment
, unsigned format
,
2082 int width
, int height
)
2084 struct intel_buffer
*intelBuffer
;
2085 struct intel_screen
*screen
= dri_screen
->driverPrivate
;
2087 assert(attachment
== __DRI_BUFFER_FRONT_LEFT
||
2088 attachment
== __DRI_BUFFER_BACK_LEFT
);
2090 intelBuffer
= calloc(1, sizeof *intelBuffer
);
2091 if (intelBuffer
== NULL
)
2094 /* The front and back buffers are color buffers, which are X tiled. GEN9+
2095 * supports Y tiled and compressed buffers, but there is no way to plumb that
2096 * through to here. */
2098 int cpp
= format
/ 8;
2099 intelBuffer
->bo
= brw_bo_alloc_tiled(screen
->bufmgr
,
2100 "intelAllocateBuffer",
2104 I915_TILING_X
, &pitch
,
2105 BO_ALLOC_FOR_RENDER
);
2107 if (intelBuffer
->bo
== NULL
) {
2112 brw_bo_flink(intelBuffer
->bo
, &intelBuffer
->base
.name
);
2114 intelBuffer
->base
.attachment
= attachment
;
2115 intelBuffer
->base
.cpp
= cpp
;
2116 intelBuffer
->base
.pitch
= pitch
;
2118 return &intelBuffer
->base
;
2122 intelReleaseBuffer(__DRIscreen
*dri_screen
, __DRIbuffer
*buffer
)
2124 struct intel_buffer
*intelBuffer
= (struct intel_buffer
*) buffer
;
2126 brw_bo_unreference(intelBuffer
->bo
);
2130 static const struct __DriverAPIRec brw_driver_api
= {
2131 .InitScreen
= intelInitScreen2
,
2132 .DestroyScreen
= intelDestroyScreen
,
2133 .CreateContext
= brwCreateContext
,
2134 .DestroyContext
= intelDestroyContext
,
2135 .CreateBuffer
= intelCreateBuffer
,
2136 .DestroyBuffer
= intelDestroyBuffer
,
2137 .MakeCurrent
= intelMakeCurrent
,
2138 .UnbindContext
= intelUnbindContext
,
2139 .AllocateBuffer
= intelAllocateBuffer
,
2140 .ReleaseBuffer
= intelReleaseBuffer
2143 static const struct __DRIDriverVtableExtensionRec brw_vtable
= {
2144 .base
= { __DRI_DRIVER_VTABLE
, 1 },
2145 .vtable
= &brw_driver_api
,
2148 static const __DRIextension
*brw_driver_extensions
[] = {
2149 &driCoreExtension
.base
,
2150 &driImageDriverExtension
.base
,
2151 &driDRI2Extension
.base
,
2153 &brw_config_options
.base
,
2157 PUBLIC
const __DRIextension
**__driDriverGetExtensions_i965(void)
2159 globalDriverAPI
= &brw_driver_api
;
2161 return brw_driver_extensions
;